2 * arch/arm/mach-orion5x/pci.c
4 * PCI and PCIe functions for Marvell Orion System On Chip
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/mbus.h>
16 #include <asm/mach/pci.h>
17 #include <asm/plat-orion/pcie.h>
20 /*****************************************************************************
21 * Orion has one PCIe controller and one PCI controller.
23 * Note1: The local PCIe bus number is '0'. The local PCI bus number
24 * follows the scanned PCIe bridged busses, if any.
26 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
27 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
28 * device bus, Orion registers, etc. However this code only enable the
29 * access to DDR banks.
30 ****************************************************************************/
33 /*****************************************************************************
35 ****************************************************************************/
36 #define PCIE_BASE ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
38 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
40 *dev = orion_pcie_dev_id(PCIE_BASE);
41 *rev = orion_pcie_rev(PCIE_BASE);
44 static int pcie_valid_config(int bus, int dev)
47 * Don't go out when trying to access --
48 * 1. nonexisting device on local bus
49 * 2. where there's no device connected (no link)
51 if (bus == 0 && dev == 0)
54 if (!orion_pcie_link_up(PCIE_BASE))
57 if (bus == 0 && dev != 1)
65 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
66 * and then reading the PCIE_CONF_DATA register. Need to make sure these
67 * transactions are atomic.
69 static DEFINE_SPINLOCK(orion5x_pcie_lock);
71 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
77 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
79 return PCIBIOS_DEVICE_NOT_FOUND;
82 spin_lock_irqsave(&orion5x_pcie_lock, flags);
83 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
84 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
89 static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
90 int where, int size, u32 *val)
94 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
96 return PCIBIOS_DEVICE_NOT_FOUND;
100 * We only support access to the non-extended configuration
101 * space when using the WA access method (or we would have to
102 * sacrifice 256M of CPU virtual address space.)
104 if (where >= 0x100) {
106 return PCIBIOS_DEVICE_NOT_FOUND;
109 ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
110 bus, devfn, where, size, val);
115 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
116 int where, int size, u32 val)
121 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
122 return PCIBIOS_DEVICE_NOT_FOUND;
124 spin_lock_irqsave(&orion5x_pcie_lock, flags);
125 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
126 spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
131 static struct pci_ops pcie_ops = {
132 .read = pcie_rd_conf,
133 .write = pcie_wr_conf,
137 static int __init pcie_setup(struct pci_sys_data *sys)
139 struct resource *res;
143 * Generic PCIe unit setup.
145 orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
148 * Check whether to apply Orion-1/Orion-NAS PCIe config
149 * read transaction workaround.
151 dev = orion_pcie_dev_id(PCIE_BASE);
152 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
153 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
154 "read transaction workaround\n");
155 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
156 ORION5X_PCIE_WA_SIZE);
157 pcie_ops.read = pcie_rd_conf_wa;
163 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
165 panic("pcie_setup unable to alloc resources");
170 res[0].name = "PCIe I/O Space";
171 res[0].flags = IORESOURCE_IO;
172 res[0].start = ORION5X_PCIE_IO_BUS_BASE;
173 res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
174 if (request_resource(&ioport_resource, &res[0]))
175 panic("Request PCIe IO resource failed\n");
176 sys->resource[0] = &res[0];
181 res[1].name = "PCIe Memory Space";
182 res[1].flags = IORESOURCE_MEM;
183 res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
184 res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
185 if (request_resource(&iomem_resource, &res[1]))
186 panic("Request PCIe Memory resource failed\n");
187 sys->resource[1] = &res[1];
189 sys->resource[2] = NULL;
195 /*****************************************************************************
197 ****************************************************************************/
198 #define PCI_MODE ORION5X_PCI_REG(0xd00)
199 #define PCI_CMD ORION5X_PCI_REG(0xc00)
200 #define PCI_P2P_CONF ORION5X_PCI_REG(0x1d14)
201 #define PCI_CONF_ADDR ORION5X_PCI_REG(0xc78)
202 #define PCI_CONF_DATA ORION5X_PCI_REG(0xc7c)
207 #define PCI_MODE_64BIT (1 << 2)
208 #define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
213 #define PCI_CMD_HOST_REORDER (1 << 29)
218 #define PCI_P2P_BUS_OFFS 16
219 #define PCI_P2P_BUS_MASK (0xff << PCI_P2P_BUS_OFFS)
220 #define PCI_P2P_DEV_OFFS 24
221 #define PCI_P2P_DEV_MASK (0x1f << PCI_P2P_DEV_OFFS)
226 #define PCI_CONF_REG(reg) ((reg) & 0xfc)
227 #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
228 #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
229 #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
230 #define PCI_CONF_ADDR_EN (1 << 31)
233 * Internal configuration space
235 #define PCI_CONF_FUNC_STAT_CMD 0
236 #define PCI_CONF_REG_STAT_CMD 4
237 #define PCIX_STAT 0x64
238 #define PCIX_STAT_BUS_OFFS 8
239 #define PCIX_STAT_BUS_MASK (0xff << PCIX_STAT_BUS_OFFS)
242 * PCI Address Decode Windows registers
244 #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
245 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
246 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
247 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
248 #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
249 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
250 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
251 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
252 #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
253 #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
256 * PCI configuration helpers for BAR settings
258 #define PCI_CONF_FUNC_BAR_CS(n) ((n) >> 1)
259 #define PCI_CONF_REG_BAR_LO_CS(n) (((n) & 1) ? 0x18 : 0x10)
260 #define PCI_CONF_REG_BAR_HI_CS(n) (((n) & 1) ? 0x1c : 0x14)
263 * PCI config cycles are done by programming the PCI_CONF_ADDR register
264 * and then reading the PCI_CONF_DATA register. Need to make sure these
265 * transactions are atomic.
267 static DEFINE_SPINLOCK(orion5x_pci_lock);
269 static int orion5x_pci_local_bus_nr(void)
271 u32 conf = readl(PCI_P2P_CONF);
272 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
275 static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
276 u32 where, u32 size, u32 *val)
279 spin_lock_irqsave(&orion5x_pci_lock, flags);
281 writel(PCI_CONF_BUS(bus) |
282 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
283 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
285 *val = readl(PCI_CONF_DATA);
288 *val = (*val >> (8*(where & 0x3))) & 0xff;
290 *val = (*val >> (8*(where & 0x3))) & 0xffff;
292 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
294 return PCIBIOS_SUCCESSFUL;
297 static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
298 u32 where, u32 size, u32 val)
301 int ret = PCIBIOS_SUCCESSFUL;
303 spin_lock_irqsave(&orion5x_pci_lock, flags);
305 writel(PCI_CONF_BUS(bus) |
306 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
307 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
310 __raw_writel(val, PCI_CONF_DATA);
311 } else if (size == 2) {
312 __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
313 } else if (size == 1) {
314 __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
316 ret = PCIBIOS_BAD_REGISTER_NUMBER;
319 spin_unlock_irqrestore(&orion5x_pci_lock, flags);
324 static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
325 int where, int size, u32 *val)
328 * Don't go out for local device
330 if (bus->number == orion5x_pci_local_bus_nr() &&
331 PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
333 return PCIBIOS_DEVICE_NOT_FOUND;
336 return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
337 PCI_FUNC(devfn), where, size, val);
340 static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
341 int where, int size, u32 val)
343 if (bus->number == orion5x_pci_local_bus_nr() &&
344 PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
345 return PCIBIOS_DEVICE_NOT_FOUND;
347 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
348 PCI_FUNC(devfn), where, size, val);
351 static struct pci_ops pci_ops = {
352 .read = orion5x_pci_rd_conf,
353 .write = orion5x_pci_wr_conf,
356 static void __init orion5x_pci_set_bus_nr(int nr)
358 u32 p2p = readl(PCI_P2P_CONF);
360 if (readl(PCI_MODE) & PCI_MODE_PCIX) {
364 u32 pcix_status, bus, dev;
365 bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
366 dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
367 orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
368 pcix_status &= ~PCIX_STAT_BUS_MASK;
369 pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
370 orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
373 * PCI Conventional mode
375 p2p &= ~PCI_P2P_BUS_MASK;
376 p2p |= (nr << PCI_P2P_BUS_OFFS);
377 writel(p2p, PCI_P2P_CONF);
381 static void __init orion5x_pci_master_slave_enable(void)
383 int bus_nr, func, reg;
386 bus_nr = orion5x_pci_local_bus_nr();
387 func = PCI_CONF_FUNC_STAT_CMD;
388 reg = PCI_CONF_REG_STAT_CMD;
389 orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
390 val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
391 orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
394 static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
401 * First, disable windows.
403 win_enable = 0xffffffff;
404 writel(win_enable, PCI_BAR_ENABLE);
407 * Setup windows for DDR banks.
409 bus = orion5x_pci_local_bus_nr();
411 for (i = 0; i < dram->num_cs; i++) {
412 struct mbus_dram_window *cs = dram->cs + i;
413 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
418 * Write DRAM bank base address register.
420 reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
421 orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
422 val = (cs->base & 0xfffff000) | (val & 0xfff);
423 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
426 * Write DRAM bank size register.
428 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
429 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
430 writel((cs->size - 1) & 0xfffff000,
431 PCI_BAR_SIZE_DDR_CS(cs->cs_index));
432 writel(cs->base & 0xfffff000,
433 PCI_BAR_REMAP_DDR_CS(cs->cs_index));
436 * Enable decode window for this chip select.
438 win_enable &= ~(1 << cs->cs_index);
442 * Re-enable decode windows.
444 writel(win_enable, PCI_BAR_ENABLE);
447 * Disable automatic update of address remaping when writing to BARs.
449 orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
452 static int __init pci_setup(struct pci_sys_data *sys)
454 struct resource *res;
457 * Point PCI unit MBUS decode windows to DRAM space.
459 orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
462 * Master + Slave enable
464 orion5x_pci_master_slave_enable();
469 orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
474 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
476 panic("pci_setup unable to alloc resources");
481 res[0].name = "PCI I/O Space";
482 res[0].flags = IORESOURCE_IO;
483 res[0].start = ORION5X_PCI_IO_BUS_BASE;
484 res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
485 if (request_resource(&ioport_resource, &res[0]))
486 panic("Request PCI IO resource failed\n");
487 sys->resource[0] = &res[0];
492 res[1].name = "PCI Memory Space";
493 res[1].flags = IORESOURCE_MEM;
494 res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
495 res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
496 if (request_resource(&iomem_resource, &res[1]))
497 panic("Request PCI Memory resource failed\n");
498 sys->resource[1] = &res[1];
500 sys->resource[2] = NULL;
507 /*****************************************************************************
509 ****************************************************************************/
510 static void __devinit rc_pci_fixup(struct pci_dev *dev)
513 * Prevent enumeration of root complex.
515 if (dev->bus->parent == NULL && dev->devfn == 0) {
518 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
519 dev->resource[i].start = 0;
520 dev->resource[i].end = 0;
521 dev->resource[i].flags = 0;
525 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
527 int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
532 orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
533 ret = pcie_setup(sys);
534 } else if (nr == 1) {
535 orion5x_pci_set_bus_nr(sys->busnr);
536 ret = pci_setup(sys);
542 struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
547 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
548 } else if (nr == 1) {
549 bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
558 int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
560 int bus = dev->bus->number;
565 if (bus < orion5x_pci_local_bus_nr())
566 return IRQ_ORION5X_PCIE0_INT;