2 * arch/arm/mach-orion5x/common.c
4 * Core functions for Marvell Orion 5x SoCs
6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/serial_8250.h>
18 #include <linux/mbus.h>
19 #include <linux/mv643xx_i2c.h>
20 #include <linux/ata_platform.h>
23 #include <asm/setup.h>
24 #include <asm/timex.h>
25 #include <asm/mach/arch.h>
26 #include <asm/mach/map.h>
27 #include <asm/mach/time.h>
28 #include <mach/bridge-regs.h>
29 #include <mach/hardware.h>
30 #include <mach/orion5x.h>
31 #include <plat/orion_nand.h>
32 #include <plat/ehci-orion.h>
33 #include <plat/time.h>
34 #include <plat/common.h>
37 /*****************************************************************************
39 ****************************************************************************/
40 static struct map_desc orion5x_io_desc[] __initdata = {
42 .virtual = ORION5X_REGS_VIRT_BASE,
43 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
44 .length = ORION5X_REGS_SIZE,
47 .virtual = ORION5X_PCIE_IO_VIRT_BASE,
48 .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
49 .length = ORION5X_PCIE_IO_SIZE,
52 .virtual = ORION5X_PCI_IO_VIRT_BASE,
53 .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
54 .length = ORION5X_PCI_IO_SIZE,
57 .virtual = ORION5X_PCIE_WA_VIRT_BASE,
58 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
59 .length = ORION5X_PCIE_WA_SIZE,
64 void __init orion5x_map_io(void)
66 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
70 /*****************************************************************************
72 ****************************************************************************/
73 void __init orion5x_ehci0_init(void)
75 orion_ehci_init(&orion5x_mbus_dram_info,
76 ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
81 /*****************************************************************************
83 ****************************************************************************/
84 void __init orion5x_ehci1_init(void)
86 orion_ehci_1_init(&orion5x_mbus_dram_info,
87 ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
91 /*****************************************************************************
93 ****************************************************************************/
94 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
96 orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
97 ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
98 IRQ_ORION5X_ETH_ERR, orion5x_tclk,
99 MV643XX_TX_CSUM_DEFAULT_LIMIT);
103 /*****************************************************************************
105 ****************************************************************************/
106 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
108 orion_ge00_switch_init(d, irq);
112 /*****************************************************************************
114 ****************************************************************************/
115 void __init orion5x_i2c_init(void)
117 orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
122 /*****************************************************************************
124 ****************************************************************************/
125 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
127 orion_sata_init(sata_data, &orion5x_mbus_dram_info,
128 ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
132 /*****************************************************************************
134 ****************************************************************************/
135 void __init orion5x_spi_init()
137 orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
141 /*****************************************************************************
143 ****************************************************************************/
144 void __init orion5x_uart0_init(void)
146 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
147 IRQ_ORION5X_UART0, orion5x_tclk);
150 /*****************************************************************************
152 ****************************************************************************/
153 void __init orion5x_uart1_init(void)
155 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
156 IRQ_ORION5X_UART1, orion5x_tclk);
159 /*****************************************************************************
161 ****************************************************************************/
162 void __init orion5x_xor_init(void)
164 orion_xor0_init(&orion5x_mbus_dram_info,
165 ORION5X_XOR_PHYS_BASE,
166 ORION5X_XOR_PHYS_BASE + 0x200,
167 IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
170 /*****************************************************************************
171 * Cryptographic Engines and Security Accelerator (CESA)
172 ****************************************************************************/
173 static void __init orion5x_crypto_init(void)
177 ret = orion5x_setup_sram_win();
181 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
182 SZ_8K, IRQ_ORION5X_CESA);
185 /*****************************************************************************
187 ****************************************************************************/
188 void __init orion5x_wdt_init(void)
190 orion_wdt_init(orion5x_tclk);
194 /*****************************************************************************
196 ****************************************************************************/
197 void __init orion5x_init_early(void)
199 orion_time_set_base(TIMER_VIRT_BASE);
204 int __init orion5x_find_tclk(void)
208 orion5x_pcie_id(&dev, &rev);
209 if (dev == MV88F6183_DEV_ID &&
210 (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
216 static void orion5x_timer_init(void)
218 orion5x_tclk = orion5x_find_tclk();
220 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
221 IRQ_ORION5X_BRIDGE, orion5x_tclk);
224 struct sys_timer orion5x_timer = {
225 .init = orion5x_timer_init,
229 /*****************************************************************************
231 ****************************************************************************/
233 * Identify device ID and rev from PCIe configuration header space '0'.
235 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
237 orion5x_pcie_id(dev, rev);
239 if (*dev == MV88F5281_DEV_ID) {
240 if (*rev == MV88F5281_REV_D2) {
241 *dev_name = "MV88F5281-D2";
242 } else if (*rev == MV88F5281_REV_D1) {
243 *dev_name = "MV88F5281-D1";
244 } else if (*rev == MV88F5281_REV_D0) {
245 *dev_name = "MV88F5281-D0";
247 *dev_name = "MV88F5281-Rev-Unsupported";
249 } else if (*dev == MV88F5182_DEV_ID) {
250 if (*rev == MV88F5182_REV_A2) {
251 *dev_name = "MV88F5182-A2";
253 *dev_name = "MV88F5182-Rev-Unsupported";
255 } else if (*dev == MV88F5181_DEV_ID) {
256 if (*rev == MV88F5181_REV_B1) {
257 *dev_name = "MV88F5181-Rev-B1";
258 } else if (*rev == MV88F5181L_REV_A1) {
259 *dev_name = "MV88F5181L-Rev-A1";
261 *dev_name = "MV88F5181(L)-Rev-Unsupported";
263 } else if (*dev == MV88F6183_DEV_ID) {
264 if (*rev == MV88F6183_REV_B0) {
265 *dev_name = "MV88F6183-Rev-B0";
267 *dev_name = "MV88F6183-Rev-Unsupported";
270 *dev_name = "Device-Unknown";
274 void __init orion5x_init(void)
279 orion5x_id(&dev, &rev, &dev_name);
280 printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
283 * Setup Orion address map
285 orion5x_setup_cpu_mbus_bridge();
288 * Don't issue "Wait for Interrupt" instruction if we are
289 * running on D0 5281 silicon.
291 if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
292 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
297 * The 5082/5181l/5182/6082/6082l/6183 have crypto
298 * while 5180n/5181/5281 don't have crypto.
300 if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
301 dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
302 orion5x_crypto_init();
305 * Register watchdog driver
311 * Many orion-based systems have buggy bootloader implementations.
312 * This is a common fixup for bogus memory tags.
314 void __init tag_fixup_mem32(struct tag *t, char **from,
315 struct meminfo *meminfo)
317 for (; t->hdr.size; t = tag_next(t))
318 if (t->hdr.tag == ATAG_MEM &&
319 (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
320 t->u.mem.start & ~PAGE_MASK)) {
322 "Clearing invalid memory bank %dKB@0x%08x\n",
323 t->u.mem.size / 1024, t->u.mem.start);