2 * OMAP Voltage Controller (VC) interface
4 * Copyright (C) 2011 Texas Instruments, Inc.
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/bug.h>
16 #include <asm/div64.h>
22 #include "prm-regbits-34xx.h"
23 #include "prm-regbits-44xx.h"
30 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
31 * @sa: bit for slave address
32 * @rav: bit for voltage configuration register
33 * @rac: bit for command configuration register
34 * @racen: enable bit for RAC
35 * @cmd: bit for command value set selection
37 * Channel configuration bits, common for OMAP3+
38 * OMAP3 register: PRM_VC_CH_CONF
39 * OMAP4 register: PRM_VC_CFG_CHANNEL
40 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
42 struct omap_vc_channel_cfg {
50 static struct omap_vc_channel_cfg vc_default_channel_cfg = {
59 * On OMAP3+, all VC channels have the above default bitfield
60 * configuration, except the OMAP4 MPU channel. This appears
61 * to be a freak accident as every other VC channel has the
62 * default configuration, thus creating a mutant channel config.
64 static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
72 static struct omap_vc_channel_cfg *vc_cfg_bits;
74 /* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
75 static u32 sr_i2c_pcb_length = 63;
76 #define CFG_CHANNEL_MASK 0x1f
79 * omap_vc_config_channel - configure VC channel to PMIC mappings
80 * @voltdm: pointer to voltagdomain defining the desired VC channel
82 * Configures the VC channel to PMIC mappings for the following
84 * - i2c slave address (SA)
85 * - voltage configuration address (RAV)
86 * - command configuration address (RAC) and enable bit (RACEN)
87 * - command values for ON, ONLP, RET and OFF (CMD)
89 * This function currently only allows flexible configuration of the
90 * non-default channel. Starting with OMAP4, there are more than 2
91 * channels, with one defined as the default (on OMAP4, it's MPU.)
92 * Only the non-default channel can be configured.
94 static int omap_vc_config_channel(struct voltagedomain *voltdm)
96 struct omap_vc_channel *vc = voltdm->vc;
99 * For default channel, the only configurable bit is RACEN.
100 * All others must stay at zero (see function comment above.)
102 if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
103 vc->cfg_channel &= vc_cfg_bits->racen;
105 voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
106 vc->cfg_channel << vc->cfg_channel_sa_shift,
107 vc->cfg_channel_reg);
112 /* Voltage scale and accessory APIs */
113 int omap_vc_pre_scale(struct voltagedomain *voltdm,
114 unsigned long target_volt,
115 u8 *target_vsel, u8 *current_vsel)
117 struct omap_vc_channel *vc = voltdm->vc;
120 /* Check if sufficient pmic info is available for this vdd */
122 pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
123 __func__, voltdm->name);
127 if (!voltdm->pmic->uv_to_vsel) {
128 pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
129 __func__, voltdm->name);
133 if (!voltdm->read || !voltdm->write) {
134 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
135 __func__, voltdm->name);
139 *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
140 *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
142 /* Setting the ON voltage to the new target voltage */
143 vc_cmdval = voltdm->read(vc->cmdval_reg);
144 vc_cmdval &= ~vc->common->cmd_on_mask;
145 vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
146 voltdm->write(vc_cmdval, vc->cmdval_reg);
148 voltdm->vc_param->on = target_volt;
150 omap_vp_update_errorgain(voltdm, target_volt);
155 void omap_vc_post_scale(struct voltagedomain *voltdm,
156 unsigned long target_volt,
157 u8 target_vsel, u8 current_vsel)
159 u32 smps_steps = 0, smps_delay = 0;
161 smps_steps = abs(target_vsel - current_vsel);
162 /* SMPS slew rate / step size. 2us added as buffer. */
163 smps_delay = ((smps_steps * voltdm->pmic->step_size) /
164 voltdm->pmic->slew_rate) + 2;
168 /* vc_bypass_scale - VC bypass method of voltage scaling */
169 int omap_vc_bypass_scale(struct voltagedomain *voltdm,
170 unsigned long target_volt)
172 struct omap_vc_channel *vc = voltdm->vc;
173 u32 loop_cnt = 0, retries_cnt = 0;
174 u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
175 u8 target_vsel, current_vsel;
178 ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel);
182 vc_valid = vc->common->valid;
183 vc_bypass_val_reg = vc->common->bypass_val_reg;
184 vc_bypass_value = (target_vsel << vc->common->data_shift) |
185 (vc->volt_reg_addr << vc->common->regaddr_shift) |
186 (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
188 voltdm->write(vc_bypass_value, vc_bypass_val_reg);
189 voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
191 vc_bypass_value = voltdm->read(vc_bypass_val_reg);
193 * Loop till the bypass command is acknowledged from the SMPS.
194 * NOTE: This is legacy code. The loop count and retry count needs
197 while (!(vc_bypass_value & vc_valid)) {
200 if (retries_cnt > 10) {
201 pr_warning("%s: Retry count exceeded\n", __func__);
210 vc_bypass_value = voltdm->read(vc_bypass_val_reg);
213 omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
217 /* Convert microsecond value to number of 32kHz clock cycles */
218 static inline u32 omap_usec_to_32k(u32 usec)
220 return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
224 struct voltagedomain *vd;
227 static struct omap3_vc vc;
229 void omap3_vc_set_pmic_signaling(int core_next_state)
231 struct voltagedomain *vd = vc.vd;
234 voltctrl = vc.voltctrl;
235 switch (core_next_state) {
236 case PWRDM_POWER_OFF:
237 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET |
238 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
239 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF;
241 case PWRDM_POWER_RET:
243 voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF |
244 OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
245 voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET;
248 if (voltctrl != vc.voltctrl) {
249 vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET);
250 vc.voltctrl = voltctrl;
254 #define PRM_POLCTRL_TWL_MASK (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \
255 OMAP3430_PRM_POLCTRL_CLKREQ_POL)
256 #define PRM_POLCTRL_TWL_VAL OMAP3430_PRM_POLCTRL_CLKREQ_POL
259 * Configure signal polarity for sys_clkreq and sys_off_mode pins
260 * as the default values are wrong and can cause the system to hang
261 * if any twl4030 scripts are loaded.
263 static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
272 val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
273 if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
274 (val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) {
275 val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
276 val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
277 pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
279 voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET);
283 * By default let's use I2C4 signaling for retention idle
284 * and sys_off_mode pin signaling for off idle. This way we
285 * have sys_clk_req pin go down for retention and both
286 * sys_clk_req and sys_off_mode pins will go down for off
287 * idle. And we can also scale voltages to zero for off-idle.
288 * Note that no actual voltage scaling during off-idle will
289 * happen unless the board specific twl4030 PMIC scripts are
292 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
293 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
294 val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF;
295 pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
297 voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET);
301 omap3_vc_set_pmic_signaling(PWRDM_POWER_ON);
304 /* Set oscillator setup time for omap3 */
305 static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm)
307 voltdm->write(omap_usec_to_32k(usec), OMAP3_PRM_CLKSETUP_OFFSET);
311 * omap3_set_i2c_timings - sets i2c sleep timings for a channel
312 * @voltdm: channel to configure
313 * @off_mode: select whether retention or off mode values used
315 * Calculates and sets up voltage controller to use I2C based
316 * voltage scaling for sleep modes. This can be used for either off mode
317 * or retention. Off mode has additionally an option to use sys_off_mode
318 * pad, which uses a global signal to program the whole power IC to
321 static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode)
323 unsigned long voltsetup1;
327 * Oscillator is shut down only if we are using sys_off_mode pad,
328 * thus we set a minimal setup time here
330 omap3_set_clksetup(1, voltdm);
333 tgt_volt = voltdm->vc_param->off;
335 tgt_volt = voltdm->vc_param->ret;
337 voltsetup1 = (voltdm->vc_param->on - tgt_volt) /
338 voltdm->pmic->slew_rate;
340 voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1;
342 voltdm->rmw(voltdm->vfsm->voltsetup_mask,
343 voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask),
344 voltdm->vfsm->voltsetup_reg);
347 * pmic is not controlling the voltage scaling during retention,
348 * thus set voltsetup2 to 0
350 voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET);
354 * omap3_set_off_timings - sets off-mode timings for a channel
355 * @voltdm: channel to configure
357 * Calculates and sets up off-mode timings for a channel. Off-mode
358 * can use either I2C based voltage scaling, or alternatively
359 * sys_off_mode pad can be used to send a global command to power IC.
360 * This function first checks which mode is being used, and calls
361 * omap3_set_i2c_timings() if the system is using I2C control mode.
362 * sys_off_mode has the additional benefit that voltages can be
363 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
366 static void omap3_set_off_timings(struct voltagedomain *voltdm)
368 unsigned long clksetup;
369 unsigned long voltsetup2;
370 unsigned long voltsetup2_old;
374 /* check if sys_off_mode is used to control off-mode voltages */
375 val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
376 if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
377 /* No, omap is controlling them over I2C */
378 omap3_set_i2c_timings(voltdm, true);
382 omap_pm_get_oscillator(&tstart, &tshut);
383 omap3_set_clksetup(tstart, voltdm);
385 clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET);
387 /* voltsetup 2 in us */
388 voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate;
390 /* convert to 32k clk cycles */
391 voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000);
393 voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET);
396 * Update voltsetup2 if higher than current value (needed because
397 * we have multiple channels with different ramp times), also
398 * update voltoffset always to value recommended by TRM
400 if (voltsetup2 > voltsetup2_old) {
401 voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET);
402 voltdm->write(clksetup - voltsetup2,
403 OMAP3_PRM_VOLTOFFSET_OFFSET);
405 voltdm->write(clksetup - voltsetup2_old,
406 OMAP3_PRM_VOLTOFFSET_OFFSET);
409 * omap is not controlling voltage scaling during off-mode,
410 * thus set voltsetup1 to 0
412 voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0,
413 voltdm->vfsm->voltsetup_reg);
415 /* voltoffset must be clksetup minus voltsetup2 according to TRM */
416 voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET);
419 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
421 omap3_vc_init_pmic_signaling(voltdm);
422 omap3_set_off_timings(voltdm);
426 * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
427 * @voltdm: channel to calculate values for
428 * @voltage_diff: voltage difference in microvolts
430 * Calculates voltage ramp prescaler + counter values for a voltage
431 * difference on omap4. Returns a field value suitable for writing to
432 * VOLTSETUP register for a channel in following format:
433 * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
435 static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
441 time = voltage_diff / voltdm->pmic->slew_rate;
443 cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
448 /* shift to next prescaler until no overflow */
450 /* scale for div 256 = 64 * 4 */
456 /* scale for div 512 = 256 * 2 */
462 /* scale for div 2048 = 512 * 4 */
468 /* check for overflow => invalid ramp time */
470 pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
477 return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
478 (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
482 * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
483 * @usec: microseconds
484 * @shift: number of bits to shift left
485 * @mask: bitfield mask
487 * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
488 * shifted to requested position, and checked agains the mask value.
489 * If larger, forced to the max value of the field (i.e. the mask itself.)
490 * Returns the SCRM bitfield value.
492 static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
496 val = omap_usec_to_32k(usec) << shift;
498 /* Check for overflow, if yes, force to max value */
506 * omap4_set_timings - set voltage ramp timings for a channel
507 * @voltdm: channel to configure
508 * @off_mode: whether off-mode values are used
510 * Calculates and sets the voltage ramp up / down values for a channel.
512 static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
520 ramp = omap4_calc_volt_ramp(voltdm,
521 voltdm->vc_param->on - voltdm->vc_param->off);
522 offset = voltdm->vfsm->voltsetup_off_reg;
524 ramp = omap4_calc_volt_ramp(voltdm,
525 voltdm->vc_param->on - voltdm->vc_param->ret);
526 offset = voltdm->vfsm->voltsetup_reg;
532 val = voltdm->read(offset);
534 val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
536 val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
538 voltdm->write(val, offset);
540 omap_pm_get_oscillator(&tstart, &tshut);
542 val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
543 OMAP4_SETUPTIME_MASK);
544 val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
545 OMAP4_DOWNTIME_MASK);
547 __raw_writel(val, OMAP4_SCRM_CLKSETUPTIME);
550 /* OMAP4 specific voltage init functions */
551 static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
553 omap4_set_timings(voltdm, true);
554 omap4_set_timings(voltdm, false);
557 struct i2c_init_data {
567 static const __initdata struct i2c_init_data omap4_i2c_timing_data[] = {
607 * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
608 * @voltdm: voltagedomain pointer to get data from
610 * Use PMIC + board supplied settings for calculating the total I2C
611 * channel capacitance and set the timing parameters based on this.
612 * Pre-calculated values are provided in data tables, as it is not
613 * too straightforward to calculate these runtime.
615 static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
620 const struct i2c_init_data *i2c_data;
622 if (!voltdm->pmic->i2c_high_speed) {
623 pr_warn("%s: only high speed supported!\n", __func__);
627 /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
628 capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
630 /* OMAP pad capacitance */
633 /* PMIC pad capacitance */
634 capacitance += voltdm->pmic->i2c_pad_load;
636 /* Search for capacitance match in the table */
637 i2c_data = omap4_i2c_timing_data;
639 while (i2c_data->load > capacitance)
642 /* Select proper values based on sysclk frequency */
643 switch (voltdm->sys_clk.rate) {
645 hsscll = i2c_data->hsscll_38_4;
648 hsscll = i2c_data->hsscll_26;
651 hsscll = i2c_data->hsscll_19_2;
654 hsscll = i2c_data->hsscll_16_8;
657 hsscll = i2c_data->hsscll_12;
660 pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
661 voltdm->sys_clk.rate);
665 /* Loadbits define pull setup for the I2C channels */
666 val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
668 /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
669 __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
670 OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
672 /* HSSCLH can always be zero */
673 val = hsscll << OMAP4430_HSSCLL_SHIFT;
674 val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
676 /* Write setup times to I2C config register */
677 voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
683 * omap_vc_i2c_init - initialize I2C interface to PMIC
684 * @voltdm: voltage domain containing VC data
686 * Use PMIC supplied settings for I2C high-speed mode and
687 * master code (if set) and program the VC I2C configuration
690 * The VC I2C configuration is common to all VC channels,
691 * so this function only configures I2C for the first VC
692 * channel registers. All other VC channels will use the
693 * same configuration.
695 static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
697 struct omap_vc_channel *vc = voltdm->vc;
698 static bool initialized;
699 static bool i2c_high_speed;
703 if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
704 pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
705 __func__, voltdm->name, i2c_high_speed);
709 i2c_high_speed = voltdm->pmic->i2c_high_speed;
711 voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
712 vc->common->i2c_cfg_hsen_mask,
713 vc->common->i2c_cfg_reg);
715 mcode = voltdm->pmic->i2c_mcode;
717 voltdm->rmw(vc->common->i2c_mcode_mask,
718 mcode << __ffs(vc->common->i2c_mcode_mask),
719 vc->common->i2c_cfg_reg);
721 if (cpu_is_omap44xx())
722 omap4_vc_i2c_timing_init(voltdm);
728 * omap_vc_calc_vsel - calculate vsel value for a channel
729 * @voltdm: channel to calculate value for
730 * @uvolt: microvolt value to convert to vsel
732 * Converts a microvolt value to vsel value for the used PMIC.
733 * This checks whether the microvolt value is out of bounds, and
734 * adjusts the value accordingly. If unsupported value detected,
737 static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
739 if (voltdm->pmic->vddmin > uvolt)
740 uvolt = voltdm->pmic->vddmin;
741 if (voltdm->pmic->vddmax < uvolt) {
742 WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
743 __func__, uvolt, voltdm->pmic->vddmax);
744 /* Lets try maximum value anyway */
745 uvolt = voltdm->pmic->vddmax;
748 return voltdm->pmic->uv_to_vsel(uvolt);
753 * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
754 * @mm: length of the PCB trace in millimetres
756 * Sets the PCB trace length for the I2C channel. By default uses 63mm.
757 * This is needed for properly calculating the capacitance value for
758 * the PCB trace, and for setting the SR I2C channel timing parameters.
760 void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
762 sr_i2c_pcb_length = mm;
766 void __init omap_vc_init_channel(struct voltagedomain *voltdm)
768 struct omap_vc_channel *vc = voltdm->vc;
769 u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
772 if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
773 pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
777 if (!voltdm->read || !voltdm->write) {
778 pr_err("%s: No read/write API for accessing vdd_%s regs\n",
779 __func__, voltdm->name);
784 if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
785 vc_cfg_bits = &vc_mutant_channel_cfg;
787 vc_cfg_bits = &vc_default_channel_cfg;
789 /* get PMIC/board specific settings */
790 vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
791 vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
792 vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
794 /* Configure the i2c slave address for this VC */
795 voltdm->rmw(vc->smps_sa_mask,
796 vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
798 vc->cfg_channel |= vc_cfg_bits->sa;
801 * Configure the PMIC register addresses.
803 voltdm->rmw(vc->smps_volra_mask,
804 vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
806 vc->cfg_channel |= vc_cfg_bits->rav;
808 if (vc->cmd_reg_addr) {
809 voltdm->rmw(vc->smps_cmdra_mask,
810 vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
812 vc->cfg_channel |= vc_cfg_bits->rac;
815 if (vc->cmd_reg_addr == vc->volt_reg_addr)
816 vc->cfg_channel |= vc_cfg_bits->racen;
818 /* Set up the on, inactive, retention and off voltage */
819 on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
820 onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
821 ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
822 off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
824 val = ((on_vsel << vc->common->cmd_on_shift) |
825 (onlp_vsel << vc->common->cmd_onlp_shift) |
826 (ret_vsel << vc->common->cmd_ret_shift) |
827 (off_vsel << vc->common->cmd_off_shift));
828 voltdm->write(val, vc->cmdval_reg);
829 vc->cfg_channel |= vc_cfg_bits->cmd;
831 /* Channel configuration */
832 omap_vc_config_channel(voltdm);
834 omap_vc_i2c_init(voltdm);
836 if (cpu_is_omap34xx())
837 omap3_vc_init_channel(voltdm);
838 else if (cpu_is_omap44xx())
839 omap4_vc_init_channel(voltdm);