2 * linux/arch/arm/mach-omap3/sram.S
4 * Omap3 specific functions that need to be run in internal SRAM
6 * Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
7 * Copyright (C) 2008 Nokia Corporation
9 * Rajendra Nayak <rnayak@ti.com>
10 * Richard Woodruff <r-woodruff2@ti.com>
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <linux/linkage.h>
29 #include <asm/assembler.h>
30 #include <mach/hardware.h>
35 #include "cm2xxx_3xxx.h"
38 * This file needs be built unconditionally as ARM to interoperate correctly
39 * with non-Thumb-2-capable firmware.
46 #define SDRC_NO_UNLOCK_DLL 0x0
47 #define SDRC_UNLOCK_DLL 0x1
49 /* SDRC_DLLA_CTRL bit settings */
50 #define FIXEDDELAY_SHIFT 24
51 #define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
52 #define DLLIDLE_MASK 0x4
55 * SDRC_DLLA_CTRL default values: TI hardware team indicates that
56 * FIXEDDELAY should be initialized to 0xf. This apparently was
57 * empirically determined during process testing, so no derivation
60 #define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
62 /* SDRC_DLLA_STATUS bit settings */
63 #define LOCKSTATUS_MASK 0x4
65 /* SDRC_POWER bit settings */
66 #define SRFRONIDLEREQ_MASK 0x40
68 /* CM_IDLEST1_CORE bit settings */
69 #define ST_SDRC_MASK 0x2
71 /* CM_ICLKEN1_CORE bit settings */
72 #define EN_SDRC_MASK 0x2
74 /* CM_CLKSEL1_PLL bit settings */
75 #define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
78 * omap3_sram_configure_core_dpll - change DPLL3 M2 divider
80 * Params passed in registers:
81 * r0 = new M2 divider setting (only 1 and 2 supported right now)
82 * r1 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
84 * r2 = number of MPU cycles to wait for SDRC to stabilize after
85 * reprogramming the SDRC when switching to a slower MPU speed
86 * r3 = increasing SDRC rate? (1 = yes, 0 = no)
88 * Params passed via the stack. The needed params will be copied in SRAM
89 * before use by the code in SRAM (SDRAM is not accessible during SDRC
91 * new SDRC_RFR_CTRL_0 register contents
92 * new SDRC_ACTIM_CTRL_A_0 register contents
93 * new SDRC_ACTIM_CTRL_B_0 register contents
94 * new SDRC_MR_0 register value
95 * new SDRC_RFR_CTRL_1 register contents
96 * new SDRC_ACTIM_CTRL_A_1 register contents
97 * new SDRC_ACTIM_CTRL_B_1 register contents
98 * new SDRC_MR_1 register value
100 * If the param SDRC_RFR_CTRL_1 is 0, the parameters are not programmed into
101 * the SDRC CS1 registers
103 * NOTE: This code no longer attempts to program the SDRC AC timing and MR
104 * registers. This is because the code currently cannot ensure that all
105 * L3 initiators (e.g., sDMA, IVA, DSS DISPC, etc.) are not accessing the
106 * SDRAM when the registers are written. If the registers are changed while
107 * an initiator is accessing SDRAM, memory can be corrupted and/or the SDRC
108 * may enter an unpredictable state. In the future, the intent is to
109 * re-enable this code in cases where we can ensure that no initiators are
110 * touching the SDRAM. Until that time, users who know that their use case
111 * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
114 * Richard Woodruff notes that any changes to this code must be carefully
115 * audited and tested to ensure that they don't cause a TLB miss while
116 * the SDRAM is inaccessible. Such a situation will crash the system
117 * since it will cause the ARM MMU to attempt to walk the page tables.
118 * These crashes may be intermittent.
121 ENTRY(omap3_sram_configure_core_dpll)
122 stmfd sp!, {r1-r12, lr} @ store regs to stack
124 @ pull the extra args off the stack
125 @ and store them in SRAM
128 * PC-relative stores are deprecated in ARMv7 and lead to undefined behaviour
129 * in Thumb-2: use a r7 as a base instead.
130 * Be careful not to clobber r7 when maintaing this file.
132 THUMB( adr r7, omap3_sram_configure_core_dpll )
133 .macro strtext Rt:req, label:req
134 ARM( str \Rt, \label )
135 THUMB( str \Rt, [r7, \label - omap3_sram_configure_core_dpll] )
139 strtext r4, omap_sdrc_rfr_ctrl_0_val
141 strtext r4, omap_sdrc_actim_ctrl_a_0_val
143 strtext r4, omap_sdrc_actim_ctrl_b_0_val
145 strtext r4, omap_sdrc_mr_0_val
147 strtext r4, omap_sdrc_rfr_ctrl_1_val
148 cmp r4, #0 @ if SDRC_RFR_CTRL_1 is 0,
149 beq skip_cs1_params @ do not use cs1 params
151 strtext r4, omap_sdrc_actim_ctrl_a_1_val
153 strtext r4, omap_sdrc_actim_ctrl_b_1_val
155 strtext r4, omap_sdrc_mr_1_val
157 mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
158 bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
159 mcr p15, 0, r10, c1, c0, 0 @ write ctrl register
160 dsb @ flush buffered writes to interconnect
161 isb @ prevent speculative exec past here
162 cmp r3, #1 @ if increasing SDRC clk rate,
163 bleq configure_sdrc @ program the SDRC regs early (for RFR)
164 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
167 bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
168 bl configure_core_dpll @ change the DPLL3 M2 divider
170 bl wait_clk_stable @ wait for SDRC to stabilize
171 bl enable_sdrc @ take SDRC out of idle
172 cmp r1, #SDRC_UNLOCK_DLL @ wait for DLL status to change
175 cmp r3, #1 @ if increasing SDRC clk rate,
176 beq return_to_sdram @ return to SDRAM code, otherwise,
177 bl configure_sdrc @ reprogram SDRC regs now
179 mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
180 isb @ prevent speculative exec past here
181 mov r0, #0 @ return value
182 ldmfd sp!, {r1-r12, pc} @ restore regs and return
184 ldr r11, omap3_sdrc_dlla_ctrl
186 bic r12, r12, #FIXEDDELAY_MASK
187 orr r12, r12, #FIXEDDELAY_DEFAULT
188 orr r12, r12, #DLLIDLE_MASK
189 str r12, [r11] @ (no OCP barrier needed)
192 ldr r11, omap3_sdrc_dlla_ctrl
194 bic r12, r12, #DLLIDLE_MASK
195 str r12, [r11] @ (no OCP barrier needed)
197 sdram_in_selfrefresh:
198 ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
199 ldr r12, [r11] @ read the contents of SDRC_POWER
200 mov r9, r12 @ keep a copy of SDRC_POWER bits
201 orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
202 str r12, [r11] @ write back to SDRC_POWER register
203 ldr r12, [r11] @ posted-write barrier for SDRC
205 ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
207 bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
210 ldr r11, omap3_cm_idlest1_core
212 and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
213 cmp r12, #ST_SDRC_MASK
217 ldr r11, omap3_cm_clksel1_pll
220 ldr r10, core_m2_mask_val @ modify m2 for core dpll
222 orr r12, r12, r0, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
227 ldr r12, [r11] @ posted-write barrier for CM
234 ldr r11, omap3_cm_iclken1_core
236 orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
239 ldr r11, omap3_cm_idlest1_core
241 and r12, r12, #ST_SDRC_MASK
244 restore_sdrc_power_val:
245 ldr r11, omap3_sdrc_power
246 str r9, [r11] @ restore SDRC_POWER, no barrier needed
249 ldr r11, omap3_sdrc_dlla_status
251 and r12, r12, #LOCKSTATUS_MASK
252 cmp r12, #LOCKSTATUS_MASK
256 ldr r11, omap3_sdrc_dlla_status
258 and r12, r12, #LOCKSTATUS_MASK
263 ldr r12, omap_sdrc_rfr_ctrl_0_val @ fetch value from SRAM
264 ldr r11, omap3_sdrc_rfr_ctrl_0 @ fetch addr from SRAM
265 str r12, [r11] @ store
266 #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
267 ldr r12, omap_sdrc_actim_ctrl_a_0_val
268 ldr r11, omap3_sdrc_actim_ctrl_a_0
270 ldr r12, omap_sdrc_actim_ctrl_b_0_val
271 ldr r11, omap3_sdrc_actim_ctrl_b_0
273 ldr r12, omap_sdrc_mr_0_val
274 ldr r11, omap3_sdrc_mr_0
277 ldr r12, omap_sdrc_rfr_ctrl_1_val
278 cmp r12, #0 @ if SDRC_RFR_CTRL_1 is 0,
279 beq skip_cs1_prog @ do not program cs1 params
280 ldr r11, omap3_sdrc_rfr_ctrl_1
282 #ifdef CONFIG_OMAP3_SDRC_AC_TIMING
283 ldr r12, omap_sdrc_actim_ctrl_a_1_val
284 ldr r11, omap3_sdrc_actim_ctrl_a_1
286 ldr r12, omap_sdrc_actim_ctrl_b_1_val
287 ldr r11, omap3_sdrc_actim_ctrl_b_1
289 ldr r12, omap_sdrc_mr_1_val
290 ldr r11, omap3_sdrc_mr_1
294 ldr r12, [r11] @ posted-write barrier for SDRC
299 .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
300 omap3_cm_clksel1_pll:
301 .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
302 omap3_cm_idlest1_core:
303 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
304 omap3_cm_iclken1_core:
305 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
307 omap3_sdrc_rfr_ctrl_0:
308 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
309 omap3_sdrc_rfr_ctrl_1:
310 .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_1)
311 omap3_sdrc_actim_ctrl_a_0:
312 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
313 omap3_sdrc_actim_ctrl_a_1:
314 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_1)
315 omap3_sdrc_actim_ctrl_b_0:
316 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
317 omap3_sdrc_actim_ctrl_b_1:
318 .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_1)
320 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
322 .word OMAP34XX_SDRC_REGADDR(SDRC_MR_1)
323 omap_sdrc_rfr_ctrl_0_val:
325 omap_sdrc_rfr_ctrl_1_val:
327 omap_sdrc_actim_ctrl_a_0_val:
329 omap_sdrc_actim_ctrl_a_1_val:
331 omap_sdrc_actim_ctrl_b_0_val:
333 omap_sdrc_actim_ctrl_b_1_val:
340 omap3_sdrc_dlla_status:
341 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
342 omap3_sdrc_dlla_ctrl:
343 .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
346 ENDPROC(omap3_sram_configure_core_dpll)
348 ENTRY(omap3_sram_configure_core_dpll_sz)
349 .word . - omap3_sram_configure_core_dpll