4 * Karthik Dasu <karthik-dp@ti.com>
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <linux/linkage.h>
26 #include <asm/assembler.h>
27 #include <plat/sram.h>
30 #include "cm2xxx_3xxx.h"
31 #include "prm2xxx_3xxx.h"
36 * Registers access definitions
38 #define SDRC_SCRATCHPAD_SEM_OFFS 0xc
39 #define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
40 (SDRC_SCRATCHPAD_SEM_OFFS)
41 #define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
43 #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
44 #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
45 #define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
46 #define SRAM_BASE_P OMAP3_SRAM_PA
47 #define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
48 #define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
49 OMAP36XX_CONTROL_MEM_RTA_CTRL)
51 /* Move this as correct place is available */
52 #define SCRATCHPAD_MEM_OFFS 0x310
53 #define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
54 OMAP343X_CONTROL_MEM_WKUP +\
56 #define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
57 #define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
58 #define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
59 #define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
60 #define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
61 #define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
62 #define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
63 #define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
64 #define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
65 #define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
68 * This file needs be built unconditionally as ARM to interoperate correctly
69 * with non-Thumb-2-capable firmware.
78 * The "get_*restore_pointer" functions are used to provide a
79 * physical restore address where the ROM code jumps while waking
80 * up from MPU OFF/OSWR state.
81 * The restore pointer is stored into the scratchpad.
85 /* Function call to get the restore pointer for resume from OFF */
86 ENTRY(get_restore_pointer)
87 stmfd sp!, {lr} @ save registers on stack
89 ldmfd sp!, {pc} @ restore regs and return
90 ENDPROC(get_restore_pointer)
92 ENTRY(get_restore_pointer_sz)
93 .word . - get_restore_pointer
96 /* Function call to get the restore pointer for 3630 resume from OFF */
97 ENTRY(get_omap3630_restore_pointer)
98 stmfd sp!, {lr} @ save registers on stack
100 ldmfd sp!, {pc} @ restore regs and return
101 ENDPROC(get_omap3630_restore_pointer)
103 ENTRY(get_omap3630_restore_pointer_sz)
104 .word . - get_omap3630_restore_pointer
107 /* Function call to get the restore pointer for ES3 to resume from OFF */
108 ENTRY(get_es3_restore_pointer)
109 stmfd sp!, {lr} @ save registers on stack
111 ldmfd sp!, {pc} @ restore regs and return
112 ENDPROC(get_es3_restore_pointer)
114 ENTRY(get_es3_restore_pointer_sz)
115 .word . - get_es3_restore_pointer
119 * L2 cache needs to be toggled for stable OFF mode functionality on 3630.
120 * This function sets up a flag that will allow for this toggling to take
121 * place on 3630. Hopefully some version in the future may not need this.
123 ENTRY(enable_omap3630_toggle_l2_on_restore)
124 stmfd sp!, {lr} @ save registers on stack
125 /* Setup so that we will disable and enable l2 */
127 adrl r2, l2dis_3630 @ may be too distant for plain adr
129 ldmfd sp!, {pc} @ restore regs and return
130 ENDPROC(enable_omap3630_toggle_l2_on_restore)
133 /* Function to call rom code to save secure ram context */
134 ENTRY(save_secure_ram_context)
135 stmfd sp!, {r1-r12, lr} @ save registers on stack
136 adr r3, api_params @ r3 points to parameters
137 str r0, [r3,#0x4] @ r0 has sdram address
140 ldr r12, sram_phy_addr_mask
142 mov r0, #25 @ set service ID for PPA
143 mov r12, r0 @ copy secure service ID in r12
144 mov r1, #0 @ set task id for ROM code in r1
145 mov r2, #4 @ set some flags in r2, r6
147 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
148 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
149 smc #1 @ call SMI monitor (smi #1)
154 ldmfd sp!, {r1-r12, pc}
161 .word 0x4, 0x0, 0x0, 0x1, 0x1
162 ENDPROC(save_secure_ram_context)
163 ENTRY(save_secure_ram_context_sz)
164 .word . - save_secure_ram_context
167 * ======================
168 * == Idle entry point ==
169 * ======================
173 * Forces OMAP into idle state
175 * omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
176 * and executes the WFI instruction. Calling WFI effectively changes the
177 * power domains states to the desired target power states.
181 * - this code gets copied to internal SRAM at boot and after wake-up
182 * from OFF mode. The execution pointer in SRAM is _omap_sram_idle.
183 * - when the OMAP wakes up it continues at different execution points
184 * depending on the low power mode (non-OFF vs OFF modes),
185 * cf. 'Resume path for xxx mode' comments.
187 ENTRY(omap34xx_cpu_suspend)
188 stmfd sp!, {r0-r12, lr} @ save registers on stack
191 * r0 contains restore pointer in sdram
192 * r1 contains information about saving context:
193 * 0 - No context lost
194 * 1 - Only L1 and logic lost
196 * 3 - Both L1 and L2 lost
199 /* Directly jump to WFI is the context save is not required */
203 /* Otherwise fall through to the save context code */
205 mov r8, r0 @ Store SDRAM address in r8
206 mrc p15, 0, r5, c1, c0, 1 @ Read Auxiliary Control Register
207 mov r4, #0x1 @ Number of parameters for restore call
208 stmia r8!, {r4-r5} @ Push parameters for restore call
209 mrc p15, 1, r5, c9, c0, 2 @ Read L2 AUX ctrl register
210 stmia r8!, {r4-r5} @ Push parameters for restore call
212 /* Check what that target sleep state is from r1 */
213 cmp r1, #0x2 @ Only L2 lost, no need to save context
217 /* Store sp and spsr to SDRAM */
222 /* Save all ARM registers */
223 /* Coprocessor access control register */
224 mrc p15, 0, r6, c1, c0, 2
226 /* TTBR0, TTBR1 and Translation table base control */
227 mrc p15, 0, r4, c2, c0, 0
228 mrc p15, 0, r5, c2, c0, 1
229 mrc p15, 0, r6, c2, c0, 2
232 * Domain access control register, data fault status register,
233 * and instruction fault status register
235 mrc p15, 0, r4, c3, c0, 0
236 mrc p15, 0, r5, c5, c0, 0
237 mrc p15, 0, r6, c5, c0, 1
240 * Data aux fault status register, instruction aux fault status,
241 * data fault address register and instruction fault address register
243 mrc p15, 0, r4, c5, c1, 0
244 mrc p15, 0, r5, c5, c1, 1
245 mrc p15, 0, r6, c6, c0, 0
246 mrc p15, 0, r7, c6, c0, 2
249 * user r/w thread and process ID, user r/o thread and process ID,
250 * priv only thread and process ID, cache size selection
252 mrc p15, 0, r4, c13, c0, 2
253 mrc p15, 0, r5, c13, c0, 3
254 mrc p15, 0, r6, c13, c0, 4
255 mrc p15, 2, r7, c0, c0, 0
257 /* Data TLB lockdown, instruction TLB lockdown registers */
258 mrc p15, 0, r5, c10, c0, 0
259 mrc p15, 0, r6, c10, c0, 1
261 /* Secure or non secure vector base address, FCSE PID, Context PID*/
262 mrc p15, 0, r4, c12, c0, 0
263 mrc p15, 0, r5, c13, c0, 0
264 mrc p15, 0, r6, c13, c0, 1
266 /* Primary remap, normal remap registers */
267 mrc p15, 0, r4, c10, c2, 0
268 mrc p15, 0, r5, c10, c2, 1
271 /* Store current cpsr*/
275 mrc p15, 0, r4, c1, c0, 0
276 /* save control register */
281 * Clean Data or unified cache to POU
282 * How to invalidate only L1 cache???? - #FIX_ME#
283 * mcr p15, 0, r11, c7, c11, 1
285 cmp r1, #0x1 @ Check whether L2 inval is required
290 * jump out to kernel flush routine
291 * - reuse that code is better
292 * - it executes in a cached space so is faster than refetch per-block
293 * - should be faster and will change with kernel
294 * - 'might' have to copy address, load and jump to it
299 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
300 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
301 * This sequence switches back to ARM. Note that .align may insert a
302 * nop: bx pc needs to be word-aligned in order to work.
311 ldr r4, sdrc_power @ read the SDRC_POWER register
312 ldr r5, [r4] @ read the contents of SDRC_POWER
313 orr r5, r5, #0x40 @ enable self refresh on idle req
314 str r5, [r4] @ write back to SDRC_POWER register
316 /* Data memory barrier and Data sync barrier */
318 mcr p15, 0, r1, c7, c10, 4
319 mcr p15, 0, r1, c7, c10, 5
322 * ===================================
323 * == WFI instruction => Enter idle ==
324 * ===================================
326 wfi @ wait for interrupt
329 * ===================================
330 * == Resume path for non-OFF modes ==
331 * ===================================
346 * ===================================
347 * == Exit point from non-OFF modes ==
348 * ===================================
350 ldmfd sp!, {r0-r12, pc} @ restore regs and return
354 * ==============================
355 * == Resume path for OFF mode ==
356 * ==============================
360 * The restore_* functions are called by the ROM code
361 * when back from WFI in OFF mode.
362 * Cf. the get_*restore_pointer functions.
364 * restore_es3: applies to 34xx >= ES3.0
365 * restore_3630: applies to 36xx
366 * restore: common code for 3xxx
369 ldr r5, pm_prepwstst_core_p
372 cmp r4, #0x0 @ Check if previous power state of CORE is OFF
376 ldr r2, es3_sdrc_fix_sz
379 ldmia r0!, {r3} @ val = *src
380 stmia r1!, {r3} @ *dst = val
381 subs r2, r2, #0x1 @ num_words--
388 ldr r1, pm_prepwstst_core_p
391 cmp r2, #0x0 @ Check if previous power state of CORE is OFF
393 /* Disable RTA before giving control */
394 ldr r1, control_mem_rta
395 mov r2, #OMAP36XX_RTA_DISABLE
398 /* Fall through to common code for the remaining logic */
402 * Check what was the reason for mpu reset and store the reason in r9:
403 * 0 - No context lost
404 * 1 - Only L1 and logic lost
405 * 2 - Only L2 lost - In this case, we wont be here
406 * 3 - Both L1 and L2 lost
408 ldr r1, pm_pwstctrl_mpu
411 cmp r2, #0x0 @ Check if target power state was OFF or RET
412 moveq r9, #0x3 @ MPU OFF => L1 and L2 lost
413 movne r9, #0x1 @ Only L1 and L2 lost => avoid L2 invalidation
417 cmp r0, #0x1 @ should we disable L2 on 3630?
419 mrc p15, 0, r0, c1, c0, 1
420 bic r0, r0, #2 @ disable L2 cache
421 mcr p15, 0, r0, c1, c0, 1
428 mov r0, #40 @ set service ID for PPA
429 mov r12, r0 @ copy secure Service ID in r12
430 mov r1, #0 @ set task id for ROM code in r1
431 mov r2, #4 @ set some flags in r2, r6
433 adr r3, l2_inv_api_params @ r3 points to dummy parameters
434 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
435 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
436 smc #1 @ call SMI monitor (smi #1)
437 /* Write to Aux control register to set some bits */
438 mov r0, #42 @ set service ID for PPA
439 mov r12, r0 @ copy secure Service ID in r12
440 mov r1, #0 @ set task id for ROM code in r1
441 mov r2, #4 @ set some flags in r2, r6
443 ldr r4, scratchpad_base
444 ldr r3, [r4, #0xBC] @ r3 points to parameters
445 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
446 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
447 smc #1 @ call SMI monitor (smi #1)
449 #ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
450 /* Restore L2 aux control register */
451 @ set service ID for PPA
452 mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
453 mov r12, r0 @ copy service ID in r12
454 mov r1, #0 @ set task ID for ROM code in r1
455 mov r2, #4 @ set some flags in r2, r6
457 ldr r4, scratchpad_base
459 adds r3, r3, #8 @ r3 points to parameters
460 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
461 mcr p15, 0, r0, c7, c10, 5 @ data memory barrier
462 smc #1 @ call SMI monitor (smi #1)
470 /* Execute smi to invalidate L2 cache */
471 mov r12, #0x1 @ set up to invalidate L2
472 smc #0 @ Call SMI monitor (smieq)
473 /* Write to Aux control register to set some bits */
474 ldr r4, scratchpad_base
478 smc #0 @ Call SMI monitor (smieq)
479 ldr r4, scratchpad_base
483 smc #0 @ Call SMI monitor (smieq)
486 cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
488 mrc p15, 0, r1, c1, c0, 1
489 orr r1, r1, #2 @ re-enable L2 cache
490 mcr p15, 0, r1, c1, c0, 1
494 * Invalidate all instruction caches to PoU
495 * and flush branch target cache
497 mcr p15, 0, r1, c7, c5, 0
499 ldr r4, scratchpad_base
508 /* Coprocessor access Control Register */
509 mcr p15, 0, r4, c1, c0, 2
512 MCR p15, 0, r5, c2, c0, 0
514 MCR p15, 0, r6, c2, c0, 1
515 /* Translation table base control register */
516 MCR p15, 0, r7, c2, c0, 2
517 /* Domain access Control Register */
518 MCR p15, 0, r8, c3, c0, 0
519 /* Data fault status Register */
520 MCR p15, 0, r9, c5, c0, 0
523 /* Instruction fault status Register */
524 MCR p15, 0, r4, c5, c0, 1
525 /* Data Auxiliary Fault Status Register */
526 MCR p15, 0, r5, c5, c1, 0
527 /* Instruction Auxiliary Fault Status Register*/
528 MCR p15, 0, r6, c5, c1, 1
529 /* Data Fault Address Register */
530 MCR p15, 0, r7, c6, c0, 0
531 /* Instruction Fault Address Register*/
532 MCR p15, 0, r8, c6, c0, 2
535 /* User r/w thread and process ID */
536 MCR p15, 0, r4, c13, c0, 2
537 /* User ro thread and process ID */
538 MCR p15, 0, r5, c13, c0, 3
539 /* Privileged only thread and process ID */
540 MCR p15, 0, r6, c13, c0, 4
541 /* Cache size selection */
542 MCR p15, 2, r7, c0, c0, 0
544 /* Data TLB lockdown registers */
545 MCR p15, 0, r4, c10, c0, 0
546 /* Instruction TLB lockdown registers */
547 MCR p15, 0, r5, c10, c0, 1
548 /* Secure or Nonsecure Vector Base Address */
549 MCR p15, 0, r6, c12, c0, 0
551 MCR p15, 0, r7, c13, c0, 0
553 MCR p15, 0, r8, c13, c0, 1
556 /* Primary memory remap register */
557 MCR p15, 0, r4, c10, c2, 0
558 /* Normal memory remap register */
559 MCR p15, 0, r5, c10, c2, 1
562 ldmia r3!,{r4} @ load CPSR from SDRAM
563 msr cpsr, r4 @ store cpsr
565 /* Enabling MMU here */
566 mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
567 /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
573 * More work needs to be done to support N[0:2] value other than 0
574 * So looping here so that the error can be detected
578 mrc p15, 0, r2, c2, c0, 0
582 ldr r5, table_index_mask
583 and r4, r5 @ r4 = 31 to 20 bits of pc
584 /* Extract the value to be written to table entry */
586 /* r1 has the value to be written to table entry*/
588 /* Getting the address of table entry to modify */
590 /* r2 has the location which needs to be modified */
592 /* Storing previous entry of location being modified */
593 ldr r5, scratchpad_base
596 /* Modify the table entry */
599 * Storing address of entry being modified
600 * - will be restored after enabling MMU
602 ldr r5, scratchpad_base
606 mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
607 mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
608 mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
609 mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
611 * Restore control register. This enables the MMU.
612 * The caches and prediction are not enabled here, they
613 * will be enabled after restoring the MMU table entry.
616 /* Store previous value of control register in scratchpad */
618 ldr r2, cache_pred_disable_mask
620 mcr p15, 0, r4, c1, c0, 0
623 * ==============================
624 * == Exit point from OFF mode ==
625 * ==============================
627 ldmfd sp!, {r0-r12, pc} @ restore regs and return
634 /* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0 */
638 ldr r4, sdrc_syscfg @ get config addr
639 ldr r5, [r4] @ get value
640 tst r5, #0x100 @ is part access blocked
642 biceq r5, r5, #0x100 @ clear bit if set
643 str r5, [r4] @ write back change
644 ldr r4, sdrc_mr_0 @ get config addr
645 ldr r5, [r4] @ get value
646 str r5, [r4] @ write back change
647 ldr r4, sdrc_emr2_0 @ get config addr
648 ldr r5, [r4] @ get value
649 str r5, [r4] @ write back change
650 ldr r4, sdrc_manual_0 @ get config addr
651 mov r5, #0x2 @ autorefresh command
652 str r5, [r4] @ kick off refreshes
653 ldr r4, sdrc_mr_1 @ get config addr
654 ldr r5, [r4] @ get value
655 str r5, [r4] @ write back change
656 ldr r4, sdrc_emr2_1 @ get config addr
657 ldr r5, [r4] @ get value
658 str r5, [r4] @ write back change
659 ldr r4, sdrc_manual_1 @ get config addr
660 mov r5, #0x2 @ autorefresh command
661 str r5, [r4] @ kick off refreshes
666 .word SDRC_SYSCONFIG_P
672 .word SDRC_MANUAL_0_P
678 .word SDRC_MANUAL_1_P
679 ENDPROC(es3_sdrc_fix)
680 ENTRY(es3_sdrc_fix_sz)
681 .word . - es3_sdrc_fix
684 * This function implements the erratum ID i581 WA:
685 * SDRC state restore before accessing the SDRAM
687 * Only used at return from non-OFF mode. For OFF
688 * mode the ROM code configures the SDRC and
689 * the DPLL before calling the restore code directly
693 /* Make sure SDRC accesses are ok */
696 /* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
697 ldr r4, cm_idlest_ckgen
703 ldr r4, cm_idlest1_core
708 /* allow DLL powerdown upon hw idle req */
715 * PC-relative stores lead to undefined behaviour in Thumb-2: use a r7 as a
717 * Be careful not to clobber r7 when maintaing this code.
721 /* Is dll in lock mode? */
722 ldr r4, sdrc_dlla_ctrl
725 bxne lr @ Return if locked
726 /* wait till dll locks */
729 ldr r4, wait_dll_lock_counter
731 str r4, [r7, #wait_dll_lock_counter - kick_counter]
732 ldr r4, sdrc_dlla_status
733 /* Wait 20uS for lock */
742 bx lr @ Return when locked
744 /* disable/reenable DLL if not locked */
746 ldr r4, sdrc_dlla_ctrl
749 bic r6, #(1<<3) @ disable dll
752 orr r6, r6, #(1<<3) @ enable dll
757 str r4, [r7] @ kick_counter
758 b wait_dll_lock_timed
762 .word CM_IDLEST1_CORE_V
764 .word CM_IDLEST_CKGEN_V
766 .word SDRC_DLLA_STATUS_V
768 .word SDRC_DLLA_CTRL_V
770 .word PM_PREPWSTST_CORE_P
772 .word PM_PWSTCTRL_MPU_P
774 .word SCRATCHPAD_BASE_P
776 .word SRAM_BASE_P + 0x8000
785 cache_pred_disable_mask:
790 .word CONTROL_MEM_RTA_CTRL
792 .word v7_flush_dcache_all
796 * When exporting to userspace while the counters are in SRAM,
797 * these 2 words need to be at the end to facilitate retrival!
801 wait_dll_lock_counter:
803 ENDPROC(omap34xx_cpu_suspend)
805 ENTRY(omap34xx_cpu_suspend_sz)
806 .word . - omap34xx_cpu_suspend