2 * arch/arm/mach-omap2/serial.c
4 * OMAP2 serial support.
6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * Major rework for PM support by Kevin Hilman
11 * Based off of arch/arm/mach-omap/omap1/serial.c
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/serial_8250.h>
23 #include <linux/serial_reg.h>
24 #include <linux/clk.h>
27 #include <mach/common.h>
28 #include <mach/board.h>
29 #include <mach/clock.h>
30 #include <mach/control.h>
34 #include "prm-regbits-34xx.h"
36 #define UART_OMAP_WER 0x17 /* Wake-up enable register */
38 #define DEFAULT_TIMEOUT (5 * HZ)
40 struct omap_uart_state {
43 struct timer_list timer;
55 struct plat_serial8250_port *p;
56 struct list_head node;
57 struct platform_device pdev;
59 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
62 /* Registers to be saved/restored for OFF-mode */
72 static LIST_HEAD(uart_list);
74 static struct plat_serial8250_port serial_platform_data0[] = {
76 .membase = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
77 .mapbase = OMAP_UART1_BASE,
79 .flags = UPF_BOOT_AUTOCONF,
82 .uartclk = OMAP24XX_BASE_BAUD * 16,
88 static struct plat_serial8250_port serial_platform_data1[] = {
90 .membase = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
91 .mapbase = OMAP_UART2_BASE,
93 .flags = UPF_BOOT_AUTOCONF,
96 .uartclk = OMAP24XX_BASE_BAUD * 16,
102 static struct plat_serial8250_port serial_platform_data2[] = {
104 .membase = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
105 .mapbase = OMAP_UART3_BASE,
107 .flags = UPF_BOOT_AUTOCONF,
110 .uartclk = OMAP24XX_BASE_BAUD * 16,
116 #ifdef CONFIG_ARCH_OMAP4
117 static struct plat_serial8250_port serial_platform_data3[] = {
119 .membase = IO_ADDRESS(OMAP_UART4_BASE),
120 .mapbase = OMAP_UART4_BASE,
122 .flags = UPF_BOOT_AUTOCONF,
125 .uartclk = OMAP24XX_BASE_BAUD * 16,
131 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
134 offset <<= up->regshift;
135 return (unsigned int)__raw_readb(up->membase + offset);
138 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
141 offset <<= p->regshift;
142 __raw_writeb(value, p->membase + offset);
146 * Internal UARTs need to be initialized for the 8250 autoconfig to work
147 * properly. Note that the TX watermark initialization may not be needed
148 * once the 8250.c watermark handling code is merged.
150 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
152 struct plat_serial8250_port *p = uart->p;
154 serial_write_reg(p, UART_OMAP_MDR1, 0x07);
155 serial_write_reg(p, UART_OMAP_SCR, 0x08);
156 serial_write_reg(p, UART_OMAP_MDR1, 0x00);
157 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
160 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
162 static int enable_off_mode; /* to be removed by full off-mode patches */
164 static void omap_uart_save_context(struct omap_uart_state *uart)
167 struct plat_serial8250_port *p = uart->p;
169 if (!enable_off_mode)
172 lcr = serial_read_reg(p, UART_LCR);
173 serial_write_reg(p, UART_LCR, 0xBF);
174 uart->dll = serial_read_reg(p, UART_DLL);
175 uart->dlh = serial_read_reg(p, UART_DLM);
176 serial_write_reg(p, UART_LCR, lcr);
177 uart->ier = serial_read_reg(p, UART_IER);
178 uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
179 uart->scr = serial_read_reg(p, UART_OMAP_SCR);
180 uart->wer = serial_read_reg(p, UART_OMAP_WER);
182 uart->context_valid = 1;
185 static void omap_uart_restore_context(struct omap_uart_state *uart)
188 struct plat_serial8250_port *p = uart->p;
190 if (!enable_off_mode)
193 if (!uart->context_valid)
196 uart->context_valid = 0;
198 serial_write_reg(p, UART_OMAP_MDR1, 0x7);
199 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
200 efr = serial_read_reg(p, UART_EFR);
201 serial_write_reg(p, UART_EFR, UART_EFR_ECB);
202 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
203 serial_write_reg(p, UART_IER, 0x0);
204 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
205 serial_write_reg(p, UART_DLL, uart->dll);
206 serial_write_reg(p, UART_DLM, uart->dlh);
207 serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
208 serial_write_reg(p, UART_IER, uart->ier);
209 serial_write_reg(p, UART_FCR, 0xA1);
210 serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
211 serial_write_reg(p, UART_EFR, efr);
212 serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
213 serial_write_reg(p, UART_OMAP_SCR, uart->scr);
214 serial_write_reg(p, UART_OMAP_WER, uart->wer);
215 serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
216 serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
219 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
220 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
221 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
223 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
228 clk_enable(uart->ick);
229 clk_enable(uart->fck);
231 omap_uart_restore_context(uart);
236 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
241 omap_uart_save_context(uart);
243 clk_disable(uart->ick);
244 clk_disable(uart->fck);
247 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
249 /* Set wake-enable bit */
250 if (uart->wk_en && uart->wk_mask) {
251 u32 v = __raw_readl(uart->wk_en);
253 __raw_writel(v, uart->wk_en);
256 /* Ensure IOPAD wake-enables are set */
257 if (cpu_is_omap34xx() && uart->padconf) {
258 u16 v = omap_ctrl_readw(uart->padconf);
259 v |= OMAP3_PADCONF_WAKEUPENABLE0;
260 omap_ctrl_writew(v, uart->padconf);
264 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
266 /* Clear wake-enable bit */
267 if (uart->wk_en && uart->wk_mask) {
268 u32 v = __raw_readl(uart->wk_en);
270 __raw_writel(v, uart->wk_en);
273 /* Ensure IOPAD wake-enables are cleared */
274 if (cpu_is_omap34xx() && uart->padconf) {
275 u16 v = omap_ctrl_readw(uart->padconf);
276 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
277 omap_ctrl_writew(v, uart->padconf);
281 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
284 struct plat_serial8250_port *p = uart->p;
287 sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
293 serial_write_reg(p, UART_OMAP_SYSC, sysc);
296 static void omap_uart_block_sleep(struct omap_uart_state *uart)
298 omap_uart_enable_clocks(uart);
300 omap_uart_smart_idle_enable(uart, 0);
303 mod_timer(&uart->timer, jiffies + uart->timeout);
305 del_timer(&uart->timer);
308 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
310 if (device_may_wakeup(&uart->pdev.dev))
311 omap_uart_enable_wakeup(uart);
313 omap_uart_disable_wakeup(uart);
318 omap_uart_smart_idle_enable(uart, 1);
320 del_timer(&uart->timer);
323 static void omap_uart_idle_timer(unsigned long data)
325 struct omap_uart_state *uart = (struct omap_uart_state *)data;
327 omap_uart_allow_sleep(uart);
330 void omap_uart_prepare_idle(int num)
332 struct omap_uart_state *uart;
334 list_for_each_entry(uart, &uart_list, node) {
335 if (num == uart->num && uart->can_sleep) {
336 omap_uart_disable_clocks(uart);
342 void omap_uart_resume_idle(int num)
344 struct omap_uart_state *uart;
346 list_for_each_entry(uart, &uart_list, node) {
347 if (num == uart->num) {
348 omap_uart_enable_clocks(uart);
350 /* Check for IO pad wakeup */
351 if (cpu_is_omap34xx() && uart->padconf) {
352 u16 p = omap_ctrl_readw(uart->padconf);
354 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
355 omap_uart_block_sleep(uart);
358 /* Check for normal UART wakeup */
359 if (__raw_readl(uart->wk_st) & uart->wk_mask)
360 omap_uart_block_sleep(uart);
366 void omap_uart_prepare_suspend(void)
368 struct omap_uart_state *uart;
370 list_for_each_entry(uart, &uart_list, node) {
371 omap_uart_allow_sleep(uart);
375 int omap_uart_can_sleep(void)
377 struct omap_uart_state *uart;
380 list_for_each_entry(uart, &uart_list, node) {
384 if (!uart->can_sleep) {
389 /* This UART can now safely sleep. */
390 omap_uart_allow_sleep(uart);
397 * omap_uart_interrupt()
399 * This handler is used only to detect that *any* UART interrupt has
400 * occurred. It does _nothing_ to handle the interrupt. Rather,
401 * any UART interrupt will trigger the inactivity timer so the
402 * UART will not idle or sleep for its timeout period.
405 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
407 struct omap_uart_state *uart = dev_id;
409 omap_uart_block_sleep(uart);
414 static void omap_uart_idle_init(struct omap_uart_state *uart)
416 struct plat_serial8250_port *p = uart->p;
420 uart->timeout = DEFAULT_TIMEOUT;
421 setup_timer(&uart->timer, omap_uart_idle_timer,
422 (unsigned long) uart);
423 mod_timer(&uart->timer, jiffies + uart->timeout);
424 omap_uart_smart_idle_enable(uart, 0);
426 if (cpu_is_omap34xx()) {
427 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
431 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
432 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
435 wk_mask = OMAP3430_ST_UART1_MASK;
439 wk_mask = OMAP3430_ST_UART2_MASK;
443 wk_mask = OMAP3430_ST_UART3_MASK;
447 uart->wk_mask = wk_mask;
448 uart->padconf = padconf;
449 } else if (cpu_is_omap24xx()) {
452 if (cpu_is_omap2430()) {
453 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
454 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
455 } else if (cpu_is_omap2420()) {
456 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
457 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
461 wk_mask = OMAP24XX_ST_UART1_MASK;
464 wk_mask = OMAP24XX_ST_UART2_MASK;
467 wk_mask = OMAP24XX_ST_UART3_MASK;
470 uart->wk_mask = wk_mask;
478 p->irqflags |= IRQF_SHARED;
479 ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
480 "serial idle", (void *)uart);
484 void omap_uart_enable_irqs(int enable)
487 struct omap_uart_state *uart;
489 list_for_each_entry(uart, &uart_list, node) {
491 ret = request_irq(uart->p->irq, omap_uart_interrupt,
492 IRQF_SHARED, "serial idle", (void *)uart);
494 free_irq(uart->p->irq, (void *)uart);
498 static ssize_t sleep_timeout_show(struct device *dev,
499 struct device_attribute *attr,
502 struct platform_device *pdev = container_of(dev,
503 struct platform_device, dev);
504 struct omap_uart_state *uart = container_of(pdev,
505 struct omap_uart_state, pdev);
507 return sprintf(buf, "%u\n", uart->timeout / HZ);
510 static ssize_t sleep_timeout_store(struct device *dev,
511 struct device_attribute *attr,
512 const char *buf, size_t n)
514 struct platform_device *pdev = container_of(dev,
515 struct platform_device, dev);
516 struct omap_uart_state *uart = container_of(pdev,
517 struct omap_uart_state, pdev);
520 if (sscanf(buf, "%u", &value) != 1) {
521 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
525 uart->timeout = value * HZ;
527 mod_timer(&uart->timer, jiffies + uart->timeout);
529 /* A zero value means disable timeout feature */
530 omap_uart_block_sleep(uart);
535 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
536 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
538 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
539 #define DEV_CREATE_FILE(dev, attr)
540 #endif /* CONFIG_PM */
542 static struct omap_uart_state omap_uart[OMAP_MAX_NR_PORTS] = {
545 .name = "serial8250",
546 .id = PLAT8250_DEV_PLATFORM,
548 .platform_data = serial_platform_data0,
553 .name = "serial8250",
554 .id = PLAT8250_DEV_PLATFORM1,
556 .platform_data = serial_platform_data1,
561 .name = "serial8250",
562 .id = PLAT8250_DEV_PLATFORM2,
564 .platform_data = serial_platform_data2,
568 #ifdef CONFIG_ARCH_OMAP4
571 .name = "serial8250",
574 .platform_data = serial_platform_data3,
581 void __init omap_serial_init(void)
587 * Make sure the serial ports are muxed on at this point.
588 * You have to mux them off in device drivers later on
592 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
593 struct omap_uart_state *uart = &omap_uart[i];
594 struct platform_device *pdev = &uart->pdev;
595 struct device *dev = &pdev->dev;
596 struct plat_serial8250_port *p = dev->platform_data;
598 sprintf(name, "uart%d_ick", i+1);
599 uart->ick = clk_get(NULL, name);
600 if (IS_ERR(uart->ick)) {
601 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
605 sprintf(name, "uart%d_fck", i+1);
606 uart->fck = clk_get(NULL, name);
607 if (IS_ERR(uart->fck)) {
608 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
612 if (!uart->ick || !uart->fck)
616 p->private_data = uart;
618 list_add_tail(&uart->node, &uart_list);
620 if (cpu_is_omap44xx())
623 omap_uart_enable_clocks(uart);
624 omap_uart_reset(uart);
625 omap_uart_idle_init(uart);
627 if (WARN_ON(platform_device_register(pdev)))
629 if ((cpu_is_omap34xx() && uart->padconf) ||
630 (uart->wk_en && uart->wk_mask)) {
631 device_init_wakeup(dev, true);
632 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);