arch/arm/mach-omap2/prcm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/prcm.c
   3  *
   4  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  *
   8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
   9  *
  10  * Copyright (C) 2007 Texas Instruments, Inc.
  11  * Rajendra Nayak <rnayak@ti.com>
  12  *
  13  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
  14  * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/delay.h>
  25
  26 #include <plat/common.h>
  27 #include <plat/prcm.h>
  28 #include <plat/irqs.h>
  29
  30 #include "clock.h"
  31 #include "clock2xxx.h"
  32 #include "cm2xxx_3xxx.h"
  33 #include "cm44xx.h"
  34 #include "prm2xxx_3xxx.h"
  35 #include "prm44xx.h"
  36 #include "prm-regbits-24xx.h"
  37 #include "prm-regbits-44xx.h"
  38 #include "control.h"
  39
  40 void __iomem *prm_base;
  41 void __iomem *cm_base;
  42 void __iomem *cm2_base;
  43
  44 #define MAX_MODULE_ENABLE_WAIT          100000
  45
  46 struct omap3_prcm_regs {
  47         u32 iva2_cm_clksel1;
  48         u32 iva2_cm_clksel2;
  49         u32 cm_sysconfig;
  50         u32 sgx_cm_clksel;
  51         u32 dss_cm_clksel;
  52         u32 cam_cm_clksel;
  53         u32 per_cm_clksel;
  54         u32 emu_cm_clksel;
  55         u32 emu_cm_clkstctrl;
  56         u32 pll_cm_autoidle2;
  57         u32 pll_cm_clksel4;
  58         u32 pll_cm_clksel5;
  59         u32 pll_cm_clken2;
  60         u32 cm_polctrl;
  61         u32 iva2_cm_fclken;
  62         u32 iva2_cm_clken_pll;
  63         u32 core_cm_fclken1;
  64         u32 core_cm_fclken3;
  65         u32 sgx_cm_fclken;
  66         u32 wkup_cm_fclken;
  67         u32 dss_cm_fclken;
  68         u32 cam_cm_fclken;
  69         u32 per_cm_fclken;
  70         u32 usbhost_cm_fclken;
  71         u32 core_cm_iclken1;
  72         u32 core_cm_iclken2;
  73         u32 core_cm_iclken3;
  74         u32 sgx_cm_iclken;
  75         u32 wkup_cm_iclken;
  76         u32 dss_cm_iclken;
  77         u32 cam_cm_iclken;
  78         u32 per_cm_iclken;
  79         u32 usbhost_cm_iclken;
  80         u32 iva2_cm_autiidle2;
  81         u32 mpu_cm_autoidle2;
  82         u32 iva2_cm_clkstctrl;
  83         u32 mpu_cm_clkstctrl;
  84         u32 core_cm_clkstctrl;
  85         u32 sgx_cm_clkstctrl;
  86         u32 dss_cm_clkstctrl;
  87         u32 cam_cm_clkstctrl;
  88         u32 per_cm_clkstctrl;
  89         u32 neon_cm_clkstctrl;
  90         u32 usbhost_cm_clkstctrl;
  91         u32 core_cm_autoidle1;
  92         u32 core_cm_autoidle2;
  93         u32 core_cm_autoidle3;
  94         u32 wkup_cm_autoidle;
  95         u32 dss_cm_autoidle;
  96         u32 cam_cm_autoidle;
  97         u32 per_cm_autoidle;
  98         u32 usbhost_cm_autoidle;
  99         u32 sgx_cm_sleepdep;
 100         u32 dss_cm_sleepdep;
 101         u32 cam_cm_sleepdep;
 102         u32 per_cm_sleepdep;
 103         u32 usbhost_cm_sleepdep;
 104         u32 cm_clkout_ctrl;
 105         u32 prm_clkout_ctrl;
 106         u32 sgx_pm_wkdep;
 107         u32 dss_pm_wkdep;
 108         u32 cam_pm_wkdep;
 109         u32 per_pm_wkdep;
 110         u32 neon_pm_wkdep;
 111         u32 usbhost_pm_wkdep;
 112         u32 core_pm_mpugrpsel1;
 113         u32 iva2_pm_ivagrpsel1;
 114         u32 core_pm_mpugrpsel3;
 115         u32 core_pm_ivagrpsel3;
 116         u32 wkup_pm_mpugrpsel;
 117         u32 wkup_pm_ivagrpsel;
 118         u32 per_pm_mpugrpsel;
 119         u32 per_pm_ivagrpsel;
 120         u32 wkup_pm_wken;
 121 };
 122
 123 static struct omap3_prcm_regs prcm_context;
 124
 125 u32 omap_prcm_get_reset_sources(void)
 126 {
 127         /* XXX This presumably needs modification for 34XX */
 128         if (cpu_is_omap24xx() || cpu_is_omap34xx())
 129                 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
 130         if (cpu_is_omap44xx())
 131                 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
 132
 133         return 0;
 134 }
 135 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 136
 137 /* Resets clock rates and reboots the system. Only called from system.h */
 138 void omap_prcm_arch_reset(char mode, const char *cmd)
 139 {
 140         s16 prcm_offs = 0;
 141
 142         if (cpu_is_omap24xx()) {
 143                 omap2xxx_clk_prepare_for_reboot();
 144
 145                 prcm_offs = WKUP_MOD;
 146         } else if (cpu_is_omap34xx()) {
 147                 prcm_offs = OMAP3430_GR_MOD;
 148                 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 149         } else if (cpu_is_omap44xx())
 150                 prcm_offs = OMAP4430_PRM_DEVICE_INST;
 151         else
 152                 WARN_ON(1);
 153
 154         if (cpu_is_omap24xx() || cpu_is_omap34xx())
 155                 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
 156                                                  OMAP2_RM_RSTCTRL);
 157         if (cpu_is_omap44xx())
 158                 prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
 159                                      prcm_offs, OMAP4_RM_RSTCTRL);
 160 }
 161
 162 /* Read a PRM register, AND it, and shift the result down to bit 0 */
 163 u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
 164 {
 165         u32 v;
 166
 167         v = __raw_readl(reg);
 168         v &= mask;
 169         v >>= __ffs(mask);
 170
 171         return v;
 172 }
 173
 174 /* Read-modify-write a register in a PRM module. Caller must lock */
 175 u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
 176 {
 177         u32 v;
 178
 179         v = __raw_readl(reg);
 180         v &= ~mask;
 181         v |= bits;
 182         __raw_writel(v, reg);
 183
 184         return v;
 185 }
 186
 187 /**
 188  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
 189  * @reg: physical address of module IDLEST register
 190  * @mask: value to mask against to determine if the module is active
 191  * @idlest: idle state indicator (0 or 1) for the clock
 192  * @name: name of the clock (for printk)
 193  *
 194  * Returns 1 if the module indicated readiness in time, or 0 if it
 195  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
 196  *
 197  * XXX This function is deprecated.  It should be removed once the
 198  * hwmod conversion is complete.
 199  */
 200 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
 201                                 const char *name)
 202 {
 203         int i = 0;
 204         int ena = 0;
 205
 206         if (idlest)
 207                 ena = 0;
 208         else
 209                 ena = mask;
 210
 211         /* Wait for lock */
 212         omap_test_timeout(((__raw_readl(reg) & mask) == ena),
 213                           MAX_MODULE_ENABLE_WAIT, i);
 214
 215         if (i < MAX_MODULE_ENABLE_WAIT)
 216                 pr_debug("cm: Module associated with clock %s ready after %d "
 217                          "loops\n", name, i);
 218         else
 219                 pr_err("cm: Module associated with clock %s didn't enable in "
 220                        "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
 221
 222         return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 223 };
 224
 225 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 226 {
 227         /* Static mapping, never released */
 228         if (omap2_globals->prm) {
 229                 prm_base = ioremap(omap2_globals->prm, SZ_8K);
 230                 WARN_ON(!prm_base);
 231         }
 232         if (omap2_globals->cm) {
 233                 cm_base = ioremap(omap2_globals->cm, SZ_8K);
 234                 WARN_ON(!cm_base);
 235         }
 236         if (omap2_globals->cm2) {
 237                 cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
 238                 WARN_ON(!cm2_base);
 239         }
 240 }
 241
 242 #ifdef CONFIG_ARCH_OMAP3
 243 void omap3_prcm_save_context(void)
 244 {
 245         prcm_context.iva2_cm_clksel1 =
 246                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
 247         prcm_context.iva2_cm_clksel2 =
 248                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
 249         prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
 250         prcm_context.sgx_cm_clksel =
 251                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
 252         prcm_context.dss_cm_clksel =
 253                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
 254         prcm_context.cam_cm_clksel =
 255                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
 256         prcm_context.per_cm_clksel =
 257                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
 258         prcm_context.emu_cm_clksel =
 259                          cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
 260         prcm_context.emu_cm_clkstctrl =
 261                          cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
 262         prcm_context.pll_cm_autoidle2 =
 263                          cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
 264         prcm_context.pll_cm_clksel4 =
 265                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 266         prcm_context.pll_cm_clksel5 =
 267                          cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 268         prcm_context.pll_cm_clken2 =
 269                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 270         prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
 271         prcm_context.iva2_cm_fclken =
 272                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
 273         prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
 274                         OMAP3430_CM_CLKEN_PLL);
 275         prcm_context.core_cm_fclken1 =
 276                          cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 277         prcm_context.core_cm_fclken3 =
 278                          cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
 279         prcm_context.sgx_cm_fclken =
 280                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
 281         prcm_context.wkup_cm_fclken =
 282                          cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
 283         prcm_context.dss_cm_fclken =
 284                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
 285         prcm_context.cam_cm_fclken =
 286                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
 287         prcm_context.per_cm_fclken =
 288                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 289         prcm_context.usbhost_cm_fclken =
 290                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 291         prcm_context.core_cm_iclken1 =
 292                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
 293         prcm_context.core_cm_iclken2 =
 294                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
 295         prcm_context.core_cm_iclken3 =
 296                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
 297         prcm_context.sgx_cm_iclken =
 298                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
 299         prcm_context.wkup_cm_iclken =
 300                          cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
 301         prcm_context.dss_cm_iclken =
 302                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
 303         prcm_context.cam_cm_iclken =
 304                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
 305         prcm_context.per_cm_iclken =
 306                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 307         prcm_context.usbhost_cm_iclken =
 308                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 309         prcm_context.iva2_cm_autiidle2 =
 310                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 311         prcm_context.mpu_cm_autoidle2 =
 312                          cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
 313         prcm_context.iva2_cm_clkstctrl =
 314                          cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 315         prcm_context.mpu_cm_clkstctrl =
 316                          cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
 317         prcm_context.core_cm_clkstctrl =
 318                          cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
 319         prcm_context.sgx_cm_clkstctrl =
 320                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 321                                                 OMAP2_CM_CLKSTCTRL);
 322         prcm_context.dss_cm_clkstctrl =
 323                          cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
 324         prcm_context.cam_cm_clkstctrl =
 325                          cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
 326         prcm_context.per_cm_clkstctrl =
 327                          cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
 328         prcm_context.neon_cm_clkstctrl =
 329                          cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
 330         prcm_context.usbhost_cm_clkstctrl =
 331                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 332                                                 OMAP2_CM_CLKSTCTRL);
 333         prcm_context.core_cm_autoidle1 =
 334                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
 335         prcm_context.core_cm_autoidle2 =
 336                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
 337         prcm_context.core_cm_autoidle3 =
 338                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
 339         prcm_context.wkup_cm_autoidle =
 340                          cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
 341         prcm_context.dss_cm_autoidle =
 342                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
 343         prcm_context.cam_cm_autoidle =
 344                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
 345         prcm_context.per_cm_autoidle =
 346                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 347         prcm_context.usbhost_cm_autoidle =
 348                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 349         prcm_context.sgx_cm_sleepdep =
 350                  cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
 351         prcm_context.dss_cm_sleepdep =
 352                  cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
 353         prcm_context.cam_cm_sleepdep =
 354                  cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
 355         prcm_context.per_cm_sleepdep =
 356                  cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
 357         prcm_context.usbhost_cm_sleepdep =
 358                  cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 359         prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
 360                  OMAP3_CM_CLKOUT_CTRL_OFFSET);
 361         prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
 362                 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
 363         prcm_context.sgx_pm_wkdep =
 364                  prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
 365         prcm_context.dss_pm_wkdep =
 366                  prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
 367         prcm_context.cam_pm_wkdep =
 368                  prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
 369         prcm_context.per_pm_wkdep =
 370                  prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
 371         prcm_context.neon_pm_wkdep =
 372                  prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
 373         prcm_context.usbhost_pm_wkdep =
 374                  prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 375         prcm_context.core_pm_mpugrpsel1 =
 376                  prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
 377         prcm_context.iva2_pm_ivagrpsel1 =
 378                  prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
 379         prcm_context.core_pm_mpugrpsel3 =
 380                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
 381         prcm_context.core_pm_ivagrpsel3 =
 382                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 383         prcm_context.wkup_pm_mpugrpsel =
 384                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 385         prcm_context.wkup_pm_ivagrpsel =
 386                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 387         prcm_context.per_pm_mpugrpsel =
 388                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 389         prcm_context.per_pm_ivagrpsel =
 390                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 391         prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 392         return;
 393 }
 394
 395 void omap3_prcm_restore_context(void)
 396 {
 397         cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
 398                                          CM_CLKSEL1);
 399         cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
 400                                          CM_CLKSEL2);
 401         __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
 402         cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
 403                                          CM_CLKSEL);
 404         cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
 405                                          CM_CLKSEL);
 406         cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
 407                                          CM_CLKSEL);
 408         cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
 409                                          CM_CLKSEL);
 410         cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
 411                                          CM_CLKSEL1);
 412         cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
 413                                          OMAP2_CM_CLKSTCTRL);
 414         cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
 415                                          CM_AUTOIDLE2);
 416         cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
 417                                         OMAP3430ES2_CM_CLKSEL4);
 418         cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
 419                                          OMAP3430ES2_CM_CLKSEL5);
 420         cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
 421                                         OMAP3430ES2_CM_CLKEN2);
 422         __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
 423         cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
 424                                          CM_FCLKEN);
 425         cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
 426                                         OMAP3430_CM_CLKEN_PLL);
 427         cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
 428         cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
 429                                          OMAP3430ES2_CM_FCLKEN3);
 430         cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
 431                                          CM_FCLKEN);
 432         cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
 433         cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
 434                                          CM_FCLKEN);
 435         cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
 436                                          CM_FCLKEN);
 437         cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
 438                                          CM_FCLKEN);
 439         cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
 440                                          OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 441         cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
 442         cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
 443         cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
 444         cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
 445                                         CM_ICLKEN);
 446         cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
 447         cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
 448                                         CM_ICLKEN);
 449         cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
 450                                         CM_ICLKEN);
 451         cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
 452                                         CM_ICLKEN);
 453         cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
 454                                         OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 455         cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
 456                                         CM_AUTOIDLE2);
 457         cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
 458         cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
 459                                         OMAP2_CM_CLKSTCTRL);
 460         cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
 461                                         OMAP2_CM_CLKSTCTRL);
 462         cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
 463                                         OMAP2_CM_CLKSTCTRL);
 464         cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
 465                                         OMAP2_CM_CLKSTCTRL);
 466         cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
 467                                         OMAP2_CM_CLKSTCTRL);
 468         cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
 469                                         OMAP2_CM_CLKSTCTRL);
 470         cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
 471                                         OMAP2_CM_CLKSTCTRL);
 472         cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
 473                                         OMAP2_CM_CLKSTCTRL);
 474         cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
 475                                 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
 476         cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
 477                                         CM_AUTOIDLE1);
 478         cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
 479                                         CM_AUTOIDLE2);
 480         cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
 481                                         CM_AUTOIDLE3);
 482         cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
 483         cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
 484                                         CM_AUTOIDLE);
 485         cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
 486                                         CM_AUTOIDLE);
 487         cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
 488                                         CM_AUTOIDLE);
 489         cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
 490                                         OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 491         cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
 492                                         OMAP3430_CM_SLEEPDEP);
 493         cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
 494                                         OMAP3430_CM_SLEEPDEP);
 495         cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
 496                                         OMAP3430_CM_SLEEPDEP);
 497         cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
 498                                         OMAP3430_CM_SLEEPDEP);
 499         cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
 500                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 501         cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
 502                                         OMAP3_CM_CLKOUT_CTRL_OFFSET);
 503         prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
 504                                         OMAP3_PRM_CLKOUT_CTRL_OFFSET);
 505         prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
 506                                         PM_WKDEP);
 507         prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
 508                                         PM_WKDEP);
 509         prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
 510                                         PM_WKDEP);
 511         prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
 512                                         PM_WKDEP);
 513         prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
 514                                         PM_WKDEP);
 515         prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
 516                                         OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 517         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
 518                                         OMAP3430_PM_MPUGRPSEL1);
 519         prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
 520                                         OMAP3430_PM_IVAGRPSEL1);
 521         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
 522                                         OMAP3430ES2_PM_MPUGRPSEL3);
 523         prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
 524                                         OMAP3430ES2_PM_IVAGRPSEL3);
 525         prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
 526                                         OMAP3430_PM_MPUGRPSEL);
 527         prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
 528                                         OMAP3430_PM_IVAGRPSEL);
 529         prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
 530                                         OMAP3430_PM_MPUGRPSEL);
 531         prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
 532                                          OMAP3430_PM_IVAGRPSEL);
 533         prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
 534         return;
 535 }
 536 #endif