2 * linux/arch/arm/mach-omap2/prcm.c
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
6 * Copyright (C) 2005 Nokia Corporation
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/clk.h>
24 #include <linux/delay.h>
26 #include <plat/common.h>
27 #include <plat/prcm.h>
28 #include <plat/irqs.h>
29 #include <plat/control.h>
34 #include "prm-regbits-24xx.h"
36 static void __iomem *prm_base;
37 static void __iomem *cm_base;
38 static void __iomem *cm2_base;
40 #define MAX_MODULE_ENABLE_WAIT 100000
42 struct omap3_prcm_regs {
43 u32 control_padconf_sys_nirq;
59 u32 iva2_cm_clken_pll;
67 u32 usbhost_cm_fclken;
76 u32 usbhost_cm_iclken;
77 u32 iva2_cm_autiidle2;
79 u32 iva2_cm_clkstctrl;
81 u32 core_cm_clkstctrl;
86 u32 neon_cm_clkstctrl;
87 u32 usbhost_cm_clkstctrl;
88 u32 core_cm_autoidle1;
89 u32 core_cm_autoidle2;
90 u32 core_cm_autoidle3;
95 u32 usbhost_cm_autoidle;
100 u32 usbhost_cm_sleepdep;
108 u32 usbhost_pm_wkdep;
109 u32 core_pm_mpugrpsel1;
110 u32 iva2_pm_ivagrpsel1;
111 u32 core_pm_mpugrpsel3;
112 u32 core_pm_ivagrpsel3;
113 u32 wkup_pm_mpugrpsel;
114 u32 wkup_pm_ivagrpsel;
115 u32 per_pm_mpugrpsel;
116 u32 per_pm_ivagrpsel;
120 struct omap3_prcm_regs prcm_context;
122 u32 omap_prcm_get_reset_sources(void)
124 /* XXX This presumably needs modification for 34XX */
125 if (cpu_is_omap24xx() | cpu_is_omap34xx())
126 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
127 if (cpu_is_omap44xx())
128 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
130 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
132 /* Resets clock rates and reboots the system. Only called from system.h */
133 void omap_prcm_arch_reset(char mode)
136 omap2_clk_prepare_for_reboot();
138 if (cpu_is_omap24xx())
139 prcm_offs = WKUP_MOD;
140 else if (cpu_is_omap34xx()) {
143 prcm_offs = OMAP3430_GR_MOD;
144 l = ('B' << 24) | ('M' << 16) | mode;
145 /* Reserve the first word in scratchpad for communicating
146 * with the boot ROM. A pointer to a data structure
147 * describing the boot process can be stored there,
148 * cf. OMAP34xx TRM, Initialization / Software Booting
150 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
151 } else if (cpu_is_omap44xx())
152 prcm_offs = OMAP4430_PRM_DEVICE_MOD;
156 if (cpu_is_omap24xx() | cpu_is_omap34xx())
157 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
159 if (cpu_is_omap44xx())
160 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
164 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
167 return __raw_readl(base + module + reg);
170 static inline void __omap_prcm_write(u32 value, void __iomem *base,
174 __raw_writel(value, base + module + reg);
177 /* Read a register in a PRM module */
178 u32 prm_read_mod_reg(s16 module, u16 idx)
180 return __omap_prcm_read(prm_base, module, idx);
183 /* Write into a register in a PRM module */
184 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
186 __omap_prcm_write(val, prm_base, module, idx);
189 /* Read-modify-write a register in a PRM module. Caller must lock */
190 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
194 v = prm_read_mod_reg(module, idx);
197 prm_write_mod_reg(v, module, idx);
202 /* Read a register in a CM module */
203 u32 cm_read_mod_reg(s16 module, u16 idx)
205 return __omap_prcm_read(cm_base, module, idx);
208 /* Write into a register in a CM module */
209 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
211 __omap_prcm_write(val, cm_base, module, idx);
214 /* Read-modify-write a register in a CM module. Caller must lock */
215 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
219 v = cm_read_mod_reg(module, idx);
222 cm_write_mod_reg(v, module, idx);
228 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
229 * @reg: physical address of module IDLEST register
230 * @mask: value to mask against to determine if the module is active
231 * @name: name of the clock (for printk)
233 * Returns 1 if the module indicated readiness in time, or 0 if it
234 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
236 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
242 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
243 * 34xx reverses this, just to keep us on our toes
245 if (cpu_is_omap24xx())
247 else if (cpu_is_omap34xx())
253 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
254 MAX_MODULE_ENABLE_WAIT, i);
256 if (i < MAX_MODULE_ENABLE_WAIT)
257 pr_debug("cm: Module associated with clock %s ready after %d "
260 pr_err("cm: Module associated with clock %s didn't enable in "
261 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
263 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
266 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
268 prm_base = omap2_globals->prm;
269 cm_base = omap2_globals->cm;
270 cm2_base = omap2_globals->cm2;
273 #ifdef CONFIG_ARCH_OMAP3
274 void omap3_prcm_save_context(void)
276 prcm_context.control_padconf_sys_nirq =
277 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
278 prcm_context.iva2_cm_clksel1 =
279 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
280 prcm_context.iva2_cm_clksel2 =
281 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
282 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
283 prcm_context.sgx_cm_clksel =
284 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
285 prcm_context.dss_cm_clksel =
286 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
287 prcm_context.cam_cm_clksel =
288 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
289 prcm_context.per_cm_clksel =
290 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
291 prcm_context.emu_cm_clksel =
292 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
293 prcm_context.emu_cm_clkstctrl =
294 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
295 prcm_context.pll_cm_autoidle2 =
296 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
297 prcm_context.pll_cm_clksel4 =
298 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
299 prcm_context.pll_cm_clksel5 =
300 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
301 prcm_context.pll_cm_clken2 =
302 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
303 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
304 prcm_context.iva2_cm_fclken =
305 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
306 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
307 OMAP3430_CM_CLKEN_PLL);
308 prcm_context.core_cm_fclken1 =
309 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
310 prcm_context.core_cm_fclken3 =
311 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
312 prcm_context.sgx_cm_fclken =
313 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
314 prcm_context.wkup_cm_fclken =
315 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
316 prcm_context.dss_cm_fclken =
317 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
318 prcm_context.cam_cm_fclken =
319 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
320 prcm_context.per_cm_fclken =
321 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
322 prcm_context.usbhost_cm_fclken =
323 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
324 prcm_context.core_cm_iclken1 =
325 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
326 prcm_context.core_cm_iclken2 =
327 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
328 prcm_context.core_cm_iclken3 =
329 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
330 prcm_context.sgx_cm_iclken =
331 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
332 prcm_context.wkup_cm_iclken =
333 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
334 prcm_context.dss_cm_iclken =
335 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
336 prcm_context.cam_cm_iclken =
337 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
338 prcm_context.per_cm_iclken =
339 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
340 prcm_context.usbhost_cm_iclken =
341 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
342 prcm_context.iva2_cm_autiidle2 =
343 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
344 prcm_context.mpu_cm_autoidle2 =
345 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
346 prcm_context.iva2_cm_clkstctrl =
347 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
348 prcm_context.mpu_cm_clkstctrl =
349 cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
350 prcm_context.core_cm_clkstctrl =
351 cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
352 prcm_context.sgx_cm_clkstctrl =
353 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
354 prcm_context.dss_cm_clkstctrl =
355 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
356 prcm_context.cam_cm_clkstctrl =
357 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
358 prcm_context.per_cm_clkstctrl =
359 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
360 prcm_context.neon_cm_clkstctrl =
361 cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
362 prcm_context.usbhost_cm_clkstctrl =
363 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
364 prcm_context.core_cm_autoidle1 =
365 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
366 prcm_context.core_cm_autoidle2 =
367 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
368 prcm_context.core_cm_autoidle3 =
369 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
370 prcm_context.wkup_cm_autoidle =
371 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
372 prcm_context.dss_cm_autoidle =
373 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
374 prcm_context.cam_cm_autoidle =
375 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
376 prcm_context.per_cm_autoidle =
377 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
378 prcm_context.usbhost_cm_autoidle =
379 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
380 prcm_context.sgx_cm_sleepdep =
381 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
382 prcm_context.dss_cm_sleepdep =
383 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
384 prcm_context.cam_cm_sleepdep =
385 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
386 prcm_context.per_cm_sleepdep =
387 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
388 prcm_context.usbhost_cm_sleepdep =
389 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
390 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
391 OMAP3_CM_CLKOUT_CTRL_OFFSET);
392 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
393 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
394 prcm_context.sgx_pm_wkdep =
395 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
396 prcm_context.dss_pm_wkdep =
397 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
398 prcm_context.cam_pm_wkdep =
399 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
400 prcm_context.per_pm_wkdep =
401 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
402 prcm_context.neon_pm_wkdep =
403 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
404 prcm_context.usbhost_pm_wkdep =
405 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
406 prcm_context.core_pm_mpugrpsel1 =
407 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
408 prcm_context.iva2_pm_ivagrpsel1 =
409 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
410 prcm_context.core_pm_mpugrpsel3 =
411 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
412 prcm_context.core_pm_ivagrpsel3 =
413 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
414 prcm_context.wkup_pm_mpugrpsel =
415 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
416 prcm_context.wkup_pm_ivagrpsel =
417 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
418 prcm_context.per_pm_mpugrpsel =
419 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
420 prcm_context.per_pm_ivagrpsel =
421 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
422 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
426 void omap3_prcm_restore_context(void)
428 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
429 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
430 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
432 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
434 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
435 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
437 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
439 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
441 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
443 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
445 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
447 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
449 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
450 OMAP3430ES2_CM_CLKSEL4);
451 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
452 OMAP3430ES2_CM_CLKSEL5);
453 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
454 OMAP3430ES2_CM_CLKEN2);
455 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
456 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
458 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
459 OMAP3430_CM_CLKEN_PLL);
460 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
461 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
462 OMAP3430ES2_CM_FCLKEN3);
463 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
465 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
466 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
468 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
470 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
472 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
473 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
474 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
475 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
476 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
477 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
479 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
480 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
482 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
484 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
486 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
487 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
488 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
490 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
491 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
493 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
494 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
496 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
498 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
500 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
502 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
504 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
506 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
507 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
508 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
510 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
512 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
514 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
515 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
517 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
519 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
521 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
522 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
523 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
524 OMAP3430_CM_SLEEPDEP);
525 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
526 OMAP3430_CM_SLEEPDEP);
527 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
528 OMAP3430_CM_SLEEPDEP);
529 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
530 OMAP3430_CM_SLEEPDEP);
531 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
532 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
533 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
534 OMAP3_CM_CLKOUT_CTRL_OFFSET);
535 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
536 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
537 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
539 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
541 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
543 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
545 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
547 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
548 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
549 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
550 OMAP3430_PM_MPUGRPSEL1);
551 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
552 OMAP3430_PM_IVAGRPSEL1);
553 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
554 OMAP3430ES2_PM_MPUGRPSEL3);
555 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
556 OMAP3430ES2_PM_IVAGRPSEL3);
557 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
558 OMAP3430_PM_MPUGRPSEL);
559 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
560 OMAP3430_PM_IVAGRPSEL);
561 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
562 OMAP3430_PM_MPUGRPSEL);
563 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
564 OMAP3430_PM_IVAGRPSEL);
565 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);