arch/arm/mach-omap2/prcm.c

   1 /*
   2  * linux/arch/arm/mach-omap2/prcm.c
   3  *
   4  * OMAP 24xx Power Reset and Clock Management (PRCM) functions
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  *
   8  * Written by Tony Lindgren <tony.lindgren@nokia.com>
   9  *
  10  * Copyright (C) 2007 Texas Instruments, Inc.
  11  * Rajendra Nayak <rnayak@ti.com>
  12  *
  13  * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
  14  * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/clk.h>
  23 #include <linux/io.h>
  24 #include <linux/delay.h>
  25
  26 #include <plat/common.h>
  27 #include <plat/prcm.h>
  28 #include <plat/irqs.h>
  29
  30 #include "clock.h"
  31 #include "clock2xxx.h"
  32 #include "cm.h"
  33 #include "prm.h"
  34 #include "prm-regbits-24xx.h"
  35 #include "prm-regbits-44xx.h"
  36 #include "control.h"
  37
  38 static void __iomem *prm_base;
  39 static void __iomem *cm_base;
  40 static void __iomem *cm2_base;
  41
  42 #define MAX_MODULE_ENABLE_WAIT          100000
  43
  44 struct omap3_prcm_regs {
  45         u32 iva2_cm_clksel1;
  46         u32 iva2_cm_clksel2;
  47         u32 cm_sysconfig;
  48         u32 sgx_cm_clksel;
  49         u32 dss_cm_clksel;
  50         u32 cam_cm_clksel;
  51         u32 per_cm_clksel;
  52         u32 emu_cm_clksel;
  53         u32 emu_cm_clkstctrl;
  54         u32 pll_cm_autoidle2;
  55         u32 pll_cm_clksel4;
  56         u32 pll_cm_clksel5;
  57         u32 pll_cm_clken2;
  58         u32 cm_polctrl;
  59         u32 iva2_cm_fclken;
  60         u32 iva2_cm_clken_pll;
  61         u32 core_cm_fclken1;
  62         u32 core_cm_fclken3;
  63         u32 sgx_cm_fclken;
  64         u32 wkup_cm_fclken;
  65         u32 dss_cm_fclken;
  66         u32 cam_cm_fclken;
  67         u32 per_cm_fclken;
  68         u32 usbhost_cm_fclken;
  69         u32 core_cm_iclken1;
  70         u32 core_cm_iclken2;
  71         u32 core_cm_iclken3;
  72         u32 sgx_cm_iclken;
  73         u32 wkup_cm_iclken;
  74         u32 dss_cm_iclken;
  75         u32 cam_cm_iclken;
  76         u32 per_cm_iclken;
  77         u32 usbhost_cm_iclken;
  78         u32 iva2_cm_autiidle2;
  79         u32 mpu_cm_autoidle2;
  80         u32 iva2_cm_clkstctrl;
  81         u32 mpu_cm_clkstctrl;
  82         u32 core_cm_clkstctrl;
  83         u32 sgx_cm_clkstctrl;
  84         u32 dss_cm_clkstctrl;
  85         u32 cam_cm_clkstctrl;
  86         u32 per_cm_clkstctrl;
  87         u32 neon_cm_clkstctrl;
  88         u32 usbhost_cm_clkstctrl;
  89         u32 core_cm_autoidle1;
  90         u32 core_cm_autoidle2;
  91         u32 core_cm_autoidle3;
  92         u32 wkup_cm_autoidle;
  93         u32 dss_cm_autoidle;
  94         u32 cam_cm_autoidle;
  95         u32 per_cm_autoidle;
  96         u32 usbhost_cm_autoidle;
  97         u32 sgx_cm_sleepdep;
  98         u32 dss_cm_sleepdep;
  99         u32 cam_cm_sleepdep;
 100         u32 per_cm_sleepdep;
 101         u32 usbhost_cm_sleepdep;
 102         u32 cm_clkout_ctrl;
 103         u32 prm_clkout_ctrl;
 104         u32 sgx_pm_wkdep;
 105         u32 dss_pm_wkdep;
 106         u32 cam_pm_wkdep;
 107         u32 per_pm_wkdep;
 108         u32 neon_pm_wkdep;
 109         u32 usbhost_pm_wkdep;
 110         u32 core_pm_mpugrpsel1;
 111         u32 iva2_pm_ivagrpsel1;
 112         u32 core_pm_mpugrpsel3;
 113         u32 core_pm_ivagrpsel3;
 114         u32 wkup_pm_mpugrpsel;
 115         u32 wkup_pm_ivagrpsel;
 116         u32 per_pm_mpugrpsel;
 117         u32 per_pm_ivagrpsel;
 118         u32 wkup_pm_wken;
 119 };
 120
 121 static struct omap3_prcm_regs prcm_context;
 122
 123 u32 omap_prcm_get_reset_sources(void)
 124 {
 125         /* XXX This presumably needs modification for 34XX */
 126         if (cpu_is_omap24xx() || cpu_is_omap34xx())
 127                 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
 128         if (cpu_is_omap44xx())
 129                 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
 130
 131         return 0;
 132 }
 133 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
 134
 135 /* Resets clock rates and reboots the system. Only called from system.h */
 136 void omap_prcm_arch_reset(char mode, const char *cmd)
 137 {
 138         s16 prcm_offs = 0;
 139
 140         if (cpu_is_omap24xx()) {
 141                 omap2xxx_clk_prepare_for_reboot();
 142
 143                 prcm_offs = WKUP_MOD;
 144         } else if (cpu_is_omap34xx()) {
 145                 prcm_offs = OMAP3430_GR_MOD;
 146                 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
 147         } else if (cpu_is_omap44xx())
 148                 prcm_offs = OMAP4430_PRM_DEVICE_MOD;
 149         else
 150                 WARN_ON(1);
 151
 152         if (cpu_is_omap24xx() || cpu_is_omap34xx())
 153                 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
 154                                                  OMAP2_RM_RSTCTRL);
 155         if (cpu_is_omap44xx())
 156                 prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
 157                                      prcm_offs, OMAP4_RM_RSTCTRL);
 158 }
 159
 160 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
 161 {
 162         BUG_ON(!base);
 163         return __raw_readl(base + module + reg);
 164 }
 165
 166 static inline void __omap_prcm_write(u32 value, void __iomem *base,
 167                                                 s16 module, u16 reg)
 168 {
 169         BUG_ON(!base);
 170         __raw_writel(value, base + module + reg);
 171 }
 172
 173 /* Read a register in a PRM module */
 174 u32 prm_read_mod_reg(s16 module, u16 idx)
 175 {
 176         return __omap_prcm_read(prm_base, module, idx);
 177 }
 178
 179 /* Write into a register in a PRM module */
 180 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
 181 {
 182         __omap_prcm_write(val, prm_base, module, idx);
 183 }
 184
 185 /* Read-modify-write a register in a PRM module. Caller must lock */
 186 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 187 {
 188         u32 v;
 189
 190         v = prm_read_mod_reg(module, idx);
 191         v &= ~mask;
 192         v |= bits;
 193         prm_write_mod_reg(v, module, idx);
 194
 195         return v;
 196 }
 197
 198 /* Read a PRM register, AND it, and shift the result down to bit 0 */
 199 u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
 200 {
 201         u32 v;
 202
 203         v = prm_read_mod_reg(domain, idx);
 204         v &= mask;
 205         v >>= __ffs(mask);
 206
 207         return v;
 208 }
 209
 210 /* Read a PRM register, AND it, and shift the result down to bit 0 */
 211 u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
 212 {
 213         u32 v;
 214
 215         v = __raw_readl(reg);
 216         v &= mask;
 217         v >>= __ffs(mask);
 218
 219         return v;
 220 }
 221
 222 /* Read-modify-write a register in a PRM module. Caller must lock */
 223 u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
 224 {
 225         u32 v;
 226
 227         v = __raw_readl(reg);
 228         v &= ~mask;
 229         v |= bits;
 230         __raw_writel(v, reg);
 231
 232         return v;
 233 }
 234 /* Read a register in a CM module */
 235 u32 cm_read_mod_reg(s16 module, u16 idx)
 236 {
 237         return __omap_prcm_read(cm_base, module, idx);
 238 }
 239
 240 /* Write into a register in a CM module */
 241 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
 242 {
 243         __omap_prcm_write(val, cm_base, module, idx);
 244 }
 245
 246 /* Read-modify-write a register in a CM module. Caller must lock */
 247 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
 248 {
 249         u32 v;
 250
 251         v = cm_read_mod_reg(module, idx);
 252         v &= ~mask;
 253         v |= bits;
 254         cm_write_mod_reg(v, module, idx);
 255
 256         return v;
 257 }
 258
 259 /**
 260  * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
 261  * @reg: physical address of module IDLEST register
 262  * @mask: value to mask against to determine if the module is active
 263  * @idlest: idle state indicator (0 or 1) for the clock
 264  * @name: name of the clock (for printk)
 265  *
 266  * Returns 1 if the module indicated readiness in time, or 0 if it
 267  * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
 268  */
 269 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
 270                                 const char *name)
 271 {
 272         int i = 0;
 273         int ena = 0;
 274
 275         if (idlest)
 276                 ena = 0;
 277         else
 278                 ena = mask;
 279
 280         /* Wait for lock */
 281         omap_test_timeout(((__raw_readl(reg) & mask) == ena),
 282                           MAX_MODULE_ENABLE_WAIT, i);
 283
 284         if (i < MAX_MODULE_ENABLE_WAIT)
 285                 pr_debug("cm: Module associated with clock %s ready after %d "
 286                          "loops\n", name, i);
 287         else
 288                 pr_err("cm: Module associated with clock %s didn't enable in "
 289                        "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
 290
 291         return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
 292 };
 293
 294 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
 295 {
 296         /* Static mapping, never released */
 297         if (omap2_globals->prm) {
 298                 prm_base = ioremap(omap2_globals->prm, SZ_8K);
 299                 WARN_ON(!prm_base);
 300         }
 301         if (omap2_globals->cm) {
 302                 cm_base = ioremap(omap2_globals->cm, SZ_8K);
 303                 WARN_ON(!cm_base);
 304         }
 305         if (omap2_globals->cm2) {
 306                 cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
 307                 WARN_ON(!cm2_base);
 308         }
 309 }
 310
 311 #ifdef CONFIG_ARCH_OMAP3
 312 void omap3_prcm_save_context(void)
 313 {
 314         prcm_context.iva2_cm_clksel1 =
 315                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
 316         prcm_context.iva2_cm_clksel2 =
 317                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
 318         prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
 319         prcm_context.sgx_cm_clksel =
 320                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
 321         prcm_context.dss_cm_clksel =
 322                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
 323         prcm_context.cam_cm_clksel =
 324                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
 325         prcm_context.per_cm_clksel =
 326                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
 327         prcm_context.emu_cm_clksel =
 328                          cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
 329         prcm_context.emu_cm_clkstctrl =
 330                          cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
 331         prcm_context.pll_cm_autoidle2 =
 332                          cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
 333         prcm_context.pll_cm_clksel4 =
 334                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
 335         prcm_context.pll_cm_clksel5 =
 336                          cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
 337         prcm_context.pll_cm_clken2 =
 338                         cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
 339         prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
 340         prcm_context.iva2_cm_fclken =
 341                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
 342         prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
 343                         OMAP3430_CM_CLKEN_PLL);
 344         prcm_context.core_cm_fclken1 =
 345                          cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 346         prcm_context.core_cm_fclken3 =
 347                          cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
 348         prcm_context.sgx_cm_fclken =
 349                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
 350         prcm_context.wkup_cm_fclken =
 351                          cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
 352         prcm_context.dss_cm_fclken =
 353                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
 354         prcm_context.cam_cm_fclken =
 355                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
 356         prcm_context.per_cm_fclken =
 357                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
 358         prcm_context.usbhost_cm_fclken =
 359                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 360         prcm_context.core_cm_iclken1 =
 361                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
 362         prcm_context.core_cm_iclken2 =
 363                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
 364         prcm_context.core_cm_iclken3 =
 365                          cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
 366         prcm_context.sgx_cm_iclken =
 367                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
 368         prcm_context.wkup_cm_iclken =
 369                          cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
 370         prcm_context.dss_cm_iclken =
 371                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
 372         prcm_context.cam_cm_iclken =
 373                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
 374         prcm_context.per_cm_iclken =
 375                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
 376         prcm_context.usbhost_cm_iclken =
 377                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 378         prcm_context.iva2_cm_autiidle2 =
 379                          cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 380         prcm_context.mpu_cm_autoidle2 =
 381                          cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
 382         prcm_context.iva2_cm_clkstctrl =
 383                          cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
 384         prcm_context.mpu_cm_clkstctrl =
 385                          cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
 386         prcm_context.core_cm_clkstctrl =
 387                          cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
 388         prcm_context.sgx_cm_clkstctrl =
 389                          cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 390                                                 OMAP2_CM_CLKSTCTRL);
 391         prcm_context.dss_cm_clkstctrl =
 392                          cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
 393         prcm_context.cam_cm_clkstctrl =
 394                          cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
 395         prcm_context.per_cm_clkstctrl =
 396                          cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
 397         prcm_context.neon_cm_clkstctrl =
 398                          cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
 399         prcm_context.usbhost_cm_clkstctrl =
 400                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 401                                                 OMAP2_CM_CLKSTCTRL);
 402         prcm_context.core_cm_autoidle1 =
 403                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
 404         prcm_context.core_cm_autoidle2 =
 405                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
 406         prcm_context.core_cm_autoidle3 =
 407                          cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
 408         prcm_context.wkup_cm_autoidle =
 409                          cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
 410         prcm_context.dss_cm_autoidle =
 411                          cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
 412         prcm_context.cam_cm_autoidle =
 413                          cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
 414         prcm_context.per_cm_autoidle =
 415                          cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 416         prcm_context.usbhost_cm_autoidle =
 417                          cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 418         prcm_context.sgx_cm_sleepdep =
 419                  cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
 420         prcm_context.dss_cm_sleepdep =
 421                  cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
 422         prcm_context.cam_cm_sleepdep =
 423                  cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
 424         prcm_context.per_cm_sleepdep =
 425                  cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
 426         prcm_context.usbhost_cm_sleepdep =
 427                  cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 428         prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
 429                  OMAP3_CM_CLKOUT_CTRL_OFFSET);
 430         prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
 431                 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
 432         prcm_context.sgx_pm_wkdep =
 433                  prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
 434         prcm_context.dss_pm_wkdep =
 435                  prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
 436         prcm_context.cam_pm_wkdep =
 437                  prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
 438         prcm_context.per_pm_wkdep =
 439                  prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
 440         prcm_context.neon_pm_wkdep =
 441                  prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
 442         prcm_context.usbhost_pm_wkdep =
 443                  prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 444         prcm_context.core_pm_mpugrpsel1 =
 445                  prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
 446         prcm_context.iva2_pm_ivagrpsel1 =
 447                  prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
 448         prcm_context.core_pm_mpugrpsel3 =
 449                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
 450         prcm_context.core_pm_ivagrpsel3 =
 451                  prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 452         prcm_context.wkup_pm_mpugrpsel =
 453                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 454         prcm_context.wkup_pm_ivagrpsel =
 455                  prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 456         prcm_context.per_pm_mpugrpsel =
 457                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 458         prcm_context.per_pm_ivagrpsel =
 459                  prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 460         prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 461         return;
 462 }
 463
 464 void omap3_prcm_restore_context(void)
 465 {
 466         cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
 467                                          CM_CLKSEL1);
 468         cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
 469                                          CM_CLKSEL2);
 470         __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
 471         cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
 472                                          CM_CLKSEL);
 473         cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
 474                                          CM_CLKSEL);
 475         cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
 476                                          CM_CLKSEL);
 477         cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
 478                                          CM_CLKSEL);
 479         cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
 480                                          CM_CLKSEL1);
 481         cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
 482                                          OMAP2_CM_CLKSTCTRL);
 483         cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
 484                                          CM_AUTOIDLE2);
 485         cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
 486                                         OMAP3430ES2_CM_CLKSEL4);
 487         cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
 488                                          OMAP3430ES2_CM_CLKSEL5);
 489         cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
 490                                         OMAP3430ES2_CM_CLKEN2);
 491         __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
 492         cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
 493                                          CM_FCLKEN);
 494         cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
 495                                         OMAP3430_CM_CLKEN_PLL);
 496         cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
 497         cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
 498                                          OMAP3430ES2_CM_FCLKEN3);
 499         cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
 500                                          CM_FCLKEN);
 501         cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
 502         cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
 503                                          CM_FCLKEN);
 504         cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
 505                                          CM_FCLKEN);
 506         cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
 507                                          CM_FCLKEN);
 508         cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
 509                                          OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
 510         cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
 511         cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
 512         cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
 513         cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
 514                                         CM_ICLKEN);
 515         cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
 516         cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
 517                                         CM_ICLKEN);
 518         cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
 519                                         CM_ICLKEN);
 520         cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
 521                                         CM_ICLKEN);
 522         cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
 523                                         OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
 524         cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
 525                                         CM_AUTOIDLE2);
 526         cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
 527         cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
 528                                         OMAP2_CM_CLKSTCTRL);
 529         cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
 530                                         OMAP2_CM_CLKSTCTRL);
 531         cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
 532                                         OMAP2_CM_CLKSTCTRL);
 533         cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
 534                                         OMAP2_CM_CLKSTCTRL);
 535         cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
 536                                         OMAP2_CM_CLKSTCTRL);
 537         cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
 538                                         OMAP2_CM_CLKSTCTRL);
 539         cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
 540                                         OMAP2_CM_CLKSTCTRL);
 541         cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
 542                                         OMAP2_CM_CLKSTCTRL);
 543         cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
 544                                 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
 545         cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
 546                                         CM_AUTOIDLE1);
 547         cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
 548                                         CM_AUTOIDLE2);
 549         cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
 550                                         CM_AUTOIDLE3);
 551         cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
 552         cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
 553                                         CM_AUTOIDLE);
 554         cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
 555                                         CM_AUTOIDLE);
 556         cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
 557                                         CM_AUTOIDLE);
 558         cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
 559                                         OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
 560         cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
 561                                         OMAP3430_CM_SLEEPDEP);
 562         cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
 563                                         OMAP3430_CM_SLEEPDEP);
 564         cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
 565                                         OMAP3430_CM_SLEEPDEP);
 566         cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
 567                                         OMAP3430_CM_SLEEPDEP);
 568         cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
 569                                 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
 570         cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
 571                                         OMAP3_CM_CLKOUT_CTRL_OFFSET);
 572         prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
 573                                         OMAP3_PRM_CLKOUT_CTRL_OFFSET);
 574         prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
 575                                         PM_WKDEP);
 576         prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
 577                                         PM_WKDEP);
 578         prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
 579                                         PM_WKDEP);
 580         prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
 581                                         PM_WKDEP);
 582         prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
 583                                         PM_WKDEP);
 584         prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
 585                                         OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 586         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
 587                                         OMAP3430_PM_MPUGRPSEL1);
 588         prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
 589                                         OMAP3430_PM_IVAGRPSEL1);
 590         prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
 591                                         OMAP3430ES2_PM_MPUGRPSEL3);
 592         prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
 593                                         OMAP3430ES2_PM_IVAGRPSEL3);
 594         prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
 595                                         OMAP3430_PM_MPUGRPSEL);
 596         prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
 597                                         OMAP3430_PM_IVAGRPSEL);
 598         prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
 599                                         OMAP3430_PM_MPUGRPSEL);
 600         prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
 601                                          OMAP3430_PM_IVAGRPSEL);
 602         prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
 603         return;
 604 }
 605 #endif