1 #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
2 #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H
5 * OMAP2/3 PRCM base and module definitions
7 * Copyright (C) 2007-2009 Texas Instruments, Inc.
8 * Copyright (C) 2007-2009 Nokia Corporation
10 * Written by Paul Walmsley
11 * OMAP4 defines in this file are automatically generated from the OMAP hardware
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 /* Module offsets from both CM_BASE & PRM_BASE */
23 * Offsets that are the same on 24xx and 34xx
25 * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is
26 * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2.
30 #define CORE_MOD 0x200
32 #define WKUP_MOD 0x400
36 /* Chip-specific module offsets */
37 #define OMAP24XX_GR_MOD OCP_MOD
38 #define OMAP24XX_DSP_MOD 0x800
40 #define OMAP2430_MDM_MOD 0xc00
42 /* IVA2 module is < base on 3430 */
43 #define OMAP3430_IVA2_MOD -0x800
44 #define OMAP3430ES2_SGX_MOD GFX_MOD
45 #define OMAP3430_CCR_MOD PLL_MOD
46 #define OMAP3430_DSS_MOD 0x600
47 #define OMAP3430_CAM_MOD 0x700
48 #define OMAP3430_PER_MOD 0x800
49 #define OMAP3430_EMU_MOD 0x900
50 #define OMAP3430_GR_MOD 0xa00
51 #define OMAP3430_NEON_MOD 0xb00
52 #define OMAP3430ES2_USBHOST_MOD 0xc00
54 /* OMAP44XX specific module offsets */
58 #define OMAP4430_CM1_OCP_SOCKET_MOD 0x0000
59 #define OMAP4430_CM1_CKGEN_MOD 0x0100
60 #define OMAP4430_CM1_MPU_MOD 0x0300
61 #define OMAP4430_CM1_TESLA_MOD 0x0400
62 #define OMAP4430_CM1_ABE_MOD 0x0500
63 #define OMAP4430_CM1_RESTORE_MOD 0x0e00
64 #define OMAP4430_CM1_INSTR_MOD 0x0f00
68 #define OMAP4430_CM2_OCP_SOCKET_MOD 0x0000
69 #define OMAP4430_CM2_CKGEN_MOD 0x0100
70 #define OMAP4430_CM2_ALWAYS_ON_MOD 0x0600
71 #define OMAP4430_CM2_CORE_MOD 0x0700
72 #define OMAP4430_CM2_IVAHD_MOD 0x0f00
73 #define OMAP4430_CM2_CAM_MOD 0x1000
74 #define OMAP4430_CM2_DSS_MOD 0x1100
75 #define OMAP4430_CM2_GFX_MOD 0x1200
76 #define OMAP4430_CM2_L3INIT_MOD 0x1300
77 #define OMAP4430_CM2_L4PER_MOD 0x1400
78 #define OMAP4430_CM2_CEFUSE_MOD 0x1600
79 #define OMAP4430_CM2_RESTORE_MOD 0x1e00
80 #define OMAP4430_CM2_INSTR_MOD 0x1f00
84 #define OMAP4430_PRM_OCP_SOCKET_MOD 0x0000
85 #define OMAP4430_PRM_CKGEN_MOD 0x0100
86 #define OMAP4430_PRM_MPU_MOD 0x0300
87 #define OMAP4430_PRM_TESLA_MOD 0x0400
88 #define OMAP4430_PRM_ABE_MOD 0x0500
89 #define OMAP4430_PRM_ALWAYS_ON_MOD 0x0600
90 #define OMAP4430_PRM_CORE_MOD 0x0700
91 #define OMAP4430_PRM_IVAHD_MOD 0x0f00
92 #define OMAP4430_PRM_CAM_MOD 0x1000
93 #define OMAP4430_PRM_DSS_MOD 0x1100
94 #define OMAP4430_PRM_GFX_MOD 0x1200
95 #define OMAP4430_PRM_L3INIT_MOD 0x1300
96 #define OMAP4430_PRM_L4PER_MOD 0x1400
97 #define OMAP4430_PRM_CEFUSE_MOD 0x1600
98 #define OMAP4430_PRM_WKUP_MOD 0x1700
99 #define OMAP4430_PRM_WKUP_CM_MOD 0x1800
100 #define OMAP4430_PRM_EMU_MOD 0x1900
101 #define OMAP4430_PRM_EMU_CM_MOD 0x1a00
102 #define OMAP4430_PRM_DEVICE_MOD 0x1b00
103 #define OMAP4430_PRM_INSTR_MOD 0x1f00
107 #define OMAP4430_SCRM_SCRM_MOD 0x0000
109 /* CHIRONSS instances */
111 #define OMAP4430_CHIRONSS_CHIRONSS_OCP_SOCKET_PRCM_MOD 0x0000
112 #define OMAP4430_CHIRONSS_CHIRONSS_DEVICE_PRM_MOD 0x0200
113 #define OMAP4430_CHIRONSS_CHIRONSS_CPU0_MOD 0x0400
114 #define OMAP4430_CHIRONSS_CHIRONSS_CPU1_MOD 0x0800
116 /* 24XX register bits shared between CM & PRM registers */
118 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
119 #define OMAP2420_EN_MMC_SHIFT 26
120 #define OMAP2420_EN_MMC (1 << 26)
121 #define OMAP24XX_EN_UART2_SHIFT 22
122 #define OMAP24XX_EN_UART2 (1 << 22)
123 #define OMAP24XX_EN_UART1_SHIFT 21
124 #define OMAP24XX_EN_UART1 (1 << 21)
125 #define OMAP24XX_EN_MCSPI2_SHIFT 18
126 #define OMAP24XX_EN_MCSPI2 (1 << 18)
127 #define OMAP24XX_EN_MCSPI1_SHIFT 17
128 #define OMAP24XX_EN_MCSPI1 (1 << 17)
129 #define OMAP24XX_EN_MCBSP2_SHIFT 16
130 #define OMAP24XX_EN_MCBSP2 (1 << 16)
131 #define OMAP24XX_EN_MCBSP1_SHIFT 15
132 #define OMAP24XX_EN_MCBSP1 (1 << 15)
133 #define OMAP24XX_EN_GPT12_SHIFT 14
134 #define OMAP24XX_EN_GPT12 (1 << 14)
135 #define OMAP24XX_EN_GPT11_SHIFT 13
136 #define OMAP24XX_EN_GPT11 (1 << 13)
137 #define OMAP24XX_EN_GPT10_SHIFT 12
138 #define OMAP24XX_EN_GPT10 (1 << 12)
139 #define OMAP24XX_EN_GPT9_SHIFT 11
140 #define OMAP24XX_EN_GPT9 (1 << 11)
141 #define OMAP24XX_EN_GPT8_SHIFT 10
142 #define OMAP24XX_EN_GPT8 (1 << 10)
143 #define OMAP24XX_EN_GPT7_SHIFT 9
144 #define OMAP24XX_EN_GPT7 (1 << 9)
145 #define OMAP24XX_EN_GPT6_SHIFT 8
146 #define OMAP24XX_EN_GPT6 (1 << 8)
147 #define OMAP24XX_EN_GPT5_SHIFT 7
148 #define OMAP24XX_EN_GPT5 (1 << 7)
149 #define OMAP24XX_EN_GPT4_SHIFT 6
150 #define OMAP24XX_EN_GPT4 (1 << 6)
151 #define OMAP24XX_EN_GPT3_SHIFT 5
152 #define OMAP24XX_EN_GPT3 (1 << 5)
153 #define OMAP24XX_EN_GPT2_SHIFT 4
154 #define OMAP24XX_EN_GPT2 (1 << 4)
155 #define OMAP2420_EN_VLYNQ_SHIFT 3
156 #define OMAP2420_EN_VLYNQ (1 << 3)
158 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
159 #define OMAP2430_EN_GPIO5_SHIFT 10
160 #define OMAP2430_EN_GPIO5 (1 << 10)
161 #define OMAP2430_EN_MCSPI3_SHIFT 9
162 #define OMAP2430_EN_MCSPI3 (1 << 9)
163 #define OMAP2430_EN_MMCHS2_SHIFT 8
164 #define OMAP2430_EN_MMCHS2 (1 << 8)
165 #define OMAP2430_EN_MMCHS1_SHIFT 7
166 #define OMAP2430_EN_MMCHS1 (1 << 7)
167 #define OMAP24XX_EN_UART3_SHIFT 2
168 #define OMAP24XX_EN_UART3 (1 << 2)
169 #define OMAP24XX_EN_USB_SHIFT 0
170 #define OMAP24XX_EN_USB (1 << 0)
172 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
173 #define OMAP2430_EN_MDM_INTC_SHIFT 11
174 #define OMAP2430_EN_MDM_INTC (1 << 11)
175 #define OMAP2430_EN_USBHS_SHIFT 6
176 #define OMAP2430_EN_USBHS (1 << 6)
178 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
179 #define OMAP2420_ST_MMC_SHIFT 26
180 #define OMAP2420_ST_MMC_MASK (1 << 26)
181 #define OMAP24XX_ST_UART2_SHIFT 22
182 #define OMAP24XX_ST_UART2_MASK (1 << 22)
183 #define OMAP24XX_ST_UART1_SHIFT 21
184 #define OMAP24XX_ST_UART1_MASK (1 << 21)
185 #define OMAP24XX_ST_MCSPI2_SHIFT 18
186 #define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
187 #define OMAP24XX_ST_MCSPI1_SHIFT 17
188 #define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
189 #define OMAP24XX_ST_GPT12_SHIFT 14
190 #define OMAP24XX_ST_GPT12_MASK (1 << 14)
191 #define OMAP24XX_ST_GPT11_SHIFT 13
192 #define OMAP24XX_ST_GPT11_MASK (1 << 13)
193 #define OMAP24XX_ST_GPT10_SHIFT 12
194 #define OMAP24XX_ST_GPT10_MASK (1 << 12)
195 #define OMAP24XX_ST_GPT9_SHIFT 11
196 #define OMAP24XX_ST_GPT9_MASK (1 << 11)
197 #define OMAP24XX_ST_GPT8_SHIFT 10
198 #define OMAP24XX_ST_GPT8_MASK (1 << 10)
199 #define OMAP24XX_ST_GPT7_SHIFT 9
200 #define OMAP24XX_ST_GPT7_MASK (1 << 9)
201 #define OMAP24XX_ST_GPT6_SHIFT 8
202 #define OMAP24XX_ST_GPT6_MASK (1 << 8)
203 #define OMAP24XX_ST_GPT5_SHIFT 7
204 #define OMAP24XX_ST_GPT5_MASK (1 << 7)
205 #define OMAP24XX_ST_GPT4_SHIFT 6
206 #define OMAP24XX_ST_GPT4_MASK (1 << 6)
207 #define OMAP24XX_ST_GPT3_SHIFT 5
208 #define OMAP24XX_ST_GPT3_MASK (1 << 5)
209 #define OMAP24XX_ST_GPT2_SHIFT 4
210 #define OMAP24XX_ST_GPT2_MASK (1 << 4)
211 #define OMAP2420_ST_VLYNQ_SHIFT 3
212 #define OMAP2420_ST_VLYNQ_MASK (1 << 3)
214 /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */
215 #define OMAP2430_ST_MDM_INTC_SHIFT 11
216 #define OMAP2430_ST_MDM_INTC_MASK (1 << 11)
217 #define OMAP2430_ST_GPIO5_SHIFT 10
218 #define OMAP2430_ST_GPIO5_MASK (1 << 10)
219 #define OMAP2430_ST_MCSPI3_SHIFT 9
220 #define OMAP2430_ST_MCSPI3_MASK (1 << 9)
221 #define OMAP2430_ST_MMCHS2_SHIFT 8
222 #define OMAP2430_ST_MMCHS2_MASK (1 << 8)
223 #define OMAP2430_ST_MMCHS1_SHIFT 7
224 #define OMAP2430_ST_MMCHS1_MASK (1 << 7)
225 #define OMAP2430_ST_USBHS_SHIFT 6
226 #define OMAP2430_ST_USBHS_MASK (1 << 6)
227 #define OMAP24XX_ST_UART3_SHIFT 2
228 #define OMAP24XX_ST_UART3_MASK (1 << 2)
229 #define OMAP24XX_ST_USB_SHIFT 0
230 #define OMAP24XX_ST_USB_MASK (1 << 0)
232 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
233 #define OMAP24XX_EN_GPIOS_SHIFT 2
234 #define OMAP24XX_EN_GPIOS (1 << 2)
235 #define OMAP24XX_EN_GPT1_SHIFT 0
236 #define OMAP24XX_EN_GPT1 (1 << 0)
238 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
239 #define OMAP24XX_ST_GPIOS_SHIFT (1 << 2)
240 #define OMAP24XX_ST_GPIOS_MASK 2
241 #define OMAP24XX_ST_GPT1_SHIFT (1 << 0)
242 #define OMAP24XX_ST_GPT1_MASK 0
244 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
245 #define OMAP2430_ST_MDM_SHIFT (1 << 0)
248 /* 3430 register bits shared between CM & PRM registers */
250 /* CM_REVISION, PRM_REVISION shared bits */
251 #define OMAP3430_REV_SHIFT 0
252 #define OMAP3430_REV_MASK (0xff << 0)
254 /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */
255 #define OMAP3430_AUTOIDLE (1 << 0)
257 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
258 #define OMAP3430_EN_MMC2 (1 << 25)
259 #define OMAP3430_EN_MMC2_SHIFT 25
260 #define OMAP3430_EN_MMC1 (1 << 24)
261 #define OMAP3430_EN_MMC1_SHIFT 24
262 #define OMAP3430_EN_MCSPI4 (1 << 21)
263 #define OMAP3430_EN_MCSPI4_SHIFT 21
264 #define OMAP3430_EN_MCSPI3 (1 << 20)
265 #define OMAP3430_EN_MCSPI3_SHIFT 20
266 #define OMAP3430_EN_MCSPI2 (1 << 19)
267 #define OMAP3430_EN_MCSPI2_SHIFT 19
268 #define OMAP3430_EN_MCSPI1 (1 << 18)
269 #define OMAP3430_EN_MCSPI1_SHIFT 18
270 #define OMAP3430_EN_I2C3 (1 << 17)
271 #define OMAP3430_EN_I2C3_SHIFT 17
272 #define OMAP3430_EN_I2C2 (1 << 16)
273 #define OMAP3430_EN_I2C2_SHIFT 16
274 #define OMAP3430_EN_I2C1 (1 << 15)
275 #define OMAP3430_EN_I2C1_SHIFT 15
276 #define OMAP3430_EN_UART2 (1 << 14)
277 #define OMAP3430_EN_UART2_SHIFT 14
278 #define OMAP3430_EN_UART1 (1 << 13)
279 #define OMAP3430_EN_UART1_SHIFT 13
280 #define OMAP3430_EN_GPT11 (1 << 12)
281 #define OMAP3430_EN_GPT11_SHIFT 12
282 #define OMAP3430_EN_GPT10 (1 << 11)
283 #define OMAP3430_EN_GPT10_SHIFT 11
284 #define OMAP3430_EN_MCBSP5 (1 << 10)
285 #define OMAP3430_EN_MCBSP5_SHIFT 10
286 #define OMAP3430_EN_MCBSP1 (1 << 9)
287 #define OMAP3430_EN_MCBSP1_SHIFT 9
288 #define OMAP3430_EN_FSHOSTUSB (1 << 5)
289 #define OMAP3430_EN_FSHOSTUSB_SHIFT 5
290 #define OMAP3430_EN_D2D (1 << 3)
291 #define OMAP3430_EN_D2D_SHIFT 3
293 /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
294 #define OMAP3430_EN_HSOTGUSB (1 << 4)
295 #define OMAP3430_EN_HSOTGUSB_SHIFT 4
297 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
298 #define OMAP3430_ST_MMC2_SHIFT 25
299 #define OMAP3430_ST_MMC2_MASK (1 << 25)
300 #define OMAP3430_ST_MMC1_SHIFT 24
301 #define OMAP3430_ST_MMC1_MASK (1 << 24)
302 #define OMAP3430_ST_MCSPI4_SHIFT 21
303 #define OMAP3430_ST_MCSPI4_MASK (1 << 21)
304 #define OMAP3430_ST_MCSPI3_SHIFT 20
305 #define OMAP3430_ST_MCSPI3_MASK (1 << 20)
306 #define OMAP3430_ST_MCSPI2_SHIFT 19
307 #define OMAP3430_ST_MCSPI2_MASK (1 << 19)
308 #define OMAP3430_ST_MCSPI1_SHIFT 18
309 #define OMAP3430_ST_MCSPI1_MASK (1 << 18)
310 #define OMAP3430_ST_I2C3_SHIFT 17
311 #define OMAP3430_ST_I2C3_MASK (1 << 17)
312 #define OMAP3430_ST_I2C2_SHIFT 16
313 #define OMAP3430_ST_I2C2_MASK (1 << 16)
314 #define OMAP3430_ST_I2C1_SHIFT 15
315 #define OMAP3430_ST_I2C1_MASK (1 << 15)
316 #define OMAP3430_ST_UART2_SHIFT 14
317 #define OMAP3430_ST_UART2_MASK (1 << 14)
318 #define OMAP3430_ST_UART1_SHIFT 13
319 #define OMAP3430_ST_UART1_MASK (1 << 13)
320 #define OMAP3430_ST_GPT11_SHIFT 12
321 #define OMAP3430_ST_GPT11_MASK (1 << 12)
322 #define OMAP3430_ST_GPT10_SHIFT 11
323 #define OMAP3430_ST_GPT10_MASK (1 << 11)
324 #define OMAP3430_ST_MCBSP5_SHIFT 10
325 #define OMAP3430_ST_MCBSP5_MASK (1 << 10)
326 #define OMAP3430_ST_MCBSP1_SHIFT 9
327 #define OMAP3430_ST_MCBSP1_MASK (1 << 9)
328 #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5
329 #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5)
330 #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4
331 #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4)
332 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5
333 #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5)
334 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4
335 #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4)
336 #define OMAP3430_ST_D2D_SHIFT 3
337 #define OMAP3430_ST_D2D_MASK (1 << 3)
339 /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
340 #define OMAP3430_EN_GPIO1 (1 << 3)
341 #define OMAP3430_EN_GPIO1_SHIFT 3
342 #define OMAP3430_EN_GPT12 (1 << 1)
343 #define OMAP3430_EN_GPT12_SHIFT 1
344 #define OMAP3430_EN_GPT1 (1 << 0)
345 #define OMAP3430_EN_GPT1_SHIFT 0
347 /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */
348 #define OMAP3430_EN_SR2 (1 << 7)
349 #define OMAP3430_EN_SR2_SHIFT 7
350 #define OMAP3430_EN_SR1 (1 << 6)
351 #define OMAP3430_EN_SR1_SHIFT 6
353 /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */
354 #define OMAP3430_EN_GPT12 (1 << 1)
355 #define OMAP3430_EN_GPT12_SHIFT 1
357 /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */
358 #define OMAP3430_ST_SR2_SHIFT 7
359 #define OMAP3430_ST_SR2_MASK (1 << 7)
360 #define OMAP3430_ST_SR1_SHIFT 6
361 #define OMAP3430_ST_SR1_MASK (1 << 6)
362 #define OMAP3430_ST_GPIO1_SHIFT 3
363 #define OMAP3430_ST_GPIO1_MASK (1 << 3)
364 #define OMAP3430_ST_GPT12_SHIFT 1
365 #define OMAP3430_ST_GPT12_MASK (1 << 1)
366 #define OMAP3430_ST_GPT1_SHIFT 0
367 #define OMAP3430_ST_GPT1_MASK (1 << 0)
370 * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM,
371 * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX,
372 * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits
374 #define OMAP3430_EN_MPU (1 << 1)
375 #define OMAP3430_EN_MPU_SHIFT 1
377 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */
378 #define OMAP3430_EN_GPIO6 (1 << 17)
379 #define OMAP3430_EN_GPIO6_SHIFT 17
380 #define OMAP3430_EN_GPIO5 (1 << 16)
381 #define OMAP3430_EN_GPIO5_SHIFT 16
382 #define OMAP3430_EN_GPIO4 (1 << 15)
383 #define OMAP3430_EN_GPIO4_SHIFT 15
384 #define OMAP3430_EN_GPIO3 (1 << 14)
385 #define OMAP3430_EN_GPIO3_SHIFT 14
386 #define OMAP3430_EN_GPIO2 (1 << 13)
387 #define OMAP3430_EN_GPIO2_SHIFT 13
388 #define OMAP3430_EN_UART3 (1 << 11)
389 #define OMAP3430_EN_UART3_SHIFT 11
390 #define OMAP3430_EN_GPT9 (1 << 10)
391 #define OMAP3430_EN_GPT9_SHIFT 10
392 #define OMAP3430_EN_GPT8 (1 << 9)
393 #define OMAP3430_EN_GPT8_SHIFT 9
394 #define OMAP3430_EN_GPT7 (1 << 8)
395 #define OMAP3430_EN_GPT7_SHIFT 8
396 #define OMAP3430_EN_GPT6 (1 << 7)
397 #define OMAP3430_EN_GPT6_SHIFT 7
398 #define OMAP3430_EN_GPT5 (1 << 6)
399 #define OMAP3430_EN_GPT5_SHIFT 6
400 #define OMAP3430_EN_GPT4 (1 << 5)
401 #define OMAP3430_EN_GPT4_SHIFT 5
402 #define OMAP3430_EN_GPT3 (1 << 4)
403 #define OMAP3430_EN_GPT3_SHIFT 4
404 #define OMAP3430_EN_GPT2 (1 << 3)
405 #define OMAP3430_EN_GPT2_SHIFT 3
407 /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */
408 /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits
409 * be ST_* bits instead? */
410 #define OMAP3430_EN_MCBSP4 (1 << 2)
411 #define OMAP3430_EN_MCBSP4_SHIFT 2
412 #define OMAP3430_EN_MCBSP3 (1 << 1)
413 #define OMAP3430_EN_MCBSP3_SHIFT 1
414 #define OMAP3430_EN_MCBSP2 (1 << 0)
415 #define OMAP3430_EN_MCBSP2_SHIFT 0
417 /* CM_IDLEST_PER, PM_WKST_PER shared bits */
418 #define OMAP3430_ST_GPIO6_SHIFT 17
419 #define OMAP3430_ST_GPIO6_MASK (1 << 17)
420 #define OMAP3430_ST_GPIO5_SHIFT 16
421 #define OMAP3430_ST_GPIO5_MASK (1 << 16)
422 #define OMAP3430_ST_GPIO4_SHIFT 15
423 #define OMAP3430_ST_GPIO4_MASK (1 << 15)
424 #define OMAP3430_ST_GPIO3_SHIFT 14
425 #define OMAP3430_ST_GPIO3_MASK (1 << 14)
426 #define OMAP3430_ST_GPIO2_SHIFT 13
427 #define OMAP3430_ST_GPIO2_MASK (1 << 13)
428 #define OMAP3430_ST_UART3_SHIFT 11
429 #define OMAP3430_ST_UART3_MASK (1 << 11)
430 #define OMAP3430_ST_GPT9_SHIFT 10
431 #define OMAP3430_ST_GPT9_MASK (1 << 10)
432 #define OMAP3430_ST_GPT8_SHIFT 9
433 #define OMAP3430_ST_GPT8_MASK (1 << 9)
434 #define OMAP3430_ST_GPT7_SHIFT 8
435 #define OMAP3430_ST_GPT7_MASK (1 << 8)
436 #define OMAP3430_ST_GPT6_SHIFT 7
437 #define OMAP3430_ST_GPT6_MASK (1 << 7)
438 #define OMAP3430_ST_GPT5_SHIFT 6
439 #define OMAP3430_ST_GPT5_MASK (1 << 6)
440 #define OMAP3430_ST_GPT4_SHIFT 5
441 #define OMAP3430_ST_GPT4_MASK (1 << 5)
442 #define OMAP3430_ST_GPT3_SHIFT 4
443 #define OMAP3430_ST_GPT3_MASK (1 << 4)
444 #define OMAP3430_ST_GPT2_SHIFT 3
445 #define OMAP3430_ST_GPT2_MASK (1 << 3)
447 /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */
448 #define OMAP3430_EN_CORE_SHIFT 0
449 #define OMAP3430_EN_CORE_MASK (1 << 0)