2 * OMAP3 powerdomain definitions
4 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
5 * Copyright (C) 2007-2011 Nokia Corporation
7 * Paul Walmsley, Jouni Högander
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
19 #include "powerdomain.h"
20 #include "powerdomains2xxx_3xxx_data.h"
22 #include "prcm-common.h"
23 #include "prm2xxx_3xxx.h"
24 #include "prm-regbits-34xx.h"
25 #include "cm2xxx_3xxx.h"
26 #include "cm-regbits-34xx.h"
29 * 34XX-specific powerdomains, dependencies
36 static struct powerdomain iva2_pwrdm = {
38 .prcm_offs = OMAP3430_IVA2_MOD,
39 .pwrsts = PWRSTS_OFF_RET_ON,
40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
54 .voltdm = { .name = "mpu_iva" },
57 static struct powerdomain mpu_3xxx_pwrdm = {
60 .pwrsts = PWRSTS_OFF_RET_ON,
61 .pwrsts_logic_ret = PWRSTS_OFF_RET,
62 .flags = PWRDM_HAS_MPU_QUIRK,
70 .voltdm = { .name = "mpu_iva" },
74 * The USBTLL Save-and-Restore mechanism is broken on
75 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
76 * needs to be disabled on these chips.
77 * Refer: 3430 errata ID i459 and 3630 errata ID i579
79 * Note: setting the SAR flag could help for errata ID i478
80 * which applies to 3430 <= ES3.1, but since the SAR feature
81 * is broken, do not use it.
83 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
85 .prcm_offs = CORE_MOD,
86 .pwrsts = PWRSTS_OFF_RET_ON,
87 .pwrsts_logic_ret = PWRSTS_OFF_RET,
90 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
91 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
94 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
95 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
97 .voltdm = { .name = "core" },
100 static struct powerdomain core_3xxx_es3_1_pwrdm = {
101 .name = "core_pwrdm",
102 .prcm_offs = CORE_MOD,
103 .pwrsts = PWRSTS_OFF_RET_ON,
104 .pwrsts_logic_ret = PWRSTS_OFF_RET,
106 * Setting the SAR flag for errata ID i478 which applies
109 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
112 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
113 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
116 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
117 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
119 .voltdm = { .name = "core" },
122 static struct powerdomain dss_pwrdm = {
124 .prcm_offs = OMAP3430_DSS_MOD,
125 .pwrsts = PWRSTS_OFF_RET_ON,
126 .pwrsts_logic_ret = PWRSTS_RET,
129 [0] = PWRSTS_RET, /* MEMRETSTATE */
132 [0] = PWRSTS_ON, /* MEMONSTATE */
134 .voltdm = { .name = "core" },
138 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
139 * possible SGX powerstate, the SGX device itself does not support
142 static struct powerdomain sgx_pwrdm = {
144 .prcm_offs = OMAP3430ES2_SGX_MOD,
145 /* XXX This is accurate for 3430 SGX, but what about GFX? */
146 .pwrsts = PWRSTS_OFF_ON,
147 .pwrsts_logic_ret = PWRSTS_RET,
150 [0] = PWRSTS_RET, /* MEMRETSTATE */
153 [0] = PWRSTS_ON, /* MEMONSTATE */
155 .voltdm = { .name = "core" },
158 static struct powerdomain cam_pwrdm = {
160 .prcm_offs = OMAP3430_CAM_MOD,
161 .pwrsts = PWRSTS_OFF_RET_ON,
162 .pwrsts_logic_ret = PWRSTS_RET,
165 [0] = PWRSTS_RET, /* MEMRETSTATE */
168 [0] = PWRSTS_ON, /* MEMONSTATE */
170 .voltdm = { .name = "core" },
173 static struct powerdomain per_pwrdm = {
175 .prcm_offs = OMAP3430_PER_MOD,
176 .pwrsts = PWRSTS_OFF_RET_ON,
177 .pwrsts_logic_ret = PWRSTS_OFF_RET,
180 [0] = PWRSTS_RET, /* MEMRETSTATE */
183 [0] = PWRSTS_ON, /* MEMONSTATE */
185 .voltdm = { .name = "core" },
188 static struct powerdomain emu_pwrdm = {
190 .prcm_offs = OMAP3430_EMU_MOD,
191 .voltdm = { .name = "core" },
194 static struct powerdomain neon_pwrdm = {
195 .name = "neon_pwrdm",
196 .prcm_offs = OMAP3430_NEON_MOD,
197 .pwrsts = PWRSTS_OFF_RET_ON,
198 .pwrsts_logic_ret = PWRSTS_RET,
199 .voltdm = { .name = "mpu_iva" },
202 static struct powerdomain usbhost_pwrdm = {
203 .name = "usbhost_pwrdm",
204 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
205 .pwrsts = PWRSTS_OFF_RET_ON,
206 .pwrsts_logic_ret = PWRSTS_RET,
208 * REVISIT: Enabling usb host save and restore mechanism seems to
209 * leave the usb host domain permanently in ACTIVE mode after
210 * changing the usb host power domain state from OFF to active once.
213 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
216 [0] = PWRSTS_RET, /* MEMRETSTATE */
219 [0] = PWRSTS_ON, /* MEMONSTATE */
221 .voltdm = { .name = "core" },
224 static struct powerdomain dpll1_pwrdm = {
225 .name = "dpll1_pwrdm",
226 .prcm_offs = MPU_MOD,
227 .voltdm = { .name = "mpu_iva" },
230 static struct powerdomain dpll2_pwrdm = {
231 .name = "dpll2_pwrdm",
232 .prcm_offs = OMAP3430_IVA2_MOD,
233 .voltdm = { .name = "mpu_iva" },
236 static struct powerdomain dpll3_pwrdm = {
237 .name = "dpll3_pwrdm",
238 .prcm_offs = PLL_MOD,
239 .voltdm = { .name = "core" },
242 static struct powerdomain dpll4_pwrdm = {
243 .name = "dpll4_pwrdm",
244 .prcm_offs = PLL_MOD,
245 .voltdm = { .name = "core" },
248 static struct powerdomain dpll5_pwrdm = {
249 .name = "dpll5_pwrdm",
250 .prcm_offs = PLL_MOD,
251 .voltdm = { .name = "core" },
254 /* As powerdomains are added or removed above, this list must also be changed */
255 static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
271 static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
273 &core_3xxx_pre_es3_1_pwrdm,
277 /* also includes 3630ES1.0 */
278 static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
279 &core_3xxx_pre_es3_1_pwrdm,
286 /* also includes 3630ES1.1+ */
287 static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
288 &core_3xxx_es3_1_pwrdm,
295 void __init omap3xxx_powerdomains_init(void)
299 if (!cpu_is_omap34xx())
302 pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
303 pwrdm_register_pwrdms(powerdomains_omap3430_common);
307 if (rev == OMAP3430_REV_ES1_0)
308 pwrdm_register_pwrdms(powerdomains_omap3430es1);
309 else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
310 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
311 pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
312 else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
313 rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1 ||
314 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
315 pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
317 WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
319 pwrdm_complete_init();