arch/arm/mach-omap2/powerdomains3xxx_data.c

   1 /*
   2  * OMAP3 powerdomain definitions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley, Jouni Högander
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16
  17 #include <plat/powerdomain.h>
  18 #include "powerdomains2xxx_3xxx_data.h"
  19 #include "powerdomains.h"
  20
  21 #include "prcm-common.h"
  22 #include "prm.h"
  23 #include "prm-regbits-34xx.h"
  24 #include "cm.h"
  25 #include "cm-regbits-34xx.h"
  26
  27 /*
  28  * 34XX-specific powerdomains, dependencies
  29  */
  30
  31 #ifdef CONFIG_ARCH_OMAP3
  32
  33 /*
  34  * Powerdomains
  35  */
  36
  37 static struct powerdomain iva2_pwrdm = {
  38         .name             = "iva2_pwrdm",
  39         .prcm_offs        = OMAP3430_IVA2_MOD,
  40         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  41         .pwrsts           = PWRSTS_OFF_RET_ON,
  42         .pwrsts_logic_ret = PWRSTS_OFF_RET,
  43         .banks            = 4,
  44         .pwrsts_mem_ret   = {
  45                 [0] = PWRSTS_OFF_RET,
  46                 [1] = PWRSTS_OFF_RET,
  47                 [2] = PWRSTS_OFF_RET,
  48                 [3] = PWRSTS_OFF_RET,
  49         },
  50         .pwrsts_mem_on    = {
  51                 [0] = PWRDM_POWER_ON,
  52                 [1] = PWRDM_POWER_ON,
  53                 [2] = PWRSTS_OFF_ON,
  54                 [3] = PWRDM_POWER_ON,
  55         },
  56 };
  57
  58 static struct powerdomain mpu_3xxx_pwrdm = {
  59         .name             = "mpu_pwrdm",
  60         .prcm_offs        = MPU_MOD,
  61         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  62         .pwrsts           = PWRSTS_OFF_RET_ON,
  63         .pwrsts_logic_ret = PWRSTS_OFF_RET,
  64         .flags            = PWRDM_HAS_MPU_QUIRK,
  65         .banks            = 1,
  66         .pwrsts_mem_ret   = {
  67                 [0] = PWRSTS_OFF_RET,
  68         },
  69         .pwrsts_mem_on    = {
  70                 [0] = PWRSTS_OFF_ON,
  71         },
  72 };
  73
  74 /*
  75  * The USBTLL Save-and-Restore mechanism is broken on
  76  * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
  77  * needs to be disabled on these chips.
  78  * Refer: 3430 errata ID i459 and 3630 errata ID i579
  79  *
  80  * Note: setting the SAR flag could help for errata ID i478
  81  *  which applies to 3430 <= ES3.1, but since the SAR feature
  82  *  is broken, do not use it.
  83  */
  84 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
  85         .name             = "core_pwrdm",
  86         .prcm_offs        = CORE_MOD,
  87         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
  88                                            CHIP_IS_OMAP3430ES2 |
  89                                            CHIP_IS_OMAP3430ES3_0 |
  90                                            CHIP_IS_OMAP3630ES1),
  91         .pwrsts           = PWRSTS_OFF_RET_ON,
  92         .pwrsts_logic_ret = PWRSTS_OFF_RET,
  93         .banks            = 2,
  94         .pwrsts_mem_ret   = {
  95                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
  96                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
  97         },
  98         .pwrsts_mem_on    = {
  99                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
 100                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
 101         },
 102 };
 103
 104 static struct powerdomain core_3xxx_es3_1_pwrdm = {
 105         .name             = "core_pwrdm",
 106         .prcm_offs        = CORE_MOD,
 107         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
 108                                           CHIP_GE_OMAP3630ES1_1),
 109         .pwrsts           = PWRSTS_OFF_RET_ON,
 110         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 111         /*
 112          * Setting the SAR flag for errata ID i478 which applies
 113          *  to 3430 <= ES3.1
 114          */
 115         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
 116         .banks            = 2,
 117         .pwrsts_mem_ret   = {
 118                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
 119                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
 120         },
 121         .pwrsts_mem_on    = {
 122                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
 123                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
 124         },
 125 };
 126
 127 static struct powerdomain dss_pwrdm = {
 128         .name             = "dss_pwrdm",
 129         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 130         .prcm_offs        = OMAP3430_DSS_MOD,
 131         .pwrsts           = PWRSTS_OFF_RET_ON,
 132         .pwrsts_logic_ret = PWRDM_POWER_RET,
 133         .banks            = 1,
 134         .pwrsts_mem_ret   = {
 135                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 136         },
 137         .pwrsts_mem_on    = {
 138                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 139         },
 140 };
 141
 142 /*
 143  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 144  * possible SGX powerstate, the SGX device itself does not support
 145  * retention.
 146  */
 147 static struct powerdomain sgx_pwrdm = {
 148         .name             = "sgx_pwrdm",
 149         .prcm_offs        = OMAP3430ES2_SGX_MOD,
 150         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 151         /* XXX This is accurate for 3430 SGX, but what about GFX? */
 152         .pwrsts           = PWRSTS_OFF_ON,
 153         .pwrsts_logic_ret = PWRDM_POWER_RET,
 154         .banks            = 1,
 155         .pwrsts_mem_ret   = {
 156                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 157         },
 158         .pwrsts_mem_on    = {
 159                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 160         },
 161 };
 162
 163 static struct powerdomain cam_pwrdm = {
 164         .name             = "cam_pwrdm",
 165         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 166         .prcm_offs        = OMAP3430_CAM_MOD,
 167         .pwrsts           = PWRSTS_OFF_RET_ON,
 168         .pwrsts_logic_ret = PWRDM_POWER_RET,
 169         .banks            = 1,
 170         .pwrsts_mem_ret   = {
 171                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 172         },
 173         .pwrsts_mem_on    = {
 174                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 175         },
 176 };
 177
 178 static struct powerdomain per_pwrdm = {
 179         .name             = "per_pwrdm",
 180         .prcm_offs        = OMAP3430_PER_MOD,
 181         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 182         .pwrsts           = PWRSTS_OFF_RET_ON,
 183         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 184         .banks            = 1,
 185         .pwrsts_mem_ret   = {
 186                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 187         },
 188         .pwrsts_mem_on    = {
 189                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 190         },
 191 };
 192
 193 static struct powerdomain emu_pwrdm = {
 194         .name           = "emu_pwrdm",
 195         .prcm_offs      = OMAP3430_EMU_MOD,
 196         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 197 };
 198
 199 static struct powerdomain neon_pwrdm = {
 200         .name             = "neon_pwrdm",
 201         .prcm_offs        = OMAP3430_NEON_MOD,
 202         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 203         .pwrsts           = PWRSTS_OFF_RET_ON,
 204         .pwrsts_logic_ret = PWRDM_POWER_RET,
 205 };
 206
 207 static struct powerdomain usbhost_pwrdm = {
 208         .name             = "usbhost_pwrdm",
 209         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
 210         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 211         .pwrsts           = PWRSTS_OFF_RET_ON,
 212         .pwrsts_logic_ret = PWRDM_POWER_RET,
 213         /*
 214          * REVISIT: Enabling usb host save and restore mechanism seems to
 215          * leave the usb host domain permanently in ACTIVE mode after
 216          * changing the usb host power domain state from OFF to active once.
 217          * Disabling for now.
 218          */
 219         /*.flags          = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
 220         .banks            = 1,
 221         .pwrsts_mem_ret   = {
 222                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 223         },
 224         .pwrsts_mem_on    = {
 225                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 226         },
 227 };
 228
 229 static struct powerdomain dpll1_pwrdm = {
 230         .name           = "dpll1_pwrdm",
 231         .prcm_offs      = MPU_MOD,
 232         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 233 };
 234
 235 static struct powerdomain dpll2_pwrdm = {
 236         .name           = "dpll2_pwrdm",
 237         .prcm_offs      = OMAP3430_IVA2_MOD,
 238         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 239 };
 240
 241 static struct powerdomain dpll3_pwrdm = {
 242         .name           = "dpll3_pwrdm",
 243         .prcm_offs      = PLL_MOD,
 244         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 245 };
 246
 247 static struct powerdomain dpll4_pwrdm = {
 248         .name           = "dpll4_pwrdm",
 249         .prcm_offs      = PLL_MOD,
 250         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 251 };
 252
 253 static struct powerdomain dpll5_pwrdm = {
 254         .name           = "dpll5_pwrdm",
 255         .prcm_offs      = PLL_MOD,
 256         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 257 };
 258
 259 /* As powerdomains are added or removed above, this list must also be changed */
 260 static struct powerdomain *powerdomains_omap3xxx[] __initdata = {
 261
 262         &wkup_omap2_pwrdm,
 263         &gfx_omap2_pwrdm,
 264         &iva2_pwrdm,
 265         &mpu_3xxx_pwrdm,
 266         &neon_pwrdm,
 267         &core_3xxx_pre_es3_1_pwrdm,
 268         &core_3xxx_es3_1_pwrdm,
 269         &cam_pwrdm,
 270         &dss_pwrdm,
 271         &per_pwrdm,
 272         &emu_pwrdm,
 273         &sgx_pwrdm,
 274         &usbhost_pwrdm,
 275         &dpll1_pwrdm,
 276         &dpll2_pwrdm,
 277         &dpll3_pwrdm,
 278         &dpll4_pwrdm,
 279         &dpll5_pwrdm,
 280 #endif
 281         NULL
 282 };
 283
 284
 285 void __init omap3xxx_powerdomains_init(void)
 286 {
 287         pwrdm_init(powerdomains_omap3xxx, &omap3_pwrdm_operations);
 288 }