2 * OMAP3 powerdomain definitions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * Debugging and integration fixes by Jouni Högander
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
16 #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
19 * N.B. If powerdomains are added or removed from this file, update
20 * the array in mach-omap2/powerdomains.h.
23 #include <plat/powerdomain.h>
25 #include "prcm-common.h"
27 #include "prm-regbits-34xx.h"
29 #include "cm-regbits-34xx.h"
32 * 34XX-specific powerdomains, dependencies
35 #ifdef CONFIG_ARCH_OMAP3
41 static struct powerdomain iva2_pwrdm = {
43 .prcm_offs = OMAP3430_IVA2_MOD,
44 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
45 .pwrsts = PWRSTS_OFF_RET_ON,
46 .pwrsts_logic_ret = PWRSTS_OFF_RET,
62 static struct powerdomain mpu_3xxx_pwrdm = {
65 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
66 .pwrsts = PWRSTS_OFF_RET_ON,
67 .pwrsts_logic_ret = PWRSTS_OFF_RET,
68 .flags = PWRDM_HAS_MPU_QUIRK,
78 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
80 .prcm_offs = CORE_MOD,
81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
83 CHIP_IS_OMAP3430ES3_0),
84 .pwrsts = PWRSTS_OFF_RET_ON,
85 .pwrsts_logic_ret = PWRSTS_OFF_RET,
88 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
89 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
92 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
93 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
97 static struct powerdomain core_3xxx_es3_1_pwrdm = {
99 .prcm_offs = CORE_MOD,
100 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
101 .pwrsts = PWRSTS_OFF_RET_ON,
102 .pwrsts_logic_ret = PWRSTS_OFF_RET,
103 .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
106 [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
107 [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
110 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
111 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
115 static struct powerdomain dss_pwrdm = {
117 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
118 .prcm_offs = OMAP3430_DSS_MOD,
119 .pwrsts = PWRSTS_OFF_RET_ON,
120 .pwrsts_logic_ret = PWRDM_POWER_RET,
123 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
126 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
131 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
132 * possible SGX powerstate, the SGX device itself does not support
135 static struct powerdomain sgx_pwrdm = {
137 .prcm_offs = OMAP3430ES2_SGX_MOD,
138 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
139 /* XXX This is accurate for 3430 SGX, but what about GFX? */
140 .pwrsts = PWRSTS_OFF_ON,
141 .pwrsts_logic_ret = PWRDM_POWER_RET,
144 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
147 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
151 static struct powerdomain cam_pwrdm = {
153 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
154 .prcm_offs = OMAP3430_CAM_MOD,
155 .pwrsts = PWRSTS_OFF_RET_ON,
156 .pwrsts_logic_ret = PWRDM_POWER_RET,
159 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
162 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
166 static struct powerdomain per_pwrdm = {
168 .prcm_offs = OMAP3430_PER_MOD,
169 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
170 .pwrsts = PWRSTS_OFF_RET_ON,
171 .pwrsts_logic_ret = PWRSTS_OFF_RET,
174 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
177 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
181 static struct powerdomain emu_pwrdm = {
183 .prcm_offs = OMAP3430_EMU_MOD,
184 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
187 static struct powerdomain neon_pwrdm = {
188 .name = "neon_pwrdm",
189 .prcm_offs = OMAP3430_NEON_MOD,
190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
191 .pwrsts = PWRSTS_OFF_RET_ON,
192 .pwrsts_logic_ret = PWRDM_POWER_RET,
195 static struct powerdomain usbhost_pwrdm = {
196 .name = "usbhost_pwrdm",
197 .prcm_offs = OMAP3430ES2_USBHOST_MOD,
198 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
199 .pwrsts = PWRSTS_OFF_RET_ON,
200 .pwrsts_logic_ret = PWRDM_POWER_RET,
202 * REVISIT: Enabling usb host save and restore mechanism seems to
203 * leave the usb host domain permanently in ACTIVE mode after
204 * changing the usb host power domain state from OFF to active once.
207 /*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
210 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
213 [0] = PWRDM_POWER_ON, /* MEMONSTATE */
217 static struct powerdomain dpll1_pwrdm = {
218 .name = "dpll1_pwrdm",
219 .prcm_offs = MPU_MOD,
220 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
223 static struct powerdomain dpll2_pwrdm = {
224 .name = "dpll2_pwrdm",
225 .prcm_offs = OMAP3430_IVA2_MOD,
226 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
229 static struct powerdomain dpll3_pwrdm = {
230 .name = "dpll3_pwrdm",
231 .prcm_offs = PLL_MOD,
232 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
235 static struct powerdomain dpll4_pwrdm = {
236 .name = "dpll4_pwrdm",
237 .prcm_offs = PLL_MOD,
238 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
241 static struct powerdomain dpll5_pwrdm = {
242 .name = "dpll5_pwrdm",
243 .prcm_offs = PLL_MOD,
244 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
248 #endif /* CONFIG_ARCH_OMAP3 */