2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/console.h>
32 #include <trace/events/power.h>
34 #include <asm/suspend.h>
36 #include <plat/sram.h>
37 #include "clockdomain.h"
38 #include "powerdomain.h"
39 #include <plat/serial.h>
40 #include <plat/sdrc.h>
41 #include <plat/prcm.h>
42 #include <plat/gpmc.h>
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
49 #include "prm2xxx_3xxx.h"
55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
56 static inline bool is_suspending(void)
58 return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
61 static inline bool is_suspending(void)
67 /* pm34xx errata defined in pm.h */
71 struct powerdomain *pwrdm;
76 struct list_head node;
79 static LIST_HEAD(pwrst_list);
81 static int (*_omap_save_secure_sram)(u32 *addr);
82 void (*omap3_do_wfi_sram)(void);
84 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
85 static struct powerdomain *core_pwrdm, *per_pwrdm;
87 static inline void omap3_per_save_context(void)
89 omap_gpio_save_context();
92 static inline void omap3_per_restore_context(void)
94 omap_gpio_restore_context();
97 static void omap3_enable_io_chain(void)
101 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
103 /* Do a readback to assure write has been done */
104 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
106 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
107 OMAP3430_ST_IO_CHAIN_MASK)) {
109 if (timeout > 1000) {
110 pr_err("Wake up daisy chain activation failed.\n");
113 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
118 static void omap3_disable_io_chain(void)
120 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
124 static void omap3_core_save_context(void)
126 omap3_ctrl_save_padconf();
129 * Force write last pad into memory, as this can fail in some
130 * cases according to errata 1.157, 1.185
132 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
133 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
135 /* Save the Interrupt controller context */
136 omap_intc_save_context();
137 /* Save the GPMC context */
138 omap3_gpmc_save_context();
139 /* Save the system control module context, padconf already save above*/
140 omap3_control_save_context();
141 omap_dma_global_context_save();
144 static void omap3_core_restore_context(void)
146 /* Restore the control module context, padconf restored by h/w */
147 omap3_control_restore_context();
148 /* Restore the GPMC context */
149 omap3_gpmc_restore_context();
150 /* Restore the interrupt controller context */
151 omap_intc_restore_context();
152 omap_dma_global_context_restore();
156 * FIXME: This function should be called before entering off-mode after
157 * OMAP3 secure services have been accessed. Currently it is only called
158 * once during boot sequence, but this works as we are not using secure
161 static void omap3_save_secure_ram_context(void)
164 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
166 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
168 * MPU next state must be set to POWER_ON temporarily,
169 * otherwise the WFI executed inside the ROM code
170 * will hang the system.
172 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
173 ret = _omap_save_secure_sram((u32 *)
174 __pa(omap3_secure_ram_storage));
175 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
176 /* Following is for error tracking, it should not happen */
178 printk(KERN_ERR "save_secure_sram() returns %08x\n",
187 * PRCM Interrupt Handler Helper Function
189 * The purpose of this function is to clear any wake-up events latched
190 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
191 * may occur whilst attempting to clear a PM_WKST_x register and thus
192 * set another bit in this register. A while loop is used to ensure
193 * that any peripheral wake-up events occurring while attempting to
194 * clear the PM_WKST_x are detected and cleared.
196 static int prcm_clear_mod_irqs(s16 module, u8 regs)
198 u32 wkst, fclk, iclk, clken;
199 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
200 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
201 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
202 u16 grpsel_off = (regs == 3) ?
203 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
206 wkst = omap2_prm_read_mod_reg(module, wkst_off);
207 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
209 iclk = omap2_cm_read_mod_reg(module, iclk_off);
210 fclk = omap2_cm_read_mod_reg(module, fclk_off);
213 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
215 * For USBHOST, we don't know whether HOST1 or
216 * HOST2 woke us up, so enable both f-clocks
218 if (module == OMAP3430ES2_USBHOST_MOD)
219 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
220 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
221 omap2_prm_write_mod_reg(wkst, module, wkst_off);
222 wkst = omap2_prm_read_mod_reg(module, wkst_off);
225 omap2_cm_write_mod_reg(iclk, module, iclk_off);
226 omap2_cm_write_mod_reg(fclk, module, fclk_off);
232 static int _prcm_int_handle_wakeup(void)
236 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
237 c += prcm_clear_mod_irqs(CORE_MOD, 1);
238 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
239 if (omap_rev() > OMAP3430_REV_ES1_0) {
240 c += prcm_clear_mod_irqs(CORE_MOD, 3);
241 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
248 * PRCM Interrupt Handler
250 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
251 * interrupts from the PRCM for the MPU. These bits must be cleared in
252 * order to clear the PRCM interrupt. The PRCM interrupt handler is
253 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
254 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
255 * register indicates that a wake-up event is pending for the MPU and
256 * this bit can only be cleared if the all the wake-up events latched
257 * in the various PM_WKST_x registers have been cleared. The interrupt
258 * handler is implemented using a do-while loop so that if a wake-up
259 * event occurred during the processing of the prcm interrupt handler
260 * (setting a bit in the corresponding PM_WKST_x register and thus
261 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
262 * this would be handled.
264 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
266 u32 irqenable_mpu, irqstatus_mpu;
269 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
270 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
271 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
272 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
273 irqstatus_mpu &= irqenable_mpu;
276 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
277 OMAP3430_IO_ST_MASK)) {
278 c = _prcm_int_handle_wakeup();
281 * Is the MPU PRCM interrupt handler racing with the
282 * IVA2 PRCM interrupt handler ?
284 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
285 "but no wakeup sources are marked\n");
287 /* XXX we need to expand our PRCM interrupt handler */
288 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
289 "no code to handle it (%08x)\n", irqstatus_mpu);
292 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
293 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
295 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
296 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
297 irqstatus_mpu &= irqenable_mpu;
299 } while (irqstatus_mpu);
304 static void omap34xx_save_context(u32 *save)
308 /* Read Auxiliary Control Register */
309 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
313 /* Read L2 AUX ctrl register */
314 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
319 static int omap34xx_do_sram_idle(unsigned long save_state)
321 omap34xx_cpu_suspend(save_state);
325 void omap_sram_idle(void)
327 /* Variable to tell what needs to be saved and restored
328 * in omap_sram_idle*/
329 /* save_state = 0 => Nothing to save and restored */
330 /* save_state = 1 => Only L1 and logic lost */
331 /* save_state = 2 => Only L2 lost */
332 /* save_state = 3 => L1, L2 and logic lost */
334 int mpu_next_state = PWRDM_POWER_ON;
335 int per_next_state = PWRDM_POWER_ON;
336 int core_next_state = PWRDM_POWER_ON;
338 int core_prev_state, per_prev_state;
341 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
342 switch (mpu_next_state) {
344 case PWRDM_POWER_RET:
345 /* No need to save context */
348 case PWRDM_POWER_OFF:
353 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
358 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
359 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
361 /* Enable IO-PAD and IO-CHAIN wakeups */
362 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
363 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
364 if (omap3_has_io_wakeup() &&
365 (per_next_state < PWRDM_POWER_ON ||
366 core_next_state < PWRDM_POWER_ON)) {
367 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
368 if (omap3_has_io_chain_ctrl())
369 omap3_enable_io_chain();
372 /* Block console output in case it is on one of the OMAP UARTs */
373 if (!is_suspending())
374 if (per_next_state < PWRDM_POWER_ON ||
375 core_next_state < PWRDM_POWER_ON)
376 if (!console_trylock())
377 goto console_still_active;
379 if (mpu_next_state < PWRDM_POWER_ON)
380 pwrdm_pre_transition(mpu_pwrdm);
383 if (per_next_state < PWRDM_POWER_ON) {
384 pwrdm_pre_transition(per_pwrdm);
385 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
386 omap_uart_prepare_idle(2);
387 omap_uart_prepare_idle(3);
388 omap2_gpio_prepare_for_idle(per_going_off);
389 if (per_next_state == PWRDM_POWER_OFF)
390 omap3_per_save_context();
394 if (core_next_state < PWRDM_POWER_ON) {
395 omap_uart_prepare_idle(0);
396 omap_uart_prepare_idle(1);
397 pwrdm_pre_transition(core_pwrdm);
398 if (core_next_state == PWRDM_POWER_OFF) {
399 omap3_core_save_context();
400 omap3_cm_save_context();
404 omap3_intc_prepare_idle();
407 * On EMU/HS devices ROM code restores a SRDC value
408 * from scratchpad which has automatic self refresh on timeout
409 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
410 * Hence store/restore the SDRC_POWER register here.
412 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
413 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
414 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
415 core_next_state == PWRDM_POWER_OFF)
416 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
419 * omap3_arm_context is the location where some ARM context
420 * get saved. The rest is placed on the stack, and restored
421 * from there before resuming.
424 omap34xx_save_context(omap3_arm_context);
425 if (save_state == 1 || save_state == 3)
426 cpu_suspend(save_state, omap34xx_do_sram_idle);
428 omap34xx_do_sram_idle(save_state);
430 /* Restore normal SDRC POWER settings */
431 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
432 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
433 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
434 core_next_state == PWRDM_POWER_OFF)
435 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
438 if (core_next_state < PWRDM_POWER_ON) {
439 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
440 if (core_prev_state == PWRDM_POWER_OFF) {
441 omap3_core_restore_context();
442 omap3_cm_restore_context();
443 omap3_sram_restore_context();
444 omap2_sms_restore_context();
446 omap_uart_resume_idle(0);
447 omap_uart_resume_idle(1);
448 if (core_next_state == PWRDM_POWER_OFF)
449 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
451 OMAP3_PRM_VOLTCTRL_OFFSET);
452 pwrdm_post_transition(core_pwrdm);
454 omap3_intc_resume_idle();
457 if (per_next_state < PWRDM_POWER_ON) {
458 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
459 omap2_gpio_resume_after_idle();
460 if (per_prev_state == PWRDM_POWER_OFF)
461 omap3_per_restore_context();
462 omap_uart_resume_idle(2);
463 omap_uart_resume_idle(3);
464 pwrdm_post_transition(per_pwrdm);
467 if (!is_suspending())
470 console_still_active:
471 /* Disable IO-PAD and IO-CHAIN wakeup */
472 if (omap3_has_io_wakeup() &&
473 (per_next_state < PWRDM_POWER_ON ||
474 core_next_state < PWRDM_POWER_ON)) {
475 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
477 if (omap3_has_io_chain_ctrl())
478 omap3_disable_io_chain();
481 if (mpu_next_state < PWRDM_POWER_ON)
482 pwrdm_post_transition(mpu_pwrdm);
485 static void omap3_pm_idle(void)
489 if (omap_irq_pending() || need_resched())
492 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
493 trace_cpu_idle(1, smp_processor_id());
497 trace_power_end(smp_processor_id());
498 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
504 #ifdef CONFIG_SUSPEND
505 static int omap3_pm_suspend(void)
507 struct power_state *pwrst;
510 /* Read current next_pwrsts */
511 list_for_each_entry(pwrst, &pwrst_list, node)
512 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
513 /* Set ones wanted by suspend */
514 list_for_each_entry(pwrst, &pwrst_list, node) {
515 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
517 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
521 omap_uart_prepare_suspend();
522 omap3_intc_suspend();
527 /* Restore next_pwrsts */
528 list_for_each_entry(pwrst, &pwrst_list, node) {
529 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
530 if (state > pwrst->next_state) {
531 printk(KERN_INFO "Powerdomain (%s) didn't enter "
533 pwrst->pwrdm->name, pwrst->next_state);
536 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
539 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
541 printk(KERN_INFO "Successfully put all powerdomains "
542 "to target state\n");
547 static int omap3_pm_enter(suspend_state_t unused)
551 switch (suspend_state) {
552 case PM_SUSPEND_STANDBY:
554 ret = omap3_pm_suspend();
563 /* Hooks to enable / disable UART interrupts during suspend */
564 static int omap3_pm_begin(suspend_state_t state)
567 suspend_state = state;
568 omap_uart_enable_irqs(0);
572 static void omap3_pm_end(void)
574 suspend_state = PM_SUSPEND_ON;
575 omap_uart_enable_irqs(1);
580 static const struct platform_suspend_ops omap_pm_ops = {
581 .begin = omap3_pm_begin,
583 .enter = omap3_pm_enter,
584 .valid = suspend_valid_only_mem,
586 #endif /* CONFIG_SUSPEND */
590 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
593 * In cases where IVA2 is activated by bootcode, it may prevent
594 * full-chip retention or off-mode because it is not idle. This
595 * function forces the IVA2 into idle state so it can go
596 * into retention/off and thus allow full-chip retention/off.
599 static void __init omap3_iva_idle(void)
601 /* ensure IVA2 clock is disabled */
602 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
604 /* if no clock activity, nothing else to do */
605 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
606 OMAP3430_CLKACTIVITY_IVA2_MASK))
610 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
611 OMAP3430_RST2_IVA2_MASK |
612 OMAP3430_RST3_IVA2_MASK,
613 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
615 /* Enable IVA2 clock */
616 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
617 OMAP3430_IVA2_MOD, CM_FCLKEN);
619 /* Set IVA2 boot mode to 'idle' */
620 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
621 OMAP343X_CONTROL_IVA2_BOOTMOD);
624 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
626 /* Disable IVA2 clock */
627 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
630 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
631 OMAP3430_RST2_IVA2_MASK |
632 OMAP3430_RST3_IVA2_MASK,
633 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
636 static void __init omap3_d2d_idle(void)
640 /* In a stand alone OMAP3430 where there is not a stacked
641 * modem for the D2D Idle Ack and D2D MStandby must be pulled
642 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
643 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
644 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
645 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
647 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
649 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
651 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
654 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
655 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
656 CORE_MOD, OMAP2_RM_RSTCTRL);
657 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
660 static void __init prcm_setup_regs(void)
662 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
663 OMAP3630_EN_UART4_MASK : 0;
664 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
665 OMAP3630_GRPSEL_UART4_MASK : 0;
667 /* XXX This should be handled by hwmod code or SCM init code */
668 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
671 * Enable control of expternal oscillator through
672 * sys_clkreq. In the long run clock framework should
675 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
676 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
678 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
680 /* setup wakup source */
681 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
682 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
684 /* No need to write EN_IO, that is always enabled */
685 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
686 OMAP3430_GRPSEL_GPT1_MASK |
687 OMAP3430_GRPSEL_GPT12_MASK,
688 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
689 /* For some reason IO doesn't generate wakeup event even if
690 * it is selected to mpu wakeup goup */
691 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
692 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
694 /* Enable PM_WKEN to support DSS LPR */
695 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
696 OMAP3430_DSS_MOD, PM_WKEN);
698 /* Enable wakeups in PER */
699 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
700 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
701 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
702 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
703 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
704 OMAP3430_EN_MCBSP4_MASK,
705 OMAP3430_PER_MOD, PM_WKEN);
706 /* and allow them to wake up MPU */
707 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
708 OMAP3430_GRPSEL_GPIO2_MASK |
709 OMAP3430_GRPSEL_GPIO3_MASK |
710 OMAP3430_GRPSEL_GPIO4_MASK |
711 OMAP3430_GRPSEL_GPIO5_MASK |
712 OMAP3430_GRPSEL_GPIO6_MASK |
713 OMAP3430_GRPSEL_UART3_MASK |
714 OMAP3430_GRPSEL_MCBSP2_MASK |
715 OMAP3430_GRPSEL_MCBSP3_MASK |
716 OMAP3430_GRPSEL_MCBSP4_MASK,
717 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
719 /* Don't attach IVA interrupts */
720 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
721 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
722 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
723 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
725 /* Clear any pending 'reset' flags */
726 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
727 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
728 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
729 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
730 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
731 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
732 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
734 /* Clear any pending PRCM interrupts */
735 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
741 void omap3_pm_off_mode_enable(int enable)
743 struct power_state *pwrst;
747 state = PWRDM_POWER_OFF;
749 state = PWRDM_POWER_RET;
751 list_for_each_entry(pwrst, &pwrst_list, node) {
752 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
753 pwrst->pwrdm == core_pwrdm &&
754 state == PWRDM_POWER_OFF) {
755 pwrst->next_state = PWRDM_POWER_RET;
756 pr_warn("%s: Core OFF disabled due to errata i583\n",
759 pwrst->next_state = state;
761 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
765 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
767 struct power_state *pwrst;
769 list_for_each_entry(pwrst, &pwrst_list, node) {
770 if (pwrst->pwrdm == pwrdm)
771 return pwrst->next_state;
776 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
778 struct power_state *pwrst;
780 list_for_each_entry(pwrst, &pwrst_list, node) {
781 if (pwrst->pwrdm == pwrdm) {
782 pwrst->next_state = state;
789 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
791 struct power_state *pwrst;
796 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
799 pwrst->pwrdm = pwrdm;
800 pwrst->next_state = PWRDM_POWER_RET;
801 list_add(&pwrst->node, &pwrst_list);
803 if (pwrdm_has_hdwr_sar(pwrdm))
804 pwrdm_enable_hdwr_sar(pwrdm);
806 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
810 * Enable hw supervised mode for all clockdomains if it's
811 * supported. Initiate sleep transition for other clockdomains, if
814 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
816 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
817 clkdm_allow_idle(clkdm);
818 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
819 atomic_read(&clkdm->usecount) == 0)
825 * Push functions to SRAM
827 * The minimum set of functions is pushed to SRAM for execution:
828 * - omap3_do_wfi for erratum i581 WA,
829 * - save_secure_ram_context for security extensions.
831 void omap_push_sram_idle(void)
833 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
835 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
836 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
837 save_secure_ram_context_sz);
840 static void __init pm_errata_configure(void)
842 if (cpu_is_omap3630()) {
843 pm34xx_errata |= PM_RTA_ERRATUM_i608;
844 /* Enable the l2 cache toggling in sleep logic */
845 enable_omap3630_toggle_l2_on_restore();
846 if (omap_rev() < OMAP3630_REV_ES1_2)
847 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
851 static int __init omap3_pm_init(void)
853 struct power_state *pwrst, *tmp;
854 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
857 if (!cpu_is_omap34xx())
860 if (!omap3_has_io_chain_ctrl())
861 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
863 pm_errata_configure();
865 /* XXX prcm_setup_regs needs to be before enabling hw
866 * supervised mode for powerdomains */
869 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
870 (irq_handler_t)prcm_interrupt_handler,
871 IRQF_DISABLED, "prcm", NULL);
873 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
874 INT_34XX_PRCM_MPU_IRQ);
878 ret = pwrdm_for_each(pwrdms_setup, NULL);
880 printk(KERN_ERR "Failed to setup powerdomains\n");
884 (void) clkdm_for_each(clkdms_setup, NULL);
886 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
887 if (mpu_pwrdm == NULL) {
888 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
892 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
893 per_pwrdm = pwrdm_lookup("per_pwrdm");
894 core_pwrdm = pwrdm_lookup("core_pwrdm");
896 neon_clkdm = clkdm_lookup("neon_clkdm");
897 mpu_clkdm = clkdm_lookup("mpu_clkdm");
898 per_clkdm = clkdm_lookup("per_clkdm");
899 core_clkdm = clkdm_lookup("core_clkdm");
901 #ifdef CONFIG_SUSPEND
902 suspend_set_ops(&omap_pm_ops);
903 #endif /* CONFIG_SUSPEND */
905 pm_idle = omap3_pm_idle;
909 * RTA is disabled during initialization as per erratum i608
910 * it is safer to disable RTA by the bootloader, but we would like
911 * to be doubly sure here and prevent any mishaps.
913 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
914 omap3630_ctrl_disable_rta();
916 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
917 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
918 omap3_secure_ram_storage =
919 kmalloc(0x803F, GFP_KERNEL);
920 if (!omap3_secure_ram_storage)
921 printk(KERN_ERR "Memory allocation failed when"
922 "allocating for secure sram context\n");
926 omap_dma_global_context_save();
927 omap3_save_secure_ram_context();
928 omap_dma_global_context_restore();
933 omap3_save_scratchpad_contents();
937 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
938 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
939 list_del(&pwrst->node);
945 late_initcall(omap3_pm_init);