2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/console.h>
32 #include <trace/events/power.h>
34 #include <asm/suspend.h>
36 #include <plat/sram.h>
37 #include "clockdomain.h"
38 #include "powerdomain.h"
39 #include <plat/serial.h>
40 #include <plat/sdrc.h>
41 #include <plat/prcm.h>
42 #include <plat/gpmc.h>
45 #include "cm2xxx_3xxx.h"
46 #include "cm-regbits-34xx.h"
47 #include "prm-regbits-34xx.h"
49 #include "prm2xxx_3xxx.h"
55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
56 static inline bool is_suspending(void)
58 return (suspend_state != PM_SUSPEND_ON);
61 static inline bool is_suspending(void)
67 /* pm34xx errata defined in pm.h */
71 struct powerdomain *pwrdm;
76 struct list_head node;
79 static LIST_HEAD(pwrst_list);
81 static int (*_omap_save_secure_sram)(u32 *addr);
82 void (*omap3_do_wfi_sram)(void);
84 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
85 static struct powerdomain *core_pwrdm, *per_pwrdm;
86 static struct powerdomain *cam_pwrdm;
88 static inline void omap3_per_save_context(void)
90 omap_gpio_save_context();
93 static inline void omap3_per_restore_context(void)
95 omap_gpio_restore_context();
98 static void omap3_enable_io_chain(void)
102 if (omap_rev() >= OMAP3430_REV_ES3_1) {
103 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
105 /* Do a readback to assure write has been done */
106 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
108 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
109 OMAP3430_ST_IO_CHAIN_MASK)) {
111 if (timeout > 1000) {
112 printk(KERN_ERR "Wake up daisy chain "
113 "activation failed.\n");
116 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
122 static void omap3_disable_io_chain(void)
124 if (omap_rev() >= OMAP3430_REV_ES3_1)
125 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
129 static void omap3_core_save_context(void)
131 omap3_ctrl_save_padconf();
134 * Force write last pad into memory, as this can fail in some
135 * cases according to errata 1.157, 1.185
137 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
138 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
140 /* Save the Interrupt controller context */
141 omap_intc_save_context();
142 /* Save the GPMC context */
143 omap3_gpmc_save_context();
144 /* Save the system control module context, padconf already save above*/
145 omap3_control_save_context();
146 omap_dma_global_context_save();
149 static void omap3_core_restore_context(void)
151 /* Restore the control module context, padconf restored by h/w */
152 omap3_control_restore_context();
153 /* Restore the GPMC context */
154 omap3_gpmc_restore_context();
155 /* Restore the interrupt controller context */
156 omap_intc_restore_context();
157 omap_dma_global_context_restore();
161 * FIXME: This function should be called before entering off-mode after
162 * OMAP3 secure services have been accessed. Currently it is only called
163 * once during boot sequence, but this works as we are not using secure
166 static void omap3_save_secure_ram_context(void)
169 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
171 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
173 * MPU next state must be set to POWER_ON temporarily,
174 * otherwise the WFI executed inside the ROM code
175 * will hang the system.
177 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
178 ret = _omap_save_secure_sram((u32 *)
179 __pa(omap3_secure_ram_storage));
180 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
181 /* Following is for error tracking, it should not happen */
183 printk(KERN_ERR "save_secure_sram() returns %08x\n",
192 * PRCM Interrupt Handler Helper Function
194 * The purpose of this function is to clear any wake-up events latched
195 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
196 * may occur whilst attempting to clear a PM_WKST_x register and thus
197 * set another bit in this register. A while loop is used to ensure
198 * that any peripheral wake-up events occurring while attempting to
199 * clear the PM_WKST_x are detected and cleared.
201 static int prcm_clear_mod_irqs(s16 module, u8 regs)
203 u32 wkst, fclk, iclk, clken;
204 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
205 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
206 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
207 u16 grpsel_off = (regs == 3) ?
208 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
211 wkst = omap2_prm_read_mod_reg(module, wkst_off);
212 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
214 iclk = omap2_cm_read_mod_reg(module, iclk_off);
215 fclk = omap2_cm_read_mod_reg(module, fclk_off);
218 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
220 * For USBHOST, we don't know whether HOST1 or
221 * HOST2 woke us up, so enable both f-clocks
223 if (module == OMAP3430ES2_USBHOST_MOD)
224 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
225 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
226 omap2_prm_write_mod_reg(wkst, module, wkst_off);
227 wkst = omap2_prm_read_mod_reg(module, wkst_off);
230 omap2_cm_write_mod_reg(iclk, module, iclk_off);
231 omap2_cm_write_mod_reg(fclk, module, fclk_off);
237 static int _prcm_int_handle_wakeup(void)
241 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
242 c += prcm_clear_mod_irqs(CORE_MOD, 1);
243 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
244 if (omap_rev() > OMAP3430_REV_ES1_0) {
245 c += prcm_clear_mod_irqs(CORE_MOD, 3);
246 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
253 * PRCM Interrupt Handler
255 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
256 * interrupts from the PRCM for the MPU. These bits must be cleared in
257 * order to clear the PRCM interrupt. The PRCM interrupt handler is
258 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
259 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
260 * register indicates that a wake-up event is pending for the MPU and
261 * this bit can only be cleared if the all the wake-up events latched
262 * in the various PM_WKST_x registers have been cleared. The interrupt
263 * handler is implemented using a do-while loop so that if a wake-up
264 * event occurred during the processing of the prcm interrupt handler
265 * (setting a bit in the corresponding PM_WKST_x register and thus
266 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
267 * this would be handled.
269 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
271 u32 irqenable_mpu, irqstatus_mpu;
274 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
275 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
276 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
277 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
278 irqstatus_mpu &= irqenable_mpu;
281 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
282 OMAP3430_IO_ST_MASK)) {
283 c = _prcm_int_handle_wakeup();
286 * Is the MPU PRCM interrupt handler racing with the
287 * IVA2 PRCM interrupt handler ?
289 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
290 "but no wakeup sources are marked\n");
292 /* XXX we need to expand our PRCM interrupt handler */
293 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
294 "no code to handle it (%08x)\n", irqstatus_mpu);
297 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
298 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
300 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
301 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
302 irqstatus_mpu &= irqenable_mpu;
304 } while (irqstatus_mpu);
309 static void omap34xx_save_context(u32 *save)
313 /* Read Auxiliary Control Register */
314 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
318 /* Read L2 AUX ctrl register */
319 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
324 static int omap34xx_do_sram_idle(unsigned long save_state)
326 omap34xx_cpu_suspend(save_state);
330 void omap_sram_idle(void)
332 /* Variable to tell what needs to be saved and restored
333 * in omap_sram_idle*/
334 /* save_state = 0 => Nothing to save and restored */
335 /* save_state = 1 => Only L1 and logic lost */
336 /* save_state = 2 => Only L2 lost */
337 /* save_state = 3 => L1, L2 and logic lost */
339 int mpu_next_state = PWRDM_POWER_ON;
340 int per_next_state = PWRDM_POWER_ON;
341 int core_next_state = PWRDM_POWER_ON;
343 int core_prev_state, per_prev_state;
346 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
347 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
348 pwrdm_clear_all_prev_pwrst(core_pwrdm);
349 pwrdm_clear_all_prev_pwrst(per_pwrdm);
351 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
352 switch (mpu_next_state) {
354 case PWRDM_POWER_RET:
355 /* No need to save context */
358 case PWRDM_POWER_OFF:
363 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
366 pwrdm_pre_transition();
369 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
370 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
372 /* Enable IO-PAD and IO-CHAIN wakeups */
373 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
374 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
375 if (omap3_has_io_wakeup() &&
376 (per_next_state < PWRDM_POWER_ON ||
377 core_next_state < PWRDM_POWER_ON)) {
378 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
379 omap3_enable_io_chain();
382 /* Block console output in case it is on one of the OMAP UARTs */
383 if (!is_suspending())
384 if (per_next_state < PWRDM_POWER_ON ||
385 core_next_state < PWRDM_POWER_ON)
386 if (!console_trylock())
387 goto console_still_active;
390 if (per_next_state < PWRDM_POWER_ON) {
391 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
392 omap_uart_prepare_idle(2);
393 omap_uart_prepare_idle(3);
394 omap2_gpio_prepare_for_idle(per_going_off);
395 if (per_next_state == PWRDM_POWER_OFF)
396 omap3_per_save_context();
400 if (core_next_state < PWRDM_POWER_ON) {
401 omap_uart_prepare_idle(0);
402 omap_uart_prepare_idle(1);
403 if (core_next_state == PWRDM_POWER_OFF) {
404 omap3_core_save_context();
405 omap3_cm_save_context();
409 omap3_intc_prepare_idle();
412 * On EMU/HS devices ROM code restores a SRDC value
413 * from scratchpad which has automatic self refresh on timeout
414 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
415 * Hence store/restore the SDRC_POWER register here.
417 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
418 omap_type() != OMAP2_DEVICE_TYPE_GP &&
419 core_next_state == PWRDM_POWER_OFF)
420 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
423 * omap3_arm_context is the location where some ARM context
424 * get saved. The rest is placed on the stack, and restored
425 * from there before resuming.
428 omap34xx_save_context(omap3_arm_context);
429 if (save_state == 1 || save_state == 3)
430 cpu_suspend(save_state, omap34xx_do_sram_idle);
432 omap34xx_do_sram_idle(save_state);
434 /* Restore normal SDRC POWER settings */
435 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
436 omap_type() != OMAP2_DEVICE_TYPE_GP &&
437 core_next_state == PWRDM_POWER_OFF)
438 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
441 if (core_next_state < PWRDM_POWER_ON) {
442 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
443 if (core_prev_state == PWRDM_POWER_OFF) {
444 omap3_core_restore_context();
445 omap3_cm_restore_context();
446 omap3_sram_restore_context();
447 omap2_sms_restore_context();
449 omap_uart_resume_idle(0);
450 omap_uart_resume_idle(1);
451 if (core_next_state == PWRDM_POWER_OFF)
452 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
454 OMAP3_PRM_VOLTCTRL_OFFSET);
456 omap3_intc_resume_idle();
459 if (per_next_state < PWRDM_POWER_ON) {
460 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
461 omap2_gpio_resume_after_idle();
462 if (per_prev_state == PWRDM_POWER_OFF)
463 omap3_per_restore_context();
464 omap_uart_resume_idle(2);
465 omap_uart_resume_idle(3);
468 if (!is_suspending())
471 console_still_active:
472 /* Disable IO-PAD and IO-CHAIN wakeup */
473 if (omap3_has_io_wakeup() &&
474 (per_next_state < PWRDM_POWER_ON ||
475 core_next_state < PWRDM_POWER_ON)) {
476 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
478 omap3_disable_io_chain();
481 pwrdm_post_transition();
483 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
486 int omap3_can_sleep(void)
488 if (!sleep_while_idle)
490 if (!omap_uart_can_sleep())
495 static void omap3_pm_idle(void)
500 if (!omap3_can_sleep())
503 if (omap_irq_pending() || need_resched())
506 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
507 trace_cpu_idle(1, smp_processor_id());
511 trace_power_end(smp_processor_id());
512 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
519 #ifdef CONFIG_SUSPEND
520 static int omap3_pm_suspend(void)
522 struct power_state *pwrst;
525 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
526 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
527 wakeup_timer_milliseconds);
529 /* Read current next_pwrsts */
530 list_for_each_entry(pwrst, &pwrst_list, node)
531 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
532 /* Set ones wanted by suspend */
533 list_for_each_entry(pwrst, &pwrst_list, node) {
534 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
536 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
540 omap_uart_prepare_suspend();
541 omap3_intc_suspend();
546 /* Restore next_pwrsts */
547 list_for_each_entry(pwrst, &pwrst_list, node) {
548 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
549 if (state > pwrst->next_state) {
550 printk(KERN_INFO "Powerdomain (%s) didn't enter "
552 pwrst->pwrdm->name, pwrst->next_state);
555 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
558 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
560 printk(KERN_INFO "Successfully put all powerdomains "
561 "to target state\n");
566 static int omap3_pm_enter(suspend_state_t unused)
570 switch (suspend_state) {
571 case PM_SUSPEND_STANDBY:
573 ret = omap3_pm_suspend();
582 /* Hooks to enable / disable UART interrupts during suspend */
583 static int omap3_pm_begin(suspend_state_t state)
586 suspend_state = state;
587 omap_uart_enable_irqs(0);
591 static void omap3_pm_end(void)
593 suspend_state = PM_SUSPEND_ON;
594 omap_uart_enable_irqs(1);
599 static const struct platform_suspend_ops omap_pm_ops = {
600 .begin = omap3_pm_begin,
602 .enter = omap3_pm_enter,
603 .valid = suspend_valid_only_mem,
605 #endif /* CONFIG_SUSPEND */
609 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
612 * In cases where IVA2 is activated by bootcode, it may prevent
613 * full-chip retention or off-mode because it is not idle. This
614 * function forces the IVA2 into idle state so it can go
615 * into retention/off and thus allow full-chip retention/off.
618 static void __init omap3_iva_idle(void)
620 /* ensure IVA2 clock is disabled */
621 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
623 /* if no clock activity, nothing else to do */
624 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
625 OMAP3430_CLKACTIVITY_IVA2_MASK))
629 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
630 OMAP3430_RST2_IVA2_MASK |
631 OMAP3430_RST3_IVA2_MASK,
632 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
634 /* Enable IVA2 clock */
635 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
636 OMAP3430_IVA2_MOD, CM_FCLKEN);
638 /* Set IVA2 boot mode to 'idle' */
639 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
640 OMAP343X_CONTROL_IVA2_BOOTMOD);
643 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
645 /* Disable IVA2 clock */
646 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
649 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
650 OMAP3430_RST2_IVA2_MASK |
651 OMAP3430_RST3_IVA2_MASK,
652 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
655 static void __init omap3_d2d_idle(void)
659 /* In a stand alone OMAP3430 where there is not a stacked
660 * modem for the D2D Idle Ack and D2D MStandby must be pulled
661 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
662 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
663 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
664 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
666 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
668 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
670 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
673 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
674 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
675 CORE_MOD, OMAP2_RM_RSTCTRL);
676 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
679 static void __init prcm_setup_regs(void)
681 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
682 OMAP3630_EN_UART4_MASK : 0;
683 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
684 OMAP3630_GRPSEL_UART4_MASK : 0;
686 /* XXX This should be handled by hwmod code or SCM init code */
687 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
690 * Enable control of expternal oscillator through
691 * sys_clkreq. In the long run clock framework should
694 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
695 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
697 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
699 /* setup wakup source */
700 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
701 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
703 /* No need to write EN_IO, that is always enabled */
704 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
705 OMAP3430_GRPSEL_GPT1_MASK |
706 OMAP3430_GRPSEL_GPT12_MASK,
707 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
708 /* For some reason IO doesn't generate wakeup event even if
709 * it is selected to mpu wakeup goup */
710 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
711 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
713 /* Enable PM_WKEN to support DSS LPR */
714 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
715 OMAP3430_DSS_MOD, PM_WKEN);
717 /* Enable wakeups in PER */
718 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
719 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
720 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
721 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
722 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
723 OMAP3430_EN_MCBSP4_MASK,
724 OMAP3430_PER_MOD, PM_WKEN);
725 /* and allow them to wake up MPU */
726 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
727 OMAP3430_GRPSEL_GPIO2_MASK |
728 OMAP3430_GRPSEL_GPIO3_MASK |
729 OMAP3430_GRPSEL_GPIO4_MASK |
730 OMAP3430_GRPSEL_GPIO5_MASK |
731 OMAP3430_GRPSEL_GPIO6_MASK |
732 OMAP3430_GRPSEL_UART3_MASK |
733 OMAP3430_GRPSEL_MCBSP2_MASK |
734 OMAP3430_GRPSEL_MCBSP3_MASK |
735 OMAP3430_GRPSEL_MCBSP4_MASK,
736 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
738 /* Don't attach IVA interrupts */
739 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
740 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
741 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
742 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
744 /* Clear any pending 'reset' flags */
745 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
746 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
747 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
748 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
749 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
750 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
751 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
753 /* Clear any pending PRCM interrupts */
754 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
760 void omap3_pm_off_mode_enable(int enable)
762 struct power_state *pwrst;
766 state = PWRDM_POWER_OFF;
768 state = PWRDM_POWER_RET;
770 list_for_each_entry(pwrst, &pwrst_list, node) {
771 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
772 pwrst->pwrdm == core_pwrdm &&
773 state == PWRDM_POWER_OFF) {
774 pwrst->next_state = PWRDM_POWER_RET;
775 pr_warn("%s: Core OFF disabled due to errata i583\n",
778 pwrst->next_state = state;
780 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
784 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
786 struct power_state *pwrst;
788 list_for_each_entry(pwrst, &pwrst_list, node) {
789 if (pwrst->pwrdm == pwrdm)
790 return pwrst->next_state;
795 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
797 struct power_state *pwrst;
799 list_for_each_entry(pwrst, &pwrst_list, node) {
800 if (pwrst->pwrdm == pwrdm) {
801 pwrst->next_state = state;
808 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
810 struct power_state *pwrst;
815 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
818 pwrst->pwrdm = pwrdm;
819 pwrst->next_state = PWRDM_POWER_RET;
820 list_add(&pwrst->node, &pwrst_list);
822 if (pwrdm_has_hdwr_sar(pwrdm))
823 pwrdm_enable_hdwr_sar(pwrdm);
825 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
829 * Enable hw supervised mode for all clockdomains if it's
830 * supported. Initiate sleep transition for other clockdomains, if
833 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
835 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
836 clkdm_allow_idle(clkdm);
837 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
838 atomic_read(&clkdm->usecount) == 0)
844 * Push functions to SRAM
846 * The minimum set of functions is pushed to SRAM for execution:
847 * - omap3_do_wfi for erratum i581 WA,
848 * - save_secure_ram_context for security extensions.
850 void omap_push_sram_idle(void)
852 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
854 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
855 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
856 save_secure_ram_context_sz);
859 static void __init pm_errata_configure(void)
861 if (cpu_is_omap3630()) {
862 pm34xx_errata |= PM_RTA_ERRATUM_i608;
863 /* Enable the l2 cache toggling in sleep logic */
864 enable_omap3630_toggle_l2_on_restore();
865 if (omap_rev() < OMAP3630_REV_ES1_2)
866 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
870 static int __init omap3_pm_init(void)
872 struct power_state *pwrst, *tmp;
873 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
876 if (!cpu_is_omap34xx())
879 pm_errata_configure();
881 /* XXX prcm_setup_regs needs to be before enabling hw
882 * supervised mode for powerdomains */
885 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
886 (irq_handler_t)prcm_interrupt_handler,
887 IRQF_DISABLED, "prcm", NULL);
889 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
890 INT_34XX_PRCM_MPU_IRQ);
894 ret = pwrdm_for_each(pwrdms_setup, NULL);
896 printk(KERN_ERR "Failed to setup powerdomains\n");
900 (void) clkdm_for_each(clkdms_setup, NULL);
902 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
903 if (mpu_pwrdm == NULL) {
904 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
908 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
909 per_pwrdm = pwrdm_lookup("per_pwrdm");
910 core_pwrdm = pwrdm_lookup("core_pwrdm");
911 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
913 neon_clkdm = clkdm_lookup("neon_clkdm");
914 mpu_clkdm = clkdm_lookup("mpu_clkdm");
915 per_clkdm = clkdm_lookup("per_clkdm");
916 core_clkdm = clkdm_lookup("core_clkdm");
918 #ifdef CONFIG_SUSPEND
919 suspend_set_ops(&omap_pm_ops);
920 #endif /* CONFIG_SUSPEND */
922 pm_idle = omap3_pm_idle;
926 * RTA is disabled during initialization as per erratum i608
927 * it is safer to disable RTA by the bootloader, but we would like
928 * to be doubly sure here and prevent any mishaps.
930 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
931 omap3630_ctrl_disable_rta();
933 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
934 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
935 omap3_secure_ram_storage =
936 kmalloc(0x803F, GFP_KERNEL);
937 if (!omap3_secure_ram_storage)
938 printk(KERN_ERR "Memory allocation failed when"
939 "allocating for secure sram context\n");
944 omap_dma_global_context_save();
945 omap3_save_secure_ram_context();
946 omap_dma_global_context_restore();
952 omap3_save_scratchpad_contents();
956 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
957 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
958 list_del(&pwrst->node);
964 late_initcall(omap3_pm_init);