arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <plat/sram.h>
  35 #include "clockdomain.h"
  36 #include "powerdomain.h"
  37 #include <plat/serial.h>
  38 #include <plat/sdrc.h>
  39 #include <plat/prcm.h>
  40 #include <plat/gpmc.h>
  41 #include <plat/dma.h>
  42
  43 #include <asm/tlbflush.h>
  44
  45 #include "cm2xxx_3xxx.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "prm-regbits-34xx.h"
  48
  49 #include "prm2xxx_3xxx.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52 #include "control.h"
  53
  54 #ifdef CONFIG_SUSPEND
  55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  56 static inline bool is_suspending(void)
  57 {
  58         return (suspend_state != PM_SUSPEND_ON);
  59 }
  60 #else
  61 static inline bool is_suspending(void)
  62 {
  63         return false;
  64 }
  65 #endif
  66
  67 /* Scratchpad offsets */
  68 #define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
  69 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
  70 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
  71
  72 /* pm34xx errata defined in pm.h */
  73 u16 pm34xx_errata;
  74
  75 struct power_state {
  76         struct powerdomain *pwrdm;
  77         u32 next_state;
  78 #ifdef CONFIG_SUSPEND
  79         u32 saved_state;
  80 #endif
  81         struct list_head node;
  82 };
  83
  84 static LIST_HEAD(pwrst_list);
  85
  86 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  87
  88 static int (*_omap_save_secure_sram)(u32 *addr);
  89
  90 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  91 static struct powerdomain *core_pwrdm, *per_pwrdm;
  92 static struct powerdomain *cam_pwrdm;
  93
  94 static inline void omap3_per_save_context(void)
  95 {
  96         omap_gpio_save_context();
  97 }
  98
  99 static inline void omap3_per_restore_context(void)
 100 {
 101         omap_gpio_restore_context();
 102 }
 103
 104 static void omap3_enable_io_chain(void)
 105 {
 106         int timeout = 0;
 107
 108         if (omap_rev() >= OMAP3430_REV_ES3_1) {
 109                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 110                                      PM_WKEN);
 111                 /* Do a readback to assure write has been done */
 112                 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 113
 114                 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 115                          OMAP3430_ST_IO_CHAIN_MASK)) {
 116                         timeout++;
 117                         if (timeout > 1000) {
 118                                 printk(KERN_ERR "Wake up daisy chain "
 119                                        "activation failed.\n");
 120                                 return;
 121                         }
 122                         omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 123                                              WKUP_MOD, PM_WKEN);
 124                 }
 125         }
 126 }
 127
 128 static void omap3_disable_io_chain(void)
 129 {
 130         if (omap_rev() >= OMAP3430_REV_ES3_1)
 131                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 132                                        PM_WKEN);
 133 }
 134
 135 static void omap3_core_save_context(void)
 136 {
 137         omap3_ctrl_save_padconf();
 138
 139         /*
 140          * Force write last pad into memory, as this can fail in some
 141          * cases according to errata 1.157, 1.185
 142          */
 143         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 144                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 145
 146         /* Save the Interrupt controller context */
 147         omap_intc_save_context();
 148         /* Save the GPMC context */
 149         omap3_gpmc_save_context();
 150         /* Save the system control module context, padconf already save above*/
 151         omap3_control_save_context();
 152         omap_dma_global_context_save();
 153 }
 154
 155 static void omap3_core_restore_context(void)
 156 {
 157         /* Restore the control module context, padconf restored by h/w */
 158         omap3_control_restore_context();
 159         /* Restore the GPMC context */
 160         omap3_gpmc_restore_context();
 161         /* Restore the interrupt controller context */
 162         omap_intc_restore_context();
 163         omap_dma_global_context_restore();
 164 }
 165
 166 /*
 167  * FIXME: This function should be called before entering off-mode after
 168  * OMAP3 secure services have been accessed. Currently it is only called
 169  * once during boot sequence, but this works as we are not using secure
 170  * services.
 171  */
 172 static void omap3_save_secure_ram_context(void)
 173 {
 174         u32 ret;
 175         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 176
 177         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 178                 /*
 179                  * MPU next state must be set to POWER_ON temporarily,
 180                  * otherwise the WFI executed inside the ROM code
 181                  * will hang the system.
 182                  */
 183                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 184                 ret = _omap_save_secure_sram((u32 *)
 185                                 __pa(omap3_secure_ram_storage));
 186                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 187                 /* Following is for error tracking, it should not happen */
 188                 if (ret) {
 189                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 190                                 ret);
 191                         while (1)
 192                                 ;
 193                 }
 194         }
 195 }
 196
 197 /*
 198  * PRCM Interrupt Handler Helper Function
 199  *
 200  * The purpose of this function is to clear any wake-up events latched
 201  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 202  * may occur whilst attempting to clear a PM_WKST_x register and thus
 203  * set another bit in this register. A while loop is used to ensure
 204  * that any peripheral wake-up events occurring while attempting to
 205  * clear the PM_WKST_x are detected and cleared.
 206  */
 207 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 208 {
 209         u32 wkst, fclk, iclk, clken;
 210         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 211         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 212         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 213         u16 grpsel_off = (regs == 3) ?
 214                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 215         int c = 0;
 216
 217         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 218         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 219         if (wkst) {
 220                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 221                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 222                 while (wkst) {
 223                         clken = wkst;
 224                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 225                         /*
 226                          * For USBHOST, we don't know whether HOST1 or
 227                          * HOST2 woke us up, so enable both f-clocks
 228                          */
 229                         if (module == OMAP3430ES2_USBHOST_MOD)
 230                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 231                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 232                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 233                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 234                         c++;
 235                 }
 236                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 237                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 238         }
 239
 240         return c;
 241 }
 242
 243 static int _prcm_int_handle_wakeup(void)
 244 {
 245         int c;
 246
 247         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 248         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 249         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 250         if (omap_rev() > OMAP3430_REV_ES1_0) {
 251                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 252                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 253         }
 254
 255         return c;
 256 }
 257
 258 /*
 259  * PRCM Interrupt Handler
 260  *
 261  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 262  * interrupts from the PRCM for the MPU. These bits must be cleared in
 263  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 264  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 265  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 266  * register indicates that a wake-up event is pending for the MPU and
 267  * this bit can only be cleared if the all the wake-up events latched
 268  * in the various PM_WKST_x registers have been cleared. The interrupt
 269  * handler is implemented using a do-while loop so that if a wake-up
 270  * event occurred during the processing of the prcm interrupt handler
 271  * (setting a bit in the corresponding PM_WKST_x register and thus
 272  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 273  * this would be handled.
 274  */
 275 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 276 {
 277         u32 irqenable_mpu, irqstatus_mpu;
 278         int c = 0;
 279
 280         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 281                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 282         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 283                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 284         irqstatus_mpu &= irqenable_mpu;
 285
 286         do {
 287                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 288                                      OMAP3430_IO_ST_MASK)) {
 289                         c = _prcm_int_handle_wakeup();
 290
 291                         /*
 292                          * Is the MPU PRCM interrupt handler racing with the
 293                          * IVA2 PRCM interrupt handler ?
 294                          */
 295                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 296                              "but no wakeup sources are marked\n");
 297                 } else {
 298                         /* XXX we need to expand our PRCM interrupt handler */
 299                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 300                              "no code to handle it (%08x)\n", irqstatus_mpu);
 301                 }
 302
 303                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 304                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 305
 306                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 307                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 308                 irqstatus_mpu &= irqenable_mpu;
 309
 310         } while (irqstatus_mpu);
 311
 312         return IRQ_HANDLED;
 313 }
 314
 315 /* Function to restore the table entry that was modified for enabling MMU */
 316 static void restore_table_entry(void)
 317 {
 318         void __iomem *scratchpad_address;
 319         u32 previous_value, control_reg_value;
 320         u32 *address;
 321
 322         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 323
 324         /* Get address of entry that was modified */
 325         address = (u32 *)__raw_readl(scratchpad_address +
 326                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 327         /* Get the previous value which needs to be restored */
 328         previous_value = __raw_readl(scratchpad_address +
 329                                      OMAP343X_TABLE_VALUE_OFFSET);
 330         address = __va(address);
 331         *address = previous_value;
 332         flush_tlb_all();
 333         control_reg_value = __raw_readl(scratchpad_address
 334                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 335         /* This will enable caches and prediction */
 336         set_cr(control_reg_value);
 337 }
 338
 339 void omap_sram_idle(void)
 340 {
 341         /* Variable to tell what needs to be saved and restored
 342          * in omap_sram_idle*/
 343         /* save_state = 0 => Nothing to save and restored */
 344         /* save_state = 1 => Only L1 and logic lost */
 345         /* save_state = 2 => Only L2 lost */
 346         /* save_state = 3 => L1, L2 and logic lost */
 347         int save_state = 0;
 348         int mpu_next_state = PWRDM_POWER_ON;
 349         int per_next_state = PWRDM_POWER_ON;
 350         int core_next_state = PWRDM_POWER_ON;
 351         int per_going_off;
 352         int core_prev_state, per_prev_state;
 353         u32 sdrc_pwr = 0;
 354
 355         if (!_omap_sram_idle)
 356                 return;
 357
 358         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 359         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 360         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 361         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 362
 363         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 364         switch (mpu_next_state) {
 365         case PWRDM_POWER_ON:
 366         case PWRDM_POWER_RET:
 367                 /* No need to save context */
 368                 save_state = 0;
 369                 break;
 370         case PWRDM_POWER_OFF:
 371                 save_state = 3;
 372                 break;
 373         default:
 374                 /* Invalid state */
 375                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 376                 return;
 377         }
 378         pwrdm_pre_transition();
 379
 380         /* NEON control */
 381         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 382                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 383
 384         /* Enable IO-PAD and IO-CHAIN wakeups */
 385         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 386         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 387         if (omap3_has_io_wakeup() &&
 388             (per_next_state < PWRDM_POWER_ON ||
 389              core_next_state < PWRDM_POWER_ON)) {
 390                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 391                 omap3_enable_io_chain();
 392         }
 393
 394         /* Block console output in case it is on one of the OMAP UARTs */
 395         if (!is_suspending())
 396                 if (per_next_state < PWRDM_POWER_ON ||
 397                     core_next_state < PWRDM_POWER_ON)
 398                         if (!console_trylock())
 399                                 goto console_still_active;
 400
 401         /* PER */
 402         if (per_next_state < PWRDM_POWER_ON) {
 403                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 404                 omap_uart_prepare_idle(2);
 405                 omap_uart_prepare_idle(3);
 406                 omap2_gpio_prepare_for_idle(per_going_off);
 407                 if (per_next_state == PWRDM_POWER_OFF)
 408                                 omap3_per_save_context();
 409         }
 410
 411         /* CORE */
 412         if (core_next_state < PWRDM_POWER_ON) {
 413                 omap_uart_prepare_idle(0);
 414                 omap_uart_prepare_idle(1);
 415                 if (core_next_state == PWRDM_POWER_OFF) {
 416                         omap3_core_save_context();
 417                         omap3_cm_save_context();
 418                 }
 419         }
 420
 421         omap3_intc_prepare_idle();
 422
 423         /*
 424         * On EMU/HS devices ROM code restores a SRDC value
 425         * from scratchpad which has automatic self refresh on timeout
 426         * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 427         * Hence store/restore the SDRC_POWER register here.
 428         */
 429         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 430             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 431             core_next_state == PWRDM_POWER_OFF)
 432                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 433
 434         /*
 435          * omap3_arm_context is the location where ARM registers
 436          * get saved. The restore path then reads from this
 437          * location and restores them back.
 438          */
 439         _omap_sram_idle(omap3_arm_context, save_state);
 440         cpu_init();
 441
 442         /* Restore normal SDRC POWER settings */
 443         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 444             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 445             core_next_state == PWRDM_POWER_OFF)
 446                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 447
 448         /* Restore table entry modified during MMU restoration */
 449         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 450                 restore_table_entry();
 451
 452         /* CORE */
 453         if (core_next_state < PWRDM_POWER_ON) {
 454                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 455                 if (core_prev_state == PWRDM_POWER_OFF) {
 456                         omap3_core_restore_context();
 457                         omap3_cm_restore_context();
 458                         omap3_sram_restore_context();
 459                         omap2_sms_restore_context();
 460                 }
 461                 omap_uart_resume_idle(0);
 462                 omap_uart_resume_idle(1);
 463                 if (core_next_state == PWRDM_POWER_OFF)
 464                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 465                                                OMAP3430_GR_MOD,
 466                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 467         }
 468         omap3_intc_resume_idle();
 469
 470         /* PER */
 471         if (per_next_state < PWRDM_POWER_ON) {
 472                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 473                 omap2_gpio_resume_after_idle();
 474                 if (per_prev_state == PWRDM_POWER_OFF)
 475                         omap3_per_restore_context();
 476                 omap_uart_resume_idle(2);
 477                 omap_uart_resume_idle(3);
 478         }
 479
 480         if (!is_suspending())
 481                 console_unlock();
 482
 483 console_still_active:
 484         /* Disable IO-PAD and IO-CHAIN wakeup */
 485         if (omap3_has_io_wakeup() &&
 486             (per_next_state < PWRDM_POWER_ON ||
 487              core_next_state < PWRDM_POWER_ON)) {
 488                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 489                                              PM_WKEN);
 490                 omap3_disable_io_chain();
 491         }
 492
 493         pwrdm_post_transition();
 494
 495         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 496 }
 497
 498 int omap3_can_sleep(void)
 499 {
 500         if (!sleep_while_idle)
 501                 return 0;
 502         if (!omap_uart_can_sleep())
 503                 return 0;
 504         return 1;
 505 }
 506
 507 static void omap3_pm_idle(void)
 508 {
 509         local_irq_disable();
 510         local_fiq_disable();
 511
 512         if (!omap3_can_sleep())
 513                 goto out;
 514
 515         if (omap_irq_pending() || need_resched())
 516                 goto out;
 517
 518         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 519         trace_cpu_idle(1, smp_processor_id());
 520
 521         omap_sram_idle();
 522
 523         trace_power_end(smp_processor_id());
 524         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 525
 526 out:
 527         local_fiq_enable();
 528         local_irq_enable();
 529 }
 530
 531 #ifdef CONFIG_SUSPEND
 532 static int omap3_pm_suspend(void)
 533 {
 534         struct power_state *pwrst;
 535         int state, ret = 0;
 536
 537         /* Read current next_pwrsts */
 538         list_for_each_entry(pwrst, &pwrst_list, node)
 539                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 540         /* Set ones wanted by suspend */
 541         list_for_each_entry(pwrst, &pwrst_list, node) {
 542                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 543                         goto restore;
 544                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 545                         goto restore;
 546         }
 547
 548         omap_uart_prepare_suspend();
 549         omap3_intc_suspend();
 550
 551         omap_sram_idle();
 552
 553 restore:
 554         /* Restore next_pwrsts */
 555         list_for_each_entry(pwrst, &pwrst_list, node) {
 556                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 557                 if (state > pwrst->next_state) {
 558                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 559                                "target state %d\n",
 560                                pwrst->pwrdm->name, pwrst->next_state);
 561                         ret = -1;
 562                 }
 563                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 564         }
 565         if (ret)
 566                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 567         else
 568                 printk(KERN_INFO "Successfully put all powerdomains "
 569                        "to target state\n");
 570
 571         return ret;
 572 }
 573
 574 static int omap3_pm_enter(suspend_state_t unused)
 575 {
 576         int ret = 0;
 577
 578         switch (suspend_state) {
 579         case PM_SUSPEND_STANDBY:
 580         case PM_SUSPEND_MEM:
 581                 ret = omap3_pm_suspend();
 582                 break;
 583         default:
 584                 ret = -EINVAL;
 585         }
 586
 587         return ret;
 588 }
 589
 590 /* Hooks to enable / disable UART interrupts during suspend */
 591 static int omap3_pm_begin(suspend_state_t state)
 592 {
 593         disable_hlt();
 594         suspend_state = state;
 595         omap_uart_enable_irqs(0);
 596         return 0;
 597 }
 598
 599 static void omap3_pm_end(void)
 600 {
 601         suspend_state = PM_SUSPEND_ON;
 602         omap_uart_enable_irqs(1);
 603         enable_hlt();
 604         return;
 605 }
 606
 607 static const struct platform_suspend_ops omap_pm_ops = {
 608         .begin          = omap3_pm_begin,
 609         .end            = omap3_pm_end,
 610         .enter          = omap3_pm_enter,
 611         .valid          = suspend_valid_only_mem,
 612 };
 613 #endif /* CONFIG_SUSPEND */
 614
 615
 616 /**
 617  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 618  *                   retention
 619  *
 620  * In cases where IVA2 is activated by bootcode, it may prevent
 621  * full-chip retention or off-mode because it is not idle.  This
 622  * function forces the IVA2 into idle state so it can go
 623  * into retention/off and thus allow full-chip retention/off.
 624  *
 625  **/
 626 static void __init omap3_iva_idle(void)
 627 {
 628         /* ensure IVA2 clock is disabled */
 629         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 630
 631         /* if no clock activity, nothing else to do */
 632         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 633               OMAP3430_CLKACTIVITY_IVA2_MASK))
 634                 return;
 635
 636         /* Reset IVA2 */
 637         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 638                           OMAP3430_RST2_IVA2_MASK |
 639                           OMAP3430_RST3_IVA2_MASK,
 640                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 641
 642         /* Enable IVA2 clock */
 643         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 644                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 645
 646         /* Set IVA2 boot mode to 'idle' */
 647         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 648                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 649
 650         /* Un-reset IVA2 */
 651         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 652
 653         /* Disable IVA2 clock */
 654         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 655
 656         /* Reset IVA2 */
 657         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 658                           OMAP3430_RST2_IVA2_MASK |
 659                           OMAP3430_RST3_IVA2_MASK,
 660                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 661 }
 662
 663 static void __init omap3_d2d_idle(void)
 664 {
 665         u16 mask, padconf;
 666
 667         /* In a stand alone OMAP3430 where there is not a stacked
 668          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 669          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 670          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 671         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 672         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 673         padconf |= mask;
 674         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 675
 676         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 677         padconf |= mask;
 678         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 679
 680         /* reset modem */
 681         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 682                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 683                           CORE_MOD, OMAP2_RM_RSTCTRL);
 684         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 685 }
 686
 687 static void __init prcm_setup_regs(void)
 688 {
 689         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 690                                         OMAP3630_EN_UART4_MASK : 0;
 691         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 692                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 693
 694         /* XXX This should be handled by hwmod code or SCM init code */
 695         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 696
 697         /*
 698          * Enable control of expternal oscillator through
 699          * sys_clkreq. In the long run clock framework should
 700          * take care of this.
 701          */
 702         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 703                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 704                              OMAP3430_GR_MOD,
 705                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 706
 707         /* setup wakup source */
 708         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 709                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 710                           WKUP_MOD, PM_WKEN);
 711         /* No need to write EN_IO, that is always enabled */
 712         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 713                           OMAP3430_GRPSEL_GPT1_MASK |
 714                           OMAP3430_GRPSEL_GPT12_MASK,
 715                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 716         /* For some reason IO doesn't generate wakeup event even if
 717          * it is selected to mpu wakeup goup */
 718         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 719                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 720
 721         /* Enable PM_WKEN to support DSS LPR */
 722         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 723                                 OMAP3430_DSS_MOD, PM_WKEN);
 724
 725         /* Enable wakeups in PER */
 726         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 727                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 728                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 729                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 730                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 731                           OMAP3430_EN_MCBSP4_MASK,
 732                           OMAP3430_PER_MOD, PM_WKEN);
 733         /* and allow them to wake up MPU */
 734         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 735                           OMAP3430_GRPSEL_GPIO2_MASK |
 736                           OMAP3430_GRPSEL_GPIO3_MASK |
 737                           OMAP3430_GRPSEL_GPIO4_MASK |
 738                           OMAP3430_GRPSEL_GPIO5_MASK |
 739                           OMAP3430_GRPSEL_GPIO6_MASK |
 740                           OMAP3430_GRPSEL_UART3_MASK |
 741                           OMAP3430_GRPSEL_MCBSP2_MASK |
 742                           OMAP3430_GRPSEL_MCBSP3_MASK |
 743                           OMAP3430_GRPSEL_MCBSP4_MASK,
 744                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 745
 746         /* Don't attach IVA interrupts */
 747         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 748         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 749         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 750         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 751
 752         /* Clear any pending 'reset' flags */
 753         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 754         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 755         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 756         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 757         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 758         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 759         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 760
 761         /* Clear any pending PRCM interrupts */
 762         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 763
 764         omap3_iva_idle();
 765         omap3_d2d_idle();
 766 }
 767
 768 void omap3_pm_off_mode_enable(int enable)
 769 {
 770         struct power_state *pwrst;
 771         u32 state;
 772
 773         if (enable)
 774                 state = PWRDM_POWER_OFF;
 775         else
 776                 state = PWRDM_POWER_RET;
 777
 778         list_for_each_entry(pwrst, &pwrst_list, node) {
 779                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 780                                 pwrst->pwrdm == core_pwrdm &&
 781                                 state == PWRDM_POWER_OFF) {
 782                         pwrst->next_state = PWRDM_POWER_RET;
 783                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 784                                 __func__);
 785                 } else {
 786                         pwrst->next_state = state;
 787                 }
 788                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 789         }
 790 }
 791
 792 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 793 {
 794         struct power_state *pwrst;
 795
 796         list_for_each_entry(pwrst, &pwrst_list, node) {
 797                 if (pwrst->pwrdm == pwrdm)
 798                         return pwrst->next_state;
 799         }
 800         return -EINVAL;
 801 }
 802
 803 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 804 {
 805         struct power_state *pwrst;
 806
 807         list_for_each_entry(pwrst, &pwrst_list, node) {
 808                 if (pwrst->pwrdm == pwrdm) {
 809                         pwrst->next_state = state;
 810                         return 0;
 811                 }
 812         }
 813         return -EINVAL;
 814 }
 815
 816 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 817 {
 818         struct power_state *pwrst;
 819
 820         if (!pwrdm->pwrsts)
 821                 return 0;
 822
 823         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 824         if (!pwrst)
 825                 return -ENOMEM;
 826         pwrst->pwrdm = pwrdm;
 827         pwrst->next_state = PWRDM_POWER_RET;
 828         list_add(&pwrst->node, &pwrst_list);
 829
 830         if (pwrdm_has_hdwr_sar(pwrdm))
 831                 pwrdm_enable_hdwr_sar(pwrdm);
 832
 833         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 834 }
 835
 836 /*
 837  * Enable hw supervised mode for all clockdomains if it's
 838  * supported. Initiate sleep transition for other clockdomains, if
 839  * they are not used
 840  */
 841 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 842 {
 843         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 844                 clkdm_allow_idle(clkdm);
 845         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 846                  atomic_read(&clkdm->usecount) == 0)
 847                 clkdm_sleep(clkdm);
 848         return 0;
 849 }
 850
 851 void omap_push_sram_idle(void)
 852 {
 853         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 854                                         omap34xx_cpu_suspend_sz);
 855         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 856                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 857                                 save_secure_ram_context_sz);
 858 }
 859
 860 static void __init pm_errata_configure(void)
 861 {
 862         if (cpu_is_omap3630()) {
 863                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 864                 /* Enable the l2 cache toggling in sleep logic */
 865                 enable_omap3630_toggle_l2_on_restore();
 866                 if (omap_rev() < OMAP3630_REV_ES1_2)
 867                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 868         }
 869 }
 870
 871 static int __init omap3_pm_init(void)
 872 {
 873         struct power_state *pwrst, *tmp;
 874         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 875         int ret;
 876
 877         if (!cpu_is_omap34xx())
 878                 return -ENODEV;
 879
 880         pm_errata_configure();
 881
 882         /* XXX prcm_setup_regs needs to be before enabling hw
 883          * supervised mode for powerdomains */
 884         prcm_setup_regs();
 885
 886         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 887                           (irq_handler_t)prcm_interrupt_handler,
 888                           IRQF_DISABLED, "prcm", NULL);
 889         if (ret) {
 890                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 891                        INT_34XX_PRCM_MPU_IRQ);
 892                 goto err1;
 893         }
 894
 895         ret = pwrdm_for_each(pwrdms_setup, NULL);
 896         if (ret) {
 897                 printk(KERN_ERR "Failed to setup powerdomains\n");
 898                 goto err2;
 899         }
 900
 901         (void) clkdm_for_each(clkdms_setup, NULL);
 902
 903         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 904         if (mpu_pwrdm == NULL) {
 905                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 906                 goto err2;
 907         }
 908
 909         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 910         per_pwrdm = pwrdm_lookup("per_pwrdm");
 911         core_pwrdm = pwrdm_lookup("core_pwrdm");
 912         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 913
 914         neon_clkdm = clkdm_lookup("neon_clkdm");
 915         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 916         per_clkdm = clkdm_lookup("per_clkdm");
 917         core_clkdm = clkdm_lookup("core_clkdm");
 918
 919         omap_push_sram_idle();
 920 #ifdef CONFIG_SUSPEND
 921         suspend_set_ops(&omap_pm_ops);
 922 #endif /* CONFIG_SUSPEND */
 923
 924         pm_idle = omap3_pm_idle;
 925         omap3_idle_init();
 926
 927         /*
 928          * RTA is disabled during initialization as per erratum i608
 929          * it is safer to disable RTA by the bootloader, but we would like
 930          * to be doubly sure here and prevent any mishaps.
 931          */
 932         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 933                 omap3630_ctrl_disable_rta();
 934
 935         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 936         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 937                 omap3_secure_ram_storage =
 938                         kmalloc(0x803F, GFP_KERNEL);
 939                 if (!omap3_secure_ram_storage)
 940                         printk(KERN_ERR "Memory allocation failed when"
 941                                         "allocating for secure sram context\n");
 942
 943                 local_irq_disable();
 944                 local_fiq_disable();
 945
 946                 omap_dma_global_context_save();
 947                 omap3_save_secure_ram_context();
 948                 omap_dma_global_context_restore();
 949
 950                 local_irq_enable();
 951                 local_fiq_enable();
 952         }
 953
 954         omap3_save_scratchpad_contents();
 955 err1:
 956         return ret;
 957 err2:
 958         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 959         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 960                 list_del(&pwrst->node);
 961                 kfree(pwrst);
 962         }
 963         return ret;
 964 }
 965
 966 late_initcall(omap3_pm_init);