arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33 #include <linux/console.h>
  34
  35 #include <asm/mach/time.h>
  36 #include <asm/mach/irq.h>
  37 #include <asm/mach-types.h>
  38
  39 #include <mach/irqs.h>
  40 #include <plat/clock.h>
  41 #include <plat/sram.h>
  42 #include <plat/dma.h>
  43 #include <plat/board.h>
  44
  45 #include "prm.h"
  46 #include "prm-regbits-24xx.h"
  47 #include "cm.h"
  48 #include "cm-regbits-24xx.h"
  49 #include "sdrc.h"
  50 #include "pm.h"
  51 #include "control.h"
  52
  53 #include <plat/powerdomain.h>
  54 #include <plat/clockdomain.h>
  55
  56 #ifdef CONFIG_SUSPEND
  57 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  58 static inline bool is_suspending(void)
  59 {
  60         return (suspend_state != PM_SUSPEND_ON);
  61 }
  62 #else
  63 static inline bool is_suspending(void)
  64 {
  65         return false;
  66 }
  67 #endif
  68
  69 static void (*omap2_sram_idle)(void);
  70 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  71                                   void __iomem *sdrc_power);
  72
  73 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  74 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  75
  76 static struct clk *osc_ck, *emul_ck;
  77
  78 static int omap2_fclks_active(void)
  79 {
  80         u32 f1, f2;
  81
  82         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  83         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  84
  85         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
  86         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
  87         f2 &= ~OMAP24XX_EN_UART3_MASK;
  88
  89         if (f1 | f2)
  90                 return 1;
  91         return 0;
  92 }
  93
  94 static void omap2_enter_full_retention(void)
  95 {
  96         u32 l;
  97         struct timespec ts_preidle, ts_postidle, ts_idle;
  98
  99         /* There is 1 reference hold for all children of the oscillator
 100          * clock, the following will remove it. If no one else uses the
 101          * oscillator itself it will be disabled if/when we enter retention
 102          * mode.
 103          */
 104         clk_disable(osc_ck);
 105
 106         /* Clear old wake-up events */
 107         /* REVISIT: These write to reserved bits? */
 108         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 109         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 110         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 111
 112         /*
 113          * Set MPU powerdomain's next power state to RETENTION;
 114          * preserve logic state during retention
 115          */
 116         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 117         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 118
 119         /* Workaround to kill USB */
 120         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 121         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 122
 123         omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
 124
 125         if (omap2_pm_debug) {
 126                 omap2_pm_dump(0, 0, 0);
 127                 getnstimeofday(&ts_preidle);
 128         }
 129
 130         /* One last check for pending IRQs to avoid extra latency due
 131          * to sleeping unnecessarily. */
 132         if (omap_irq_pending())
 133                 goto no_sleep;
 134
 135         /* Block console output in case it is on one of the OMAP UARTs */
 136         if (!is_suspending())
 137                 if (try_acquire_console_sem())
 138                         goto no_sleep;
 139
 140         omap_uart_prepare_idle(0);
 141         omap_uart_prepare_idle(1);
 142         omap_uart_prepare_idle(2);
 143
 144         /* Jump to SRAM suspend code */
 145         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 146                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 147                            OMAP_SDRC_REGADDR(SDRC_POWER));
 148
 149         omap_uart_resume_idle(2);
 150         omap_uart_resume_idle(1);
 151         omap_uart_resume_idle(0);
 152
 153         if (!is_suspending())
 154                 release_console_sem();
 155
 156 no_sleep:
 157         if (omap2_pm_debug) {
 158                 unsigned long long tmp;
 159
 160                 getnstimeofday(&ts_postidle);
 161                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 162                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 163                 omap2_pm_dump(0, 1, tmp);
 164         }
 165         omap2_gpio_resume_after_idle();
 166
 167         clk_enable(osc_ck);
 168
 169         /* clear CORE wake-up events */
 170         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 171         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 172
 173         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 174         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 175
 176         /* MPU domain wake events */
 177         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 178         if (l & 0x01)
 179                 prm_write_mod_reg(0x01, OCP_MOD,
 180                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 181         if (l & 0x20)
 182                 prm_write_mod_reg(0x20, OCP_MOD,
 183                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 184
 185         /* Mask future PRCM-to-MPU interrupts */
 186         prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 187 }
 188
 189 static int omap2_i2c_active(void)
 190 {
 191         u32 l;
 192
 193         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 194         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 195 }
 196
 197 static int sti_console_enabled;
 198
 199 static int omap2_allow_mpu_retention(void)
 200 {
 201         u32 l;
 202
 203         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 204         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 205         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 206                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 207                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 208                 return 0;
 209         /* Check for UART3. */
 210         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 211         if (l & OMAP24XX_EN_UART3_MASK)
 212                 return 0;
 213         if (sti_console_enabled)
 214                 return 0;
 215
 216         return 1;
 217 }
 218
 219 static void omap2_enter_mpu_retention(void)
 220 {
 221         int only_idle = 0;
 222         struct timespec ts_preidle, ts_postidle, ts_idle;
 223
 224         /* Putting MPU into the WFI state while a transfer is active
 225          * seems to cause the I2C block to timeout. Why? Good question. */
 226         if (omap2_i2c_active())
 227                 return;
 228
 229         /* The peripherals seem not to be able to wake up the MPU when
 230          * it is in retention mode. */
 231         if (omap2_allow_mpu_retention()) {
 232                 /* REVISIT: These write to reserved bits? */
 233                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 234                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 235                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 236
 237                 /* Try to enter MPU retention */
 238                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 239                                   OMAP_LOGICRETSTATE_MASK,
 240                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 241         } else {
 242                 /* Block MPU retention */
 243
 244                 prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 245                                                  OMAP2_PM_PWSTCTRL);
 246                 only_idle = 1;
 247         }
 248
 249         if (omap2_pm_debug) {
 250                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 251                 getnstimeofday(&ts_preidle);
 252         }
 253
 254         omap2_sram_idle();
 255
 256         if (omap2_pm_debug) {
 257                 unsigned long long tmp;
 258
 259                 getnstimeofday(&ts_postidle);
 260                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 261                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 262                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
 263         }
 264 }
 265
 266 static int omap2_can_sleep(void)
 267 {
 268         if (omap2_fclks_active())
 269                 return 0;
 270         if (!omap_uart_can_sleep())
 271                 return 0;
 272         if (osc_ck->usecount > 1)
 273                 return 0;
 274         if (omap_dma_running())
 275                 return 0;
 276
 277         return 1;
 278 }
 279
 280 static void omap2_pm_idle(void)
 281 {
 282         local_irq_disable();
 283         local_fiq_disable();
 284
 285         if (!omap2_can_sleep()) {
 286                 if (omap_irq_pending())
 287                         goto out;
 288                 omap2_enter_mpu_retention();
 289                 goto out;
 290         }
 291
 292         if (omap_irq_pending())
 293                 goto out;
 294
 295         omap2_enter_full_retention();
 296
 297 out:
 298         local_fiq_enable();
 299         local_irq_enable();
 300 }
 301
 302 static int omap2_pm_begin(suspend_state_t state)
 303 {
 304         disable_hlt();
 305         suspend_state = state;
 306         return 0;
 307 }
 308
 309 static int omap2_pm_suspend(void)
 310 {
 311         u32 wken_wkup, mir1;
 312
 313         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 314         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
 315         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 316
 317         /* Mask GPT1 */
 318         mir1 = omap_readl(0x480fe0a4);
 319         omap_writel(1 << 5, 0x480fe0ac);
 320
 321         omap_uart_prepare_suspend();
 322         omap2_enter_full_retention();
 323
 324         omap_writel(mir1, 0x480fe0a4);
 325         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 326
 327         return 0;
 328 }
 329
 330 static int omap2_pm_enter(suspend_state_t state)
 331 {
 332         int ret = 0;
 333
 334         switch (state) {
 335         case PM_SUSPEND_STANDBY:
 336         case PM_SUSPEND_MEM:
 337                 ret = omap2_pm_suspend();
 338                 break;
 339         default:
 340                 ret = -EINVAL;
 341         }
 342
 343         return ret;
 344 }
 345
 346 static void omap2_pm_end(void)
 347 {
 348         suspend_state = PM_SUSPEND_ON;
 349         enable_hlt();
 350 }
 351
 352 static struct platform_suspend_ops omap_pm_ops = {
 353         .begin          = omap2_pm_begin,
 354         .enter          = omap2_pm_enter,
 355         .end            = omap2_pm_end,
 356         .valid          = suspend_valid_only_mem,
 357 };
 358
 359 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 360 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 361 {
 362         clkdm_clear_all_wkdeps(clkdm);
 363         clkdm_clear_all_sleepdeps(clkdm);
 364
 365         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 366                 omap2_clkdm_allow_idle(clkdm);
 367         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 368                  atomic_read(&clkdm->usecount) == 0)
 369                 omap2_clkdm_sleep(clkdm);
 370         return 0;
 371 }
 372
 373 static void __init prcm_setup_regs(void)
 374 {
 375         int i, num_mem_banks;
 376         struct powerdomain *pwrdm;
 377
 378         /* Enable autoidle */
 379         prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 380                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 381
 382         /*
 383          * Set CORE powerdomain memory banks to retain their contents
 384          * during RETENTION
 385          */
 386         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 387         for (i = 0; i < num_mem_banks; i++)
 388                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 389
 390         /* Set CORE powerdomain's next power state to RETENTION */
 391         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 392
 393         /*
 394          * Set MPU powerdomain's next power state to RETENTION;
 395          * preserve logic state during retention
 396          */
 397         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 398         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 399
 400         /* Force-power down DSP, GFX powerdomains */
 401
 402         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 403         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 404         omap2_clkdm_sleep(dsp_clkdm);
 405
 406         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 407         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 408         omap2_clkdm_sleep(gfx_clkdm);
 409
 410         /*
 411          * Clear clockdomain wakeup dependencies and enable
 412          * hardware-supervised idle for all clkdms
 413          */
 414         clkdm_for_each(clkdms_setup, NULL);
 415         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 416
 417         /* Enable clock autoidle for all domains */
 418         cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
 419                          OMAP24XX_AUTO_MAILBOXES_MASK |
 420                          OMAP24XX_AUTO_WDT4_MASK |
 421                          OMAP2420_AUTO_WDT3_MASK |
 422                          OMAP24XX_AUTO_MSPRO_MASK |
 423                          OMAP2420_AUTO_MMC_MASK |
 424                          OMAP24XX_AUTO_FAC_MASK |
 425                          OMAP2420_AUTO_EAC_MASK |
 426                          OMAP24XX_AUTO_HDQ_MASK |
 427                          OMAP24XX_AUTO_UART2_MASK |
 428                          OMAP24XX_AUTO_UART1_MASK |
 429                          OMAP24XX_AUTO_I2C2_MASK |
 430                          OMAP24XX_AUTO_I2C1_MASK |
 431                          OMAP24XX_AUTO_MCSPI2_MASK |
 432                          OMAP24XX_AUTO_MCSPI1_MASK |
 433                          OMAP24XX_AUTO_MCBSP2_MASK |
 434                          OMAP24XX_AUTO_MCBSP1_MASK |
 435                          OMAP24XX_AUTO_GPT12_MASK |
 436                          OMAP24XX_AUTO_GPT11_MASK |
 437                          OMAP24XX_AUTO_GPT10_MASK |
 438                          OMAP24XX_AUTO_GPT9_MASK |
 439                          OMAP24XX_AUTO_GPT8_MASK |
 440                          OMAP24XX_AUTO_GPT7_MASK |
 441                          OMAP24XX_AUTO_GPT6_MASK |
 442                          OMAP24XX_AUTO_GPT5_MASK |
 443                          OMAP24XX_AUTO_GPT4_MASK |
 444                          OMAP24XX_AUTO_GPT3_MASK |
 445                          OMAP24XX_AUTO_GPT2_MASK |
 446                          OMAP2420_AUTO_VLYNQ_MASK |
 447                          OMAP24XX_AUTO_DSS_MASK,
 448                          CORE_MOD, CM_AUTOIDLE1);
 449         cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
 450                          OMAP24XX_AUTO_SSI_MASK |
 451                          OMAP24XX_AUTO_USB_MASK,
 452                          CORE_MOD, CM_AUTOIDLE2);
 453         cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
 454                          OMAP24XX_AUTO_GPMC_MASK |
 455                          OMAP24XX_AUTO_SDMA_MASK,
 456                          CORE_MOD, CM_AUTOIDLE3);
 457         cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
 458                          OMAP24XX_AUTO_AES_MASK |
 459                          OMAP24XX_AUTO_RNG_MASK |
 460                          OMAP24XX_AUTO_SHA_MASK |
 461                          OMAP24XX_AUTO_DES_MASK,
 462                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 463
 464         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
 465                          CM_AUTOIDLE);
 466
 467         /* Put DPLL and both APLLs into autoidle mode */
 468         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 469                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 470                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 471                          PLL_MOD, CM_AUTOIDLE);
 472
 473         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
 474                          OMAP24XX_AUTO_WDT1_MASK |
 475                          OMAP24XX_AUTO_MPU_WDT_MASK |
 476                          OMAP24XX_AUTO_GPIOS_MASK |
 477                          OMAP24XX_AUTO_32KSYNC_MASK |
 478                          OMAP24XX_AUTO_GPT1_MASK,
 479                          WKUP_MOD, CM_AUTOIDLE);
 480
 481         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 482          * stabilisation */
 483         prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 484                           OMAP2_PRCM_CLKSSETUP_OFFSET);
 485
 486         /* Configure automatic voltage transition */
 487         prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 488                           OMAP2_PRCM_VOLTSETUP_OFFSET);
 489         prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 490                           (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 491                           OMAP24XX_MEMRETCTRL_MASK |
 492                           (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 493                           (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 494                           OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 495
 496         /* Enable wake-up events */
 497         prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 498                           WKUP_MOD, PM_WKEN);
 499 }
 500
 501 static int __init omap2_pm_init(void)
 502 {
 503         u32 l;
 504
 505         if (!cpu_is_omap24xx())
 506                 return -ENODEV;
 507
 508         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 509         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 510         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 511
 512         /* Look up important powerdomains */
 513
 514         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 515         if (!mpu_pwrdm)
 516                 pr_err("PM: mpu_pwrdm not found\n");
 517
 518         core_pwrdm = pwrdm_lookup("core_pwrdm");
 519         if (!core_pwrdm)
 520                 pr_err("PM: core_pwrdm not found\n");
 521
 522         /* Look up important clockdomains */
 523
 524         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 525         if (!mpu_clkdm)
 526                 pr_err("PM: mpu_clkdm not found\n");
 527
 528         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 529         if (!wkup_clkdm)
 530                 pr_err("PM: wkup_clkdm not found\n");
 531
 532         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 533         if (!dsp_clkdm)
 534                 pr_err("PM: dsp_clkdm not found\n");
 535
 536         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 537         if (!gfx_clkdm)
 538                 pr_err("PM: gfx_clkdm not found\n");
 539
 540
 541         osc_ck = clk_get(NULL, "osc_ck");
 542         if (IS_ERR(osc_ck)) {
 543                 printk(KERN_ERR "could not get osc_ck\n");
 544                 return -ENODEV;
 545         }
 546
 547         if (cpu_is_omap242x()) {
 548                 emul_ck = clk_get(NULL, "emul_ck");
 549                 if (IS_ERR(emul_ck)) {
 550                         printk(KERN_ERR "could not get emul_ck\n");
 551                         clk_put(osc_ck);
 552                         return -ENODEV;
 553                 }
 554         }
 555
 556         prcm_setup_regs();
 557
 558         /* Hack to prevent MPU retention when STI console is enabled. */
 559         {
 560                 const struct omap_sti_console_config *sti;
 561
 562                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 563                                       struct omap_sti_console_config);
 564                 if (sti != NULL && sti->enable)
 565                         sti_console_enabled = 1;
 566         }
 567
 568         /*
 569          * We copy the assembler sleep/wakeup routines to SRAM.
 570          * These routines need to be in SRAM as that's the only
 571          * memory the MPU can see when it wakes up.
 572          */
 573         if (cpu_is_omap24xx()) {
 574                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 575                                                  omap24xx_idle_loop_suspend_sz);
 576
 577                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 578                                                     omap24xx_cpu_suspend_sz);
 579         }
 580
 581         suspend_set_ops(&omap_pm_ops);
 582         pm_idle = omap2_pm_idle;
 583
 584         return 0;
 585 }
 586
 587 late_initcall(omap2_pm_init);