2 * OMAP and TWL PMIC specific intializations.
4 * Copyright (C) 2010 Texas Instruments Incorporated.
6 * Copyright (C) 2009 Texas Instruments Incorporated.
8 * Copyright (C) 2009 Nokia Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/err.h>
18 #include <linux/kernel.h>
19 #include <linux/i2c/twl.h>
25 #define OMAP3_SRI2C_SLAVE_ADDR 0x12
26 #define OMAP3_VDD_MPU_SR_CONTROL_REG 0x00
27 #define OMAP3_VDD_CORE_SR_CONTROL_REG 0x01
28 #define OMAP3_VP_CONFIG_ERROROFFSET 0x00
29 #define OMAP3_VP_VSTEPMIN_VSTEPMIN 0x1
30 #define OMAP3_VP_VSTEPMAX_VSTEPMAX 0x04
31 #define OMAP3_VP_VLIMITTO_TIMEOUT_US 200
33 #define OMAP3430_VP1_VLIMITTO_VDDMIN 0x14
34 #define OMAP3430_VP1_VLIMITTO_VDDMAX 0x42
35 #define OMAP3430_VP2_VLIMITTO_VDDMIN 0x18
36 #define OMAP3430_VP2_VLIMITTO_VDDMAX 0x2c
38 #define OMAP3630_VP1_VLIMITTO_VDDMIN 0x18
39 #define OMAP3630_VP1_VLIMITTO_VDDMAX 0x3c
40 #define OMAP3630_VP2_VLIMITTO_VDDMIN 0x18
41 #define OMAP3630_VP2_VLIMITTO_VDDMAX 0x30
43 #define OMAP4_SRI2C_SLAVE_ADDR 0x12
44 #define OMAP4_VDD_MPU_SR_VOLT_REG 0x55
45 #define OMAP4_VDD_IVA_SR_VOLT_REG 0x5B
46 #define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
48 #define OMAP4_VP_CONFIG_ERROROFFSET 0x00
49 #define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
50 #define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
51 #define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
53 #define OMAP4_VP_MPU_VLIMITTO_VDDMIN 0xA
54 #define OMAP4_VP_MPU_VLIMITTO_VDDMAX 0x39
55 #define OMAP4_VP_IVA_VLIMITTO_VDDMIN 0xA
56 #define OMAP4_VP_IVA_VLIMITTO_VDDMAX 0x2D
57 #define OMAP4_VP_CORE_VLIMITTO_VDDMIN 0xA
58 #define OMAP4_VP_CORE_VLIMITTO_VDDMAX 0x28
60 static bool is_offset_valid;
61 static u8 smps_offset;
63 * Flag to ensure Smartreflex bit in TWL
64 * being cleared in board file is not overwritten.
66 static bool __initdata twl_sr_enable_autoinit;
68 #define TWL4030_DCDC_GLOBAL_CFG 0x06
69 #define REG_SMPS_OFFSET 0xE0
70 #define SMARTREFLEX_ENABLE BIT(3)
72 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
74 return (((vsel * 125) + 6000)) * 100;
77 static u8 twl4030_uv_to_vsel(unsigned long uv)
79 return DIV_ROUND_UP(uv - 600000, 12500);
82 static unsigned long twl6030_vsel_to_uv(const u8 vsel)
85 * In TWL6030 depending on the value of SMPS_OFFSET
86 * efuse register the voltage range supported in
87 * standard mode can be either between 0.6V - 1.3V or
88 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
89 * is programmed to all 0's where as starting from
90 * TWL6030 ES1.1 the efuse is programmed to 1
92 if (!is_offset_valid) {
93 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
95 is_offset_valid = true;
101 * There is no specific formula for voltage to vsel
102 * conversion above 1.3V. There are special hardcoded
103 * values for voltages above 1.3V. Currently we are
104 * hardcoding only for 1.35 V which is used for 1GH OPP for
110 if (smps_offset & 0x8)
111 return ((((vsel - 1) * 1266) + 70900)) * 10;
113 return ((((vsel - 1) * 1266) + 60770)) * 10;
116 static u8 twl6030_uv_to_vsel(unsigned long uv)
119 * In TWL6030 depending on the value of SMPS_OFFSET
120 * efuse register the voltage range supported in
121 * standard mode can be either between 0.6V - 1.3V or
122 * 0.7V - 1.4V. In TWL6030 ES1.0 SMPS_OFFSET efuse
123 * is programmed to all 0's where as starting from
124 * TWL6030 ES1.1 the efuse is programmed to 1
126 if (!is_offset_valid) {
127 twl_i2c_read_u8(TWL6030_MODULE_ID0, &smps_offset,
129 is_offset_valid = true;
135 * There is no specific formula for voltage to vsel
136 * conversion above 1.3V. There are special hardcoded
137 * values for voltages above 1.3V. Currently we are
138 * hardcoding only for 1.35 V which is used for 1GH OPP for
141 if (uv > twl6030_vsel_to_uv(0x39)) {
144 pr_err("%s:OUT OF RANGE! non mapped vsel for %ld Vs max %ld\n",
145 __func__, uv, twl6030_vsel_to_uv(0x39));
149 if (smps_offset & 0x8)
150 return DIV_ROUND_UP(uv - 709000, 12660) + 1;
152 return DIV_ROUND_UP(uv - 607700, 12660) + 1;
155 static struct omap_voltdm_pmic omap3_mpu_pmic = {
159 .onlp_volt = 1000000,
162 .volt_setup_time = 0xfff,
163 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
164 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
165 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
166 .vp_vddmin = OMAP3430_VP1_VLIMITTO_VDDMIN,
167 .vp_vddmax = OMAP3430_VP1_VLIMITTO_VDDMAX,
168 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
169 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
170 .volt_reg_addr = OMAP3_VDD_MPU_SR_CONTROL_REG,
171 .i2c_high_speed = true,
172 .vsel_to_uv = twl4030_vsel_to_uv,
173 .uv_to_vsel = twl4030_uv_to_vsel,
176 static struct omap_voltdm_pmic omap3_core_pmic = {
180 .onlp_volt = 1000000,
183 .volt_setup_time = 0xfff,
184 .vp_erroroffset = OMAP3_VP_CONFIG_ERROROFFSET,
185 .vp_vstepmin = OMAP3_VP_VSTEPMIN_VSTEPMIN,
186 .vp_vstepmax = OMAP3_VP_VSTEPMAX_VSTEPMAX,
187 .vp_vddmin = OMAP3430_VP2_VLIMITTO_VDDMIN,
188 .vp_vddmax = OMAP3430_VP2_VLIMITTO_VDDMAX,
189 .vp_timeout_us = OMAP3_VP_VLIMITTO_TIMEOUT_US,
190 .i2c_slave_addr = OMAP3_SRI2C_SLAVE_ADDR,
191 .volt_reg_addr = OMAP3_VDD_CORE_SR_CONTROL_REG,
192 .i2c_high_speed = true,
193 .vsel_to_uv = twl4030_vsel_to_uv,
194 .uv_to_vsel = twl4030_uv_to_vsel,
197 static struct omap_voltdm_pmic omap4_mpu_pmic = {
201 .onlp_volt = 1350000,
204 .volt_setup_time = 0,
205 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
206 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
207 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
208 .vp_vddmin = OMAP4_VP_MPU_VLIMITTO_VDDMIN,
209 .vp_vddmax = OMAP4_VP_MPU_VLIMITTO_VDDMAX,
210 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
211 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
212 .volt_reg_addr = OMAP4_VDD_MPU_SR_VOLT_REG,
213 .i2c_high_speed = true,
214 .vsel_to_uv = twl6030_vsel_to_uv,
215 .uv_to_vsel = twl6030_uv_to_vsel,
218 static struct omap_voltdm_pmic omap4_iva_pmic = {
222 .onlp_volt = 1100000,
225 .volt_setup_time = 0,
226 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
227 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
228 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
229 .vp_vddmin = OMAP4_VP_IVA_VLIMITTO_VDDMIN,
230 .vp_vddmax = OMAP4_VP_IVA_VLIMITTO_VDDMAX,
231 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
232 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
233 .volt_reg_addr = OMAP4_VDD_IVA_SR_VOLT_REG,
234 .i2c_high_speed = true,
235 .vsel_to_uv = twl6030_vsel_to_uv,
236 .uv_to_vsel = twl6030_uv_to_vsel,
239 static struct omap_voltdm_pmic omap4_core_pmic = {
243 .onlp_volt = 1100000,
246 .volt_setup_time = 0,
247 .vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
248 .vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
249 .vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
250 .vp_vddmin = OMAP4_VP_CORE_VLIMITTO_VDDMIN,
251 .vp_vddmax = OMAP4_VP_CORE_VLIMITTO_VDDMAX,
252 .vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
253 .i2c_slave_addr = OMAP4_SRI2C_SLAVE_ADDR,
254 .volt_reg_addr = OMAP4_VDD_CORE_SR_VOLT_REG,
255 .vsel_to_uv = twl6030_vsel_to_uv,
256 .uv_to_vsel = twl6030_uv_to_vsel,
259 int __init omap4_twl_init(void)
261 struct voltagedomain *voltdm;
263 if (!cpu_is_omap44xx())
266 voltdm = voltdm_lookup("mpu");
267 omap_voltage_register_pmic(voltdm, &omap4_mpu_pmic);
269 voltdm = voltdm_lookup("iva");
270 omap_voltage_register_pmic(voltdm, &omap4_iva_pmic);
272 voltdm = voltdm_lookup("core");
273 omap_voltage_register_pmic(voltdm, &omap4_core_pmic);
278 int __init omap3_twl_init(void)
280 struct voltagedomain *voltdm;
282 if (!cpu_is_omap34xx())
285 if (cpu_is_omap3630()) {
286 omap3_mpu_pmic.vp_vddmin = OMAP3630_VP1_VLIMITTO_VDDMIN;
287 omap3_mpu_pmic.vp_vddmax = OMAP3630_VP1_VLIMITTO_VDDMAX;
288 omap3_core_pmic.vp_vddmin = OMAP3630_VP2_VLIMITTO_VDDMIN;
289 omap3_core_pmic.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;
293 * The smartreflex bit on twl4030 specifies if the setting of voltage
294 * is done over the I2C_SR path. Since this setting is independent of
295 * the actual usage of smartreflex AVS module, we enable TWL SR bit
296 * by default irrespective of whether smartreflex AVS module is enabled
297 * on the OMAP side or not. This is because without this bit enabled,
298 * the voltage scaling through vp forceupdate/bypass mechanism of
299 * voltage scaling will not function on TWL over I2C_SR.
301 if (!twl_sr_enable_autoinit)
302 omap3_twl_set_sr_bit(true);
304 voltdm = voltdm_lookup("mpu_iva");
305 omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
307 voltdm = voltdm_lookup("core");
308 omap_voltage_register_pmic(voltdm, &omap3_core_pmic);
314 * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
315 * @enable: enable SR mode in twl or not
317 * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
318 * voltage scaling through OMAP SR works. Else, the smartreflex bit
319 * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
320 * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
321 * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
322 * in those scenarios this bit is to be cleared (enable = false).
324 * Returns 0 on success, error is returned if I2C read/write fails.
326 int __init omap3_twl_set_sr_bit(bool enable)
330 if (twl_sr_enable_autoinit)
331 pr_warning("%s: unexpected multiple calls\n", __func__);
333 ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,
334 TWL4030_DCDC_GLOBAL_CFG);
339 temp |= SMARTREFLEX_ENABLE;
341 temp &= ~SMARTREFLEX_ENABLE;
343 ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,
344 TWL4030_DCDC_GLOBAL_CFG);
346 twl_sr_enable_autoinit = true;
350 pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);