2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
39 /* Base offset for all DRA7XX interrupts external to MPUSS */
40 #define DRA7XX_IRQ_GIC_START 32
42 /* Base offset for all DRA7XX dma requests */
43 #define DRA7XX_DMA_REQ_START 1
52 * instance(s): l3_instr, l3_main_1, l3_main_2
54 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
59 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
73 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
86 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
103 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
108 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
121 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
134 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
147 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
160 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
177 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
182 static struct omap_hwmod dra7xx_atl_hwmod = {
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
201 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
206 static struct omap_hwmod dra7xx_bb2d_hwmod = {
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
225 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
231 .sysc_fields = &omap_hwmod_sysc_type1,
234 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
236 .sysc = &dra7xx_counter_sysc,
240 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
255 * 'ctrl_module' class
259 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
263 /* ctrl_module_wkup */
264 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
280 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
285 static struct omap_hwmod dra7xx_dcan1_hwmod = {
287 .class = &dra7xx_dcan_hwmod_class,
288 .clkdm_name = "wkupaon_clkdm",
289 .main_clk = "dcan1_sys_clk_mux",
292 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
300 static struct omap_hwmod dra7xx_dcan2_hwmod = {
302 .class = &dra7xx_dcan_hwmod_class,
303 .clkdm_name = "l4per2_clkdm",
304 .main_clk = "sys_clkin1",
307 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
308 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
319 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
323 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
324 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
326 SYSS_HAS_RESET_STATUS),
327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
328 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
329 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
330 .sysc_fields = &omap_hwmod_sysc_type1,
333 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
335 .sysc = &dra7xx_dma_sysc,
339 static struct omap_dma_dev_attr dma_dev_attr = {
340 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
341 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
346 static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
354 static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div",
362 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
363 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
366 .dev_attr = &dma_dev_attr,
374 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
377 .sysc_flags = SYSS_HAS_RESET_STATUS,
380 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
382 .sysc = &dra7xx_dss_sysc,
383 .reset = omap_dss_reset,
387 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
388 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
392 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
393 { .role = "dss_clk", .clk = "dss_dss_clk" },
394 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
395 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
396 { .role = "video2_clk", .clk = "dss_video2_clk" },
397 { .role = "video1_clk", .clk = "dss_video1_clk" },
398 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
401 static struct omap_hwmod dra7xx_dss_hwmod = {
403 .class = &dra7xx_dss_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406 .sdma_reqs = dra7xx_dss_sdma_reqs,
407 .main_clk = "dss_dss_clk",
410 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
412 .modulemode = MODULEMODE_SWCTRL,
415 .opt_clks = dss_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
424 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
428 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
429 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
430 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
431 SYSS_HAS_RESET_STATUS),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
437 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
439 .sysc = &dra7xx_dispc_sysc,
443 /* dss_dispc dev_attr */
444 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
445 .has_framedonetv_irq = 1,
449 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
451 .class = &dra7xx_dispc_hwmod_class,
452 .clkdm_name = "dss_clkdm",
453 .main_clk = "dss_dss_clk",
456 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
457 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
460 .dev_attr = &dss_dispc_dev_attr,
468 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
471 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
475 .sysc_fields = &omap_hwmod_sysc_type2,
478 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
480 .sysc = &dra7xx_hdmi_sysc,
485 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
486 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
489 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
491 .class = &dra7xx_hdmi_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_48mhz_clk",
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
500 .opt_clks = dss_hdmi_opt_clks,
501 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
509 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
514 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSS_HAS_RESET_STATUS),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
518 .sysc_fields = &omap_hwmod_sysc_type1,
521 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
523 .sysc = &dra7xx_elm_sysc,
528 static struct omap_hwmod dra7xx_elm_hwmod = {
530 .class = &dra7xx_elm_hwmod_class,
531 .clkdm_name = "l4per_clkdm",
532 .main_clk = "l3_iclk_div",
535 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
546 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
550 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
551 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
552 SYSS_HAS_RESET_STATUS),
553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
555 .sysc_fields = &omap_hwmod_sysc_type1,
558 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
560 .sysc = &dra7xx_gpio_sysc,
565 static struct omap_gpio_dev_attr gpio_dev_attr = {
571 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
572 { .role = "dbclk", .clk = "gpio1_dbclk" },
575 static struct omap_hwmod dra7xx_gpio1_hwmod = {
577 .class = &dra7xx_gpio_hwmod_class,
578 .clkdm_name = "wkupaon_clkdm",
579 .main_clk = "wkupaon_iclk_mux",
582 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
583 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
584 .modulemode = MODULEMODE_HWCTRL,
587 .opt_clks = gpio1_opt_clks,
588 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
589 .dev_attr = &gpio_dev_attr,
593 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
594 { .role = "dbclk", .clk = "gpio2_dbclk" },
597 static struct omap_hwmod dra7xx_gpio2_hwmod = {
599 .class = &dra7xx_gpio_hwmod_class,
600 .clkdm_name = "l4per_clkdm",
601 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
602 .main_clk = "l3_iclk_div",
605 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
606 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
607 .modulemode = MODULEMODE_HWCTRL,
610 .opt_clks = gpio2_opt_clks,
611 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
612 .dev_attr = &gpio_dev_attr,
616 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
617 { .role = "dbclk", .clk = "gpio3_dbclk" },
620 static struct omap_hwmod dra7xx_gpio3_hwmod = {
622 .class = &dra7xx_gpio_hwmod_class,
623 .clkdm_name = "l4per_clkdm",
624 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
625 .main_clk = "l3_iclk_div",
628 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
629 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
633 .opt_clks = gpio3_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
635 .dev_attr = &gpio_dev_attr,
639 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
640 { .role = "dbclk", .clk = "gpio4_dbclk" },
643 static struct omap_hwmod dra7xx_gpio4_hwmod = {
645 .class = &dra7xx_gpio_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .main_clk = "l3_iclk_div",
651 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
652 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_HWCTRL,
656 .opt_clks = gpio4_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
658 .dev_attr = &gpio_dev_attr,
662 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
663 { .role = "dbclk", .clk = "gpio5_dbclk" },
666 static struct omap_hwmod dra7xx_gpio5_hwmod = {
668 .class = &dra7xx_gpio_hwmod_class,
669 .clkdm_name = "l4per_clkdm",
670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
671 .main_clk = "l3_iclk_div",
674 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
675 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
676 .modulemode = MODULEMODE_HWCTRL,
679 .opt_clks = gpio5_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
681 .dev_attr = &gpio_dev_attr,
685 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
686 { .role = "dbclk", .clk = "gpio6_dbclk" },
689 static struct omap_hwmod dra7xx_gpio6_hwmod = {
691 .class = &dra7xx_gpio_hwmod_class,
692 .clkdm_name = "l4per_clkdm",
693 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694 .main_clk = "l3_iclk_div",
697 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
698 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
702 .opt_clks = gpio6_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
704 .dev_attr = &gpio_dev_attr,
708 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio7_dbclk" },
712 static struct omap_hwmod dra7xx_gpio7_hwmod = {
714 .class = &dra7xx_gpio_hwmod_class,
715 .clkdm_name = "l4per_clkdm",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .main_clk = "l3_iclk_div",
720 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
721 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
722 .modulemode = MODULEMODE_HWCTRL,
725 .opt_clks = gpio7_opt_clks,
726 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
727 .dev_attr = &gpio_dev_attr,
731 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
732 { .role = "dbclk", .clk = "gpio8_dbclk" },
735 static struct omap_hwmod dra7xx_gpio8_hwmod = {
737 .class = &dra7xx_gpio_hwmod_class,
738 .clkdm_name = "l4per_clkdm",
739 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
740 .main_clk = "l3_iclk_div",
743 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
744 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
745 .modulemode = MODULEMODE_HWCTRL,
748 .opt_clks = gpio8_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
750 .dev_attr = &gpio_dev_attr,
758 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
766 .sysc_fields = &omap_hwmod_sysc_type1,
769 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
771 .sysc = &dra7xx_gpmc_sysc,
776 static struct omap_hwmod dra7xx_gpmc_hwmod = {
778 .class = &dra7xx_gpmc_hwmod_class,
779 .clkdm_name = "l3main1_clkdm",
780 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
781 .main_clk = "l3_iclk_div",
784 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
796 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
801 SYSS_HAS_RESET_STATUS),
802 .sysc_fields = &omap_hwmod_sysc_type1,
805 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
807 .sysc = &dra7xx_hdq1w_sysc,
812 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
814 .class = &dra7xx_hdq1w_hwmod_class,
815 .clkdm_name = "l4per_clkdm",
816 .flags = HWMOD_INIT_NO_RESET,
817 .main_clk = "func_12m_fclk",
820 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
832 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
836 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
837 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
840 .clockact = CLOCKACT_TEST_ICLK,
841 .sysc_fields = &omap_hwmod_sysc_type1,
844 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
846 .sysc = &dra7xx_i2c_sysc,
847 .reset = &omap_i2c_reset,
848 .rev = OMAP_I2C_IP_VERSION_2,
852 static struct omap_i2c_dev_attr i2c_dev_attr = {
853 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
857 static struct omap_hwmod dra7xx_i2c1_hwmod = {
859 .class = &dra7xx_i2c_hwmod_class,
860 .clkdm_name = "l4per_clkdm",
861 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
862 .main_clk = "func_96m_fclk",
865 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
866 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
870 .dev_attr = &i2c_dev_attr,
874 static struct omap_hwmod dra7xx_i2c2_hwmod = {
876 .class = &dra7xx_i2c_hwmod_class,
877 .clkdm_name = "l4per_clkdm",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .main_clk = "func_96m_fclk",
882 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
883 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
884 .modulemode = MODULEMODE_SWCTRL,
887 .dev_attr = &i2c_dev_attr,
891 static struct omap_hwmod dra7xx_i2c3_hwmod = {
893 .class = &dra7xx_i2c_hwmod_class,
894 .clkdm_name = "l4per_clkdm",
895 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
896 .main_clk = "func_96m_fclk",
899 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
900 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
904 .dev_attr = &i2c_dev_attr,
908 static struct omap_hwmod dra7xx_i2c4_hwmod = {
910 .class = &dra7xx_i2c_hwmod_class,
911 .clkdm_name = "l4per_clkdm",
912 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
913 .main_clk = "func_96m_fclk",
916 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
917 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
921 .dev_attr = &i2c_dev_attr,
925 static struct omap_hwmod dra7xx_i2c5_hwmod = {
927 .class = &dra7xx_i2c_hwmod_class,
928 .clkdm_name = "ipu_clkdm",
929 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
930 .main_clk = "func_96m_fclk",
933 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
938 .dev_attr = &i2c_dev_attr,
946 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
949 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
950 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
953 .sysc_fields = &omap_hwmod_sysc_type2,
956 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
958 .sysc = &dra7xx_mcspi_sysc,
959 .rev = OMAP4_MCSPI_REV,
963 /* mcspi1 dev_attr */
964 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
968 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
970 .class = &dra7xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
975 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
980 .dev_attr = &mcspi1_dev_attr,
984 /* mcspi2 dev_attr */
985 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
989 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
991 .class = &dra7xx_mcspi_hwmod_class,
992 .clkdm_name = "l4per_clkdm",
993 .main_clk = "func_48m_fclk",
996 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
1001 .dev_attr = &mcspi2_dev_attr,
1005 /* mcspi3 dev_attr */
1006 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007 .num_chipselect = 2,
1010 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1012 .class = &dra7xx_mcspi_hwmod_class,
1013 .clkdm_name = "l4per_clkdm",
1014 .main_clk = "func_48m_fclk",
1017 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1022 .dev_attr = &mcspi3_dev_attr,
1026 /* mcspi4 dev_attr */
1027 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028 .num_chipselect = 1,
1031 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1033 .class = &dra7xx_mcspi_hwmod_class,
1034 .clkdm_name = "l4per_clkdm",
1035 .main_clk = "func_48m_fclk",
1038 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040 .modulemode = MODULEMODE_SWCTRL,
1043 .dev_attr = &mcspi4_dev_attr,
1051 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1053 .sysc_offs = 0x0010,
1054 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1063 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1065 .sysc = &dra7xx_mmc_sysc,
1069 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070 { .role = "clk32k", .clk = "mmc1_clk32k" },
1074 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1078 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1080 .class = &dra7xx_mmc_hwmod_class,
1081 .clkdm_name = "l3init_clkdm",
1082 .main_clk = "mmc1_fclk_div",
1085 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1090 .opt_clks = mmc1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1092 .dev_attr = &mmc1_dev_attr,
1096 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097 { .role = "clk32k", .clk = "mmc2_clk32k" },
1100 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1102 .class = &dra7xx_mmc_hwmod_class,
1103 .clkdm_name = "l3init_clkdm",
1104 .main_clk = "mmc2_fclk_div",
1107 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1112 .opt_clks = mmc2_opt_clks,
1113 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1117 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118 { .role = "clk32k", .clk = "mmc3_clk32k" },
1121 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1123 .class = &dra7xx_mmc_hwmod_class,
1124 .clkdm_name = "l4per_clkdm",
1125 .main_clk = "mmc3_gfclk_div",
1128 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1133 .opt_clks = mmc3_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1138 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139 { .role = "clk32k", .clk = "mmc4_clk32k" },
1142 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1144 .class = &dra7xx_mmc_hwmod_class,
1145 .clkdm_name = "l4per_clkdm",
1146 .main_clk = "mmc4_gfclk_div",
1149 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1154 .opt_clks = mmc4_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1163 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1168 static struct omap_hwmod dra7xx_mpu_hwmod = {
1170 .class = &dra7xx_mpu_hwmod_class,
1171 .clkdm_name = "mpu_clkdm",
1172 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173 .main_clk = "dpll_mpu_m2_ck",
1176 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1187 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0014,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1195 .sysc_fields = &omap_hwmod_sysc_type1,
1198 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1200 .sysc = &dra7xx_ocp2scp_sysc,
1204 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1206 .class = &dra7xx_ocp2scp_hwmod_class,
1207 .clkdm_name = "l3init_clkdm",
1208 .main_clk = "l4_root_clk_div",
1211 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213 .modulemode = MODULEMODE_HWCTRL,
1223 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1224 .sysc_offs = 0x0010,
1225 .sysc_flags = SYSC_HAS_SIDLEMODE,
1226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1228 .sysc_fields = &omap_hwmod_sysc_type2,
1231 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1233 .sysc = &dra7xx_qspi_sysc,
1237 static struct omap_hwmod dra7xx_qspi_hwmod = {
1239 .class = &dra7xx_qspi_hwmod_class,
1240 .clkdm_name = "l4per2_clkdm",
1241 .main_clk = "qspi_gfclk_div",
1244 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1245 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1246 .modulemode = MODULEMODE_SWCTRL,
1256 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1257 .sysc_offs = 0x0000,
1258 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1260 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1261 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1262 .sysc_fields = &omap_hwmod_sysc_type2,
1265 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1267 .sysc = &dra7xx_sata_sysc,
1272 static struct omap_hwmod dra7xx_sata_hwmod = {
1274 .class = &dra7xx_sata_hwmod_class,
1275 .clkdm_name = "l3init_clkdm",
1276 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1277 .main_clk = "func_48m_fclk",
1281 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1282 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1283 .modulemode = MODULEMODE_SWCTRL,
1289 * 'smartreflex' class
1293 /* The IP is not compliant to type1 / type2 scheme */
1294 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1299 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1300 .sysc_offs = 0x0038,
1301 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1302 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1304 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1307 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1308 .name = "smartreflex",
1309 .sysc = &dra7xx_smartreflex_sysc,
1313 /* smartreflex_core */
1314 /* smartreflex_core dev_attr */
1315 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1316 .sensor_voltdm_name = "core",
1319 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1320 .name = "smartreflex_core",
1321 .class = &dra7xx_smartreflex_hwmod_class,
1322 .clkdm_name = "coreaon_clkdm",
1323 .main_clk = "wkupaon_iclk_mux",
1326 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1327 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1328 .modulemode = MODULEMODE_SWCTRL,
1331 .dev_attr = &smartreflex_core_dev_attr,
1334 /* smartreflex_mpu */
1335 /* smartreflex_mpu dev_attr */
1336 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1337 .sensor_voltdm_name = "mpu",
1340 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1341 .name = "smartreflex_mpu",
1342 .class = &dra7xx_smartreflex_hwmod_class,
1343 .clkdm_name = "coreaon_clkdm",
1344 .main_clk = "wkupaon_iclk_mux",
1347 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1348 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1349 .modulemode = MODULEMODE_SWCTRL,
1352 .dev_attr = &smartreflex_mpu_dev_attr,
1360 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1362 .sysc_offs = 0x0010,
1363 .syss_offs = 0x0014,
1364 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1365 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1366 SYSS_HAS_RESET_STATUS),
1367 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1368 .sysc_fields = &omap_hwmod_sysc_type1,
1371 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1373 .sysc = &dra7xx_spinlock_sysc,
1377 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1379 .class = &dra7xx_spinlock_hwmod_class,
1380 .clkdm_name = "l4cfg_clkdm",
1381 .main_clk = "l3_iclk_div",
1384 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1385 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1393 * This class contains several variants: ['timer_1ms', 'timer_secure',
1397 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1399 .sysc_offs = 0x0010,
1400 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1401 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1402 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1404 .sysc_fields = &omap_hwmod_sysc_type2,
1407 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1409 .sysc = &dra7xx_timer_1ms_sysc,
1412 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1414 .sysc_offs = 0x0010,
1415 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1416 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1417 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1419 .sysc_fields = &omap_hwmod_sysc_type2,
1422 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1424 .sysc = &dra7xx_timer_secure_sysc,
1427 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1429 .sysc_offs = 0x0010,
1430 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1431 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1434 .sysc_fields = &omap_hwmod_sysc_type2,
1437 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1439 .sysc = &dra7xx_timer_sysc,
1443 static struct omap_hwmod dra7xx_timer1_hwmod = {
1445 .class = &dra7xx_timer_1ms_hwmod_class,
1446 .clkdm_name = "wkupaon_clkdm",
1447 .main_clk = "timer1_gfclk_mux",
1450 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1451 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1452 .modulemode = MODULEMODE_SWCTRL,
1458 static struct omap_hwmod dra7xx_timer2_hwmod = {
1460 .class = &dra7xx_timer_1ms_hwmod_class,
1461 .clkdm_name = "l4per_clkdm",
1462 .main_clk = "timer2_gfclk_mux",
1465 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1466 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1467 .modulemode = MODULEMODE_SWCTRL,
1473 static struct omap_hwmod dra7xx_timer3_hwmod = {
1475 .class = &dra7xx_timer_hwmod_class,
1476 .clkdm_name = "l4per_clkdm",
1477 .main_clk = "timer3_gfclk_mux",
1480 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1481 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1482 .modulemode = MODULEMODE_SWCTRL,
1488 static struct omap_hwmod dra7xx_timer4_hwmod = {
1490 .class = &dra7xx_timer_secure_hwmod_class,
1491 .clkdm_name = "l4per_clkdm",
1492 .main_clk = "timer4_gfclk_mux",
1495 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1496 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1497 .modulemode = MODULEMODE_SWCTRL,
1503 static struct omap_hwmod dra7xx_timer5_hwmod = {
1505 .class = &dra7xx_timer_hwmod_class,
1506 .clkdm_name = "ipu_clkdm",
1507 .main_clk = "timer5_gfclk_mux",
1510 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1511 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1512 .modulemode = MODULEMODE_SWCTRL,
1518 static struct omap_hwmod dra7xx_timer6_hwmod = {
1520 .class = &dra7xx_timer_hwmod_class,
1521 .clkdm_name = "ipu_clkdm",
1522 .main_clk = "timer6_gfclk_mux",
1525 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1526 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1527 .modulemode = MODULEMODE_SWCTRL,
1533 static struct omap_hwmod dra7xx_timer7_hwmod = {
1535 .class = &dra7xx_timer_hwmod_class,
1536 .clkdm_name = "ipu_clkdm",
1537 .main_clk = "timer7_gfclk_mux",
1540 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1541 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1542 .modulemode = MODULEMODE_SWCTRL,
1548 static struct omap_hwmod dra7xx_timer8_hwmod = {
1550 .class = &dra7xx_timer_hwmod_class,
1551 .clkdm_name = "ipu_clkdm",
1552 .main_clk = "timer8_gfclk_mux",
1555 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1556 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1557 .modulemode = MODULEMODE_SWCTRL,
1563 static struct omap_hwmod dra7xx_timer9_hwmod = {
1565 .class = &dra7xx_timer_hwmod_class,
1566 .clkdm_name = "l4per_clkdm",
1567 .main_clk = "timer9_gfclk_mux",
1570 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1571 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1572 .modulemode = MODULEMODE_SWCTRL,
1578 static struct omap_hwmod dra7xx_timer10_hwmod = {
1580 .class = &dra7xx_timer_1ms_hwmod_class,
1581 .clkdm_name = "l4per_clkdm",
1582 .main_clk = "timer10_gfclk_mux",
1585 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1586 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1587 .modulemode = MODULEMODE_SWCTRL,
1593 static struct omap_hwmod dra7xx_timer11_hwmod = {
1595 .class = &dra7xx_timer_hwmod_class,
1596 .clkdm_name = "l4per_clkdm",
1597 .main_clk = "timer11_gfclk_mux",
1600 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1601 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1602 .modulemode = MODULEMODE_SWCTRL,
1612 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1614 .sysc_offs = 0x0054,
1615 .syss_offs = 0x0058,
1616 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1617 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1618 SYSS_HAS_RESET_STATUS),
1619 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1621 .sysc_fields = &omap_hwmod_sysc_type1,
1624 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1626 .sysc = &dra7xx_uart_sysc,
1630 static struct omap_hwmod dra7xx_uart1_hwmod = {
1632 .class = &dra7xx_uart_hwmod_class,
1633 .clkdm_name = "l4per_clkdm",
1634 .main_clk = "uart1_gfclk_mux",
1635 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1638 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1639 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1640 .modulemode = MODULEMODE_SWCTRL,
1646 static struct omap_hwmod dra7xx_uart2_hwmod = {
1648 .class = &dra7xx_uart_hwmod_class,
1649 .clkdm_name = "l4per_clkdm",
1650 .main_clk = "uart2_gfclk_mux",
1651 .flags = HWMOD_SWSUP_SIDLE_ACT,
1654 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1655 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1656 .modulemode = MODULEMODE_SWCTRL,
1662 static struct omap_hwmod dra7xx_uart3_hwmod = {
1664 .class = &dra7xx_uart_hwmod_class,
1665 .clkdm_name = "l4per_clkdm",
1666 .main_clk = "uart3_gfclk_mux",
1667 .flags = HWMOD_SWSUP_SIDLE_ACT,
1670 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1671 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1672 .modulemode = MODULEMODE_SWCTRL,
1678 static struct omap_hwmod dra7xx_uart4_hwmod = {
1680 .class = &dra7xx_uart_hwmod_class,
1681 .clkdm_name = "l4per_clkdm",
1682 .main_clk = "uart4_gfclk_mux",
1683 .flags = HWMOD_SWSUP_SIDLE_ACT,
1686 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1687 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1688 .modulemode = MODULEMODE_SWCTRL,
1694 static struct omap_hwmod dra7xx_uart5_hwmod = {
1696 .class = &dra7xx_uart_hwmod_class,
1697 .clkdm_name = "l4per_clkdm",
1698 .main_clk = "uart5_gfclk_mux",
1699 .flags = HWMOD_SWSUP_SIDLE_ACT,
1702 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1703 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1704 .modulemode = MODULEMODE_SWCTRL,
1710 static struct omap_hwmod dra7xx_uart6_hwmod = {
1712 .class = &dra7xx_uart_hwmod_class,
1713 .clkdm_name = "ipu_clkdm",
1714 .main_clk = "uart6_gfclk_mux",
1715 .flags = HWMOD_SWSUP_SIDLE_ACT,
1718 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1719 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1720 .modulemode = MODULEMODE_SWCTRL,
1726 * 'usb_otg_ss' class
1730 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
1732 .sysc_offs = 0x0010,
1733 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1734 SYSC_HAS_SIDLEMODE),
1735 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1736 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1737 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1738 .sysc_fields = &omap_hwmod_sysc_type2,
1741 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1742 .name = "usb_otg_ss",
1743 .sysc = &dra7xx_usb_otg_ss_sysc,
1747 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1748 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1751 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1752 .name = "usb_otg_ss1",
1753 .class = &dra7xx_usb_otg_ss_hwmod_class,
1754 .clkdm_name = "l3init_clkdm",
1755 .main_clk = "dpll_core_h13x2_ck",
1758 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1759 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1760 .modulemode = MODULEMODE_HWCTRL,
1763 .opt_clks = usb_otg_ss1_opt_clks,
1764 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1768 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1769 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1772 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1773 .name = "usb_otg_ss2",
1774 .class = &dra7xx_usb_otg_ss_hwmod_class,
1775 .clkdm_name = "l3init_clkdm",
1776 .main_clk = "dpll_core_h13x2_ck",
1779 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1780 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1781 .modulemode = MODULEMODE_HWCTRL,
1784 .opt_clks = usb_otg_ss2_opt_clks,
1785 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1789 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1790 .name = "usb_otg_ss3",
1791 .class = &dra7xx_usb_otg_ss_hwmod_class,
1792 .clkdm_name = "l3init_clkdm",
1793 .main_clk = "dpll_core_h13x2_ck",
1796 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1797 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1798 .modulemode = MODULEMODE_HWCTRL,
1804 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1805 .name = "usb_otg_ss4",
1806 .class = &dra7xx_usb_otg_ss_hwmod_class,
1807 .clkdm_name = "l3init_clkdm",
1808 .main_clk = "dpll_core_h13x2_ck",
1811 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1812 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1813 .modulemode = MODULEMODE_HWCTRL,
1823 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1828 static struct omap_hwmod dra7xx_vcp1_hwmod = {
1830 .class = &dra7xx_vcp_hwmod_class,
1831 .clkdm_name = "l3main1_clkdm",
1832 .main_clk = "l3_iclk_div",
1835 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1836 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1842 static struct omap_hwmod dra7xx_vcp2_hwmod = {
1844 .class = &dra7xx_vcp_hwmod_class,
1845 .clkdm_name = "l3main1_clkdm",
1846 .main_clk = "l3_iclk_div",
1849 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1850 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1860 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1862 .sysc_offs = 0x0010,
1863 .syss_offs = 0x0014,
1864 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1865 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1866 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1868 .sysc_fields = &omap_hwmod_sysc_type1,
1871 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1873 .sysc = &dra7xx_wd_timer_sysc,
1874 .pre_shutdown = &omap2_wd_timer_disable,
1875 .reset = &omap2_wd_timer_reset,
1879 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1880 .name = "wd_timer2",
1881 .class = &dra7xx_wd_timer_hwmod_class,
1882 .clkdm_name = "wkupaon_clkdm",
1883 .main_clk = "sys_32k_ck",
1886 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1887 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1888 .modulemode = MODULEMODE_SWCTRL,
1898 /* l3_main_2 -> l3_instr */
1899 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1900 .master = &dra7xx_l3_main_2_hwmod,
1901 .slave = &dra7xx_l3_instr_hwmod,
1902 .clk = "l3_iclk_div",
1903 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906 /* l4_cfg -> l3_main_1 */
1907 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1908 .master = &dra7xx_l4_cfg_hwmod,
1909 .slave = &dra7xx_l3_main_1_hwmod,
1910 .clk = "l3_iclk_div",
1911 .user = OCP_USER_MPU | OCP_USER_SDMA,
1914 /* mpu -> l3_main_1 */
1915 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1916 .master = &dra7xx_mpu_hwmod,
1917 .slave = &dra7xx_l3_main_1_hwmod,
1918 .clk = "l3_iclk_div",
1919 .user = OCP_USER_MPU,
1922 /* l3_main_1 -> l3_main_2 */
1923 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1924 .master = &dra7xx_l3_main_1_hwmod,
1925 .slave = &dra7xx_l3_main_2_hwmod,
1926 .clk = "l3_iclk_div",
1927 .user = OCP_USER_MPU,
1930 /* l4_cfg -> l3_main_2 */
1931 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1932 .master = &dra7xx_l4_cfg_hwmod,
1933 .slave = &dra7xx_l3_main_2_hwmod,
1934 .clk = "l3_iclk_div",
1935 .user = OCP_USER_MPU | OCP_USER_SDMA,
1938 /* l3_main_1 -> l4_cfg */
1939 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1940 .master = &dra7xx_l3_main_1_hwmod,
1941 .slave = &dra7xx_l4_cfg_hwmod,
1942 .clk = "l3_iclk_div",
1943 .user = OCP_USER_MPU | OCP_USER_SDMA,
1946 /* l3_main_1 -> l4_per1 */
1947 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1948 .master = &dra7xx_l3_main_1_hwmod,
1949 .slave = &dra7xx_l4_per1_hwmod,
1950 .clk = "l3_iclk_div",
1951 .user = OCP_USER_MPU | OCP_USER_SDMA,
1954 /* l3_main_1 -> l4_per2 */
1955 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1956 .master = &dra7xx_l3_main_1_hwmod,
1957 .slave = &dra7xx_l4_per2_hwmod,
1958 .clk = "l3_iclk_div",
1959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1962 /* l3_main_1 -> l4_per3 */
1963 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1964 .master = &dra7xx_l3_main_1_hwmod,
1965 .slave = &dra7xx_l4_per3_hwmod,
1966 .clk = "l3_iclk_div",
1967 .user = OCP_USER_MPU | OCP_USER_SDMA,
1970 /* l3_main_1 -> l4_wkup */
1971 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1972 .master = &dra7xx_l3_main_1_hwmod,
1973 .slave = &dra7xx_l4_wkup_hwmod,
1974 .clk = "wkupaon_iclk_mux",
1975 .user = OCP_USER_MPU | OCP_USER_SDMA,
1978 /* l4_per2 -> atl */
1979 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1980 .master = &dra7xx_l4_per2_hwmod,
1981 .slave = &dra7xx_atl_hwmod,
1982 .clk = "l3_iclk_div",
1983 .user = OCP_USER_MPU | OCP_USER_SDMA,
1986 /* l3_main_1 -> bb2d */
1987 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1988 .master = &dra7xx_l3_main_1_hwmod,
1989 .slave = &dra7xx_bb2d_hwmod,
1990 .clk = "l3_iclk_div",
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1994 /* l4_wkup -> counter_32k */
1995 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1996 .master = &dra7xx_l4_wkup_hwmod,
1997 .slave = &dra7xx_counter_32k_hwmod,
1998 .clk = "wkupaon_iclk_mux",
1999 .user = OCP_USER_MPU | OCP_USER_SDMA,
2002 /* l4_wkup -> ctrl_module_wkup */
2003 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2004 .master = &dra7xx_l4_wkup_hwmod,
2005 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2006 .clk = "wkupaon_iclk_mux",
2007 .user = OCP_USER_MPU | OCP_USER_SDMA,
2010 /* l4_wkup -> dcan1 */
2011 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2012 .master = &dra7xx_l4_wkup_hwmod,
2013 .slave = &dra7xx_dcan1_hwmod,
2014 .clk = "wkupaon_iclk_mux",
2015 .user = OCP_USER_MPU | OCP_USER_SDMA,
2018 /* l4_per2 -> dcan2 */
2019 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2020 .master = &dra7xx_l4_per2_hwmod,
2021 .slave = &dra7xx_dcan2_hwmod,
2022 .clk = "l3_iclk_div",
2023 .user = OCP_USER_MPU | OCP_USER_SDMA,
2026 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2028 .pa_start = 0x4a056000,
2029 .pa_end = 0x4a056fff,
2030 .flags = ADDR_TYPE_RT
2035 /* l4_cfg -> dma_system */
2036 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2037 .master = &dra7xx_l4_cfg_hwmod,
2038 .slave = &dra7xx_dma_system_hwmod,
2039 .clk = "l3_iclk_div",
2040 .addr = dra7xx_dma_system_addrs,
2041 .user = OCP_USER_MPU | OCP_USER_SDMA,
2044 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2047 .pa_start = 0x58000000,
2048 .pa_end = 0x5800007f,
2049 .flags = ADDR_TYPE_RT
2053 /* l3_main_1 -> dss */
2054 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2055 .master = &dra7xx_l3_main_1_hwmod,
2056 .slave = &dra7xx_dss_hwmod,
2057 .clk = "l3_iclk_div",
2058 .addr = dra7xx_dss_addrs,
2059 .user = OCP_USER_MPU | OCP_USER_SDMA,
2062 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2065 .pa_start = 0x58001000,
2066 .pa_end = 0x58001fff,
2067 .flags = ADDR_TYPE_RT
2071 /* l3_main_1 -> dispc */
2072 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2073 .master = &dra7xx_l3_main_1_hwmod,
2074 .slave = &dra7xx_dss_dispc_hwmod,
2075 .clk = "l3_iclk_div",
2076 .addr = dra7xx_dss_dispc_addrs,
2077 .user = OCP_USER_MPU | OCP_USER_SDMA,
2080 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2083 .pa_start = 0x58040000,
2084 .pa_end = 0x580400ff,
2085 .flags = ADDR_TYPE_RT
2090 /* l3_main_1 -> dispc */
2091 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2092 .master = &dra7xx_l3_main_1_hwmod,
2093 .slave = &dra7xx_dss_hdmi_hwmod,
2094 .clk = "l3_iclk_div",
2095 .addr = dra7xx_dss_hdmi_addrs,
2096 .user = OCP_USER_MPU | OCP_USER_SDMA,
2099 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2101 .pa_start = 0x48078000,
2102 .pa_end = 0x48078fff,
2103 .flags = ADDR_TYPE_RT
2108 /* l4_per1 -> elm */
2109 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2110 .master = &dra7xx_l4_per1_hwmod,
2111 .slave = &dra7xx_elm_hwmod,
2112 .clk = "l3_iclk_div",
2113 .addr = dra7xx_elm_addrs,
2114 .user = OCP_USER_MPU | OCP_USER_SDMA,
2117 /* l4_wkup -> gpio1 */
2118 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2119 .master = &dra7xx_l4_wkup_hwmod,
2120 .slave = &dra7xx_gpio1_hwmod,
2121 .clk = "wkupaon_iclk_mux",
2122 .user = OCP_USER_MPU | OCP_USER_SDMA,
2125 /* l4_per1 -> gpio2 */
2126 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2127 .master = &dra7xx_l4_per1_hwmod,
2128 .slave = &dra7xx_gpio2_hwmod,
2129 .clk = "l3_iclk_div",
2130 .user = OCP_USER_MPU | OCP_USER_SDMA,
2133 /* l4_per1 -> gpio3 */
2134 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2135 .master = &dra7xx_l4_per1_hwmod,
2136 .slave = &dra7xx_gpio3_hwmod,
2137 .clk = "l3_iclk_div",
2138 .user = OCP_USER_MPU | OCP_USER_SDMA,
2141 /* l4_per1 -> gpio4 */
2142 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2143 .master = &dra7xx_l4_per1_hwmod,
2144 .slave = &dra7xx_gpio4_hwmod,
2145 .clk = "l3_iclk_div",
2146 .user = OCP_USER_MPU | OCP_USER_SDMA,
2149 /* l4_per1 -> gpio5 */
2150 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2151 .master = &dra7xx_l4_per1_hwmod,
2152 .slave = &dra7xx_gpio5_hwmod,
2153 .clk = "l3_iclk_div",
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2157 /* l4_per1 -> gpio6 */
2158 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2159 .master = &dra7xx_l4_per1_hwmod,
2160 .slave = &dra7xx_gpio6_hwmod,
2161 .clk = "l3_iclk_div",
2162 .user = OCP_USER_MPU | OCP_USER_SDMA,
2165 /* l4_per1 -> gpio7 */
2166 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2167 .master = &dra7xx_l4_per1_hwmod,
2168 .slave = &dra7xx_gpio7_hwmod,
2169 .clk = "l3_iclk_div",
2170 .user = OCP_USER_MPU | OCP_USER_SDMA,
2173 /* l4_per1 -> gpio8 */
2174 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2175 .master = &dra7xx_l4_per1_hwmod,
2176 .slave = &dra7xx_gpio8_hwmod,
2177 .clk = "l3_iclk_div",
2178 .user = OCP_USER_MPU | OCP_USER_SDMA,
2181 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2183 .pa_start = 0x50000000,
2184 .pa_end = 0x500003ff,
2185 .flags = ADDR_TYPE_RT
2190 /* l3_main_1 -> gpmc */
2191 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2192 .master = &dra7xx_l3_main_1_hwmod,
2193 .slave = &dra7xx_gpmc_hwmod,
2194 .clk = "l3_iclk_div",
2195 .addr = dra7xx_gpmc_addrs,
2196 .user = OCP_USER_MPU | OCP_USER_SDMA,
2199 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2201 .pa_start = 0x480b2000,
2202 .pa_end = 0x480b201f,
2203 .flags = ADDR_TYPE_RT
2208 /* l4_per1 -> hdq1w */
2209 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2210 .master = &dra7xx_l4_per1_hwmod,
2211 .slave = &dra7xx_hdq1w_hwmod,
2212 .clk = "l3_iclk_div",
2213 .addr = dra7xx_hdq1w_addrs,
2214 .user = OCP_USER_MPU | OCP_USER_SDMA,
2217 /* l4_per1 -> i2c1 */
2218 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2219 .master = &dra7xx_l4_per1_hwmod,
2220 .slave = &dra7xx_i2c1_hwmod,
2221 .clk = "l3_iclk_div",
2222 .user = OCP_USER_MPU | OCP_USER_SDMA,
2225 /* l4_per1 -> i2c2 */
2226 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2227 .master = &dra7xx_l4_per1_hwmod,
2228 .slave = &dra7xx_i2c2_hwmod,
2229 .clk = "l3_iclk_div",
2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2233 /* l4_per1 -> i2c3 */
2234 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2235 .master = &dra7xx_l4_per1_hwmod,
2236 .slave = &dra7xx_i2c3_hwmod,
2237 .clk = "l3_iclk_div",
2238 .user = OCP_USER_MPU | OCP_USER_SDMA,
2241 /* l4_per1 -> i2c4 */
2242 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2243 .master = &dra7xx_l4_per1_hwmod,
2244 .slave = &dra7xx_i2c4_hwmod,
2245 .clk = "l3_iclk_div",
2246 .user = OCP_USER_MPU | OCP_USER_SDMA,
2249 /* l4_per1 -> i2c5 */
2250 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2251 .master = &dra7xx_l4_per1_hwmod,
2252 .slave = &dra7xx_i2c5_hwmod,
2253 .clk = "l3_iclk_div",
2254 .user = OCP_USER_MPU | OCP_USER_SDMA,
2257 /* l4_per1 -> mcspi1 */
2258 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2259 .master = &dra7xx_l4_per1_hwmod,
2260 .slave = &dra7xx_mcspi1_hwmod,
2261 .clk = "l3_iclk_div",
2262 .user = OCP_USER_MPU | OCP_USER_SDMA,
2265 /* l4_per1 -> mcspi2 */
2266 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2267 .master = &dra7xx_l4_per1_hwmod,
2268 .slave = &dra7xx_mcspi2_hwmod,
2269 .clk = "l3_iclk_div",
2270 .user = OCP_USER_MPU | OCP_USER_SDMA,
2273 /* l4_per1 -> mcspi3 */
2274 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2275 .master = &dra7xx_l4_per1_hwmod,
2276 .slave = &dra7xx_mcspi3_hwmod,
2277 .clk = "l3_iclk_div",
2278 .user = OCP_USER_MPU | OCP_USER_SDMA,
2281 /* l4_per1 -> mcspi4 */
2282 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2283 .master = &dra7xx_l4_per1_hwmod,
2284 .slave = &dra7xx_mcspi4_hwmod,
2285 .clk = "l3_iclk_div",
2286 .user = OCP_USER_MPU | OCP_USER_SDMA,
2289 /* l4_per1 -> mmc1 */
2290 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2291 .master = &dra7xx_l4_per1_hwmod,
2292 .slave = &dra7xx_mmc1_hwmod,
2293 .clk = "l3_iclk_div",
2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 /* l4_per1 -> mmc2 */
2298 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2299 .master = &dra7xx_l4_per1_hwmod,
2300 .slave = &dra7xx_mmc2_hwmod,
2301 .clk = "l3_iclk_div",
2302 .user = OCP_USER_MPU | OCP_USER_SDMA,
2305 /* l4_per1 -> mmc3 */
2306 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2307 .master = &dra7xx_l4_per1_hwmod,
2308 .slave = &dra7xx_mmc3_hwmod,
2309 .clk = "l3_iclk_div",
2310 .user = OCP_USER_MPU | OCP_USER_SDMA,
2313 /* l4_per1 -> mmc4 */
2314 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2315 .master = &dra7xx_l4_per1_hwmod,
2316 .slave = &dra7xx_mmc4_hwmod,
2317 .clk = "l3_iclk_div",
2318 .user = OCP_USER_MPU | OCP_USER_SDMA,
2322 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2323 .master = &dra7xx_l4_cfg_hwmod,
2324 .slave = &dra7xx_mpu_hwmod,
2325 .clk = "l3_iclk_div",
2326 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329 /* l4_cfg -> ocp2scp1 */
2330 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2331 .master = &dra7xx_l4_cfg_hwmod,
2332 .slave = &dra7xx_ocp2scp1_hwmod,
2333 .clk = "l4_root_clk_div",
2334 .user = OCP_USER_MPU | OCP_USER_SDMA,
2337 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2339 .pa_start = 0x4b300000,
2340 .pa_end = 0x4b30007f,
2341 .flags = ADDR_TYPE_RT
2346 /* l3_main_1 -> qspi */
2347 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2348 .master = &dra7xx_l3_main_1_hwmod,
2349 .slave = &dra7xx_qspi_hwmod,
2350 .clk = "l3_iclk_div",
2351 .addr = dra7xx_qspi_addrs,
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2355 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2358 .pa_start = 0x4a141100,
2359 .pa_end = 0x4a141107,
2360 .flags = ADDR_TYPE_RT
2365 /* l4_cfg -> sata */
2366 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2367 .master = &dra7xx_l4_cfg_hwmod,
2368 .slave = &dra7xx_sata_hwmod,
2369 .clk = "l3_iclk_div",
2370 .addr = dra7xx_sata_addrs,
2371 .user = OCP_USER_MPU | OCP_USER_SDMA,
2374 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2376 .pa_start = 0x4a0dd000,
2377 .pa_end = 0x4a0dd07f,
2378 .flags = ADDR_TYPE_RT
2383 /* l4_cfg -> smartreflex_core */
2384 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2385 .master = &dra7xx_l4_cfg_hwmod,
2386 .slave = &dra7xx_smartreflex_core_hwmod,
2387 .clk = "l4_root_clk_div",
2388 .addr = dra7xx_smartreflex_core_addrs,
2389 .user = OCP_USER_MPU | OCP_USER_SDMA,
2392 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2394 .pa_start = 0x4a0d9000,
2395 .pa_end = 0x4a0d907f,
2396 .flags = ADDR_TYPE_RT
2401 /* l4_cfg -> smartreflex_mpu */
2402 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2403 .master = &dra7xx_l4_cfg_hwmod,
2404 .slave = &dra7xx_smartreflex_mpu_hwmod,
2405 .clk = "l4_root_clk_div",
2406 .addr = dra7xx_smartreflex_mpu_addrs,
2407 .user = OCP_USER_MPU | OCP_USER_SDMA,
2410 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2412 .pa_start = 0x4a0f6000,
2413 .pa_end = 0x4a0f6fff,
2414 .flags = ADDR_TYPE_RT
2419 /* l4_cfg -> spinlock */
2420 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2421 .master = &dra7xx_l4_cfg_hwmod,
2422 .slave = &dra7xx_spinlock_hwmod,
2423 .clk = "l3_iclk_div",
2424 .addr = dra7xx_spinlock_addrs,
2425 .user = OCP_USER_MPU | OCP_USER_SDMA,
2428 /* l4_wkup -> timer1 */
2429 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2430 .master = &dra7xx_l4_wkup_hwmod,
2431 .slave = &dra7xx_timer1_hwmod,
2432 .clk = "wkupaon_iclk_mux",
2433 .user = OCP_USER_MPU | OCP_USER_SDMA,
2436 /* l4_per1 -> timer2 */
2437 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2438 .master = &dra7xx_l4_per1_hwmod,
2439 .slave = &dra7xx_timer2_hwmod,
2440 .clk = "l3_iclk_div",
2441 .user = OCP_USER_MPU | OCP_USER_SDMA,
2444 /* l4_per1 -> timer3 */
2445 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2446 .master = &dra7xx_l4_per1_hwmod,
2447 .slave = &dra7xx_timer3_hwmod,
2448 .clk = "l3_iclk_div",
2449 .user = OCP_USER_MPU | OCP_USER_SDMA,
2452 /* l4_per1 -> timer4 */
2453 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2454 .master = &dra7xx_l4_per1_hwmod,
2455 .slave = &dra7xx_timer4_hwmod,
2456 .clk = "l3_iclk_div",
2457 .user = OCP_USER_MPU | OCP_USER_SDMA,
2460 /* l4_per3 -> timer5 */
2461 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2462 .master = &dra7xx_l4_per3_hwmod,
2463 .slave = &dra7xx_timer5_hwmod,
2464 .clk = "l3_iclk_div",
2465 .user = OCP_USER_MPU | OCP_USER_SDMA,
2468 /* l4_per3 -> timer6 */
2469 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2470 .master = &dra7xx_l4_per3_hwmod,
2471 .slave = &dra7xx_timer6_hwmod,
2472 .clk = "l3_iclk_div",
2473 .user = OCP_USER_MPU | OCP_USER_SDMA,
2476 /* l4_per3 -> timer7 */
2477 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2478 .master = &dra7xx_l4_per3_hwmod,
2479 .slave = &dra7xx_timer7_hwmod,
2480 .clk = "l3_iclk_div",
2481 .user = OCP_USER_MPU | OCP_USER_SDMA,
2484 /* l4_per3 -> timer8 */
2485 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2486 .master = &dra7xx_l4_per3_hwmod,
2487 .slave = &dra7xx_timer8_hwmod,
2488 .clk = "l3_iclk_div",
2489 .user = OCP_USER_MPU | OCP_USER_SDMA,
2492 /* l4_per1 -> timer9 */
2493 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2494 .master = &dra7xx_l4_per1_hwmod,
2495 .slave = &dra7xx_timer9_hwmod,
2496 .clk = "l3_iclk_div",
2497 .user = OCP_USER_MPU | OCP_USER_SDMA,
2500 /* l4_per1 -> timer10 */
2501 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2502 .master = &dra7xx_l4_per1_hwmod,
2503 .slave = &dra7xx_timer10_hwmod,
2504 .clk = "l3_iclk_div",
2505 .user = OCP_USER_MPU | OCP_USER_SDMA,
2508 /* l4_per1 -> timer11 */
2509 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2510 .master = &dra7xx_l4_per1_hwmod,
2511 .slave = &dra7xx_timer11_hwmod,
2512 .clk = "l3_iclk_div",
2513 .user = OCP_USER_MPU | OCP_USER_SDMA,
2516 /* l4_per1 -> uart1 */
2517 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2518 .master = &dra7xx_l4_per1_hwmod,
2519 .slave = &dra7xx_uart1_hwmod,
2520 .clk = "l3_iclk_div",
2521 .user = OCP_USER_MPU | OCP_USER_SDMA,
2524 /* l4_per1 -> uart2 */
2525 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2526 .master = &dra7xx_l4_per1_hwmod,
2527 .slave = &dra7xx_uart2_hwmod,
2528 .clk = "l3_iclk_div",
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532 /* l4_per1 -> uart3 */
2533 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2534 .master = &dra7xx_l4_per1_hwmod,
2535 .slave = &dra7xx_uart3_hwmod,
2536 .clk = "l3_iclk_div",
2537 .user = OCP_USER_MPU | OCP_USER_SDMA,
2540 /* l4_per1 -> uart4 */
2541 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2542 .master = &dra7xx_l4_per1_hwmod,
2543 .slave = &dra7xx_uart4_hwmod,
2544 .clk = "l3_iclk_div",
2545 .user = OCP_USER_MPU | OCP_USER_SDMA,
2548 /* l4_per1 -> uart5 */
2549 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2550 .master = &dra7xx_l4_per1_hwmod,
2551 .slave = &dra7xx_uart5_hwmod,
2552 .clk = "l3_iclk_div",
2553 .user = OCP_USER_MPU | OCP_USER_SDMA,
2556 /* l4_per1 -> uart6 */
2557 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2558 .master = &dra7xx_l4_per1_hwmod,
2559 .slave = &dra7xx_uart6_hwmod,
2560 .clk = "l3_iclk_div",
2561 .user = OCP_USER_MPU | OCP_USER_SDMA,
2564 /* l4_per3 -> usb_otg_ss1 */
2565 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2566 .master = &dra7xx_l4_per3_hwmod,
2567 .slave = &dra7xx_usb_otg_ss1_hwmod,
2568 .clk = "dpll_core_h13x2_ck",
2569 .user = OCP_USER_MPU | OCP_USER_SDMA,
2572 /* l4_per3 -> usb_otg_ss2 */
2573 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2574 .master = &dra7xx_l4_per3_hwmod,
2575 .slave = &dra7xx_usb_otg_ss2_hwmod,
2576 .clk = "dpll_core_h13x2_ck",
2577 .user = OCP_USER_MPU | OCP_USER_SDMA,
2580 /* l4_per3 -> usb_otg_ss3 */
2581 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2582 .master = &dra7xx_l4_per3_hwmod,
2583 .slave = &dra7xx_usb_otg_ss3_hwmod,
2584 .clk = "dpll_core_h13x2_ck",
2585 .user = OCP_USER_MPU | OCP_USER_SDMA,
2588 /* l4_per3 -> usb_otg_ss4 */
2589 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2590 .master = &dra7xx_l4_per3_hwmod,
2591 .slave = &dra7xx_usb_otg_ss4_hwmod,
2592 .clk = "dpll_core_h13x2_ck",
2593 .user = OCP_USER_MPU | OCP_USER_SDMA,
2596 /* l3_main_1 -> vcp1 */
2597 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2598 .master = &dra7xx_l3_main_1_hwmod,
2599 .slave = &dra7xx_vcp1_hwmod,
2600 .clk = "l3_iclk_div",
2601 .user = OCP_USER_MPU | OCP_USER_SDMA,
2604 /* l4_per2 -> vcp1 */
2605 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2606 .master = &dra7xx_l4_per2_hwmod,
2607 .slave = &dra7xx_vcp1_hwmod,
2608 .clk = "l3_iclk_div",
2609 .user = OCP_USER_MPU | OCP_USER_SDMA,
2612 /* l3_main_1 -> vcp2 */
2613 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2614 .master = &dra7xx_l3_main_1_hwmod,
2615 .slave = &dra7xx_vcp2_hwmod,
2616 .clk = "l3_iclk_div",
2617 .user = OCP_USER_MPU | OCP_USER_SDMA,
2620 /* l4_per2 -> vcp2 */
2621 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2622 .master = &dra7xx_l4_per2_hwmod,
2623 .slave = &dra7xx_vcp2_hwmod,
2624 .clk = "l3_iclk_div",
2625 .user = OCP_USER_MPU | OCP_USER_SDMA,
2628 /* l4_wkup -> wd_timer2 */
2629 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2630 .master = &dra7xx_l4_wkup_hwmod,
2631 .slave = &dra7xx_wd_timer2_hwmod,
2632 .clk = "wkupaon_iclk_mux",
2633 .user = OCP_USER_MPU | OCP_USER_SDMA,
2636 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2637 &dra7xx_l3_main_2__l3_instr,
2638 &dra7xx_l4_cfg__l3_main_1,
2639 &dra7xx_mpu__l3_main_1,
2640 &dra7xx_l3_main_1__l3_main_2,
2641 &dra7xx_l4_cfg__l3_main_2,
2642 &dra7xx_l3_main_1__l4_cfg,
2643 &dra7xx_l3_main_1__l4_per1,
2644 &dra7xx_l3_main_1__l4_per2,
2645 &dra7xx_l3_main_1__l4_per3,
2646 &dra7xx_l3_main_1__l4_wkup,
2647 &dra7xx_l4_per2__atl,
2648 &dra7xx_l3_main_1__bb2d,
2649 &dra7xx_l4_wkup__counter_32k,
2650 &dra7xx_l4_wkup__ctrl_module_wkup,
2651 &dra7xx_l4_wkup__dcan1,
2652 &dra7xx_l4_per2__dcan2,
2653 &dra7xx_l4_cfg__dma_system,
2654 &dra7xx_l3_main_1__dss,
2655 &dra7xx_l3_main_1__dispc,
2656 &dra7xx_l3_main_1__hdmi,
2657 &dra7xx_l4_per1__elm,
2658 &dra7xx_l4_wkup__gpio1,
2659 &dra7xx_l4_per1__gpio2,
2660 &dra7xx_l4_per1__gpio3,
2661 &dra7xx_l4_per1__gpio4,
2662 &dra7xx_l4_per1__gpio5,
2663 &dra7xx_l4_per1__gpio6,
2664 &dra7xx_l4_per1__gpio7,
2665 &dra7xx_l4_per1__gpio8,
2666 &dra7xx_l3_main_1__gpmc,
2667 &dra7xx_l4_per1__hdq1w,
2668 &dra7xx_l4_per1__i2c1,
2669 &dra7xx_l4_per1__i2c2,
2670 &dra7xx_l4_per1__i2c3,
2671 &dra7xx_l4_per1__i2c4,
2672 &dra7xx_l4_per1__i2c5,
2673 &dra7xx_l4_per1__mcspi1,
2674 &dra7xx_l4_per1__mcspi2,
2675 &dra7xx_l4_per1__mcspi3,
2676 &dra7xx_l4_per1__mcspi4,
2677 &dra7xx_l4_per1__mmc1,
2678 &dra7xx_l4_per1__mmc2,
2679 &dra7xx_l4_per1__mmc3,
2680 &dra7xx_l4_per1__mmc4,
2681 &dra7xx_l4_cfg__mpu,
2682 &dra7xx_l4_cfg__ocp2scp1,
2683 &dra7xx_l3_main_1__qspi,
2684 &dra7xx_l4_cfg__sata,
2685 &dra7xx_l4_cfg__smartreflex_core,
2686 &dra7xx_l4_cfg__smartreflex_mpu,
2687 &dra7xx_l4_cfg__spinlock,
2688 &dra7xx_l4_wkup__timer1,
2689 &dra7xx_l4_per1__timer2,
2690 &dra7xx_l4_per1__timer3,
2691 &dra7xx_l4_per1__timer4,
2692 &dra7xx_l4_per3__timer5,
2693 &dra7xx_l4_per3__timer6,
2694 &dra7xx_l4_per3__timer7,
2695 &dra7xx_l4_per3__timer8,
2696 &dra7xx_l4_per1__timer9,
2697 &dra7xx_l4_per1__timer10,
2698 &dra7xx_l4_per1__timer11,
2699 &dra7xx_l4_per1__uart1,
2700 &dra7xx_l4_per1__uart2,
2701 &dra7xx_l4_per1__uart3,
2702 &dra7xx_l4_per1__uart4,
2703 &dra7xx_l4_per1__uart5,
2704 &dra7xx_l4_per1__uart6,
2705 &dra7xx_l4_per3__usb_otg_ss1,
2706 &dra7xx_l4_per3__usb_otg_ss2,
2707 &dra7xx_l4_per3__usb_otg_ss3,
2708 &dra7xx_l4_per3__usb_otg_ss4,
2709 &dra7xx_l3_main_1__vcp1,
2710 &dra7xx_l4_per2__vcp1,
2711 &dra7xx_l3_main_1__vcp2,
2712 &dra7xx_l4_per2__vcp2,
2713 &dra7xx_l4_wkup__wd_timer2,
2717 int __init dra7xx_hwmod_init(void)
2720 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);