arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "wd_timer.h"
  41
  42 /* Base offset for all OMAP4 interrupts external to MPUSS */
  43 #define OMAP44XX_IRQ_GIC_START  32
  44
  45 /* Base offset for all OMAP4 dma requests */
  46 #define OMAP44XX_DMA_REQ_START  1
  47
  48 /* Backward references (IPs with Bus Master capability) */
  49 static struct omap_hwmod omap44xx_aess_hwmod;
  50 static struct omap_hwmod omap44xx_dma_system_hwmod;
  51 static struct omap_hwmod omap44xx_dmm_hwmod;
  52 static struct omap_hwmod omap44xx_dsp_hwmod;
  53 static struct omap_hwmod omap44xx_dss_hwmod;
  54 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  55 static struct omap_hwmod omap44xx_hsi_hwmod;
  56 static struct omap_hwmod omap44xx_ipu_hwmod;
  57 static struct omap_hwmod omap44xx_iss_hwmod;
  58 static struct omap_hwmod omap44xx_iva_hwmod;
  59 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  60 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  62 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  63 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  64 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  65 static struct omap_hwmod omap44xx_l4_per_hwmod;
  66 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  67 static struct omap_hwmod omap44xx_mmc1_hwmod;
  68 static struct omap_hwmod omap44xx_mmc2_hwmod;
  69 static struct omap_hwmod omap44xx_mpu_hwmod;
  70 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  71 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  72 static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
  73 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
  74
  75 /*
  76  * Interconnects omap_hwmod structures
  77  * hwmods that compose the global OMAP interconnect
  78  */
  79
  80 /*
  81  * 'dmm' class
  82  * instance(s): dmm
  83  */
  84 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  85         .name   = "dmm",
  86 };
  87
  88 /* dmm */
  89 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  90         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  91         { .irq = -1 }
  92 };
  93
  94 /* l3_main_1 -> dmm */
  95 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  96         .master         = &omap44xx_l3_main_1_hwmod,
  97         .slave          = &omap44xx_dmm_hwmod,
  98         .clk            = "l3_div_ck",
  99         .user           = OCP_USER_SDMA,
 100 };
 101
 102 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 103         {
 104                 .pa_start       = 0x4e000000,
 105                 .pa_end         = 0x4e0007ff,
 106                 .flags          = ADDR_TYPE_RT
 107         },
 108         { }
 109 };
 110
 111 /* mpu -> dmm */
 112 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 113         .master         = &omap44xx_mpu_hwmod,
 114         .slave          = &omap44xx_dmm_hwmod,
 115         .clk            = "l3_div_ck",
 116         .addr           = omap44xx_dmm_addrs,
 117         .user           = OCP_USER_MPU,
 118 };
 119
 120 /* dmm slave ports */
 121 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 122         &omap44xx_l3_main_1__dmm,
 123         &omap44xx_mpu__dmm,
 124 };
 125
 126 static struct omap_hwmod omap44xx_dmm_hwmod = {
 127         .name           = "dmm",
 128         .class          = &omap44xx_dmm_hwmod_class,
 129         .clkdm_name     = "l3_emif_clkdm",
 130         .prcm = {
 131                 .omap4 = {
 132                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
 133                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 134                 },
 135         },
 136         .slaves         = omap44xx_dmm_slaves,
 137         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 138         .mpu_irqs       = omap44xx_dmm_irqs,
 139 };
 140
 141 /*
 142  * 'emif_fw' class
 143  * instance(s): emif_fw
 144  */
 145 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 146         .name   = "emif_fw",
 147 };
 148
 149 /* emif_fw */
 150 /* dmm -> emif_fw */
 151 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 152         .master         = &omap44xx_dmm_hwmod,
 153         .slave          = &omap44xx_emif_fw_hwmod,
 154         .clk            = "l3_div_ck",
 155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 156 };
 157
 158 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 159         {
 160                 .pa_start       = 0x4a20c000,
 161                 .pa_end         = 0x4a20c0ff,
 162                 .flags          = ADDR_TYPE_RT
 163         },
 164         { }
 165 };
 166
 167 /* l4_cfg -> emif_fw */
 168 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 169         .master         = &omap44xx_l4_cfg_hwmod,
 170         .slave          = &omap44xx_emif_fw_hwmod,
 171         .clk            = "l4_div_ck",
 172         .addr           = omap44xx_emif_fw_addrs,
 173         .user           = OCP_USER_MPU,
 174 };
 175
 176 /* emif_fw slave ports */
 177 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 178         &omap44xx_dmm__emif_fw,
 179         &omap44xx_l4_cfg__emif_fw,
 180 };
 181
 182 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 183         .name           = "emif_fw",
 184         .class          = &omap44xx_emif_fw_hwmod_class,
 185         .clkdm_name     = "l3_emif_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 189                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 190                 },
 191         },
 192         .slaves         = omap44xx_emif_fw_slaves,
 193         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 194 };
 195
 196 /*
 197  * 'l3' class
 198  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 199  */
 200 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 201         .name   = "l3",
 202 };
 203
 204 /* l3_instr */
 205 /* iva -> l3_instr */
 206 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 207         .master         = &omap44xx_iva_hwmod,
 208         .slave          = &omap44xx_l3_instr_hwmod,
 209         .clk            = "l3_div_ck",
 210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 211 };
 212
 213 /* l3_main_3 -> l3_instr */
 214 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 215         .master         = &omap44xx_l3_main_3_hwmod,
 216         .slave          = &omap44xx_l3_instr_hwmod,
 217         .clk            = "l3_div_ck",
 218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 219 };
 220
 221 /* l3_instr slave ports */
 222 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 223         &omap44xx_iva__l3_instr,
 224         &omap44xx_l3_main_3__l3_instr,
 225 };
 226
 227 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 228         .name           = "l3_instr",
 229         .class          = &omap44xx_l3_hwmod_class,
 230         .clkdm_name     = "l3_instr_clkdm",
 231         .prcm = {
 232                 .omap4 = {
 233                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 234                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 235                         .modulemode   = MODULEMODE_HWCTRL,
 236                 },
 237         },
 238         .slaves         = omap44xx_l3_instr_slaves,
 239         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 240 };
 241
 242 /* l3_main_1 */
 243 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 244         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 245         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 246         { .irq = -1 }
 247 };
 248
 249 /* dsp -> l3_main_1 */
 250 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 251         .master         = &omap44xx_dsp_hwmod,
 252         .slave          = &omap44xx_l3_main_1_hwmod,
 253         .clk            = "l3_div_ck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 /* dss -> l3_main_1 */
 258 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 259         .master         = &omap44xx_dss_hwmod,
 260         .slave          = &omap44xx_l3_main_1_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* l3_main_2 -> l3_main_1 */
 266 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 267         .master         = &omap44xx_l3_main_2_hwmod,
 268         .slave          = &omap44xx_l3_main_1_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 /* l4_cfg -> l3_main_1 */
 274 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 275         .master         = &omap44xx_l4_cfg_hwmod,
 276         .slave          = &omap44xx_l3_main_1_hwmod,
 277         .clk            = "l4_div_ck",
 278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 279 };
 280
 281 /* mmc1 -> l3_main_1 */
 282 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 283         .master         = &omap44xx_mmc1_hwmod,
 284         .slave          = &omap44xx_l3_main_1_hwmod,
 285         .clk            = "l3_div_ck",
 286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 287 };
 288
 289 /* mmc2 -> l3_main_1 */
 290 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 291         .master         = &omap44xx_mmc2_hwmod,
 292         .slave          = &omap44xx_l3_main_1_hwmod,
 293         .clk            = "l3_div_ck",
 294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 295 };
 296
 297 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 298         {
 299                 .pa_start       = 0x44000000,
 300                 .pa_end         = 0x44000fff,
 301                 .flags          = ADDR_TYPE_RT
 302         },
 303         { }
 304 };
 305
 306 /* mpu -> l3_main_1 */
 307 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 308         .master         = &omap44xx_mpu_hwmod,
 309         .slave          = &omap44xx_l3_main_1_hwmod,
 310         .clk            = "l3_div_ck",
 311         .addr           = omap44xx_l3_main_1_addrs,
 312         .user           = OCP_USER_MPU,
 313 };
 314
 315 /* l3_main_1 slave ports */
 316 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 317         &omap44xx_dsp__l3_main_1,
 318         &omap44xx_dss__l3_main_1,
 319         &omap44xx_l3_main_2__l3_main_1,
 320         &omap44xx_l4_cfg__l3_main_1,
 321         &omap44xx_mmc1__l3_main_1,
 322         &omap44xx_mmc2__l3_main_1,
 323         &omap44xx_mpu__l3_main_1,
 324 };
 325
 326 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 327         .name           = "l3_main_1",
 328         .class          = &omap44xx_l3_hwmod_class,
 329         .clkdm_name     = "l3_1_clkdm",
 330         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 331         .prcm = {
 332                 .omap4 = {
 333                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 334                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 335                 },
 336         },
 337         .slaves         = omap44xx_l3_main_1_slaves,
 338         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 339 };
 340
 341 /* l3_main_2 */
 342 /* dma_system -> l3_main_2 */
 343 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 344         .master         = &omap44xx_dma_system_hwmod,
 345         .slave          = &omap44xx_l3_main_2_hwmod,
 346         .clk            = "l3_div_ck",
 347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 348 };
 349
 350 /* hsi -> l3_main_2 */
 351 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 352         .master         = &omap44xx_hsi_hwmod,
 353         .slave          = &omap44xx_l3_main_2_hwmod,
 354         .clk            = "l3_div_ck",
 355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 356 };
 357
 358 /* ipu -> l3_main_2 */
 359 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 360         .master         = &omap44xx_ipu_hwmod,
 361         .slave          = &omap44xx_l3_main_2_hwmod,
 362         .clk            = "l3_div_ck",
 363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 364 };
 365
 366 /* iss -> l3_main_2 */
 367 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 368         .master         = &omap44xx_iss_hwmod,
 369         .slave          = &omap44xx_l3_main_2_hwmod,
 370         .clk            = "l3_div_ck",
 371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 372 };
 373
 374 /* iva -> l3_main_2 */
 375 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 376         .master         = &omap44xx_iva_hwmod,
 377         .slave          = &omap44xx_l3_main_2_hwmod,
 378         .clk            = "l3_div_ck",
 379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 380 };
 381
 382 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 383         {
 384                 .pa_start       = 0x44800000,
 385                 .pa_end         = 0x44801fff,
 386                 .flags          = ADDR_TYPE_RT
 387         },
 388         { }
 389 };
 390
 391 /* l3_main_1 -> l3_main_2 */
 392 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 393         .master         = &omap44xx_l3_main_1_hwmod,
 394         .slave          = &omap44xx_l3_main_2_hwmod,
 395         .clk            = "l3_div_ck",
 396         .addr           = omap44xx_l3_main_2_addrs,
 397         .user           = OCP_USER_MPU,
 398 };
 399
 400 /* l4_cfg -> l3_main_2 */
 401 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 402         .master         = &omap44xx_l4_cfg_hwmod,
 403         .slave          = &omap44xx_l3_main_2_hwmod,
 404         .clk            = "l4_div_ck",
 405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 406 };
 407
 408 /* usb_otg_hs -> l3_main_2 */
 409 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 410         .master         = &omap44xx_usb_otg_hs_hwmod,
 411         .slave          = &omap44xx_l3_main_2_hwmod,
 412         .clk            = "l3_div_ck",
 413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 414 };
 415
 416 /* l3_main_2 slave ports */
 417 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 418         &omap44xx_dma_system__l3_main_2,
 419         &omap44xx_hsi__l3_main_2,
 420         &omap44xx_ipu__l3_main_2,
 421         &omap44xx_iss__l3_main_2,
 422         &omap44xx_iva__l3_main_2,
 423         &omap44xx_l3_main_1__l3_main_2,
 424         &omap44xx_l4_cfg__l3_main_2,
 425         &omap44xx_usb_otg_hs__l3_main_2,
 426 };
 427
 428 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 429         .name           = "l3_main_2",
 430         .class          = &omap44xx_l3_hwmod_class,
 431         .clkdm_name     = "l3_2_clkdm",
 432         .prcm = {
 433                 .omap4 = {
 434                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 435                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 436                 },
 437         },
 438         .slaves         = omap44xx_l3_main_2_slaves,
 439         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 440 };
 441
 442 /* l3_main_3 */
 443 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 444         {
 445                 .pa_start       = 0x45000000,
 446                 .pa_end         = 0x45000fff,
 447                 .flags          = ADDR_TYPE_RT
 448         },
 449         { }
 450 };
 451
 452 /* l3_main_1 -> l3_main_3 */
 453 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 454         .master         = &omap44xx_l3_main_1_hwmod,
 455         .slave          = &omap44xx_l3_main_3_hwmod,
 456         .clk            = "l3_div_ck",
 457         .addr           = omap44xx_l3_main_3_addrs,
 458         .user           = OCP_USER_MPU,
 459 };
 460
 461 /* l3_main_2 -> l3_main_3 */
 462 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 463         .master         = &omap44xx_l3_main_2_hwmod,
 464         .slave          = &omap44xx_l3_main_3_hwmod,
 465         .clk            = "l3_div_ck",
 466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 467 };
 468
 469 /* l4_cfg -> l3_main_3 */
 470 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 471         .master         = &omap44xx_l4_cfg_hwmod,
 472         .slave          = &omap44xx_l3_main_3_hwmod,
 473         .clk            = "l4_div_ck",
 474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 475 };
 476
 477 /* l3_main_3 slave ports */
 478 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 479         &omap44xx_l3_main_1__l3_main_3,
 480         &omap44xx_l3_main_2__l3_main_3,
 481         &omap44xx_l4_cfg__l3_main_3,
 482 };
 483
 484 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 485         .name           = "l3_main_3",
 486         .class          = &omap44xx_l3_hwmod_class,
 487         .clkdm_name     = "l3_instr_clkdm",
 488         .prcm = {
 489                 .omap4 = {
 490                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 491                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 492                         .modulemode   = MODULEMODE_HWCTRL,
 493                 },
 494         },
 495         .slaves         = omap44xx_l3_main_3_slaves,
 496         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 497 };
 498
 499 /*
 500  * 'l4' class
 501  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 502  */
 503 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 504         .name   = "l4",
 505 };
 506
 507 /* l4_abe */
 508 /* aess -> l4_abe */
 509 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 510         .master         = &omap44xx_aess_hwmod,
 511         .slave          = &omap44xx_l4_abe_hwmod,
 512         .clk            = "ocp_abe_iclk",
 513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 514 };
 515
 516 /* dsp -> l4_abe */
 517 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 518         .master         = &omap44xx_dsp_hwmod,
 519         .slave          = &omap44xx_l4_abe_hwmod,
 520         .clk            = "ocp_abe_iclk",
 521         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 522 };
 523
 524 /* l3_main_1 -> l4_abe */
 525 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 526         .master         = &omap44xx_l3_main_1_hwmod,
 527         .slave          = &omap44xx_l4_abe_hwmod,
 528         .clk            = "l3_div_ck",
 529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 530 };
 531
 532 /* mpu -> l4_abe */
 533 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 534         .master         = &omap44xx_mpu_hwmod,
 535         .slave          = &omap44xx_l4_abe_hwmod,
 536         .clk            = "ocp_abe_iclk",
 537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 538 };
 539
 540 /* l4_abe slave ports */
 541 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 542         &omap44xx_aess__l4_abe,
 543         &omap44xx_dsp__l4_abe,
 544         &omap44xx_l3_main_1__l4_abe,
 545         &omap44xx_mpu__l4_abe,
 546 };
 547
 548 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 549         .name           = "l4_abe",
 550         .class          = &omap44xx_l4_hwmod_class,
 551         .clkdm_name     = "abe_clkdm",
 552         .prcm = {
 553                 .omap4 = {
 554                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 555                 },
 556         },
 557         .slaves         = omap44xx_l4_abe_slaves,
 558         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 559 };
 560
 561 /* l4_cfg */
 562 /* l3_main_1 -> l4_cfg */
 563 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 564         .master         = &omap44xx_l3_main_1_hwmod,
 565         .slave          = &omap44xx_l4_cfg_hwmod,
 566         .clk            = "l3_div_ck",
 567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 568 };
 569
 570 /* l4_cfg slave ports */
 571 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 572         &omap44xx_l3_main_1__l4_cfg,
 573 };
 574
 575 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 576         .name           = "l4_cfg",
 577         .class          = &omap44xx_l4_hwmod_class,
 578         .clkdm_name     = "l4_cfg_clkdm",
 579         .prcm = {
 580                 .omap4 = {
 581                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 582                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 583                 },
 584         },
 585         .slaves         = omap44xx_l4_cfg_slaves,
 586         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 587 };
 588
 589 /* l4_per */
 590 /* l3_main_2 -> l4_per */
 591 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 592         .master         = &omap44xx_l3_main_2_hwmod,
 593         .slave          = &omap44xx_l4_per_hwmod,
 594         .clk            = "l3_div_ck",
 595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 596 };
 597
 598 /* l4_per slave ports */
 599 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 600         &omap44xx_l3_main_2__l4_per,
 601 };
 602
 603 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 604         .name           = "l4_per",
 605         .class          = &omap44xx_l4_hwmod_class,
 606         .clkdm_name     = "l4_per_clkdm",
 607         .prcm = {
 608                 .omap4 = {
 609                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 610                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 611                 },
 612         },
 613         .slaves         = omap44xx_l4_per_slaves,
 614         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 615 };
 616
 617 /* l4_wkup */
 618 /* l4_cfg -> l4_wkup */
 619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 620         .master         = &omap44xx_l4_cfg_hwmod,
 621         .slave          = &omap44xx_l4_wkup_hwmod,
 622         .clk            = "l4_div_ck",
 623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 624 };
 625
 626 /* l4_wkup slave ports */
 627 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 628         &omap44xx_l4_cfg__l4_wkup,
 629 };
 630
 631 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 632         .name           = "l4_wkup",
 633         .class          = &omap44xx_l4_hwmod_class,
 634         .clkdm_name     = "l4_wkup_clkdm",
 635         .prcm = {
 636                 .omap4 = {
 637                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 638                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 639                 },
 640         },
 641         .slaves         = omap44xx_l4_wkup_slaves,
 642         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 643 };
 644
 645 /*
 646  * 'mpu_bus' class
 647  * instance(s): mpu_private
 648  */
 649 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 650         .name   = "mpu_bus",
 651 };
 652
 653 /* mpu_private */
 654 /* mpu -> mpu_private */
 655 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 656         .master         = &omap44xx_mpu_hwmod,
 657         .slave          = &omap44xx_mpu_private_hwmod,
 658         .clk            = "l3_div_ck",
 659         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 660 };
 661
 662 /* mpu_private slave ports */
 663 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 664         &omap44xx_mpu__mpu_private,
 665 };
 666
 667 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 668         .name           = "mpu_private",
 669         .class          = &omap44xx_mpu_bus_hwmod_class,
 670         .clkdm_name     = "mpuss_clkdm",
 671         .slaves         = omap44xx_mpu_private_slaves,
 672         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 673 };
 674
 675 /*
 676  * Modules omap_hwmod structures
 677  *
 678  * The following IPs are excluded for the moment because:
 679  * - They do not need an explicit SW control using omap_hwmod API.
 680  * - They still need to be validated with the driver
 681  *   properly adapted to omap_hwmod / omap_device
 682  *
 683  *  c2c
 684  *  c2c_target_fw
 685  *  cm_core
 686  *  cm_core_aon
 687  *  ctrl_module_core
 688  *  ctrl_module_pad_core
 689  *  ctrl_module_pad_wkup
 690  *  ctrl_module_wkup
 691  *  debugss
 692  *  efuse_ctrl_cust
 693  *  efuse_ctrl_std
 694  *  elm
 695  *  emif1
 696  *  emif2
 697  *  fdif
 698  *  gpmc
 699  *  gpu
 700  *  hdq1w
 701  *  mcasp
 702  *  mpu_c0
 703  *  mpu_c1
 704  *  ocmc_ram
 705  *  ocp2scp_usb_phy
 706  *  ocp_wp_noc
 707  *  prcm_mpu
 708  *  prm
 709  *  scrm
 710  *  sl2if
 711  *  slimbus1
 712  *  slimbus2
 713  *  usb_host_fs
 714  *  usb_host_hs
 715  *  usb_phy_cm
 716  *  usb_tll_hs
 717  *  usim
 718  */
 719
 720 /*
 721  * 'aess' class
 722  * audio engine sub system
 723  */
 724
 725 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 726         .rev_offs       = 0x0000,
 727         .sysc_offs      = 0x0010,
 728         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 729         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 730                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 731                            MSTANDBY_SMART_WKUP),
 732         .sysc_fields    = &omap_hwmod_sysc_type2,
 733 };
 734
 735 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 736         .name   = "aess",
 737         .sysc   = &omap44xx_aess_sysc,
 738 };
 739
 740 /* aess */
 741 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 742         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 743         { .irq = -1 }
 744 };
 745
 746 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 747         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 748         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 749         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 750         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 751         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 752         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 753         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 754         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 755         { .dma_req = -1 }
 756 };
 757
 758 /* aess master ports */
 759 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 760         &omap44xx_aess__l4_abe,
 761 };
 762
 763 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 764         {
 765                 .pa_start       = 0x401f1000,
 766                 .pa_end         = 0x401f13ff,
 767                 .flags          = ADDR_TYPE_RT
 768         },
 769         { }
 770 };
 771
 772 /* l4_abe -> aess */
 773 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 774         .master         = &omap44xx_l4_abe_hwmod,
 775         .slave          = &omap44xx_aess_hwmod,
 776         .clk            = "ocp_abe_iclk",
 777         .addr           = omap44xx_aess_addrs,
 778         .user           = OCP_USER_MPU,
 779 };
 780
 781 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 782         {
 783                 .pa_start       = 0x490f1000,
 784                 .pa_end         = 0x490f13ff,
 785                 .flags          = ADDR_TYPE_RT
 786         },
 787         { }
 788 };
 789
 790 /* l4_abe -> aess (dma) */
 791 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 792         .master         = &omap44xx_l4_abe_hwmod,
 793         .slave          = &omap44xx_aess_hwmod,
 794         .clk            = "ocp_abe_iclk",
 795         .addr           = omap44xx_aess_dma_addrs,
 796         .user           = OCP_USER_SDMA,
 797 };
 798
 799 /* aess slave ports */
 800 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 801         &omap44xx_l4_abe__aess,
 802         &omap44xx_l4_abe__aess_dma,
 803 };
 804
 805 static struct omap_hwmod omap44xx_aess_hwmod = {
 806         .name           = "aess",
 807         .class          = &omap44xx_aess_hwmod_class,
 808         .clkdm_name     = "abe_clkdm",
 809         .mpu_irqs       = omap44xx_aess_irqs,
 810         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 811         .main_clk       = "aess_fck",
 812         .prcm = {
 813                 .omap4 = {
 814                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 815                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 816                         .modulemode   = MODULEMODE_SWCTRL,
 817                 },
 818         },
 819         .slaves         = omap44xx_aess_slaves,
 820         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 821         .masters        = omap44xx_aess_masters,
 822         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 823 };
 824
 825 /*
 826  * 'bandgap' class
 827  * bangap reference for ldo regulators
 828  */
 829
 830 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 831         .name   = "bandgap",
 832 };
 833
 834 /* bandgap */
 835 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 836         { .role = "fclk", .clk = "bandgap_fclk" },
 837 };
 838
 839 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 840         .name           = "bandgap",
 841         .class          = &omap44xx_bandgap_hwmod_class,
 842         .clkdm_name     = "l4_wkup_clkdm",
 843         .prcm = {
 844                 .omap4 = {
 845                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
 846                 },
 847         },
 848         .opt_clks       = bandgap_opt_clks,
 849         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 850 };
 851
 852 /*
 853  * 'counter' class
 854  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 855  */
 856
 857 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 858         .rev_offs       = 0x0000,
 859         .sysc_offs      = 0x0004,
 860         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 861         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 862                            SIDLE_SMART_WKUP),
 863         .sysc_fields    = &omap_hwmod_sysc_type1,
 864 };
 865
 866 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 867         .name   = "counter",
 868         .sysc   = &omap44xx_counter_sysc,
 869 };
 870
 871 /* counter_32k */
 872 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 873 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 874         {
 875                 .pa_start       = 0x4a304000,
 876                 .pa_end         = 0x4a30401f,
 877                 .flags          = ADDR_TYPE_RT
 878         },
 879         { }
 880 };
 881
 882 /* l4_wkup -> counter_32k */
 883 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 884         .master         = &omap44xx_l4_wkup_hwmod,
 885         .slave          = &omap44xx_counter_32k_hwmod,
 886         .clk            = "l4_wkup_clk_mux_ck",
 887         .addr           = omap44xx_counter_32k_addrs,
 888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 889 };
 890
 891 /* counter_32k slave ports */
 892 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 893         &omap44xx_l4_wkup__counter_32k,
 894 };
 895
 896 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 897         .name           = "counter_32k",
 898         .class          = &omap44xx_counter_hwmod_class,
 899         .clkdm_name     = "l4_wkup_clkdm",
 900         .flags          = HWMOD_SWSUP_SIDLE,
 901         .main_clk       = "sys_32k_ck",
 902         .prcm = {
 903                 .omap4 = {
 904                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 905                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 906                 },
 907         },
 908         .slaves         = omap44xx_counter_32k_slaves,
 909         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 910 };
 911
 912 /*
 913  * 'dma' class
 914  * dma controller for data exchange between memory to memory (i.e. internal or
 915  * external memory) and gp peripherals to memory or memory to gp peripherals
 916  */
 917
 918 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 919         .rev_offs       = 0x0000,
 920         .sysc_offs      = 0x002c,
 921         .syss_offs      = 0x0028,
 922         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 923                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 924                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 925                            SYSS_HAS_RESET_STATUS),
 926         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 927                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 928         .sysc_fields    = &omap_hwmod_sysc_type1,
 929 };
 930
 931 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 932         .name   = "dma",
 933         .sysc   = &omap44xx_dma_sysc,
 934 };
 935
 936 /* dma dev_attr */
 937 static struct omap_dma_dev_attr dma_dev_attr = {
 938         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 939                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 940         .lch_count      = 32,
 941 };
 942
 943 /* dma_system */
 944 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 945         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 946         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 947         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 948         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 949         { .irq = -1 }
 950 };
 951
 952 /* dma_system master ports */
 953 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 954         &omap44xx_dma_system__l3_main_2,
 955 };
 956
 957 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 958         {
 959                 .pa_start       = 0x4a056000,
 960                 .pa_end         = 0x4a056fff,
 961                 .flags          = ADDR_TYPE_RT
 962         },
 963         { }
 964 };
 965
 966 /* l4_cfg -> dma_system */
 967 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 968         .master         = &omap44xx_l4_cfg_hwmod,
 969         .slave          = &omap44xx_dma_system_hwmod,
 970         .clk            = "l4_div_ck",
 971         .addr           = omap44xx_dma_system_addrs,
 972         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 973 };
 974
 975 /* dma_system slave ports */
 976 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 977         &omap44xx_l4_cfg__dma_system,
 978 };
 979
 980 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 981         .name           = "dma_system",
 982         .class          = &omap44xx_dma_hwmod_class,
 983         .clkdm_name     = "l3_dma_clkdm",
 984         .mpu_irqs       = omap44xx_dma_system_irqs,
 985         .main_clk       = "l3_div_ck",
 986         .prcm = {
 987                 .omap4 = {
 988                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 989                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 990                 },
 991         },
 992         .dev_attr       = &dma_dev_attr,
 993         .slaves         = omap44xx_dma_system_slaves,
 994         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 995         .masters        = omap44xx_dma_system_masters,
 996         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 997 };
 998
 999 /*
1000  * 'dmic' class
1001  * digital microphone controller
1002  */
1003
1004 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1005         .rev_offs       = 0x0000,
1006         .sysc_offs      = 0x0010,
1007         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1008                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1009         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1010                            SIDLE_SMART_WKUP),
1011         .sysc_fields    = &omap_hwmod_sysc_type2,
1012 };
1013
1014 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1015         .name   = "dmic",
1016         .sysc   = &omap44xx_dmic_sysc,
1017 };
1018
1019 /* dmic */
1020 static struct omap_hwmod omap44xx_dmic_hwmod;
1021 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1022         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1023         { .irq = -1 }
1024 };
1025
1026 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1027         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1028         { .dma_req = -1 }
1029 };
1030
1031 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1032         {
1033                 .name           = "mpu",
1034                 .pa_start       = 0x4012e000,
1035                 .pa_end         = 0x4012e07f,
1036                 .flags          = ADDR_TYPE_RT
1037         },
1038         { }
1039 };
1040
1041 /* l4_abe -> dmic */
1042 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1043         .master         = &omap44xx_l4_abe_hwmod,
1044         .slave          = &omap44xx_dmic_hwmod,
1045         .clk            = "ocp_abe_iclk",
1046         .addr           = omap44xx_dmic_addrs,
1047         .user           = OCP_USER_MPU,
1048 };
1049
1050 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1051         {
1052                 .name           = "dma",
1053                 .pa_start       = 0x4902e000,
1054                 .pa_end         = 0x4902e07f,
1055                 .flags          = ADDR_TYPE_RT
1056         },
1057         { }
1058 };
1059
1060 /* l4_abe -> dmic (dma) */
1061 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1062         .master         = &omap44xx_l4_abe_hwmod,
1063         .slave          = &omap44xx_dmic_hwmod,
1064         .clk            = "ocp_abe_iclk",
1065         .addr           = omap44xx_dmic_dma_addrs,
1066         .user           = OCP_USER_SDMA,
1067 };
1068
1069 /* dmic slave ports */
1070 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1071         &omap44xx_l4_abe__dmic,
1072         &omap44xx_l4_abe__dmic_dma,
1073 };
1074
1075 static struct omap_hwmod omap44xx_dmic_hwmod = {
1076         .name           = "dmic",
1077         .class          = &omap44xx_dmic_hwmod_class,
1078         .clkdm_name     = "abe_clkdm",
1079         .mpu_irqs       = omap44xx_dmic_irqs,
1080         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1081         .main_clk       = "dmic_fck",
1082         .prcm = {
1083                 .omap4 = {
1084                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1085                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1086                         .modulemode   = MODULEMODE_SWCTRL,
1087                 },
1088         },
1089         .slaves         = omap44xx_dmic_slaves,
1090         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1091 };
1092
1093 /*
1094  * 'dsp' class
1095  * dsp sub-system
1096  */
1097
1098 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1099         .name   = "dsp",
1100 };
1101
1102 /* dsp */
1103 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1104         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1105         { .irq = -1 }
1106 };
1107
1108 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1109         { .name = "mmu_cache", .rst_shift = 1 },
1110 };
1111
1112 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1113         { .name = "dsp", .rst_shift = 0 },
1114 };
1115
1116 /* dsp -> iva */
1117 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1118         .master         = &omap44xx_dsp_hwmod,
1119         .slave          = &omap44xx_iva_hwmod,
1120         .clk            = "dpll_iva_m5x2_ck",
1121 };
1122
1123 /* dsp master ports */
1124 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1125         &omap44xx_dsp__l3_main_1,
1126         &omap44xx_dsp__l4_abe,
1127         &omap44xx_dsp__iva,
1128 };
1129
1130 /* l4_cfg -> dsp */
1131 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1132         .master         = &omap44xx_l4_cfg_hwmod,
1133         .slave          = &omap44xx_dsp_hwmod,
1134         .clk            = "l4_div_ck",
1135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1136 };
1137
1138 /* dsp slave ports */
1139 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1140         &omap44xx_l4_cfg__dsp,
1141 };
1142
1143 /* Pseudo hwmod for reset control purpose only */
1144 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1145         .name           = "dsp_c0",
1146         .class          = &omap44xx_dsp_hwmod_class,
1147         .clkdm_name     = "tesla_clkdm",
1148         .flags          = HWMOD_INIT_NO_RESET,
1149         .rst_lines      = omap44xx_dsp_c0_resets,
1150         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1151         .prcm = {
1152                 .omap4 = {
1153                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1154                 },
1155         },
1156 };
1157
1158 static struct omap_hwmod omap44xx_dsp_hwmod = {
1159         .name           = "dsp",
1160         .class          = &omap44xx_dsp_hwmod_class,
1161         .clkdm_name     = "tesla_clkdm",
1162         .mpu_irqs       = omap44xx_dsp_irqs,
1163         .rst_lines      = omap44xx_dsp_resets,
1164         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1165         .main_clk       = "dsp_fck",
1166         .prcm = {
1167                 .omap4 = {
1168                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1169                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1170                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1171                         .modulemode   = MODULEMODE_HWCTRL,
1172                 },
1173         },
1174         .slaves         = omap44xx_dsp_slaves,
1175         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1176         .masters        = omap44xx_dsp_masters,
1177         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1178 };
1179
1180 /*
1181  * 'dss' class
1182  * display sub-system
1183  */
1184
1185 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1186         .rev_offs       = 0x0000,
1187         .syss_offs      = 0x0014,
1188         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1189 };
1190
1191 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1192         .name   = "dss",
1193         .sysc   = &omap44xx_dss_sysc,
1194         .reset  = omap_dss_reset,
1195 };
1196
1197 /* dss */
1198 /* dss master ports */
1199 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1200         &omap44xx_dss__l3_main_1,
1201 };
1202
1203 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1204         {
1205                 .pa_start       = 0x58000000,
1206                 .pa_end         = 0x5800007f,
1207                 .flags          = ADDR_TYPE_RT
1208         },
1209         { }
1210 };
1211
1212 /* l3_main_2 -> dss */
1213 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1214         .master         = &omap44xx_l3_main_2_hwmod,
1215         .slave          = &omap44xx_dss_hwmod,
1216         .clk            = "dss_fck",
1217         .addr           = omap44xx_dss_dma_addrs,
1218         .user           = OCP_USER_SDMA,
1219 };
1220
1221 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1222         {
1223                 .pa_start       = 0x48040000,
1224                 .pa_end         = 0x4804007f,
1225                 .flags          = ADDR_TYPE_RT
1226         },
1227         { }
1228 };
1229
1230 /* l4_per -> dss */
1231 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1232         .master         = &omap44xx_l4_per_hwmod,
1233         .slave          = &omap44xx_dss_hwmod,
1234         .clk            = "l4_div_ck",
1235         .addr           = omap44xx_dss_addrs,
1236         .user           = OCP_USER_MPU,
1237 };
1238
1239 /* dss slave ports */
1240 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1241         &omap44xx_l3_main_2__dss,
1242         &omap44xx_l4_per__dss,
1243 };
1244
1245 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1246         { .role = "sys_clk", .clk = "dss_sys_clk" },
1247         { .role = "tv_clk", .clk = "dss_tv_clk" },
1248         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1249 };
1250
1251 static struct omap_hwmod omap44xx_dss_hwmod = {
1252         .name           = "dss_core",
1253         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1254         .class          = &omap44xx_dss_hwmod_class,
1255         .clkdm_name     = "l3_dss_clkdm",
1256         .main_clk       = "dss_dss_clk",
1257         .prcm = {
1258                 .omap4 = {
1259                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1260                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1261                 },
1262         },
1263         .opt_clks       = dss_opt_clks,
1264         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1265         .slaves         = omap44xx_dss_slaves,
1266         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1267         .masters        = omap44xx_dss_masters,
1268         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1269 };
1270
1271 /*
1272  * 'dispc' class
1273  * display controller
1274  */
1275
1276 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1277         .rev_offs       = 0x0000,
1278         .sysc_offs      = 0x0010,
1279         .syss_offs      = 0x0014,
1280         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1281                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1282                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1283                            SYSS_HAS_RESET_STATUS),
1284         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1285                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1286         .sysc_fields    = &omap_hwmod_sysc_type1,
1287 };
1288
1289 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1290         .name   = "dispc",
1291         .sysc   = &omap44xx_dispc_sysc,
1292 };
1293
1294 /* dss_dispc */
1295 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1296 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1297         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1298         { .irq = -1 }
1299 };
1300
1301 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1302         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1303         { .dma_req = -1 }
1304 };
1305
1306 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1307         {
1308                 .pa_start       = 0x58001000,
1309                 .pa_end         = 0x58001fff,
1310                 .flags          = ADDR_TYPE_RT
1311         },
1312         { }
1313 };
1314
1315 /* l3_main_2 -> dss_dispc */
1316 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1317         .master         = &omap44xx_l3_main_2_hwmod,
1318         .slave          = &omap44xx_dss_dispc_hwmod,
1319         .clk            = "dss_fck",
1320         .addr           = omap44xx_dss_dispc_dma_addrs,
1321         .user           = OCP_USER_SDMA,
1322 };
1323
1324 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1325         {
1326                 .pa_start       = 0x48041000,
1327                 .pa_end         = 0x48041fff,
1328                 .flags          = ADDR_TYPE_RT
1329         },
1330         { }
1331 };
1332
1333 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1334         .manager_count          = 3,
1335         .has_framedonetv_irq    = 1
1336 };
1337
1338 /* l4_per -> dss_dispc */
1339 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1340         .master         = &omap44xx_l4_per_hwmod,
1341         .slave          = &omap44xx_dss_dispc_hwmod,
1342         .clk            = "l4_div_ck",
1343         .addr           = omap44xx_dss_dispc_addrs,
1344         .user           = OCP_USER_MPU,
1345 };
1346
1347 /* dss_dispc slave ports */
1348 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1349         &omap44xx_l3_main_2__dss_dispc,
1350         &omap44xx_l4_per__dss_dispc,
1351 };
1352
1353 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1354         .name           = "dss_dispc",
1355         .class          = &omap44xx_dispc_hwmod_class,
1356         .clkdm_name     = "l3_dss_clkdm",
1357         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1358         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1359         .main_clk       = "dss_dss_clk",
1360         .prcm = {
1361                 .omap4 = {
1362                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1363                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1364                 },
1365         },
1366         .slaves         = omap44xx_dss_dispc_slaves,
1367         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1368         .dev_attr       = &omap44xx_dss_dispc_dev_attr
1369 };
1370
1371 /*
1372  * 'dsi' class
1373  * display serial interface controller
1374  */
1375
1376 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1377         .rev_offs       = 0x0000,
1378         .sysc_offs      = 0x0010,
1379         .syss_offs      = 0x0014,
1380         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1381                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1382                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1383         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1384         .sysc_fields    = &omap_hwmod_sysc_type1,
1385 };
1386
1387 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1388         .name   = "dsi",
1389         .sysc   = &omap44xx_dsi_sysc,
1390 };
1391
1392 /* dss_dsi1 */
1393 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1394 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1395         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1396         { .irq = -1 }
1397 };
1398
1399 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1400         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1401         { .dma_req = -1 }
1402 };
1403
1404 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1405         {
1406                 .pa_start       = 0x58004000,
1407                 .pa_end         = 0x580041ff,
1408                 .flags          = ADDR_TYPE_RT
1409         },
1410         { }
1411 };
1412
1413 /* l3_main_2 -> dss_dsi1 */
1414 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1415         .master         = &omap44xx_l3_main_2_hwmod,
1416         .slave          = &omap44xx_dss_dsi1_hwmod,
1417         .clk            = "dss_fck",
1418         .addr           = omap44xx_dss_dsi1_dma_addrs,
1419         .user           = OCP_USER_SDMA,
1420 };
1421
1422 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1423         {
1424                 .pa_start       = 0x48044000,
1425                 .pa_end         = 0x480441ff,
1426                 .flags          = ADDR_TYPE_RT
1427         },
1428         { }
1429 };
1430
1431 /* l4_per -> dss_dsi1 */
1432 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1433         .master         = &omap44xx_l4_per_hwmod,
1434         .slave          = &omap44xx_dss_dsi1_hwmod,
1435         .clk            = "l4_div_ck",
1436         .addr           = omap44xx_dss_dsi1_addrs,
1437         .user           = OCP_USER_MPU,
1438 };
1439
1440 /* dss_dsi1 slave ports */
1441 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1442         &omap44xx_l3_main_2__dss_dsi1,
1443         &omap44xx_l4_per__dss_dsi1,
1444 };
1445
1446 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1447         { .role = "sys_clk", .clk = "dss_sys_clk" },
1448 };
1449
1450 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1451         .name           = "dss_dsi1",
1452         .class          = &omap44xx_dsi_hwmod_class,
1453         .clkdm_name     = "l3_dss_clkdm",
1454         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1455         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1456         .main_clk       = "dss_dss_clk",
1457         .prcm = {
1458                 .omap4 = {
1459                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1460                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1461                 },
1462         },
1463         .opt_clks       = dss_dsi1_opt_clks,
1464         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1465         .slaves         = omap44xx_dss_dsi1_slaves,
1466         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1467 };
1468
1469 /* dss_dsi2 */
1470 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1471 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1472         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1473         { .irq = -1 }
1474 };
1475
1476 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1477         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1478         { .dma_req = -1 }
1479 };
1480
1481 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1482         {
1483                 .pa_start       = 0x58005000,
1484                 .pa_end         = 0x580051ff,
1485                 .flags          = ADDR_TYPE_RT
1486         },
1487         { }
1488 };
1489
1490 /* l3_main_2 -> dss_dsi2 */
1491 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1492         .master         = &omap44xx_l3_main_2_hwmod,
1493         .slave          = &omap44xx_dss_dsi2_hwmod,
1494         .clk            = "dss_fck",
1495         .addr           = omap44xx_dss_dsi2_dma_addrs,
1496         .user           = OCP_USER_SDMA,
1497 };
1498
1499 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1500         {
1501                 .pa_start       = 0x48045000,
1502                 .pa_end         = 0x480451ff,
1503                 .flags          = ADDR_TYPE_RT
1504         },
1505         { }
1506 };
1507
1508 /* l4_per -> dss_dsi2 */
1509 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1510         .master         = &omap44xx_l4_per_hwmod,
1511         .slave          = &omap44xx_dss_dsi2_hwmod,
1512         .clk            = "l4_div_ck",
1513         .addr           = omap44xx_dss_dsi2_addrs,
1514         .user           = OCP_USER_MPU,
1515 };
1516
1517 /* dss_dsi2 slave ports */
1518 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1519         &omap44xx_l3_main_2__dss_dsi2,
1520         &omap44xx_l4_per__dss_dsi2,
1521 };
1522
1523 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1524         { .role = "sys_clk", .clk = "dss_sys_clk" },
1525 };
1526
1527 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1528         .name           = "dss_dsi2",
1529         .class          = &omap44xx_dsi_hwmod_class,
1530         .clkdm_name     = "l3_dss_clkdm",
1531         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1532         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1533         .main_clk       = "dss_dss_clk",
1534         .prcm = {
1535                 .omap4 = {
1536                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1537                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1538                 },
1539         },
1540         .opt_clks       = dss_dsi2_opt_clks,
1541         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1542         .slaves         = omap44xx_dss_dsi2_slaves,
1543         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1544 };
1545
1546 /*
1547  * 'hdmi' class
1548  * hdmi controller
1549  */
1550
1551 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1552         .rev_offs       = 0x0000,
1553         .sysc_offs      = 0x0010,
1554         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1555                            SYSC_HAS_SOFTRESET),
1556         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1557                            SIDLE_SMART_WKUP),
1558         .sysc_fields    = &omap_hwmod_sysc_type2,
1559 };
1560
1561 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1562         .name   = "hdmi",
1563         .sysc   = &omap44xx_hdmi_sysc,
1564 };
1565
1566 /* dss_hdmi */
1567 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1568 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1569         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1570         { .irq = -1 }
1571 };
1572
1573 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1574         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1575         { .dma_req = -1 }
1576 };
1577
1578 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1579         {
1580                 .pa_start       = 0x58006000,
1581                 .pa_end         = 0x58006fff,
1582                 .flags          = ADDR_TYPE_RT
1583         },
1584         { }
1585 };
1586
1587 /* l3_main_2 -> dss_hdmi */
1588 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1589         .master         = &omap44xx_l3_main_2_hwmod,
1590         .slave          = &omap44xx_dss_hdmi_hwmod,
1591         .clk            = "dss_fck",
1592         .addr           = omap44xx_dss_hdmi_dma_addrs,
1593         .user           = OCP_USER_SDMA,
1594 };
1595
1596 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1597         {
1598                 .pa_start       = 0x48046000,
1599                 .pa_end         = 0x48046fff,
1600                 .flags          = ADDR_TYPE_RT
1601         },
1602         { }
1603 };
1604
1605 /* l4_per -> dss_hdmi */
1606 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1607         .master         = &omap44xx_l4_per_hwmod,
1608         .slave          = &omap44xx_dss_hdmi_hwmod,
1609         .clk            = "l4_div_ck",
1610         .addr           = omap44xx_dss_hdmi_addrs,
1611         .user           = OCP_USER_MPU,
1612 };
1613
1614 /* dss_hdmi slave ports */
1615 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1616         &omap44xx_l3_main_2__dss_hdmi,
1617         &omap44xx_l4_per__dss_hdmi,
1618 };
1619
1620 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1621         { .role = "sys_clk", .clk = "dss_sys_clk" },
1622 };
1623
1624 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1625         .name           = "dss_hdmi",
1626         .class          = &omap44xx_hdmi_hwmod_class,
1627         .clkdm_name     = "l3_dss_clkdm",
1628         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1629         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1630         .main_clk       = "dss_48mhz_clk",
1631         .prcm = {
1632                 .omap4 = {
1633                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1634                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1635                 },
1636         },
1637         .opt_clks       = dss_hdmi_opt_clks,
1638         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1639         .slaves         = omap44xx_dss_hdmi_slaves,
1640         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1641 };
1642
1643 /*
1644  * 'rfbi' class
1645  * remote frame buffer interface
1646  */
1647
1648 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1649         .rev_offs       = 0x0000,
1650         .sysc_offs      = 0x0010,
1651         .syss_offs      = 0x0014,
1652         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1653                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1654         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1655         .sysc_fields    = &omap_hwmod_sysc_type1,
1656 };
1657
1658 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1659         .name   = "rfbi",
1660         .sysc   = &omap44xx_rfbi_sysc,
1661 };
1662
1663 /* dss_rfbi */
1664 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1665 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1666         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1667         { .dma_req = -1 }
1668 };
1669
1670 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1671         {
1672                 .pa_start       = 0x58002000,
1673                 .pa_end         = 0x580020ff,
1674                 .flags          = ADDR_TYPE_RT
1675         },
1676         { }
1677 };
1678
1679 /* l3_main_2 -> dss_rfbi */
1680 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1681         .master         = &omap44xx_l3_main_2_hwmod,
1682         .slave          = &omap44xx_dss_rfbi_hwmod,
1683         .clk            = "dss_fck",
1684         .addr           = omap44xx_dss_rfbi_dma_addrs,
1685         .user           = OCP_USER_SDMA,
1686 };
1687
1688 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1689         {
1690                 .pa_start       = 0x48042000,
1691                 .pa_end         = 0x480420ff,
1692                 .flags          = ADDR_TYPE_RT
1693         },
1694         { }
1695 };
1696
1697 /* l4_per -> dss_rfbi */
1698 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1699         .master         = &omap44xx_l4_per_hwmod,
1700         .slave          = &omap44xx_dss_rfbi_hwmod,
1701         .clk            = "l4_div_ck",
1702         .addr           = omap44xx_dss_rfbi_addrs,
1703         .user           = OCP_USER_MPU,
1704 };
1705
1706 /* dss_rfbi slave ports */
1707 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1708         &omap44xx_l3_main_2__dss_rfbi,
1709         &omap44xx_l4_per__dss_rfbi,
1710 };
1711
1712 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1713         { .role = "ick", .clk = "dss_fck" },
1714 };
1715
1716 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1717         .name           = "dss_rfbi",
1718         .class          = &omap44xx_rfbi_hwmod_class,
1719         .clkdm_name     = "l3_dss_clkdm",
1720         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1721         .main_clk       = "dss_dss_clk",
1722         .prcm = {
1723                 .omap4 = {
1724                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1725                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1726                 },
1727         },
1728         .opt_clks       = dss_rfbi_opt_clks,
1729         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1730         .slaves         = omap44xx_dss_rfbi_slaves,
1731         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1732 };
1733
1734 /*
1735  * 'venc' class
1736  * video encoder
1737  */
1738
1739 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1740         .name   = "venc",
1741 };
1742
1743 /* dss_venc */
1744 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1745 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1746         {
1747                 .pa_start       = 0x58003000,
1748                 .pa_end         = 0x580030ff,
1749                 .flags          = ADDR_TYPE_RT
1750         },
1751         { }
1752 };
1753
1754 /* l3_main_2 -> dss_venc */
1755 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1756         .master         = &omap44xx_l3_main_2_hwmod,
1757         .slave          = &omap44xx_dss_venc_hwmod,
1758         .clk            = "dss_fck",
1759         .addr           = omap44xx_dss_venc_dma_addrs,
1760         .user           = OCP_USER_SDMA,
1761 };
1762
1763 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1764         {
1765                 .pa_start       = 0x48043000,
1766                 .pa_end         = 0x480430ff,
1767                 .flags          = ADDR_TYPE_RT
1768         },
1769         { }
1770 };
1771
1772 /* l4_per -> dss_venc */
1773 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1774         .master         = &omap44xx_l4_per_hwmod,
1775         .slave          = &omap44xx_dss_venc_hwmod,
1776         .clk            = "l4_div_ck",
1777         .addr           = omap44xx_dss_venc_addrs,
1778         .user           = OCP_USER_MPU,
1779 };
1780
1781 /* dss_venc slave ports */
1782 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1783         &omap44xx_l3_main_2__dss_venc,
1784         &omap44xx_l4_per__dss_venc,
1785 };
1786
1787 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1788         .name           = "dss_venc",
1789         .class          = &omap44xx_venc_hwmod_class,
1790         .clkdm_name     = "l3_dss_clkdm",
1791         .main_clk       = "dss_tv_clk",
1792         .prcm = {
1793                 .omap4 = {
1794                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1795                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1796                 },
1797         },
1798         .slaves         = omap44xx_dss_venc_slaves,
1799         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1800 };
1801
1802 /*
1803  * 'gpio' class
1804  * general purpose io module
1805  */
1806
1807 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1808         .rev_offs       = 0x0000,
1809         .sysc_offs      = 0x0010,
1810         .syss_offs      = 0x0114,
1811         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1812                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1813                            SYSS_HAS_RESET_STATUS),
1814         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1815                            SIDLE_SMART_WKUP),
1816         .sysc_fields    = &omap_hwmod_sysc_type1,
1817 };
1818
1819 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1820         .name   = "gpio",
1821         .sysc   = &omap44xx_gpio_sysc,
1822         .rev    = 2,
1823 };
1824
1825 /* gpio dev_attr */
1826 static struct omap_gpio_dev_attr gpio_dev_attr = {
1827         .bank_width     = 32,
1828         .dbck_flag      = true,
1829 };
1830
1831 /* gpio1 */
1832 static struct omap_hwmod omap44xx_gpio1_hwmod;
1833 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1834         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1835         { .irq = -1 }
1836 };
1837
1838 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1839         {
1840                 .pa_start       = 0x4a310000,
1841                 .pa_end         = 0x4a3101ff,
1842                 .flags          = ADDR_TYPE_RT
1843         },
1844         { }
1845 };
1846
1847 /* l4_wkup -> gpio1 */
1848 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1849         .master         = &omap44xx_l4_wkup_hwmod,
1850         .slave          = &omap44xx_gpio1_hwmod,
1851         .clk            = "l4_wkup_clk_mux_ck",
1852         .addr           = omap44xx_gpio1_addrs,
1853         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1854 };
1855
1856 /* gpio1 slave ports */
1857 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1858         &omap44xx_l4_wkup__gpio1,
1859 };
1860
1861 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1862         { .role = "dbclk", .clk = "gpio1_dbclk" },
1863 };
1864
1865 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1866         .name           = "gpio1",
1867         .class          = &omap44xx_gpio_hwmod_class,
1868         .clkdm_name     = "l4_wkup_clkdm",
1869         .mpu_irqs       = omap44xx_gpio1_irqs,
1870         .main_clk       = "gpio1_ick",
1871         .prcm = {
1872                 .omap4 = {
1873                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1874                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1875                         .modulemode   = MODULEMODE_HWCTRL,
1876                 },
1877         },
1878         .opt_clks       = gpio1_opt_clks,
1879         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1880         .dev_attr       = &gpio_dev_attr,
1881         .slaves         = omap44xx_gpio1_slaves,
1882         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1883 };
1884
1885 /* gpio2 */
1886 static struct omap_hwmod omap44xx_gpio2_hwmod;
1887 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1888         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1889         { .irq = -1 }
1890 };
1891
1892 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1893         {
1894                 .pa_start       = 0x48055000,
1895                 .pa_end         = 0x480551ff,
1896                 .flags          = ADDR_TYPE_RT
1897         },
1898         { }
1899 };
1900
1901 /* l4_per -> gpio2 */
1902 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1903         .master         = &omap44xx_l4_per_hwmod,
1904         .slave          = &omap44xx_gpio2_hwmod,
1905         .clk            = "l4_div_ck",
1906         .addr           = omap44xx_gpio2_addrs,
1907         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1908 };
1909
1910 /* gpio2 slave ports */
1911 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1912         &omap44xx_l4_per__gpio2,
1913 };
1914
1915 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1916         { .role = "dbclk", .clk = "gpio2_dbclk" },
1917 };
1918
1919 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1920         .name           = "gpio2",
1921         .class          = &omap44xx_gpio_hwmod_class,
1922         .clkdm_name     = "l4_per_clkdm",
1923         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1924         .mpu_irqs       = omap44xx_gpio2_irqs,
1925         .main_clk       = "gpio2_ick",
1926         .prcm = {
1927                 .omap4 = {
1928                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1929                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1930                         .modulemode   = MODULEMODE_HWCTRL,
1931                 },
1932         },
1933         .opt_clks       = gpio2_opt_clks,
1934         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1935         .dev_attr       = &gpio_dev_attr,
1936         .slaves         = omap44xx_gpio2_slaves,
1937         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1938 };
1939
1940 /* gpio3 */
1941 static struct omap_hwmod omap44xx_gpio3_hwmod;
1942 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1943         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1944         { .irq = -1 }
1945 };
1946
1947 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1948         {
1949                 .pa_start       = 0x48057000,
1950                 .pa_end         = 0x480571ff,
1951                 .flags          = ADDR_TYPE_RT
1952         },
1953         { }
1954 };
1955
1956 /* l4_per -> gpio3 */
1957 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1958         .master         = &omap44xx_l4_per_hwmod,
1959         .slave          = &omap44xx_gpio3_hwmod,
1960         .clk            = "l4_div_ck",
1961         .addr           = omap44xx_gpio3_addrs,
1962         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1963 };
1964
1965 /* gpio3 slave ports */
1966 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1967         &omap44xx_l4_per__gpio3,
1968 };
1969
1970 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1971         { .role = "dbclk", .clk = "gpio3_dbclk" },
1972 };
1973
1974 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1975         .name           = "gpio3",
1976         .class          = &omap44xx_gpio_hwmod_class,
1977         .clkdm_name     = "l4_per_clkdm",
1978         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1979         .mpu_irqs       = omap44xx_gpio3_irqs,
1980         .main_clk       = "gpio3_ick",
1981         .prcm = {
1982                 .omap4 = {
1983                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1984                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1985                         .modulemode   = MODULEMODE_HWCTRL,
1986                 },
1987         },
1988         .opt_clks       = gpio3_opt_clks,
1989         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1990         .dev_attr       = &gpio_dev_attr,
1991         .slaves         = omap44xx_gpio3_slaves,
1992         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1993 };
1994
1995 /* gpio4 */
1996 static struct omap_hwmod omap44xx_gpio4_hwmod;
1997 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1998         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1999         { .irq = -1 }
2000 };
2001
2002 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2003         {
2004                 .pa_start       = 0x48059000,
2005                 .pa_end         = 0x480591ff,
2006                 .flags          = ADDR_TYPE_RT
2007         },
2008         { }
2009 };
2010
2011 /* l4_per -> gpio4 */
2012 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2013         .master         = &omap44xx_l4_per_hwmod,
2014         .slave          = &omap44xx_gpio4_hwmod,
2015         .clk            = "l4_div_ck",
2016         .addr           = omap44xx_gpio4_addrs,
2017         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2018 };
2019
2020 /* gpio4 slave ports */
2021 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2022         &omap44xx_l4_per__gpio4,
2023 };
2024
2025 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2026         { .role = "dbclk", .clk = "gpio4_dbclk" },
2027 };
2028
2029 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2030         .name           = "gpio4",
2031         .class          = &omap44xx_gpio_hwmod_class,
2032         .clkdm_name     = "l4_per_clkdm",
2033         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2034         .mpu_irqs       = omap44xx_gpio4_irqs,
2035         .main_clk       = "gpio4_ick",
2036         .prcm = {
2037                 .omap4 = {
2038                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2039                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2040                         .modulemode   = MODULEMODE_HWCTRL,
2041                 },
2042         },
2043         .opt_clks       = gpio4_opt_clks,
2044         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2045         .dev_attr       = &gpio_dev_attr,
2046         .slaves         = omap44xx_gpio4_slaves,
2047         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2048 };
2049
2050 /* gpio5 */
2051 static struct omap_hwmod omap44xx_gpio5_hwmod;
2052 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2053         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2054         { .irq = -1 }
2055 };
2056
2057 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2058         {
2059                 .pa_start       = 0x4805b000,
2060                 .pa_end         = 0x4805b1ff,
2061                 .flags          = ADDR_TYPE_RT
2062         },
2063         { }
2064 };
2065
2066 /* l4_per -> gpio5 */
2067 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2068         .master         = &omap44xx_l4_per_hwmod,
2069         .slave          = &omap44xx_gpio5_hwmod,
2070         .clk            = "l4_div_ck",
2071         .addr           = omap44xx_gpio5_addrs,
2072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2073 };
2074
2075 /* gpio5 slave ports */
2076 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2077         &omap44xx_l4_per__gpio5,
2078 };
2079
2080 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2081         { .role = "dbclk", .clk = "gpio5_dbclk" },
2082 };
2083
2084 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2085         .name           = "gpio5",
2086         .class          = &omap44xx_gpio_hwmod_class,
2087         .clkdm_name     = "l4_per_clkdm",
2088         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2089         .mpu_irqs       = omap44xx_gpio5_irqs,
2090         .main_clk       = "gpio5_ick",
2091         .prcm = {
2092                 .omap4 = {
2093                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2094                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2095                         .modulemode   = MODULEMODE_HWCTRL,
2096                 },
2097         },
2098         .opt_clks       = gpio5_opt_clks,
2099         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2100         .dev_attr       = &gpio_dev_attr,
2101         .slaves         = omap44xx_gpio5_slaves,
2102         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2103 };
2104
2105 /* gpio6 */
2106 static struct omap_hwmod omap44xx_gpio6_hwmod;
2107 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2108         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2109         { .irq = -1 }
2110 };
2111
2112 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2113         {
2114                 .pa_start       = 0x4805d000,
2115                 .pa_end         = 0x4805d1ff,
2116                 .flags          = ADDR_TYPE_RT
2117         },
2118         { }
2119 };
2120
2121 /* l4_per -> gpio6 */
2122 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2123         .master         = &omap44xx_l4_per_hwmod,
2124         .slave          = &omap44xx_gpio6_hwmod,
2125         .clk            = "l4_div_ck",
2126         .addr           = omap44xx_gpio6_addrs,
2127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2128 };
2129
2130 /* gpio6 slave ports */
2131 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2132         &omap44xx_l4_per__gpio6,
2133 };
2134
2135 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2136         { .role = "dbclk", .clk = "gpio6_dbclk" },
2137 };
2138
2139 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2140         .name           = "gpio6",
2141         .class          = &omap44xx_gpio_hwmod_class,
2142         .clkdm_name     = "l4_per_clkdm",
2143         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2144         .mpu_irqs       = omap44xx_gpio6_irqs,
2145         .main_clk       = "gpio6_ick",
2146         .prcm = {
2147                 .omap4 = {
2148                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2149                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2150                         .modulemode   = MODULEMODE_HWCTRL,
2151                 },
2152         },
2153         .opt_clks       = gpio6_opt_clks,
2154         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2155         .dev_attr       = &gpio_dev_attr,
2156         .slaves         = omap44xx_gpio6_slaves,
2157         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2158 };
2159
2160 /*
2161  * 'hsi' class
2162  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2163  * serial if)
2164  */
2165
2166 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2167         .rev_offs       = 0x0000,
2168         .sysc_offs      = 0x0010,
2169         .syss_offs      = 0x0014,
2170         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2171                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2172                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2173         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2174                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2175                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2176         .sysc_fields    = &omap_hwmod_sysc_type1,
2177 };
2178
2179 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2180         .name   = "hsi",
2181         .sysc   = &omap44xx_hsi_sysc,
2182 };
2183
2184 /* hsi */
2185 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2186         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2187         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2188         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2189         { .irq = -1 }
2190 };
2191
2192 /* hsi master ports */
2193 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2194         &omap44xx_hsi__l3_main_2,
2195 };
2196
2197 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2198         {
2199                 .pa_start       = 0x4a058000,
2200                 .pa_end         = 0x4a05bfff,
2201                 .flags          = ADDR_TYPE_RT
2202         },
2203         { }
2204 };
2205
2206 /* l4_cfg -> hsi */
2207 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2208         .master         = &omap44xx_l4_cfg_hwmod,
2209         .slave          = &omap44xx_hsi_hwmod,
2210         .clk            = "l4_div_ck",
2211         .addr           = omap44xx_hsi_addrs,
2212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2213 };
2214
2215 /* hsi slave ports */
2216 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2217         &omap44xx_l4_cfg__hsi,
2218 };
2219
2220 static struct omap_hwmod omap44xx_hsi_hwmod = {
2221         .name           = "hsi",
2222         .class          = &omap44xx_hsi_hwmod_class,
2223         .clkdm_name     = "l3_init_clkdm",
2224         .mpu_irqs       = omap44xx_hsi_irqs,
2225         .main_clk       = "hsi_fck",
2226         .prcm = {
2227                 .omap4 = {
2228                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2229                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2230                         .modulemode   = MODULEMODE_HWCTRL,
2231                 },
2232         },
2233         .slaves         = omap44xx_hsi_slaves,
2234         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2235         .masters        = omap44xx_hsi_masters,
2236         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2237 };
2238
2239 /*
2240  * 'i2c' class
2241  * multimaster high-speed i2c controller
2242  */
2243
2244 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2245         .sysc_offs      = 0x0010,
2246         .syss_offs      = 0x0090,
2247         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2248                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2249                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2250         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2251                            SIDLE_SMART_WKUP),
2252         .clockact       = CLOCKACT_TEST_ICLK,
2253         .sysc_fields    = &omap_hwmod_sysc_type1,
2254 };
2255
2256 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2257         .name   = "i2c",
2258         .sysc   = &omap44xx_i2c_sysc,
2259         .rev    = OMAP_I2C_IP_VERSION_2,
2260         .reset  = &omap_i2c_reset,
2261 };
2262
2263 static struct omap_i2c_dev_attr i2c_dev_attr = {
2264         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2265 };
2266
2267 /* i2c1 */
2268 static struct omap_hwmod omap44xx_i2c1_hwmod;
2269 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2270         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2271         { .irq = -1 }
2272 };
2273
2274 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2275         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2276         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2277         { .dma_req = -1 }
2278 };
2279
2280 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2281         {
2282                 .pa_start       = 0x48070000,
2283                 .pa_end         = 0x480700ff,
2284                 .flags          = ADDR_TYPE_RT
2285         },
2286         { }
2287 };
2288
2289 /* l4_per -> i2c1 */
2290 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2291         .master         = &omap44xx_l4_per_hwmod,
2292         .slave          = &omap44xx_i2c1_hwmod,
2293         .clk            = "l4_div_ck",
2294         .addr           = omap44xx_i2c1_addrs,
2295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2296 };
2297
2298 /* i2c1 slave ports */
2299 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2300         &omap44xx_l4_per__i2c1,
2301 };
2302
2303 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2304         .name           = "i2c1",
2305         .class          = &omap44xx_i2c_hwmod_class,
2306         .clkdm_name     = "l4_per_clkdm",
2307         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2308         .mpu_irqs       = omap44xx_i2c1_irqs,
2309         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2310         .main_clk       = "i2c1_fck",
2311         .prcm = {
2312                 .omap4 = {
2313                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2314                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2315                         .modulemode   = MODULEMODE_SWCTRL,
2316                 },
2317         },
2318         .slaves         = omap44xx_i2c1_slaves,
2319         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2320         .dev_attr       = &i2c_dev_attr,
2321 };
2322
2323 /* i2c2 */
2324 static struct omap_hwmod omap44xx_i2c2_hwmod;
2325 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2326         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2327         { .irq = -1 }
2328 };
2329
2330 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2331         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2332         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2333         { .dma_req = -1 }
2334 };
2335
2336 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2337         {
2338                 .pa_start       = 0x48072000,
2339                 .pa_end         = 0x480720ff,
2340                 .flags          = ADDR_TYPE_RT
2341         },
2342         { }
2343 };
2344
2345 /* l4_per -> i2c2 */
2346 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2347         .master         = &omap44xx_l4_per_hwmod,
2348         .slave          = &omap44xx_i2c2_hwmod,
2349         .clk            = "l4_div_ck",
2350         .addr           = omap44xx_i2c2_addrs,
2351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2352 };
2353
2354 /* i2c2 slave ports */
2355 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2356         &omap44xx_l4_per__i2c2,
2357 };
2358
2359 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2360         .name           = "i2c2",
2361         .class          = &omap44xx_i2c_hwmod_class,
2362         .clkdm_name     = "l4_per_clkdm",
2363         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2364         .mpu_irqs       = omap44xx_i2c2_irqs,
2365         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2366         .main_clk       = "i2c2_fck",
2367         .prcm = {
2368                 .omap4 = {
2369                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2370                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2371                         .modulemode   = MODULEMODE_SWCTRL,
2372                 },
2373         },
2374         .slaves         = omap44xx_i2c2_slaves,
2375         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2376         .dev_attr       = &i2c_dev_attr,
2377 };
2378
2379 /* i2c3 */
2380 static struct omap_hwmod omap44xx_i2c3_hwmod;
2381 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2382         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2383         { .irq = -1 }
2384 };
2385
2386 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2387         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2388         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2389         { .dma_req = -1 }
2390 };
2391
2392 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2393         {
2394                 .pa_start       = 0x48060000,
2395                 .pa_end         = 0x480600ff,
2396                 .flags          = ADDR_TYPE_RT
2397         },
2398         { }
2399 };
2400
2401 /* l4_per -> i2c3 */
2402 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2403         .master         = &omap44xx_l4_per_hwmod,
2404         .slave          = &omap44xx_i2c3_hwmod,
2405         .clk            = "l4_div_ck",
2406         .addr           = omap44xx_i2c3_addrs,
2407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2408 };
2409
2410 /* i2c3 slave ports */
2411 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2412         &omap44xx_l4_per__i2c3,
2413 };
2414
2415 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2416         .name           = "i2c3",
2417         .class          = &omap44xx_i2c_hwmod_class,
2418         .clkdm_name     = "l4_per_clkdm",
2419         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2420         .mpu_irqs       = omap44xx_i2c3_irqs,
2421         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2422         .main_clk       = "i2c3_fck",
2423         .prcm = {
2424                 .omap4 = {
2425                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2426                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2427                         .modulemode   = MODULEMODE_SWCTRL,
2428                 },
2429         },
2430         .slaves         = omap44xx_i2c3_slaves,
2431         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2432         .dev_attr       = &i2c_dev_attr,
2433 };
2434
2435 /* i2c4 */
2436 static struct omap_hwmod omap44xx_i2c4_hwmod;
2437 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2438         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2439         { .irq = -1 }
2440 };
2441
2442 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2443         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2444         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2445         { .dma_req = -1 }
2446 };
2447
2448 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2449         {
2450                 .pa_start       = 0x48350000,
2451                 .pa_end         = 0x483500ff,
2452                 .flags          = ADDR_TYPE_RT
2453         },
2454         { }
2455 };
2456
2457 /* l4_per -> i2c4 */
2458 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2459         .master         = &omap44xx_l4_per_hwmod,
2460         .slave          = &omap44xx_i2c4_hwmod,
2461         .clk            = "l4_div_ck",
2462         .addr           = omap44xx_i2c4_addrs,
2463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2464 };
2465
2466 /* i2c4 slave ports */
2467 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2468         &omap44xx_l4_per__i2c4,
2469 };
2470
2471 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2472         .name           = "i2c4",
2473         .class          = &omap44xx_i2c_hwmod_class,
2474         .clkdm_name     = "l4_per_clkdm",
2475         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2476         .mpu_irqs       = omap44xx_i2c4_irqs,
2477         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2478         .main_clk       = "i2c4_fck",
2479         .prcm = {
2480                 .omap4 = {
2481                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2482                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2483                         .modulemode   = MODULEMODE_SWCTRL,
2484                 },
2485         },
2486         .slaves         = omap44xx_i2c4_slaves,
2487         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2488         .dev_attr       = &i2c_dev_attr,
2489 };
2490
2491 /*
2492  * 'ipu' class
2493  * imaging processor unit
2494  */
2495
2496 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2497         .name   = "ipu",
2498 };
2499
2500 /* ipu */
2501 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2502         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2503         { .irq = -1 }
2504 };
2505
2506 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2507         { .name = "cpu0", .rst_shift = 0 },
2508 };
2509
2510 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2511         { .name = "cpu1", .rst_shift = 1 },
2512 };
2513
2514 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2515         { .name = "mmu_cache", .rst_shift = 2 },
2516 };
2517
2518 /* ipu master ports */
2519 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2520         &omap44xx_ipu__l3_main_2,
2521 };
2522
2523 /* l3_main_2 -> ipu */
2524 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2525         .master         = &omap44xx_l3_main_2_hwmod,
2526         .slave          = &omap44xx_ipu_hwmod,
2527         .clk            = "l3_div_ck",
2528         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2529 };
2530
2531 /* ipu slave ports */
2532 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2533         &omap44xx_l3_main_2__ipu,
2534 };
2535
2536 /* Pseudo hwmod for reset control purpose only */
2537 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2538         .name           = "ipu_c0",
2539         .class          = &omap44xx_ipu_hwmod_class,
2540         .clkdm_name     = "ducati_clkdm",
2541         .flags          = HWMOD_INIT_NO_RESET,
2542         .rst_lines      = omap44xx_ipu_c0_resets,
2543         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2544         .prcm = {
2545                 .omap4 = {
2546                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2547                 },
2548         },
2549 };
2550
2551 /* Pseudo hwmod for reset control purpose only */
2552 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2553         .name           = "ipu_c1",
2554         .class          = &omap44xx_ipu_hwmod_class,
2555         .clkdm_name     = "ducati_clkdm",
2556         .flags          = HWMOD_INIT_NO_RESET,
2557         .rst_lines      = omap44xx_ipu_c1_resets,
2558         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2559         .prcm = {
2560                 .omap4 = {
2561                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2562                 },
2563         },
2564 };
2565
2566 static struct omap_hwmod omap44xx_ipu_hwmod = {
2567         .name           = "ipu",
2568         .class          = &omap44xx_ipu_hwmod_class,
2569         .clkdm_name     = "ducati_clkdm",
2570         .mpu_irqs       = omap44xx_ipu_irqs,
2571         .rst_lines      = omap44xx_ipu_resets,
2572         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2573         .main_clk       = "ipu_fck",
2574         .prcm = {
2575                 .omap4 = {
2576                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2577                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2578                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2579                         .modulemode   = MODULEMODE_HWCTRL,
2580                 },
2581         },
2582         .slaves         = omap44xx_ipu_slaves,
2583         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2584         .masters        = omap44xx_ipu_masters,
2585         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2586 };
2587
2588 /*
2589  * 'iss' class
2590  * external images sensor pixel data processor
2591  */
2592
2593 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2594         .rev_offs       = 0x0000,
2595         .sysc_offs      = 0x0010,
2596         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2597                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2598         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2599                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2600                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2601         .sysc_fields    = &omap_hwmod_sysc_type2,
2602 };
2603
2604 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2605         .name   = "iss",
2606         .sysc   = &omap44xx_iss_sysc,
2607 };
2608
2609 /* iss */
2610 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2611         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2612         { .irq = -1 }
2613 };
2614
2615 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2616         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2617         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2618         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2619         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2620         { .dma_req = -1 }
2621 };
2622
2623 /* iss master ports */
2624 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2625         &omap44xx_iss__l3_main_2,
2626 };
2627
2628 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2629         {
2630                 .pa_start       = 0x52000000,
2631                 .pa_end         = 0x520000ff,
2632                 .flags          = ADDR_TYPE_RT
2633         },
2634         { }
2635 };
2636
2637 /* l3_main_2 -> iss */
2638 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2639         .master         = &omap44xx_l3_main_2_hwmod,
2640         .slave          = &omap44xx_iss_hwmod,
2641         .clk            = "l3_div_ck",
2642         .addr           = omap44xx_iss_addrs,
2643         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2644 };
2645
2646 /* iss slave ports */
2647 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2648         &omap44xx_l3_main_2__iss,
2649 };
2650
2651 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2652         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2653 };
2654
2655 static struct omap_hwmod omap44xx_iss_hwmod = {
2656         .name           = "iss",
2657         .class          = &omap44xx_iss_hwmod_class,
2658         .clkdm_name     = "iss_clkdm",
2659         .mpu_irqs       = omap44xx_iss_irqs,
2660         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2661         .main_clk       = "iss_fck",
2662         .prcm = {
2663                 .omap4 = {
2664                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2665                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2666                         .modulemode   = MODULEMODE_SWCTRL,
2667                 },
2668         },
2669         .opt_clks       = iss_opt_clks,
2670         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2671         .slaves         = omap44xx_iss_slaves,
2672         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2673         .masters        = omap44xx_iss_masters,
2674         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2675 };
2676
2677 /*
2678  * 'iva' class
2679  * multi-standard video encoder/decoder hardware accelerator
2680  */
2681
2682 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2683         .name   = "iva",
2684 };
2685
2686 /* iva */
2687 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2688         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2689         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2690         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2691         { .irq = -1 }
2692 };
2693
2694 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2695         { .name = "logic", .rst_shift = 2 },
2696 };
2697
2698 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2699         { .name = "seq0", .rst_shift = 0 },
2700 };
2701
2702 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2703         { .name = "seq1", .rst_shift = 1 },
2704 };
2705
2706 /* iva master ports */
2707 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2708         &omap44xx_iva__l3_main_2,
2709         &omap44xx_iva__l3_instr,
2710 };
2711
2712 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2713         {
2714                 .pa_start       = 0x5a000000,
2715                 .pa_end         = 0x5a07ffff,
2716                 .flags          = ADDR_TYPE_RT
2717         },
2718         { }
2719 };
2720
2721 /* l3_main_2 -> iva */
2722 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2723         .master         = &omap44xx_l3_main_2_hwmod,
2724         .slave          = &omap44xx_iva_hwmod,
2725         .clk            = "l3_div_ck",
2726         .addr           = omap44xx_iva_addrs,
2727         .user           = OCP_USER_MPU,
2728 };
2729
2730 /* iva slave ports */
2731 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2732         &omap44xx_dsp__iva,
2733         &omap44xx_l3_main_2__iva,
2734 };
2735
2736 /* Pseudo hwmod for reset control purpose only */
2737 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2738         .name           = "iva_seq0",
2739         .class          = &omap44xx_iva_hwmod_class,
2740         .clkdm_name     = "ivahd_clkdm",
2741         .flags          = HWMOD_INIT_NO_RESET,
2742         .rst_lines      = omap44xx_iva_seq0_resets,
2743         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2744         .prcm = {
2745                 .omap4 = {
2746                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2747                 },
2748         },
2749 };
2750
2751 /* Pseudo hwmod for reset control purpose only */
2752 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2753         .name           = "iva_seq1",
2754         .class          = &omap44xx_iva_hwmod_class,
2755         .clkdm_name     = "ivahd_clkdm",
2756         .flags          = HWMOD_INIT_NO_RESET,
2757         .rst_lines      = omap44xx_iva_seq1_resets,
2758         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2759         .prcm = {
2760                 .omap4 = {
2761                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2762                 },
2763         },
2764 };
2765
2766 static struct omap_hwmod omap44xx_iva_hwmod = {
2767         .name           = "iva",
2768         .class          = &omap44xx_iva_hwmod_class,
2769         .clkdm_name     = "ivahd_clkdm",
2770         .mpu_irqs       = omap44xx_iva_irqs,
2771         .rst_lines      = omap44xx_iva_resets,
2772         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2773         .main_clk       = "iva_fck",
2774         .prcm = {
2775                 .omap4 = {
2776                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2777                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2778                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2779                         .modulemode   = MODULEMODE_HWCTRL,
2780                 },
2781         },
2782         .slaves         = omap44xx_iva_slaves,
2783         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2784         .masters        = omap44xx_iva_masters,
2785         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2786 };
2787
2788 /*
2789  * 'kbd' class
2790  * keyboard controller
2791  */
2792
2793 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2794         .rev_offs       = 0x0000,
2795         .sysc_offs      = 0x0010,
2796         .syss_offs      = 0x0014,
2797         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2798                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2799                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2800                            SYSS_HAS_RESET_STATUS),
2801         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2802         .sysc_fields    = &omap_hwmod_sysc_type1,
2803 };
2804
2805 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2806         .name   = "kbd",
2807         .sysc   = &omap44xx_kbd_sysc,
2808 };
2809
2810 /* kbd */
2811 static struct omap_hwmod omap44xx_kbd_hwmod;
2812 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2813         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2814         { .irq = -1 }
2815 };
2816
2817 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2818         {
2819                 .pa_start       = 0x4a31c000,
2820                 .pa_end         = 0x4a31c07f,
2821                 .flags          = ADDR_TYPE_RT
2822         },
2823         { }
2824 };
2825
2826 /* l4_wkup -> kbd */
2827 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2828         .master         = &omap44xx_l4_wkup_hwmod,
2829         .slave          = &omap44xx_kbd_hwmod,
2830         .clk            = "l4_wkup_clk_mux_ck",
2831         .addr           = omap44xx_kbd_addrs,
2832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2833 };
2834
2835 /* kbd slave ports */
2836 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2837         &omap44xx_l4_wkup__kbd,
2838 };
2839
2840 static struct omap_hwmod omap44xx_kbd_hwmod = {
2841         .name           = "kbd",
2842         .class          = &omap44xx_kbd_hwmod_class,
2843         .clkdm_name     = "l4_wkup_clkdm",
2844         .mpu_irqs       = omap44xx_kbd_irqs,
2845         .main_clk       = "kbd_fck",
2846         .prcm = {
2847                 .omap4 = {
2848                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2849                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2850                         .modulemode   = MODULEMODE_SWCTRL,
2851                 },
2852         },
2853         .slaves         = omap44xx_kbd_slaves,
2854         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2855 };
2856
2857 /*
2858  * 'mailbox' class
2859  * mailbox module allowing communication between the on-chip processors using a
2860  * queued mailbox-interrupt mechanism.
2861  */
2862
2863 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2864         .rev_offs       = 0x0000,
2865         .sysc_offs      = 0x0010,
2866         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2867                            SYSC_HAS_SOFTRESET),
2868         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2869         .sysc_fields    = &omap_hwmod_sysc_type2,
2870 };
2871
2872 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2873         .name   = "mailbox",
2874         .sysc   = &omap44xx_mailbox_sysc,
2875 };
2876
2877 /* mailbox */
2878 static struct omap_hwmod omap44xx_mailbox_hwmod;
2879 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2880         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2881         { .irq = -1 }
2882 };
2883
2884 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2885         {
2886                 .pa_start       = 0x4a0f4000,
2887                 .pa_end         = 0x4a0f41ff,
2888                 .flags          = ADDR_TYPE_RT
2889         },
2890         { }
2891 };
2892
2893 /* l4_cfg -> mailbox */
2894 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2895         .master         = &omap44xx_l4_cfg_hwmod,
2896         .slave          = &omap44xx_mailbox_hwmod,
2897         .clk            = "l4_div_ck",
2898         .addr           = omap44xx_mailbox_addrs,
2899         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2900 };
2901
2902 /* mailbox slave ports */
2903 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2904         &omap44xx_l4_cfg__mailbox,
2905 };
2906
2907 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2908         .name           = "mailbox",
2909         .class          = &omap44xx_mailbox_hwmod_class,
2910         .clkdm_name     = "l4_cfg_clkdm",
2911         .mpu_irqs       = omap44xx_mailbox_irqs,
2912         .prcm = {
2913                 .omap4 = {
2914                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2915                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2916                 },
2917         },
2918         .slaves         = omap44xx_mailbox_slaves,
2919         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2920 };
2921
2922 /*
2923  * 'mcbsp' class
2924  * multi channel buffered serial port controller
2925  */
2926
2927 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2928         .sysc_offs      = 0x008c,
2929         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2930                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2931         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2932         .sysc_fields    = &omap_hwmod_sysc_type1,
2933 };
2934
2935 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2936         .name   = "mcbsp",
2937         .sysc   = &omap44xx_mcbsp_sysc,
2938         .rev    = MCBSP_CONFIG_TYPE4,
2939 };
2940
2941 /* mcbsp1 */
2942 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2943 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2944         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2945         { .irq = -1 }
2946 };
2947
2948 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2949         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2950         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2951         { .dma_req = -1 }
2952 };
2953
2954 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2955         {
2956                 .name           = "mpu",
2957                 .pa_start       = 0x40122000,
2958                 .pa_end         = 0x401220ff,
2959                 .flags          = ADDR_TYPE_RT
2960         },
2961         { }
2962 };
2963
2964 /* l4_abe -> mcbsp1 */
2965 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2966         .master         = &omap44xx_l4_abe_hwmod,
2967         .slave          = &omap44xx_mcbsp1_hwmod,
2968         .clk            = "ocp_abe_iclk",
2969         .addr           = omap44xx_mcbsp1_addrs,
2970         .user           = OCP_USER_MPU,
2971 };
2972
2973 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2974         {
2975                 .name           = "dma",
2976                 .pa_start       = 0x49022000,
2977                 .pa_end         = 0x490220ff,
2978                 .flags          = ADDR_TYPE_RT
2979         },
2980         { }
2981 };
2982
2983 /* l4_abe -> mcbsp1 (dma) */
2984 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2985         .master         = &omap44xx_l4_abe_hwmod,
2986         .slave          = &omap44xx_mcbsp1_hwmod,
2987         .clk            = "ocp_abe_iclk",
2988         .addr           = omap44xx_mcbsp1_dma_addrs,
2989         .user           = OCP_USER_SDMA,
2990 };
2991
2992 /* mcbsp1 slave ports */
2993 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2994         &omap44xx_l4_abe__mcbsp1,
2995         &omap44xx_l4_abe__mcbsp1_dma,
2996 };
2997
2998 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2999         .name           = "mcbsp1",
3000         .class          = &omap44xx_mcbsp_hwmod_class,
3001         .clkdm_name     = "abe_clkdm",
3002         .mpu_irqs       = omap44xx_mcbsp1_irqs,
3003         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
3004         .main_clk       = "mcbsp1_fck",
3005         .prcm = {
3006                 .omap4 = {
3007                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3008                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3009                         .modulemode   = MODULEMODE_SWCTRL,
3010                 },
3011         },
3012         .slaves         = omap44xx_mcbsp1_slaves,
3013         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3014 };
3015
3016 /* mcbsp2 */
3017 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3018 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3019         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3020         { .irq = -1 }
3021 };
3022
3023 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3024         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3025         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3026         { .dma_req = -1 }
3027 };
3028
3029 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3030         {
3031                 .name           = "mpu",
3032                 .pa_start       = 0x40124000,
3033                 .pa_end         = 0x401240ff,
3034                 .flags          = ADDR_TYPE_RT
3035         },
3036         { }
3037 };
3038
3039 /* l4_abe -> mcbsp2 */
3040 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3041         .master         = &omap44xx_l4_abe_hwmod,
3042         .slave          = &omap44xx_mcbsp2_hwmod,
3043         .clk            = "ocp_abe_iclk",
3044         .addr           = omap44xx_mcbsp2_addrs,
3045         .user           = OCP_USER_MPU,
3046 };
3047
3048 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3049         {
3050                 .name           = "dma",
3051                 .pa_start       = 0x49024000,
3052                 .pa_end         = 0x490240ff,
3053                 .flags          = ADDR_TYPE_RT
3054         },
3055         { }
3056 };
3057
3058 /* l4_abe -> mcbsp2 (dma) */
3059 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3060         .master         = &omap44xx_l4_abe_hwmod,
3061         .slave          = &omap44xx_mcbsp2_hwmod,
3062         .clk            = "ocp_abe_iclk",
3063         .addr           = omap44xx_mcbsp2_dma_addrs,
3064         .user           = OCP_USER_SDMA,
3065 };
3066
3067 /* mcbsp2 slave ports */
3068 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3069         &omap44xx_l4_abe__mcbsp2,
3070         &omap44xx_l4_abe__mcbsp2_dma,
3071 };
3072
3073 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3074         .name           = "mcbsp2",
3075         .class          = &omap44xx_mcbsp_hwmod_class,
3076         .clkdm_name     = "abe_clkdm",
3077         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3078         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3079         .main_clk       = "mcbsp2_fck",
3080         .prcm = {
3081                 .omap4 = {
3082                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3083                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3084                         .modulemode   = MODULEMODE_SWCTRL,
3085                 },
3086         },
3087         .slaves         = omap44xx_mcbsp2_slaves,
3088         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3089 };
3090
3091 /* mcbsp3 */
3092 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3093 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3094         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3095         { .irq = -1 }
3096 };
3097
3098 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3099         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3100         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3101         { .dma_req = -1 }
3102 };
3103
3104 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3105         {
3106                 .name           = "mpu",
3107                 .pa_start       = 0x40126000,
3108                 .pa_end         = 0x401260ff,
3109                 .flags          = ADDR_TYPE_RT
3110         },
3111         { }
3112 };
3113
3114 /* l4_abe -> mcbsp3 */
3115 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3116         .master         = &omap44xx_l4_abe_hwmod,
3117         .slave          = &omap44xx_mcbsp3_hwmod,
3118         .clk            = "ocp_abe_iclk",
3119         .addr           = omap44xx_mcbsp3_addrs,
3120         .user           = OCP_USER_MPU,
3121 };
3122
3123 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3124         {
3125                 .name           = "dma",
3126                 .pa_start       = 0x49026000,
3127                 .pa_end         = 0x490260ff,
3128                 .flags          = ADDR_TYPE_RT
3129         },
3130         { }
3131 };
3132
3133 /* l4_abe -> mcbsp3 (dma) */
3134 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3135         .master         = &omap44xx_l4_abe_hwmod,
3136         .slave          = &omap44xx_mcbsp3_hwmod,
3137         .clk            = "ocp_abe_iclk",
3138         .addr           = omap44xx_mcbsp3_dma_addrs,
3139         .user           = OCP_USER_SDMA,
3140 };
3141
3142 /* mcbsp3 slave ports */
3143 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3144         &omap44xx_l4_abe__mcbsp3,
3145         &omap44xx_l4_abe__mcbsp3_dma,
3146 };
3147
3148 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3149         .name           = "mcbsp3",
3150         .class          = &omap44xx_mcbsp_hwmod_class,
3151         .clkdm_name     = "abe_clkdm",
3152         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3153         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3154         .main_clk       = "mcbsp3_fck",
3155         .prcm = {
3156                 .omap4 = {
3157                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3158                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3159                         .modulemode   = MODULEMODE_SWCTRL,
3160                 },
3161         },
3162         .slaves         = omap44xx_mcbsp3_slaves,
3163         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3164 };
3165
3166 /* mcbsp4 */
3167 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3168 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3169         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3170         { .irq = -1 }
3171 };
3172
3173 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3174         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3175         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3176         { .dma_req = -1 }
3177 };
3178
3179 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3180         {
3181                 .pa_start       = 0x48096000,
3182                 .pa_end         = 0x480960ff,
3183                 .flags          = ADDR_TYPE_RT
3184         },
3185         { }
3186 };
3187
3188 /* l4_per -> mcbsp4 */
3189 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3190         .master         = &omap44xx_l4_per_hwmod,
3191         .slave          = &omap44xx_mcbsp4_hwmod,
3192         .clk            = "l4_div_ck",
3193         .addr           = omap44xx_mcbsp4_addrs,
3194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3195 };
3196
3197 /* mcbsp4 slave ports */
3198 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3199         &omap44xx_l4_per__mcbsp4,
3200 };
3201
3202 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3203         .name           = "mcbsp4",
3204         .class          = &omap44xx_mcbsp_hwmod_class,
3205         .clkdm_name     = "l4_per_clkdm",
3206         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3207         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3208         .main_clk       = "mcbsp4_fck",
3209         .prcm = {
3210                 .omap4 = {
3211                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3212                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3213                         .modulemode   = MODULEMODE_SWCTRL,
3214                 },
3215         },
3216         .slaves         = omap44xx_mcbsp4_slaves,
3217         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3218 };
3219
3220 /*
3221  * 'mcpdm' class
3222  * multi channel pdm controller (proprietary interface with phoenix power
3223  * ic)
3224  */
3225
3226 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3227         .rev_offs       = 0x0000,
3228         .sysc_offs      = 0x0010,
3229         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3230                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3231         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3232                            SIDLE_SMART_WKUP),
3233         .sysc_fields    = &omap_hwmod_sysc_type2,
3234 };
3235
3236 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3237         .name   = "mcpdm",
3238         .sysc   = &omap44xx_mcpdm_sysc,
3239 };
3240
3241 /* mcpdm */
3242 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3243 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3244         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3245         { .irq = -1 }
3246 };
3247
3248 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3249         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3250         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3251         { .dma_req = -1 }
3252 };
3253
3254 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3255         {
3256                 .pa_start       = 0x40132000,
3257                 .pa_end         = 0x4013207f,
3258                 .flags          = ADDR_TYPE_RT
3259         },
3260         { }
3261 };
3262
3263 /* l4_abe -> mcpdm */
3264 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3265         .master         = &omap44xx_l4_abe_hwmod,
3266         .slave          = &omap44xx_mcpdm_hwmod,
3267         .clk            = "ocp_abe_iclk",
3268         .addr           = omap44xx_mcpdm_addrs,
3269         .user           = OCP_USER_MPU,
3270 };
3271
3272 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3273         {
3274                 .pa_start       = 0x49032000,
3275                 .pa_end         = 0x4903207f,
3276                 .flags          = ADDR_TYPE_RT
3277         },
3278         { }
3279 };
3280
3281 /* l4_abe -> mcpdm (dma) */
3282 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3283         .master         = &omap44xx_l4_abe_hwmod,
3284         .slave          = &omap44xx_mcpdm_hwmod,
3285         .clk            = "ocp_abe_iclk",
3286         .addr           = omap44xx_mcpdm_dma_addrs,
3287         .user           = OCP_USER_SDMA,
3288 };
3289
3290 /* mcpdm slave ports */
3291 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3292         &omap44xx_l4_abe__mcpdm,
3293         &omap44xx_l4_abe__mcpdm_dma,
3294 };
3295
3296 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3297         .name           = "mcpdm",
3298         .class          = &omap44xx_mcpdm_hwmod_class,
3299         .clkdm_name     = "abe_clkdm",
3300         .mpu_irqs       = omap44xx_mcpdm_irqs,
3301         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3302         .main_clk       = "mcpdm_fck",
3303         .prcm = {
3304                 .omap4 = {
3305                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3306                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3307                         .modulemode   = MODULEMODE_SWCTRL,
3308                 },
3309         },
3310         .slaves         = omap44xx_mcpdm_slaves,
3311         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3312 };
3313
3314 /*
3315  * 'mcspi' class
3316  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3317  * bus
3318  */
3319
3320 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3321         .rev_offs       = 0x0000,
3322         .sysc_offs      = 0x0010,
3323         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3324                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3325         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3326                            SIDLE_SMART_WKUP),
3327         .sysc_fields    = &omap_hwmod_sysc_type2,
3328 };
3329
3330 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3331         .name   = "mcspi",
3332         .sysc   = &omap44xx_mcspi_sysc,
3333         .rev    = OMAP4_MCSPI_REV,
3334 };
3335
3336 /* mcspi1 */
3337 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3338 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3339         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3340         { .irq = -1 }
3341 };
3342
3343 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3344         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3345         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3346         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3347         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3348         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3349         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3350         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3351         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3352         { .dma_req = -1 }
3353 };
3354
3355 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3356         {
3357                 .pa_start       = 0x48098000,
3358                 .pa_end         = 0x480981ff,
3359                 .flags          = ADDR_TYPE_RT
3360         },
3361         { }
3362 };
3363
3364 /* l4_per -> mcspi1 */
3365 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3366         .master         = &omap44xx_l4_per_hwmod,
3367         .slave          = &omap44xx_mcspi1_hwmod,
3368         .clk            = "l4_div_ck",
3369         .addr           = omap44xx_mcspi1_addrs,
3370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3371 };
3372
3373 /* mcspi1 slave ports */
3374 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3375         &omap44xx_l4_per__mcspi1,
3376 };
3377
3378 /* mcspi1 dev_attr */
3379 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3380         .num_chipselect = 4,
3381 };
3382
3383 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3384         .name           = "mcspi1",
3385         .class          = &omap44xx_mcspi_hwmod_class,
3386         .clkdm_name     = "l4_per_clkdm",
3387         .mpu_irqs       = omap44xx_mcspi1_irqs,
3388         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3389         .main_clk       = "mcspi1_fck",
3390         .prcm = {
3391                 .omap4 = {
3392                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3393                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3394                         .modulemode   = MODULEMODE_SWCTRL,
3395                 },
3396         },
3397         .dev_attr       = &mcspi1_dev_attr,
3398         .slaves         = omap44xx_mcspi1_slaves,
3399         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3400 };
3401
3402 /* mcspi2 */
3403 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3404 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3405         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3406         { .irq = -1 }
3407 };
3408
3409 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3410         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3411         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3412         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3413         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3414         { .dma_req = -1 }
3415 };
3416
3417 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3418         {
3419                 .pa_start       = 0x4809a000,
3420                 .pa_end         = 0x4809a1ff,
3421                 .flags          = ADDR_TYPE_RT
3422         },
3423         { }
3424 };
3425
3426 /* l4_per -> mcspi2 */
3427 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3428         .master         = &omap44xx_l4_per_hwmod,
3429         .slave          = &omap44xx_mcspi2_hwmod,
3430         .clk            = "l4_div_ck",
3431         .addr           = omap44xx_mcspi2_addrs,
3432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3433 };
3434
3435 /* mcspi2 slave ports */
3436 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3437         &omap44xx_l4_per__mcspi2,
3438 };
3439
3440 /* mcspi2 dev_attr */
3441 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3442         .num_chipselect = 2,
3443 };
3444
3445 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3446         .name           = "mcspi2",
3447         .class          = &omap44xx_mcspi_hwmod_class,
3448         .clkdm_name     = "l4_per_clkdm",
3449         .mpu_irqs       = omap44xx_mcspi2_irqs,
3450         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3451         .main_clk       = "mcspi2_fck",
3452         .prcm = {
3453                 .omap4 = {
3454                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3455                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3456                         .modulemode   = MODULEMODE_SWCTRL,
3457                 },
3458         },
3459         .dev_attr       = &mcspi2_dev_attr,
3460         .slaves         = omap44xx_mcspi2_slaves,
3461         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3462 };
3463
3464 /* mcspi3 */
3465 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3466 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3467         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3468         { .irq = -1 }
3469 };
3470
3471 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3472         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3473         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3474         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3475         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3476         { .dma_req = -1 }
3477 };
3478
3479 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3480         {
3481                 .pa_start       = 0x480b8000,
3482                 .pa_end         = 0x480b81ff,
3483                 .flags          = ADDR_TYPE_RT
3484         },
3485         { }
3486 };
3487
3488 /* l4_per -> mcspi3 */
3489 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3490         .master         = &omap44xx_l4_per_hwmod,
3491         .slave          = &omap44xx_mcspi3_hwmod,
3492         .clk            = "l4_div_ck",
3493         .addr           = omap44xx_mcspi3_addrs,
3494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3495 };
3496
3497 /* mcspi3 slave ports */
3498 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3499         &omap44xx_l4_per__mcspi3,
3500 };
3501
3502 /* mcspi3 dev_attr */
3503 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3504         .num_chipselect = 2,
3505 };
3506
3507 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3508         .name           = "mcspi3",
3509         .class          = &omap44xx_mcspi_hwmod_class,
3510         .clkdm_name     = "l4_per_clkdm",
3511         .mpu_irqs       = omap44xx_mcspi3_irqs,
3512         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3513         .main_clk       = "mcspi3_fck",
3514         .prcm = {
3515                 .omap4 = {
3516                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3517                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3518                         .modulemode   = MODULEMODE_SWCTRL,
3519                 },
3520         },
3521         .dev_attr       = &mcspi3_dev_attr,
3522         .slaves         = omap44xx_mcspi3_slaves,
3523         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3524 };
3525
3526 /* mcspi4 */
3527 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3528 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3529         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3530         { .irq = -1 }
3531 };
3532
3533 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3534         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3535         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3536         { .dma_req = -1 }
3537 };
3538
3539 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3540         {
3541                 .pa_start       = 0x480ba000,
3542                 .pa_end         = 0x480ba1ff,
3543                 .flags          = ADDR_TYPE_RT
3544         },
3545         { }
3546 };
3547
3548 /* l4_per -> mcspi4 */
3549 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3550         .master         = &omap44xx_l4_per_hwmod,
3551         .slave          = &omap44xx_mcspi4_hwmod,
3552         .clk            = "l4_div_ck",
3553         .addr           = omap44xx_mcspi4_addrs,
3554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3555 };
3556
3557 /* mcspi4 slave ports */
3558 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3559         &omap44xx_l4_per__mcspi4,
3560 };
3561
3562 /* mcspi4 dev_attr */
3563 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3564         .num_chipselect = 1,
3565 };
3566
3567 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3568         .name           = "mcspi4",
3569         .class          = &omap44xx_mcspi_hwmod_class,
3570         .clkdm_name     = "l4_per_clkdm",
3571         .mpu_irqs       = omap44xx_mcspi4_irqs,
3572         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3573         .main_clk       = "mcspi4_fck",
3574         .prcm = {
3575                 .omap4 = {
3576                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3577                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3578                         .modulemode   = MODULEMODE_SWCTRL,
3579                 },
3580         },
3581         .dev_attr       = &mcspi4_dev_attr,
3582         .slaves         = omap44xx_mcspi4_slaves,
3583         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3584 };
3585
3586 /*
3587  * 'mmc' class
3588  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3589  */
3590
3591 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3592         .rev_offs       = 0x0000,
3593         .sysc_offs      = 0x0010,
3594         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3595                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3596                            SYSC_HAS_SOFTRESET),
3597         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3598                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3599                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3600         .sysc_fields    = &omap_hwmod_sysc_type2,
3601 };
3602
3603 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3604         .name   = "mmc",
3605         .sysc   = &omap44xx_mmc_sysc,
3606 };
3607
3608 /* mmc1 */
3609 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3610         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3611         { .irq = -1 }
3612 };
3613
3614 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3615         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3616         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3617         { .dma_req = -1 }
3618 };
3619
3620 /* mmc1 master ports */
3621 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3622         &omap44xx_mmc1__l3_main_1,
3623 };
3624
3625 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3626         {
3627                 .pa_start       = 0x4809c000,
3628                 .pa_end         = 0x4809c3ff,
3629                 .flags          = ADDR_TYPE_RT
3630         },
3631         { }
3632 };
3633
3634 /* l4_per -> mmc1 */
3635 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3636         .master         = &omap44xx_l4_per_hwmod,
3637         .slave          = &omap44xx_mmc1_hwmod,
3638         .clk            = "l4_div_ck",
3639         .addr           = omap44xx_mmc1_addrs,
3640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3641 };
3642
3643 /* mmc1 slave ports */
3644 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3645         &omap44xx_l4_per__mmc1,
3646 };
3647
3648 /* mmc1 dev_attr */
3649 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3650         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3651 };
3652
3653 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3654         .name           = "mmc1",
3655         .class          = &omap44xx_mmc_hwmod_class,
3656         .clkdm_name     = "l3_init_clkdm",
3657         .mpu_irqs       = omap44xx_mmc1_irqs,
3658         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3659         .main_clk       = "mmc1_fck",
3660         .prcm = {
3661                 .omap4 = {
3662                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3663                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3664                         .modulemode   = MODULEMODE_SWCTRL,
3665                 },
3666         },
3667         .dev_attr       = &mmc1_dev_attr,
3668         .slaves         = omap44xx_mmc1_slaves,
3669         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3670         .masters        = omap44xx_mmc1_masters,
3671         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3672 };
3673
3674 /* mmc2 */
3675 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3676         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3677         { .irq = -1 }
3678 };
3679
3680 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3681         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3682         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3683         { .dma_req = -1 }
3684 };
3685
3686 /* mmc2 master ports */
3687 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3688         &omap44xx_mmc2__l3_main_1,
3689 };
3690
3691 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3692         {
3693                 .pa_start       = 0x480b4000,
3694                 .pa_end         = 0x480b43ff,
3695                 .flags          = ADDR_TYPE_RT
3696         },
3697         { }
3698 };
3699
3700 /* l4_per -> mmc2 */
3701 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3702         .master         = &omap44xx_l4_per_hwmod,
3703         .slave          = &omap44xx_mmc2_hwmod,
3704         .clk            = "l4_div_ck",
3705         .addr           = omap44xx_mmc2_addrs,
3706         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3707 };
3708
3709 /* mmc2 slave ports */
3710 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3711         &omap44xx_l4_per__mmc2,
3712 };
3713
3714 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3715         .name           = "mmc2",
3716         .class          = &omap44xx_mmc_hwmod_class,
3717         .clkdm_name     = "l3_init_clkdm",
3718         .mpu_irqs       = omap44xx_mmc2_irqs,
3719         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3720         .main_clk       = "mmc2_fck",
3721         .prcm = {
3722                 .omap4 = {
3723                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3724                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3725                         .modulemode   = MODULEMODE_SWCTRL,
3726                 },
3727         },
3728         .slaves         = omap44xx_mmc2_slaves,
3729         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3730         .masters        = omap44xx_mmc2_masters,
3731         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3732 };
3733
3734 /* mmc3 */
3735 static struct omap_hwmod omap44xx_mmc3_hwmod;
3736 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3737         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3738         { .irq = -1 }
3739 };
3740
3741 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3742         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3743         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3744         { .dma_req = -1 }
3745 };
3746
3747 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3748         {
3749                 .pa_start       = 0x480ad000,
3750                 .pa_end         = 0x480ad3ff,
3751                 .flags          = ADDR_TYPE_RT
3752         },
3753         { }
3754 };
3755
3756 /* l4_per -> mmc3 */
3757 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3758         .master         = &omap44xx_l4_per_hwmod,
3759         .slave          = &omap44xx_mmc3_hwmod,
3760         .clk            = "l4_div_ck",
3761         .addr           = omap44xx_mmc3_addrs,
3762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3763 };
3764
3765 /* mmc3 slave ports */
3766 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3767         &omap44xx_l4_per__mmc3,
3768 };
3769
3770 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3771         .name           = "mmc3",
3772         .class          = &omap44xx_mmc_hwmod_class,
3773         .clkdm_name     = "l4_per_clkdm",
3774         .mpu_irqs       = omap44xx_mmc3_irqs,
3775         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3776         .main_clk       = "mmc3_fck",
3777         .prcm = {
3778                 .omap4 = {
3779                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3780                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3781                         .modulemode   = MODULEMODE_SWCTRL,
3782                 },
3783         },
3784         .slaves         = omap44xx_mmc3_slaves,
3785         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3786 };
3787
3788 /* mmc4 */
3789 static struct omap_hwmod omap44xx_mmc4_hwmod;
3790 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3791         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3792         { .irq = -1 }
3793 };
3794
3795 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3796         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3797         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3798         { .dma_req = -1 }
3799 };
3800
3801 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3802         {
3803                 .pa_start       = 0x480d1000,
3804                 .pa_end         = 0x480d13ff,
3805                 .flags          = ADDR_TYPE_RT
3806         },
3807         { }
3808 };
3809
3810 /* l4_per -> mmc4 */
3811 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3812         .master         = &omap44xx_l4_per_hwmod,
3813         .slave          = &omap44xx_mmc4_hwmod,
3814         .clk            = "l4_div_ck",
3815         .addr           = omap44xx_mmc4_addrs,
3816         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3817 };
3818
3819 /* mmc4 slave ports */
3820 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3821         &omap44xx_l4_per__mmc4,
3822 };
3823
3824 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3825         .name           = "mmc4",
3826         .class          = &omap44xx_mmc_hwmod_class,
3827         .clkdm_name     = "l4_per_clkdm",
3828         .mpu_irqs       = omap44xx_mmc4_irqs,
3829
3830         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3831         .main_clk       = "mmc4_fck",
3832         .prcm = {
3833                 .omap4 = {
3834                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3835                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3836                         .modulemode   = MODULEMODE_SWCTRL,
3837                 },
3838         },
3839         .slaves         = omap44xx_mmc4_slaves,
3840         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3841 };
3842
3843 /* mmc5 */
3844 static struct omap_hwmod omap44xx_mmc5_hwmod;
3845 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3846         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3847         { .irq = -1 }
3848 };
3849
3850 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3851         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3852         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3853         { .dma_req = -1 }
3854 };
3855
3856 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3857         {
3858                 .pa_start       = 0x480d5000,
3859                 .pa_end         = 0x480d53ff,
3860                 .flags          = ADDR_TYPE_RT
3861         },
3862         { }
3863 };
3864
3865 /* l4_per -> mmc5 */
3866 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3867         .master         = &omap44xx_l4_per_hwmod,
3868         .slave          = &omap44xx_mmc5_hwmod,
3869         .clk            = "l4_div_ck",
3870         .addr           = omap44xx_mmc5_addrs,
3871         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3872 };
3873
3874 /* mmc5 slave ports */
3875 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3876         &omap44xx_l4_per__mmc5,
3877 };
3878
3879 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3880         .name           = "mmc5",
3881         .class          = &omap44xx_mmc_hwmod_class,
3882         .clkdm_name     = "l4_per_clkdm",
3883         .mpu_irqs       = omap44xx_mmc5_irqs,
3884         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3885         .main_clk       = "mmc5_fck",
3886         .prcm = {
3887                 .omap4 = {
3888                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3889                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3890                         .modulemode   = MODULEMODE_SWCTRL,
3891                 },
3892         },
3893         .slaves         = omap44xx_mmc5_slaves,
3894         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3895 };
3896
3897 /*
3898  * 'mpu' class
3899  * mpu sub-system
3900  */
3901
3902 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3903         .name   = "mpu",
3904 };
3905
3906 /* mpu */
3907 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3908         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3909         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3910         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3911         { .irq = -1 }
3912 };
3913
3914 /* mpu master ports */
3915 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3916         &omap44xx_mpu__l3_main_1,
3917         &omap44xx_mpu__l4_abe,
3918         &omap44xx_mpu__dmm,
3919 };
3920
3921 static struct omap_hwmod omap44xx_mpu_hwmod = {
3922         .name           = "mpu",
3923         .class          = &omap44xx_mpu_hwmod_class,
3924         .clkdm_name     = "mpuss_clkdm",
3925         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3926         .mpu_irqs       = omap44xx_mpu_irqs,
3927         .main_clk       = "dpll_mpu_m2_ck",
3928         .prcm = {
3929                 .omap4 = {
3930                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3931                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3932                 },
3933         },
3934         .masters        = omap44xx_mpu_masters,
3935         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3936 };
3937
3938 /*
3939  * 'smartreflex' class
3940  * smartreflex module (monitor silicon performance and outputs a measure of
3941  * performance error)
3942  */
3943
3944 /* The IP is not compliant to type1 / type2 scheme */
3945 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3946         .sidle_shift    = 24,
3947         .enwkup_shift   = 26,
3948 };
3949
3950 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3951         .sysc_offs      = 0x0038,
3952         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3953         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3954                            SIDLE_SMART_WKUP),
3955         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3956 };
3957
3958 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3959         .name   = "smartreflex",
3960         .sysc   = &omap44xx_smartreflex_sysc,
3961         .rev    = 2,
3962 };
3963
3964 /* smartreflex_core */
3965 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3966 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3967         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3968         { .irq = -1 }
3969 };
3970
3971 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3972         {
3973                 .pa_start       = 0x4a0dd000,
3974                 .pa_end         = 0x4a0dd03f,
3975                 .flags          = ADDR_TYPE_RT
3976         },
3977         { }
3978 };
3979
3980 /* l4_cfg -> smartreflex_core */
3981 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3982         .master         = &omap44xx_l4_cfg_hwmod,
3983         .slave          = &omap44xx_smartreflex_core_hwmod,
3984         .clk            = "l4_div_ck",
3985         .addr           = omap44xx_smartreflex_core_addrs,
3986         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3987 };
3988
3989 /* smartreflex_core slave ports */
3990 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3991         &omap44xx_l4_cfg__smartreflex_core,
3992 };
3993
3994 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3995         .name           = "smartreflex_core",
3996         .class          = &omap44xx_smartreflex_hwmod_class,
3997         .clkdm_name     = "l4_ao_clkdm",
3998         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3999
4000         .main_clk       = "smartreflex_core_fck",
4001         .vdd_name       = "core",
4002         .prcm = {
4003                 .omap4 = {
4004                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4005                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4006                         .modulemode   = MODULEMODE_SWCTRL,
4007                 },
4008         },
4009         .slaves         = omap44xx_smartreflex_core_slaves,
4010         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4011 };
4012
4013 /* smartreflex_iva */
4014 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4015 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4016         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4017         { .irq = -1 }
4018 };
4019
4020 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4021         {
4022                 .pa_start       = 0x4a0db000,
4023                 .pa_end         = 0x4a0db03f,
4024                 .flags          = ADDR_TYPE_RT
4025         },
4026         { }
4027 };
4028
4029 /* l4_cfg -> smartreflex_iva */
4030 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4031         .master         = &omap44xx_l4_cfg_hwmod,
4032         .slave          = &omap44xx_smartreflex_iva_hwmod,
4033         .clk            = "l4_div_ck",
4034         .addr           = omap44xx_smartreflex_iva_addrs,
4035         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4036 };
4037
4038 /* smartreflex_iva slave ports */
4039 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4040         &omap44xx_l4_cfg__smartreflex_iva,
4041 };
4042
4043 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4044         .name           = "smartreflex_iva",
4045         .class          = &omap44xx_smartreflex_hwmod_class,
4046         .clkdm_name     = "l4_ao_clkdm",
4047         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
4048         .main_clk       = "smartreflex_iva_fck",
4049         .vdd_name       = "iva",
4050         .prcm = {
4051                 .omap4 = {
4052                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4053                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4054                         .modulemode   = MODULEMODE_SWCTRL,
4055                 },
4056         },
4057         .slaves         = omap44xx_smartreflex_iva_slaves,
4058         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4059 };
4060
4061 /* smartreflex_mpu */
4062 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4063 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4064         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4065         { .irq = -1 }
4066 };
4067
4068 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4069         {
4070                 .pa_start       = 0x4a0d9000,
4071                 .pa_end         = 0x4a0d903f,
4072                 .flags          = ADDR_TYPE_RT
4073         },
4074         { }
4075 };
4076
4077 /* l4_cfg -> smartreflex_mpu */
4078 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4079         .master         = &omap44xx_l4_cfg_hwmod,
4080         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4081         .clk            = "l4_div_ck",
4082         .addr           = omap44xx_smartreflex_mpu_addrs,
4083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4084 };
4085
4086 /* smartreflex_mpu slave ports */
4087 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4088         &omap44xx_l4_cfg__smartreflex_mpu,
4089 };
4090
4091 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4092         .name           = "smartreflex_mpu",
4093         .class          = &omap44xx_smartreflex_hwmod_class,
4094         .clkdm_name     = "l4_ao_clkdm",
4095         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
4096         .main_clk       = "smartreflex_mpu_fck",
4097         .vdd_name       = "mpu",
4098         .prcm = {
4099                 .omap4 = {
4100                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4101                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4102                         .modulemode   = MODULEMODE_SWCTRL,
4103                 },
4104         },
4105         .slaves         = omap44xx_smartreflex_mpu_slaves,
4106         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4107 };
4108
4109 /*
4110  * 'spinlock' class
4111  * spinlock provides hardware assistance for synchronizing the processes
4112  * running on multiple processors
4113  */
4114
4115 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4116         .rev_offs       = 0x0000,
4117         .sysc_offs      = 0x0010,
4118         .syss_offs      = 0x0014,
4119         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4120                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4121                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4122         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4123                            SIDLE_SMART_WKUP),
4124         .sysc_fields    = &omap_hwmod_sysc_type1,
4125 };
4126
4127 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4128         .name   = "spinlock",
4129         .sysc   = &omap44xx_spinlock_sysc,
4130 };
4131
4132 /* spinlock */
4133 static struct omap_hwmod omap44xx_spinlock_hwmod;
4134 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4135         {
4136                 .pa_start       = 0x4a0f6000,
4137                 .pa_end         = 0x4a0f6fff,
4138                 .flags          = ADDR_TYPE_RT
4139         },
4140         { }
4141 };
4142
4143 /* l4_cfg -> spinlock */
4144 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4145         .master         = &omap44xx_l4_cfg_hwmod,
4146         .slave          = &omap44xx_spinlock_hwmod,
4147         .clk            = "l4_div_ck",
4148         .addr           = omap44xx_spinlock_addrs,
4149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4150 };
4151
4152 /* spinlock slave ports */
4153 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4154         &omap44xx_l4_cfg__spinlock,
4155 };
4156
4157 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4158         .name           = "spinlock",
4159         .class          = &omap44xx_spinlock_hwmod_class,
4160         .clkdm_name     = "l4_cfg_clkdm",
4161         .prcm = {
4162                 .omap4 = {
4163                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4164                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4165                 },
4166         },
4167         .slaves         = omap44xx_spinlock_slaves,
4168         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4169 };
4170
4171 /*
4172  * 'timer' class
4173  * general purpose timer module with accurate 1ms tick
4174  * This class contains several variants: ['timer_1ms', 'timer']
4175  */
4176
4177 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4178         .rev_offs       = 0x0000,
4179         .sysc_offs      = 0x0010,
4180         .syss_offs      = 0x0014,
4181         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4182                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4183                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4184                            SYSS_HAS_RESET_STATUS),
4185         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4186         .sysc_fields    = &omap_hwmod_sysc_type1,
4187 };
4188
4189 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4190         .name   = "timer",
4191         .sysc   = &omap44xx_timer_1ms_sysc,
4192 };
4193
4194 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4195         .rev_offs       = 0x0000,
4196         .sysc_offs      = 0x0010,
4197         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4198                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4199         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4200                            SIDLE_SMART_WKUP),
4201         .sysc_fields    = &omap_hwmod_sysc_type2,
4202 };
4203
4204 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4205         .name   = "timer",
4206         .sysc   = &omap44xx_timer_sysc,
4207 };
4208
4209 /* always-on timers dev attribute */
4210 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4211         .timer_capability       = OMAP_TIMER_ALWON,
4212 };
4213
4214 /* pwm timers dev attribute */
4215 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4216         .timer_capability       = OMAP_TIMER_HAS_PWM,
4217 };
4218
4219 /* timer1 */
4220 static struct omap_hwmod omap44xx_timer1_hwmod;
4221 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4222         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4223         { .irq = -1 }
4224 };
4225
4226 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4227         {
4228                 .pa_start       = 0x4a318000,
4229                 .pa_end         = 0x4a31807f,
4230                 .flags          = ADDR_TYPE_RT
4231         },
4232         { }
4233 };
4234
4235 /* l4_wkup -> timer1 */
4236 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4237         .master         = &omap44xx_l4_wkup_hwmod,
4238         .slave          = &omap44xx_timer1_hwmod,
4239         .clk            = "l4_wkup_clk_mux_ck",
4240         .addr           = omap44xx_timer1_addrs,
4241         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4242 };
4243
4244 /* timer1 slave ports */
4245 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4246         &omap44xx_l4_wkup__timer1,
4247 };
4248
4249 static struct omap_hwmod omap44xx_timer1_hwmod = {
4250         .name           = "timer1",
4251         .class          = &omap44xx_timer_1ms_hwmod_class,
4252         .clkdm_name     = "l4_wkup_clkdm",
4253         .mpu_irqs       = omap44xx_timer1_irqs,
4254         .main_clk       = "timer1_fck",
4255         .prcm = {
4256                 .omap4 = {
4257                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4258                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4259                         .modulemode   = MODULEMODE_SWCTRL,
4260                 },
4261         },
4262         .dev_attr       = &capability_alwon_dev_attr,
4263         .slaves         = omap44xx_timer1_slaves,
4264         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4265 };
4266
4267 /* timer2 */
4268 static struct omap_hwmod omap44xx_timer2_hwmod;
4269 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4270         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4271         { .irq = -1 }
4272 };
4273
4274 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4275         {
4276                 .pa_start       = 0x48032000,
4277                 .pa_end         = 0x4803207f,
4278                 .flags          = ADDR_TYPE_RT
4279         },
4280         { }
4281 };
4282
4283 /* l4_per -> timer2 */
4284 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4285         .master         = &omap44xx_l4_per_hwmod,
4286         .slave          = &omap44xx_timer2_hwmod,
4287         .clk            = "l4_div_ck",
4288         .addr           = omap44xx_timer2_addrs,
4289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4290 };
4291
4292 /* timer2 slave ports */
4293 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4294         &omap44xx_l4_per__timer2,
4295 };
4296
4297 static struct omap_hwmod omap44xx_timer2_hwmod = {
4298         .name           = "timer2",
4299         .class          = &omap44xx_timer_1ms_hwmod_class,
4300         .clkdm_name     = "l4_per_clkdm",
4301         .mpu_irqs       = omap44xx_timer2_irqs,
4302         .main_clk       = "timer2_fck",
4303         .prcm = {
4304                 .omap4 = {
4305                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4306                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4307                         .modulemode   = MODULEMODE_SWCTRL,
4308                 },
4309         },
4310         .dev_attr       = &capability_alwon_dev_attr,
4311         .slaves         = omap44xx_timer2_slaves,
4312         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4313 };
4314
4315 /* timer3 */
4316 static struct omap_hwmod omap44xx_timer3_hwmod;
4317 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4318         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4319         { .irq = -1 }
4320 };
4321
4322 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4323         {
4324                 .pa_start       = 0x48034000,
4325                 .pa_end         = 0x4803407f,
4326                 .flags          = ADDR_TYPE_RT
4327         },
4328         { }
4329 };
4330
4331 /* l4_per -> timer3 */
4332 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4333         .master         = &omap44xx_l4_per_hwmod,
4334         .slave          = &omap44xx_timer3_hwmod,
4335         .clk            = "l4_div_ck",
4336         .addr           = omap44xx_timer3_addrs,
4337         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4338 };
4339
4340 /* timer3 slave ports */
4341 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4342         &omap44xx_l4_per__timer3,
4343 };
4344
4345 static struct omap_hwmod omap44xx_timer3_hwmod = {
4346         .name           = "timer3",
4347         .class          = &omap44xx_timer_hwmod_class,
4348         .clkdm_name     = "l4_per_clkdm",
4349         .mpu_irqs       = omap44xx_timer3_irqs,
4350         .main_clk       = "timer3_fck",
4351         .prcm = {
4352                 .omap4 = {
4353                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4354                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4355                         .modulemode   = MODULEMODE_SWCTRL,
4356                 },
4357         },
4358         .dev_attr       = &capability_alwon_dev_attr,
4359         .slaves         = omap44xx_timer3_slaves,
4360         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4361 };
4362
4363 /* timer4 */
4364 static struct omap_hwmod omap44xx_timer4_hwmod;
4365 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4366         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4367         { .irq = -1 }
4368 };
4369
4370 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4371         {
4372                 .pa_start       = 0x48036000,
4373                 .pa_end         = 0x4803607f,
4374                 .flags          = ADDR_TYPE_RT
4375         },
4376         { }
4377 };
4378
4379 /* l4_per -> timer4 */
4380 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4381         .master         = &omap44xx_l4_per_hwmod,
4382         .slave          = &omap44xx_timer4_hwmod,
4383         .clk            = "l4_div_ck",
4384         .addr           = omap44xx_timer4_addrs,
4385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4386 };
4387
4388 /* timer4 slave ports */
4389 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4390         &omap44xx_l4_per__timer4,
4391 };
4392
4393 static struct omap_hwmod omap44xx_timer4_hwmod = {
4394         .name           = "timer4",
4395         .class          = &omap44xx_timer_hwmod_class,
4396         .clkdm_name     = "l4_per_clkdm",
4397         .mpu_irqs       = omap44xx_timer4_irqs,
4398         .main_clk       = "timer4_fck",
4399         .prcm = {
4400                 .omap4 = {
4401                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4402                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4403                         .modulemode   = MODULEMODE_SWCTRL,
4404                 },
4405         },
4406         .dev_attr       = &capability_alwon_dev_attr,
4407         .slaves         = omap44xx_timer4_slaves,
4408         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4409 };
4410
4411 /* timer5 */
4412 static struct omap_hwmod omap44xx_timer5_hwmod;
4413 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4414         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4415         { .irq = -1 }
4416 };
4417
4418 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4419         {
4420                 .pa_start       = 0x40138000,
4421                 .pa_end         = 0x4013807f,
4422                 .flags          = ADDR_TYPE_RT
4423         },
4424         { }
4425 };
4426
4427 /* l4_abe -> timer5 */
4428 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4429         .master         = &omap44xx_l4_abe_hwmod,
4430         .slave          = &omap44xx_timer5_hwmod,
4431         .clk            = "ocp_abe_iclk",
4432         .addr           = omap44xx_timer5_addrs,
4433         .user           = OCP_USER_MPU,
4434 };
4435
4436 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4437         {
4438                 .pa_start       = 0x49038000,
4439                 .pa_end         = 0x4903807f,
4440                 .flags          = ADDR_TYPE_RT
4441         },
4442         { }
4443 };
4444
4445 /* l4_abe -> timer5 (dma) */
4446 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4447         .master         = &omap44xx_l4_abe_hwmod,
4448         .slave          = &omap44xx_timer5_hwmod,
4449         .clk            = "ocp_abe_iclk",
4450         .addr           = omap44xx_timer5_dma_addrs,
4451         .user           = OCP_USER_SDMA,
4452 };
4453
4454 /* timer5 slave ports */
4455 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4456         &omap44xx_l4_abe__timer5,
4457         &omap44xx_l4_abe__timer5_dma,
4458 };
4459
4460 static struct omap_hwmod omap44xx_timer5_hwmod = {
4461         .name           = "timer5",
4462         .class          = &omap44xx_timer_hwmod_class,
4463         .clkdm_name     = "abe_clkdm",
4464         .mpu_irqs       = omap44xx_timer5_irqs,
4465         .main_clk       = "timer5_fck",
4466         .prcm = {
4467                 .omap4 = {
4468                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4469                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4470                         .modulemode   = MODULEMODE_SWCTRL,
4471                 },
4472         },
4473         .dev_attr       = &capability_alwon_dev_attr,
4474         .slaves         = omap44xx_timer5_slaves,
4475         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4476 };
4477
4478 /* timer6 */
4479 static struct omap_hwmod omap44xx_timer6_hwmod;
4480 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4481         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4482         { .irq = -1 }
4483 };
4484
4485 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4486         {
4487                 .pa_start       = 0x4013a000,
4488                 .pa_end         = 0x4013a07f,
4489                 .flags          = ADDR_TYPE_RT
4490         },
4491         { }
4492 };
4493
4494 /* l4_abe -> timer6 */
4495 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4496         .master         = &omap44xx_l4_abe_hwmod,
4497         .slave          = &omap44xx_timer6_hwmod,
4498         .clk            = "ocp_abe_iclk",
4499         .addr           = omap44xx_timer6_addrs,
4500         .user           = OCP_USER_MPU,
4501 };
4502
4503 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4504         {
4505                 .pa_start       = 0x4903a000,
4506                 .pa_end         = 0x4903a07f,
4507                 .flags          = ADDR_TYPE_RT
4508         },
4509         { }
4510 };
4511
4512 /* l4_abe -> timer6 (dma) */
4513 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4514         .master         = &omap44xx_l4_abe_hwmod,
4515         .slave          = &omap44xx_timer6_hwmod,
4516         .clk            = "ocp_abe_iclk",
4517         .addr           = omap44xx_timer6_dma_addrs,
4518         .user           = OCP_USER_SDMA,
4519 };
4520
4521 /* timer6 slave ports */
4522 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4523         &omap44xx_l4_abe__timer6,
4524         &omap44xx_l4_abe__timer6_dma,
4525 };
4526
4527 static struct omap_hwmod omap44xx_timer6_hwmod = {
4528         .name           = "timer6",
4529         .class          = &omap44xx_timer_hwmod_class,
4530         .clkdm_name     = "abe_clkdm",
4531         .mpu_irqs       = omap44xx_timer6_irqs,
4532
4533         .main_clk       = "timer6_fck",
4534         .prcm = {
4535                 .omap4 = {
4536                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4537                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4538                         .modulemode   = MODULEMODE_SWCTRL,
4539                 },
4540         },
4541         .dev_attr       = &capability_alwon_dev_attr,
4542         .slaves         = omap44xx_timer6_slaves,
4543         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4544 };
4545
4546 /* timer7 */
4547 static struct omap_hwmod omap44xx_timer7_hwmod;
4548 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4549         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4550         { .irq = -1 }
4551 };
4552
4553 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4554         {
4555                 .pa_start       = 0x4013c000,
4556                 .pa_end         = 0x4013c07f,
4557                 .flags          = ADDR_TYPE_RT
4558         },
4559         { }
4560 };
4561
4562 /* l4_abe -> timer7 */
4563 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4564         .master         = &omap44xx_l4_abe_hwmod,
4565         .slave          = &omap44xx_timer7_hwmod,
4566         .clk            = "ocp_abe_iclk",
4567         .addr           = omap44xx_timer7_addrs,
4568         .user           = OCP_USER_MPU,
4569 };
4570
4571 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4572         {
4573                 .pa_start       = 0x4903c000,
4574                 .pa_end         = 0x4903c07f,
4575                 .flags          = ADDR_TYPE_RT
4576         },
4577         { }
4578 };
4579
4580 /* l4_abe -> timer7 (dma) */
4581 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4582         .master         = &omap44xx_l4_abe_hwmod,
4583         .slave          = &omap44xx_timer7_hwmod,
4584         .clk            = "ocp_abe_iclk",
4585         .addr           = omap44xx_timer7_dma_addrs,
4586         .user           = OCP_USER_SDMA,
4587 };
4588
4589 /* timer7 slave ports */
4590 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4591         &omap44xx_l4_abe__timer7,
4592         &omap44xx_l4_abe__timer7_dma,
4593 };
4594
4595 static struct omap_hwmod omap44xx_timer7_hwmod = {
4596         .name           = "timer7",
4597         .class          = &omap44xx_timer_hwmod_class,
4598         .clkdm_name     = "abe_clkdm",
4599         .mpu_irqs       = omap44xx_timer7_irqs,
4600         .main_clk       = "timer7_fck",
4601         .prcm = {
4602                 .omap4 = {
4603                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4604                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4605                         .modulemode   = MODULEMODE_SWCTRL,
4606                 },
4607         },
4608         .dev_attr       = &capability_alwon_dev_attr,
4609         .slaves         = omap44xx_timer7_slaves,
4610         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4611 };
4612
4613 /* timer8 */
4614 static struct omap_hwmod omap44xx_timer8_hwmod;
4615 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4616         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4617         { .irq = -1 }
4618 };
4619
4620 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4621         {
4622                 .pa_start       = 0x4013e000,
4623                 .pa_end         = 0x4013e07f,
4624                 .flags          = ADDR_TYPE_RT
4625         },
4626         { }
4627 };
4628
4629 /* l4_abe -> timer8 */
4630 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4631         .master         = &omap44xx_l4_abe_hwmod,
4632         .slave          = &omap44xx_timer8_hwmod,
4633         .clk            = "ocp_abe_iclk",
4634         .addr           = omap44xx_timer8_addrs,
4635         .user           = OCP_USER_MPU,
4636 };
4637
4638 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4639         {
4640                 .pa_start       = 0x4903e000,
4641                 .pa_end         = 0x4903e07f,
4642                 .flags          = ADDR_TYPE_RT
4643         },
4644         { }
4645 };
4646
4647 /* l4_abe -> timer8 (dma) */
4648 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4649         .master         = &omap44xx_l4_abe_hwmod,
4650         .slave          = &omap44xx_timer8_hwmod,
4651         .clk            = "ocp_abe_iclk",
4652         .addr           = omap44xx_timer8_dma_addrs,
4653         .user           = OCP_USER_SDMA,
4654 };
4655
4656 /* timer8 slave ports */
4657 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4658         &omap44xx_l4_abe__timer8,
4659         &omap44xx_l4_abe__timer8_dma,
4660 };
4661
4662 static struct omap_hwmod omap44xx_timer8_hwmod = {
4663         .name           = "timer8",
4664         .class          = &omap44xx_timer_hwmod_class,
4665         .clkdm_name     = "abe_clkdm",
4666         .mpu_irqs       = omap44xx_timer8_irqs,
4667         .main_clk       = "timer8_fck",
4668         .prcm = {
4669                 .omap4 = {
4670                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4671                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4672                         .modulemode   = MODULEMODE_SWCTRL,
4673                 },
4674         },
4675         .dev_attr       = &capability_pwm_dev_attr,
4676         .slaves         = omap44xx_timer8_slaves,
4677         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4678 };
4679
4680 /* timer9 */
4681 static struct omap_hwmod omap44xx_timer9_hwmod;
4682 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4683         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4684         { .irq = -1 }
4685 };
4686
4687 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4688         {
4689                 .pa_start       = 0x4803e000,
4690                 .pa_end         = 0x4803e07f,
4691                 .flags          = ADDR_TYPE_RT
4692         },
4693         { }
4694 };
4695
4696 /* l4_per -> timer9 */
4697 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4698         .master         = &omap44xx_l4_per_hwmod,
4699         .slave          = &omap44xx_timer9_hwmod,
4700         .clk            = "l4_div_ck",
4701         .addr           = omap44xx_timer9_addrs,
4702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4703 };
4704
4705 /* timer9 slave ports */
4706 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4707         &omap44xx_l4_per__timer9,
4708 };
4709
4710 static struct omap_hwmod omap44xx_timer9_hwmod = {
4711         .name           = "timer9",
4712         .class          = &omap44xx_timer_hwmod_class,
4713         .clkdm_name     = "l4_per_clkdm",
4714         .mpu_irqs       = omap44xx_timer9_irqs,
4715         .main_clk       = "timer9_fck",
4716         .prcm = {
4717                 .omap4 = {
4718                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4719                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4720                         .modulemode   = MODULEMODE_SWCTRL,
4721                 },
4722         },
4723         .dev_attr       = &capability_pwm_dev_attr,
4724         .slaves         = omap44xx_timer9_slaves,
4725         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4726 };
4727
4728 /* timer10 */
4729 static struct omap_hwmod omap44xx_timer10_hwmod;
4730 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4731         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4732         { .irq = -1 }
4733 };
4734
4735 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4736         {
4737                 .pa_start       = 0x48086000,
4738                 .pa_end         = 0x4808607f,
4739                 .flags          = ADDR_TYPE_RT
4740         },
4741         { }
4742 };
4743
4744 /* l4_per -> timer10 */
4745 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4746         .master         = &omap44xx_l4_per_hwmod,
4747         .slave          = &omap44xx_timer10_hwmod,
4748         .clk            = "l4_div_ck",
4749         .addr           = omap44xx_timer10_addrs,
4750         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4751 };
4752
4753 /* timer10 slave ports */
4754 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4755         &omap44xx_l4_per__timer10,
4756 };
4757
4758 static struct omap_hwmod omap44xx_timer10_hwmod = {
4759         .name           = "timer10",
4760         .class          = &omap44xx_timer_1ms_hwmod_class,
4761         .clkdm_name     = "l4_per_clkdm",
4762         .mpu_irqs       = omap44xx_timer10_irqs,
4763         .main_clk       = "timer10_fck",
4764         .prcm = {
4765                 .omap4 = {
4766                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4767                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4768                         .modulemode   = MODULEMODE_SWCTRL,
4769                 },
4770         },
4771         .dev_attr       = &capability_pwm_dev_attr,
4772         .slaves         = omap44xx_timer10_slaves,
4773         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4774 };
4775
4776 /* timer11 */
4777 static struct omap_hwmod omap44xx_timer11_hwmod;
4778 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4779         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4780         { .irq = -1 }
4781 };
4782
4783 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4784         {
4785                 .pa_start       = 0x48088000,
4786                 .pa_end         = 0x4808807f,
4787                 .flags          = ADDR_TYPE_RT
4788         },
4789         { }
4790 };
4791
4792 /* l4_per -> timer11 */
4793 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4794         .master         = &omap44xx_l4_per_hwmod,
4795         .slave          = &omap44xx_timer11_hwmod,
4796         .clk            = "l4_div_ck",
4797         .addr           = omap44xx_timer11_addrs,
4798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4799 };
4800
4801 /* timer11 slave ports */
4802 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4803         &omap44xx_l4_per__timer11,
4804 };
4805
4806 static struct omap_hwmod omap44xx_timer11_hwmod = {
4807         .name           = "timer11",
4808         .class          = &omap44xx_timer_hwmod_class,
4809         .clkdm_name     = "l4_per_clkdm",
4810         .mpu_irqs       = omap44xx_timer11_irqs,
4811         .main_clk       = "timer11_fck",
4812         .prcm = {
4813                 .omap4 = {
4814                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4815                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4816                         .modulemode   = MODULEMODE_SWCTRL,
4817                 },
4818         },
4819         .dev_attr       = &capability_pwm_dev_attr,
4820         .slaves         = omap44xx_timer11_slaves,
4821         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4822 };
4823
4824 /*
4825  * 'uart' class
4826  * universal asynchronous receiver/transmitter (uart)
4827  */
4828
4829 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4830         .rev_offs       = 0x0050,
4831         .sysc_offs      = 0x0054,
4832         .syss_offs      = 0x0058,
4833         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4834                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4835                            SYSS_HAS_RESET_STATUS),
4836         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4837                            SIDLE_SMART_WKUP),
4838         .sysc_fields    = &omap_hwmod_sysc_type1,
4839 };
4840
4841 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4842         .name   = "uart",
4843         .sysc   = &omap44xx_uart_sysc,
4844 };
4845
4846 /* uart1 */
4847 static struct omap_hwmod omap44xx_uart1_hwmod;
4848 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4849         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4850         { .irq = -1 }
4851 };
4852
4853 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4854         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4855         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4856         { .dma_req = -1 }
4857 };
4858
4859 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4860         {
4861                 .pa_start       = 0x4806a000,
4862                 .pa_end         = 0x4806a0ff,
4863                 .flags          = ADDR_TYPE_RT
4864         },
4865         { }
4866 };
4867
4868 /* l4_per -> uart1 */
4869 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4870         .master         = &omap44xx_l4_per_hwmod,
4871         .slave          = &omap44xx_uart1_hwmod,
4872         .clk            = "l4_div_ck",
4873         .addr           = omap44xx_uart1_addrs,
4874         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4875 };
4876
4877 /* uart1 slave ports */
4878 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4879         &omap44xx_l4_per__uart1,
4880 };
4881
4882 static struct omap_hwmod omap44xx_uart1_hwmod = {
4883         .name           = "uart1",
4884         .class          = &omap44xx_uart_hwmod_class,
4885         .clkdm_name     = "l4_per_clkdm",
4886         .mpu_irqs       = omap44xx_uart1_irqs,
4887         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4888         .main_clk       = "uart1_fck",
4889         .prcm = {
4890                 .omap4 = {
4891                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4892                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4893                         .modulemode   = MODULEMODE_SWCTRL,
4894                 },
4895         },
4896         .slaves         = omap44xx_uart1_slaves,
4897         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4898 };
4899
4900 /* uart2 */
4901 static struct omap_hwmod omap44xx_uart2_hwmod;
4902 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4903         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4904         { .irq = -1 }
4905 };
4906
4907 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4908         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4909         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4910         { .dma_req = -1 }
4911 };
4912
4913 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4914         {
4915                 .pa_start       = 0x4806c000,
4916                 .pa_end         = 0x4806c0ff,
4917                 .flags          = ADDR_TYPE_RT
4918         },
4919         { }
4920 };
4921
4922 /* l4_per -> uart2 */
4923 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4924         .master         = &omap44xx_l4_per_hwmod,
4925         .slave          = &omap44xx_uart2_hwmod,
4926         .clk            = "l4_div_ck",
4927         .addr           = omap44xx_uart2_addrs,
4928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4929 };
4930
4931 /* uart2 slave ports */
4932 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4933         &omap44xx_l4_per__uart2,
4934 };
4935
4936 static struct omap_hwmod omap44xx_uart2_hwmod = {
4937         .name           = "uart2",
4938         .class          = &omap44xx_uart_hwmod_class,
4939         .clkdm_name     = "l4_per_clkdm",
4940         .mpu_irqs       = omap44xx_uart2_irqs,
4941         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4942         .main_clk       = "uart2_fck",
4943         .prcm = {
4944                 .omap4 = {
4945                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4946                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4947                         .modulemode   = MODULEMODE_SWCTRL,
4948                 },
4949         },
4950         .slaves         = omap44xx_uart2_slaves,
4951         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4952 };
4953
4954 /* uart3 */
4955 static struct omap_hwmod omap44xx_uart3_hwmod;
4956 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4957         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4958         { .irq = -1 }
4959 };
4960
4961 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4962         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4963         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4964         { .dma_req = -1 }
4965 };
4966
4967 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4968         {
4969                 .pa_start       = 0x48020000,
4970                 .pa_end         = 0x480200ff,
4971                 .flags          = ADDR_TYPE_RT
4972         },
4973         { }
4974 };
4975
4976 /* l4_per -> uart3 */
4977 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4978         .master         = &omap44xx_l4_per_hwmod,
4979         .slave          = &omap44xx_uart3_hwmod,
4980         .clk            = "l4_div_ck",
4981         .addr           = omap44xx_uart3_addrs,
4982         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4983 };
4984
4985 /* uart3 slave ports */
4986 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4987         &omap44xx_l4_per__uart3,
4988 };
4989
4990 static struct omap_hwmod omap44xx_uart3_hwmod = {
4991         .name           = "uart3",
4992         .class          = &omap44xx_uart_hwmod_class,
4993         .clkdm_name     = "l4_per_clkdm",
4994         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4995         .mpu_irqs       = omap44xx_uart3_irqs,
4996         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4997         .main_clk       = "uart3_fck",
4998         .prcm = {
4999                 .omap4 = {
5000                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5001                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5002                         .modulemode   = MODULEMODE_SWCTRL,
5003                 },
5004         },
5005         .slaves         = omap44xx_uart3_slaves,
5006         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
5007 };
5008
5009 /* uart4 */
5010 static struct omap_hwmod omap44xx_uart4_hwmod;
5011 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5012         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5013         { .irq = -1 }
5014 };
5015
5016 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5017         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5018         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5019         { .dma_req = -1 }
5020 };
5021
5022 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5023         {
5024                 .pa_start       = 0x4806e000,
5025                 .pa_end         = 0x4806e0ff,
5026                 .flags          = ADDR_TYPE_RT
5027         },
5028         { }
5029 };
5030
5031 /* l4_per -> uart4 */
5032 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5033         .master         = &omap44xx_l4_per_hwmod,
5034         .slave          = &omap44xx_uart4_hwmod,
5035         .clk            = "l4_div_ck",
5036         .addr           = omap44xx_uart4_addrs,
5037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5038 };
5039
5040 /* uart4 slave ports */
5041 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5042         &omap44xx_l4_per__uart4,
5043 };
5044
5045 static struct omap_hwmod omap44xx_uart4_hwmod = {
5046         .name           = "uart4",
5047         .class          = &omap44xx_uart_hwmod_class,
5048         .clkdm_name     = "l4_per_clkdm",
5049         .mpu_irqs       = omap44xx_uart4_irqs,
5050         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
5051         .main_clk       = "uart4_fck",
5052         .prcm = {
5053                 .omap4 = {
5054                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5055                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5056                         .modulemode   = MODULEMODE_SWCTRL,
5057                 },
5058         },
5059         .slaves         = omap44xx_uart4_slaves,
5060         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
5061 };
5062
5063 /*
5064  * 'usb_otg_hs' class
5065  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5066  */
5067
5068 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5069         .rev_offs       = 0x0400,
5070         .sysc_offs      = 0x0404,
5071         .syss_offs      = 0x0408,
5072         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5073                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5074                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5075         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5076                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5077                            MSTANDBY_SMART),
5078         .sysc_fields    = &omap_hwmod_sysc_type1,
5079 };
5080
5081 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5082         .name   = "usb_otg_hs",
5083         .sysc   = &omap44xx_usb_otg_hs_sysc,
5084 };
5085
5086 /* usb_otg_hs */
5087 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5088         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5089         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5090         { .irq = -1 }
5091 };
5092
5093 /* usb_otg_hs master ports */
5094 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5095         &omap44xx_usb_otg_hs__l3_main_2,
5096 };
5097
5098 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5099         {
5100                 .pa_start       = 0x4a0ab000,
5101                 .pa_end         = 0x4a0ab003,
5102                 .flags          = ADDR_TYPE_RT
5103         },
5104         { }
5105 };
5106
5107 /* l4_cfg -> usb_otg_hs */
5108 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5109         .master         = &omap44xx_l4_cfg_hwmod,
5110         .slave          = &omap44xx_usb_otg_hs_hwmod,
5111         .clk            = "l4_div_ck",
5112         .addr           = omap44xx_usb_otg_hs_addrs,
5113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5114 };
5115
5116 /* usb_otg_hs slave ports */
5117 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5118         &omap44xx_l4_cfg__usb_otg_hs,
5119 };
5120
5121 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5122         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5123 };
5124
5125 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5126         .name           = "usb_otg_hs",
5127         .class          = &omap44xx_usb_otg_hs_hwmod_class,
5128         .clkdm_name     = "l3_init_clkdm",
5129         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5130         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
5131         .main_clk       = "usb_otg_hs_ick",
5132         .prcm = {
5133                 .omap4 = {
5134                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5135                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5136                         .modulemode   = MODULEMODE_HWCTRL,
5137                 },
5138         },
5139         .opt_clks       = usb_otg_hs_opt_clks,
5140         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
5141         .slaves         = omap44xx_usb_otg_hs_slaves,
5142         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5143         .masters        = omap44xx_usb_otg_hs_masters,
5144         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5145 };
5146
5147 /*
5148  * 'wd_timer' class
5149  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5150  * overflow condition
5151  */
5152
5153 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5154         .rev_offs       = 0x0000,
5155         .sysc_offs      = 0x0010,
5156         .syss_offs      = 0x0014,
5157         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5158                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5159         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5160                            SIDLE_SMART_WKUP),
5161         .sysc_fields    = &omap_hwmod_sysc_type1,
5162 };
5163
5164 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5165         .name           = "wd_timer",
5166         .sysc           = &omap44xx_wd_timer_sysc,
5167         .pre_shutdown   = &omap2_wd_timer_disable,
5168 };
5169
5170 /* wd_timer2 */
5171 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5172 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5173         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5174         { .irq = -1 }
5175 };
5176
5177 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5178         {
5179                 .pa_start       = 0x4a314000,
5180                 .pa_end         = 0x4a31407f,
5181                 .flags          = ADDR_TYPE_RT
5182         },
5183         { }
5184 };
5185
5186 /* l4_wkup -> wd_timer2 */
5187 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5188         .master         = &omap44xx_l4_wkup_hwmod,
5189         .slave          = &omap44xx_wd_timer2_hwmod,
5190         .clk            = "l4_wkup_clk_mux_ck",
5191         .addr           = omap44xx_wd_timer2_addrs,
5192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5193 };
5194
5195 /* wd_timer2 slave ports */
5196 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5197         &omap44xx_l4_wkup__wd_timer2,
5198 };
5199
5200 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5201         .name           = "wd_timer2",
5202         .class          = &omap44xx_wd_timer_hwmod_class,
5203         .clkdm_name     = "l4_wkup_clkdm",
5204         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5205         .main_clk       = "wd_timer2_fck",
5206         .prcm = {
5207                 .omap4 = {
5208                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5209                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5210                         .modulemode   = MODULEMODE_SWCTRL,
5211                 },
5212         },
5213         .slaves         = omap44xx_wd_timer2_slaves,
5214         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5215 };
5216
5217 /* wd_timer3 */
5218 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5219 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5220         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5221         { .irq = -1 }
5222 };
5223
5224 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5225         {
5226                 .pa_start       = 0x40130000,
5227                 .pa_end         = 0x4013007f,
5228                 .flags          = ADDR_TYPE_RT
5229         },
5230         { }
5231 };
5232
5233 /* l4_abe -> wd_timer3 */
5234 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5235         .master         = &omap44xx_l4_abe_hwmod,
5236         .slave          = &omap44xx_wd_timer3_hwmod,
5237         .clk            = "ocp_abe_iclk",
5238         .addr           = omap44xx_wd_timer3_addrs,
5239         .user           = OCP_USER_MPU,
5240 };
5241
5242 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5243         {
5244                 .pa_start       = 0x49030000,
5245                 .pa_end         = 0x4903007f,
5246                 .flags          = ADDR_TYPE_RT
5247         },
5248         { }
5249 };
5250
5251 /* l4_abe -> wd_timer3 (dma) */
5252 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5253         .master         = &omap44xx_l4_abe_hwmod,
5254         .slave          = &omap44xx_wd_timer3_hwmod,
5255         .clk            = "ocp_abe_iclk",
5256         .addr           = omap44xx_wd_timer3_dma_addrs,
5257         .user           = OCP_USER_SDMA,
5258 };
5259
5260 /* wd_timer3 slave ports */
5261 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5262         &omap44xx_l4_abe__wd_timer3,
5263         &omap44xx_l4_abe__wd_timer3_dma,
5264 };
5265
5266 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5267         .name           = "wd_timer3",
5268         .class          = &omap44xx_wd_timer_hwmod_class,
5269         .clkdm_name     = "abe_clkdm",
5270         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5271         .main_clk       = "wd_timer3_fck",
5272         .prcm = {
5273                 .omap4 = {
5274                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5275                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5276                         .modulemode   = MODULEMODE_SWCTRL,
5277                 },
5278         },
5279         .slaves         = omap44xx_wd_timer3_slaves,
5280         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5281 };
5282
5283 /*
5284  * 'usb_host_hs' class
5285  * high-speed multi-port usb host controller
5286  */
5287 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
5288         .master         = &omap44xx_usb_host_hs_hwmod,
5289         .slave          = &omap44xx_l3_main_2_hwmod,
5290         .clk            = "l3_div_ck",
5291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5292 };
5293
5294 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
5295         .rev_offs       = 0x0000,
5296         .sysc_offs      = 0x0010,
5297         .syss_offs      = 0x0014,
5298         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5299                            SYSC_HAS_SOFTRESET),
5300         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5301                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5302                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5303         .sysc_fields    = &omap_hwmod_sysc_type2,
5304 };
5305
5306 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
5307         .name = "usb_host_hs",
5308         .sysc = &omap44xx_usb_host_hs_sysc,
5309 };
5310
5311 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
5312         &omap44xx_usb_host_hs__l3_main_2,
5313 };
5314
5315 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5316         {
5317                 .name           = "uhh",
5318                 .pa_start       = 0x4a064000,
5319                 .pa_end         = 0x4a0647ff,
5320                 .flags          = ADDR_TYPE_RT
5321         },
5322         {
5323                 .name           = "ohci",
5324                 .pa_start       = 0x4a064800,
5325                 .pa_end         = 0x4a064bff,
5326         },
5327         {
5328                 .name           = "ehci",
5329                 .pa_start       = 0x4a064c00,
5330                 .pa_end         = 0x4a064fff,
5331         },
5332         {}
5333 };
5334
5335 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
5336         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5337         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5338         { .irq = -1 }
5339 };
5340
5341 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5342         .master         = &omap44xx_l4_cfg_hwmod,
5343         .slave          = &omap44xx_usb_host_hs_hwmod,
5344         .clk            = "l4_div_ck",
5345         .addr           = omap44xx_usb_host_hs_addrs,
5346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5347 };
5348
5349 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
5350         &omap44xx_l4_cfg__usb_host_hs,
5351 };
5352
5353 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
5354         .name           = "usb_host_hs",
5355         .class          = &omap44xx_usb_host_hs_hwmod_class,
5356         .clkdm_name     = "l3_init_clkdm",
5357         .main_clk       = "usb_host_hs_fck",
5358         .prcm = {
5359                 .omap4 = {
5360                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5361                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5362                         .modulemode   = MODULEMODE_SWCTRL,
5363                 },
5364         },
5365         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
5366         .slaves         = omap44xx_usb_host_hs_slaves,
5367         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5368         .masters        = omap44xx_usb_host_hs_masters,
5369         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5370
5371         /*
5372          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5373          * id: i660
5374          *
5375          * Description:
5376          * In the following configuration :
5377          * - USBHOST module is set to smart-idle mode
5378          * - PRCM asserts idle_req to the USBHOST module ( This typically
5379          *   happens when the system is going to a low power mode : all ports
5380          *   have been suspended, the master part of the USBHOST module has
5381          *   entered the standby state, and SW has cut the functional clocks)
5382          * - an USBHOST interrupt occurs before the module is able to answer
5383          *   idle_ack, typically a remote wakeup IRQ.
5384          * Then the USB HOST module will enter a deadlock situation where it
5385          * is no more accessible nor functional.
5386          *
5387          * Workaround:
5388          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5389          */
5390
5391         /*
5392          * Errata: USB host EHCI may stall when entering smart-standby mode
5393          * Id: i571
5394          *
5395          * Description:
5396          * When the USBHOST module is set to smart-standby mode, and when it is
5397          * ready to enter the standby state (i.e. all ports are suspended and
5398          * all attached devices are in suspend mode), then it can wrongly assert
5399          * the Mstandby signal too early while there are still some residual OCP
5400          * transactions ongoing. If this condition occurs, the internal state
5401          * machine may go to an undefined state and the USB link may be stuck
5402          * upon the next resume.
5403          *
5404          * Workaround:
5405          * Don't use smart standby; use only force standby,
5406          * hence HWMOD_SWSUP_MSTANDBY
5407          */
5408
5409         /*
5410          * During system boot; If the hwmod framework resets the module
5411          * the module will have smart idle settings; which can lead to deadlock
5412          * (above Errata Id:i660); so, dont reset the module during boot;
5413          * Use HWMOD_INIT_NO_RESET.
5414          */
5415
5416         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5417                           HWMOD_INIT_NO_RESET,
5418 };
5419
5420 /*
5421  * 'usb_tll_hs' class
5422  * usb_tll_hs module is the adapter on the usb_host_hs ports
5423  */
5424 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5425         .rev_offs       = 0x0000,
5426         .sysc_offs      = 0x0010,
5427         .syss_offs      = 0x0014,
5428         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5429                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5430                            SYSC_HAS_AUTOIDLE),
5431         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5432         .sysc_fields    = &omap_hwmod_sysc_type1,
5433 };
5434
5435 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5436         .name = "usb_tll_hs",
5437         .sysc = &omap44xx_usb_tll_hs_sysc,
5438 };
5439
5440 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
5441         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
5442         { .irq = -1 }
5443 };
5444
5445 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5446         {
5447                 .name           = "tll",
5448                 .pa_start       = 0x4a062000,
5449                 .pa_end         = 0x4a063fff,
5450                 .flags          = ADDR_TYPE_RT
5451         },
5452         {}
5453 };
5454
5455 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5456         .master         = &omap44xx_l4_cfg_hwmod,
5457         .slave          = &omap44xx_usb_tll_hs_hwmod,
5458         .clk            = "l4_div_ck",
5459         .addr           = omap44xx_usb_tll_hs_addrs,
5460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5461 };
5462
5463 static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
5464         &omap44xx_l4_cfg__usb_tll_hs,
5465 };
5466
5467 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
5468         .name           = "usb_tll_hs",
5469         .class          = &omap44xx_usb_tll_hs_hwmod_class,
5470         .clkdm_name     = "l3_init_clkdm",
5471         .main_clk       = "usb_tll_hs_ick",
5472         .prcm = {
5473                 .omap4 = {
5474                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
5475                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
5476                         .modulemode   = MODULEMODE_HWCTRL,
5477                 },
5478         },
5479         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
5480         .slaves         = omap44xx_usb_tll_hs_slaves,
5481         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5482 };
5483
5484 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5485
5486         /* dmm class */
5487         &omap44xx_dmm_hwmod,
5488
5489         /* emif_fw class */
5490         &omap44xx_emif_fw_hwmod,
5491
5492         /* l3 class */
5493         &omap44xx_l3_instr_hwmod,
5494         &omap44xx_l3_main_1_hwmod,
5495         &omap44xx_l3_main_2_hwmod,
5496         &omap44xx_l3_main_3_hwmod,
5497
5498         /* l4 class */
5499         &omap44xx_l4_abe_hwmod,
5500         &omap44xx_l4_cfg_hwmod,
5501         &omap44xx_l4_per_hwmod,
5502         &omap44xx_l4_wkup_hwmod,
5503
5504         /* mpu_bus class */
5505         &omap44xx_mpu_private_hwmod,
5506
5507         /* aess class */
5508 /*      &omap44xx_aess_hwmod, */
5509
5510         /* bandgap class */
5511         &omap44xx_bandgap_hwmod,
5512
5513         /* counter class */
5514 /*      &omap44xx_counter_32k_hwmod, */
5515
5516         /* dma class */
5517         &omap44xx_dma_system_hwmod,
5518
5519         /* dmic class */
5520         &omap44xx_dmic_hwmod,
5521
5522         /* dsp class */
5523         &omap44xx_dsp_hwmod,
5524         &omap44xx_dsp_c0_hwmod,
5525
5526         /* dss class */
5527         &omap44xx_dss_hwmod,
5528         &omap44xx_dss_dispc_hwmod,
5529         &omap44xx_dss_dsi1_hwmod,
5530         &omap44xx_dss_dsi2_hwmod,
5531         &omap44xx_dss_hdmi_hwmod,
5532         &omap44xx_dss_rfbi_hwmod,
5533         &omap44xx_dss_venc_hwmod,
5534
5535         /* gpio class */
5536         &omap44xx_gpio1_hwmod,
5537         &omap44xx_gpio2_hwmod,
5538         &omap44xx_gpio3_hwmod,
5539         &omap44xx_gpio4_hwmod,
5540         &omap44xx_gpio5_hwmod,
5541         &omap44xx_gpio6_hwmod,
5542
5543         /* hsi class */
5544 /*      &omap44xx_hsi_hwmod, */
5545
5546         /* i2c class */
5547         &omap44xx_i2c1_hwmod,
5548         &omap44xx_i2c2_hwmod,
5549         &omap44xx_i2c3_hwmod,
5550         &omap44xx_i2c4_hwmod,
5551
5552         /* ipu class */
5553         &omap44xx_ipu_hwmod,
5554         &omap44xx_ipu_c0_hwmod,
5555         &omap44xx_ipu_c1_hwmod,
5556
5557         /* iss class */
5558 /*      &omap44xx_iss_hwmod, */
5559
5560         /* iva class */
5561         &omap44xx_iva_hwmod,
5562         &omap44xx_iva_seq0_hwmod,
5563         &omap44xx_iva_seq1_hwmod,
5564
5565         /* kbd class */
5566         &omap44xx_kbd_hwmod,
5567
5568         /* mailbox class */
5569         &omap44xx_mailbox_hwmod,
5570
5571         /* mcbsp class */
5572         &omap44xx_mcbsp1_hwmod,
5573         &omap44xx_mcbsp2_hwmod,
5574         &omap44xx_mcbsp3_hwmod,
5575         &omap44xx_mcbsp4_hwmod,
5576
5577         /* mcpdm class */
5578         &omap44xx_mcpdm_hwmod,
5579
5580         /* mcspi class */
5581         &omap44xx_mcspi1_hwmod,
5582         &omap44xx_mcspi2_hwmod,
5583         &omap44xx_mcspi3_hwmod,
5584         &omap44xx_mcspi4_hwmod,
5585
5586         /* mmc class */
5587         &omap44xx_mmc1_hwmod,
5588         &omap44xx_mmc2_hwmod,
5589         &omap44xx_mmc3_hwmod,
5590         &omap44xx_mmc4_hwmod,
5591         &omap44xx_mmc5_hwmod,
5592
5593         /* mpu class */
5594         &omap44xx_mpu_hwmod,
5595
5596         /* smartreflex class */
5597         &omap44xx_smartreflex_core_hwmod,
5598         &omap44xx_smartreflex_iva_hwmod,
5599         &omap44xx_smartreflex_mpu_hwmod,
5600
5601         /* spinlock class */
5602         &omap44xx_spinlock_hwmod,
5603
5604         /* timer class */
5605         &omap44xx_timer1_hwmod,
5606         &omap44xx_timer2_hwmod,
5607         &omap44xx_timer3_hwmod,
5608         &omap44xx_timer4_hwmod,
5609         &omap44xx_timer5_hwmod,
5610         &omap44xx_timer6_hwmod,
5611         &omap44xx_timer7_hwmod,
5612         &omap44xx_timer8_hwmod,
5613         &omap44xx_timer9_hwmod,
5614         &omap44xx_timer10_hwmod,
5615         &omap44xx_timer11_hwmod,
5616
5617         /* uart class */
5618         &omap44xx_uart1_hwmod,
5619         &omap44xx_uart2_hwmod,
5620         &omap44xx_uart3_hwmod,
5621         &omap44xx_uart4_hwmod,
5622
5623         /* usb host class */
5624         &omap44xx_usb_host_hs_hwmod,
5625         &omap44xx_usb_tll_hs_hwmod,
5626
5627         /* usb_otg_hs class */
5628         &omap44xx_usb_otg_hs_hwmod,
5629
5630         /* wd_timer class */
5631         &omap44xx_wd_timer2_hwmod,
5632         &omap44xx_wd_timer3_hwmod,
5633         NULL,
5634 };
5635
5636 int __init omap44xx_hwmod_init(void)
5637 {
5638         return omap_hwmod_register(omap44xx_hwmods);
5639 }
5640