2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
26 #include <plat/gpio.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
31 #include <plat/dmtimer.h>
32 #include <plat/common.h>
34 #include "omap_hwmod_common_data.h"
36 #include "smartreflex.h"
40 #include "prm-regbits-44xx.h"
43 /* Base offset for all OMAP4 interrupts external to MPUSS */
44 #define OMAP44XX_IRQ_GIC_START 32
46 /* Base offset for all OMAP4 dma requests */
47 #define OMAP44XX_DMA_REQ_START 1
49 /* Backward references (IPs with Bus Master capability) */
50 static struct omap_hwmod omap44xx_aess_hwmod;
51 static struct omap_hwmod omap44xx_dma_system_hwmod;
52 static struct omap_hwmod omap44xx_dmm_hwmod;
53 static struct omap_hwmod omap44xx_dsp_hwmod;
54 static struct omap_hwmod omap44xx_dss_hwmod;
55 static struct omap_hwmod omap44xx_emif_fw_hwmod;
56 static struct omap_hwmod omap44xx_hsi_hwmod;
57 static struct omap_hwmod omap44xx_ipu_hwmod;
58 static struct omap_hwmod omap44xx_iss_hwmod;
59 static struct omap_hwmod omap44xx_iva_hwmod;
60 static struct omap_hwmod omap44xx_l3_instr_hwmod;
61 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
62 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
63 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
64 static struct omap_hwmod omap44xx_l4_abe_hwmod;
65 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
66 static struct omap_hwmod omap44xx_l4_per_hwmod;
67 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
68 static struct omap_hwmod omap44xx_mmc1_hwmod;
69 static struct omap_hwmod omap44xx_mmc2_hwmod;
70 static struct omap_hwmod omap44xx_mpu_hwmod;
71 static struct omap_hwmod omap44xx_mpu_private_hwmod;
72 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
73 static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
74 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
77 * Interconnects omap_hwmod structures
78 * hwmods that compose the global OMAP interconnect
85 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
90 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
91 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
95 /* l3_main_1 -> dmm */
96 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
97 .master = &omap44xx_l3_main_1_hwmod,
98 .slave = &omap44xx_dmm_hwmod,
100 .user = OCP_USER_SDMA,
103 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
105 .pa_start = 0x4e000000,
106 .pa_end = 0x4e0007ff,
107 .flags = ADDR_TYPE_RT
113 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
114 .master = &omap44xx_mpu_hwmod,
115 .slave = &omap44xx_dmm_hwmod,
117 .addr = omap44xx_dmm_addrs,
118 .user = OCP_USER_MPU,
121 /* dmm slave ports */
122 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
123 &omap44xx_l3_main_1__dmm,
127 static struct omap_hwmod omap44xx_dmm_hwmod = {
129 .class = &omap44xx_dmm_hwmod_class,
130 .clkdm_name = "l3_emif_clkdm",
133 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
134 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
137 .slaves = omap44xx_dmm_slaves,
138 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
139 .mpu_irqs = omap44xx_dmm_irqs,
144 * instance(s): emif_fw
146 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
152 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
153 .master = &omap44xx_dmm_hwmod,
154 .slave = &omap44xx_emif_fw_hwmod,
156 .user = OCP_USER_MPU | OCP_USER_SDMA,
159 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
161 .pa_start = 0x4a20c000,
162 .pa_end = 0x4a20c0ff,
163 .flags = ADDR_TYPE_RT
168 /* l4_cfg -> emif_fw */
169 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
170 .master = &omap44xx_l4_cfg_hwmod,
171 .slave = &omap44xx_emif_fw_hwmod,
173 .addr = omap44xx_emif_fw_addrs,
174 .user = OCP_USER_MPU,
177 /* emif_fw slave ports */
178 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
179 &omap44xx_dmm__emif_fw,
180 &omap44xx_l4_cfg__emif_fw,
183 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
185 .class = &omap44xx_emif_fw_hwmod_class,
186 .clkdm_name = "l3_emif_clkdm",
189 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
190 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
193 .slaves = omap44xx_emif_fw_slaves,
194 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
199 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
201 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
206 /* iva -> l3_instr */
207 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
208 .master = &omap44xx_iva_hwmod,
209 .slave = &omap44xx_l3_instr_hwmod,
211 .user = OCP_USER_MPU | OCP_USER_SDMA,
214 /* l3_main_3 -> l3_instr */
215 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
216 .master = &omap44xx_l3_main_3_hwmod,
217 .slave = &omap44xx_l3_instr_hwmod,
219 .user = OCP_USER_MPU | OCP_USER_SDMA,
222 /* l3_instr slave ports */
223 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
224 &omap44xx_iva__l3_instr,
225 &omap44xx_l3_main_3__l3_instr,
228 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
230 .class = &omap44xx_l3_hwmod_class,
231 .clkdm_name = "l3_instr_clkdm",
234 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
235 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
236 .modulemode = MODULEMODE_HWCTRL,
239 .slaves = omap44xx_l3_instr_slaves,
240 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
244 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
245 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
246 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
250 /* dsp -> l3_main_1 */
251 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
252 .master = &omap44xx_dsp_hwmod,
253 .slave = &omap44xx_l3_main_1_hwmod,
255 .user = OCP_USER_MPU | OCP_USER_SDMA,
258 /* dss -> l3_main_1 */
259 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
260 .master = &omap44xx_dss_hwmod,
261 .slave = &omap44xx_l3_main_1_hwmod,
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
266 /* l3_main_2 -> l3_main_1 */
267 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
268 .master = &omap44xx_l3_main_2_hwmod,
269 .slave = &omap44xx_l3_main_1_hwmod,
271 .user = OCP_USER_MPU | OCP_USER_SDMA,
274 /* l4_cfg -> l3_main_1 */
275 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
276 .master = &omap44xx_l4_cfg_hwmod,
277 .slave = &omap44xx_l3_main_1_hwmod,
279 .user = OCP_USER_MPU | OCP_USER_SDMA,
282 /* mmc1 -> l3_main_1 */
283 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
284 .master = &omap44xx_mmc1_hwmod,
285 .slave = &omap44xx_l3_main_1_hwmod,
287 .user = OCP_USER_MPU | OCP_USER_SDMA,
290 /* mmc2 -> l3_main_1 */
291 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
292 .master = &omap44xx_mmc2_hwmod,
293 .slave = &omap44xx_l3_main_1_hwmod,
295 .user = OCP_USER_MPU | OCP_USER_SDMA,
298 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
300 .pa_start = 0x44000000,
301 .pa_end = 0x44000fff,
302 .flags = ADDR_TYPE_RT
307 /* mpu -> l3_main_1 */
308 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
309 .master = &omap44xx_mpu_hwmod,
310 .slave = &omap44xx_l3_main_1_hwmod,
312 .addr = omap44xx_l3_main_1_addrs,
313 .user = OCP_USER_MPU,
316 /* l3_main_1 slave ports */
317 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
318 &omap44xx_dsp__l3_main_1,
319 &omap44xx_dss__l3_main_1,
320 &omap44xx_l3_main_2__l3_main_1,
321 &omap44xx_l4_cfg__l3_main_1,
322 &omap44xx_mmc1__l3_main_1,
323 &omap44xx_mmc2__l3_main_1,
324 &omap44xx_mpu__l3_main_1,
327 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
329 .class = &omap44xx_l3_hwmod_class,
330 .clkdm_name = "l3_1_clkdm",
331 .mpu_irqs = omap44xx_l3_main_1_irqs,
334 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
335 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
338 .slaves = omap44xx_l3_main_1_slaves,
339 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
343 /* dma_system -> l3_main_2 */
344 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
345 .master = &omap44xx_dma_system_hwmod,
346 .slave = &omap44xx_l3_main_2_hwmod,
348 .user = OCP_USER_MPU | OCP_USER_SDMA,
351 /* hsi -> l3_main_2 */
352 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
353 .master = &omap44xx_hsi_hwmod,
354 .slave = &omap44xx_l3_main_2_hwmod,
356 .user = OCP_USER_MPU | OCP_USER_SDMA,
359 /* ipu -> l3_main_2 */
360 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
361 .master = &omap44xx_ipu_hwmod,
362 .slave = &omap44xx_l3_main_2_hwmod,
364 .user = OCP_USER_MPU | OCP_USER_SDMA,
367 /* iss -> l3_main_2 */
368 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
369 .master = &omap44xx_iss_hwmod,
370 .slave = &omap44xx_l3_main_2_hwmod,
372 .user = OCP_USER_MPU | OCP_USER_SDMA,
375 /* iva -> l3_main_2 */
376 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
377 .master = &omap44xx_iva_hwmod,
378 .slave = &omap44xx_l3_main_2_hwmod,
380 .user = OCP_USER_MPU | OCP_USER_SDMA,
383 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
385 .pa_start = 0x44800000,
386 .pa_end = 0x44801fff,
387 .flags = ADDR_TYPE_RT
392 /* l3_main_1 -> l3_main_2 */
393 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
394 .master = &omap44xx_l3_main_1_hwmod,
395 .slave = &omap44xx_l3_main_2_hwmod,
397 .addr = omap44xx_l3_main_2_addrs,
398 .user = OCP_USER_MPU,
401 /* l4_cfg -> l3_main_2 */
402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
403 .master = &omap44xx_l4_cfg_hwmod,
404 .slave = &omap44xx_l3_main_2_hwmod,
406 .user = OCP_USER_MPU | OCP_USER_SDMA,
409 /* usb_otg_hs -> l3_main_2 */
410 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
411 .master = &omap44xx_usb_otg_hs_hwmod,
412 .slave = &omap44xx_l3_main_2_hwmod,
414 .user = OCP_USER_MPU | OCP_USER_SDMA,
417 /* l3_main_2 slave ports */
418 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
419 &omap44xx_dma_system__l3_main_2,
420 &omap44xx_hsi__l3_main_2,
421 &omap44xx_ipu__l3_main_2,
422 &omap44xx_iss__l3_main_2,
423 &omap44xx_iva__l3_main_2,
424 &omap44xx_l3_main_1__l3_main_2,
425 &omap44xx_l4_cfg__l3_main_2,
426 &omap44xx_usb_otg_hs__l3_main_2,
429 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
431 .class = &omap44xx_l3_hwmod_class,
432 .clkdm_name = "l3_2_clkdm",
435 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
436 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
439 .slaves = omap44xx_l3_main_2_slaves,
440 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
444 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
446 .pa_start = 0x45000000,
447 .pa_end = 0x45000fff,
448 .flags = ADDR_TYPE_RT
453 /* l3_main_1 -> l3_main_3 */
454 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
455 .master = &omap44xx_l3_main_1_hwmod,
456 .slave = &omap44xx_l3_main_3_hwmod,
458 .addr = omap44xx_l3_main_3_addrs,
459 .user = OCP_USER_MPU,
462 /* l3_main_2 -> l3_main_3 */
463 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
464 .master = &omap44xx_l3_main_2_hwmod,
465 .slave = &omap44xx_l3_main_3_hwmod,
467 .user = OCP_USER_MPU | OCP_USER_SDMA,
470 /* l4_cfg -> l3_main_3 */
471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
472 .master = &omap44xx_l4_cfg_hwmod,
473 .slave = &omap44xx_l3_main_3_hwmod,
475 .user = OCP_USER_MPU | OCP_USER_SDMA,
478 /* l3_main_3 slave ports */
479 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
480 &omap44xx_l3_main_1__l3_main_3,
481 &omap44xx_l3_main_2__l3_main_3,
482 &omap44xx_l4_cfg__l3_main_3,
485 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
487 .class = &omap44xx_l3_hwmod_class,
488 .clkdm_name = "l3_instr_clkdm",
491 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
492 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
493 .modulemode = MODULEMODE_HWCTRL,
496 .slaves = omap44xx_l3_main_3_slaves,
497 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
502 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
504 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
510 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
511 .master = &omap44xx_aess_hwmod,
512 .slave = &omap44xx_l4_abe_hwmod,
513 .clk = "ocp_abe_iclk",
514 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
519 .master = &omap44xx_dsp_hwmod,
520 .slave = &omap44xx_l4_abe_hwmod,
521 .clk = "ocp_abe_iclk",
522 .user = OCP_USER_MPU | OCP_USER_SDMA,
525 /* l3_main_1 -> l4_abe */
526 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
527 .master = &omap44xx_l3_main_1_hwmod,
528 .slave = &omap44xx_l4_abe_hwmod,
530 .user = OCP_USER_MPU | OCP_USER_SDMA,
534 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
535 .master = &omap44xx_mpu_hwmod,
536 .slave = &omap44xx_l4_abe_hwmod,
537 .clk = "ocp_abe_iclk",
538 .user = OCP_USER_MPU | OCP_USER_SDMA,
541 /* l4_abe slave ports */
542 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
543 &omap44xx_aess__l4_abe,
544 &omap44xx_dsp__l4_abe,
545 &omap44xx_l3_main_1__l4_abe,
546 &omap44xx_mpu__l4_abe,
549 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
551 .class = &omap44xx_l4_hwmod_class,
552 .clkdm_name = "abe_clkdm",
555 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
558 .slaves = omap44xx_l4_abe_slaves,
559 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
563 /* l3_main_1 -> l4_cfg */
564 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
565 .master = &omap44xx_l3_main_1_hwmod,
566 .slave = &omap44xx_l4_cfg_hwmod,
568 .user = OCP_USER_MPU | OCP_USER_SDMA,
571 /* l4_cfg slave ports */
572 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
573 &omap44xx_l3_main_1__l4_cfg,
576 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
578 .class = &omap44xx_l4_hwmod_class,
579 .clkdm_name = "l4_cfg_clkdm",
582 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
583 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
586 .slaves = omap44xx_l4_cfg_slaves,
587 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
591 /* l3_main_2 -> l4_per */
592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
593 .master = &omap44xx_l3_main_2_hwmod,
594 .slave = &omap44xx_l4_per_hwmod,
596 .user = OCP_USER_MPU | OCP_USER_SDMA,
599 /* l4_per slave ports */
600 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
601 &omap44xx_l3_main_2__l4_per,
604 static struct omap_hwmod omap44xx_l4_per_hwmod = {
606 .class = &omap44xx_l4_hwmod_class,
607 .clkdm_name = "l4_per_clkdm",
610 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
611 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
614 .slaves = omap44xx_l4_per_slaves,
615 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
619 /* l4_cfg -> l4_wkup */
620 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
621 .master = &omap44xx_l4_cfg_hwmod,
622 .slave = &omap44xx_l4_wkup_hwmod,
624 .user = OCP_USER_MPU | OCP_USER_SDMA,
627 /* l4_wkup slave ports */
628 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
629 &omap44xx_l4_cfg__l4_wkup,
632 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
634 .class = &omap44xx_l4_hwmod_class,
635 .clkdm_name = "l4_wkup_clkdm",
638 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
639 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
642 .slaves = omap44xx_l4_wkup_slaves,
643 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
648 * instance(s): mpu_private
650 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
655 /* mpu -> mpu_private */
656 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
657 .master = &omap44xx_mpu_hwmod,
658 .slave = &omap44xx_mpu_private_hwmod,
660 .user = OCP_USER_MPU | OCP_USER_SDMA,
663 /* mpu_private slave ports */
664 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
665 &omap44xx_mpu__mpu_private,
668 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
669 .name = "mpu_private",
670 .class = &omap44xx_mpu_bus_hwmod_class,
671 .clkdm_name = "mpuss_clkdm",
672 .slaves = omap44xx_mpu_private_slaves,
673 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
677 * Modules omap_hwmod structures
679 * The following IPs are excluded for the moment because:
680 * - They do not need an explicit SW control using omap_hwmod API.
681 * - They still need to be validated with the driver
682 * properly adapted to omap_hwmod / omap_device
689 * ctrl_module_pad_core
690 * ctrl_module_pad_wkup
723 * audio engine sub system
726 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
729 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
730 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
731 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
732 MSTANDBY_SMART_WKUP),
733 .sysc_fields = &omap_hwmod_sysc_type2,
736 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
738 .sysc = &omap44xx_aess_sysc,
742 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
743 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
747 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
748 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
749 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
750 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
751 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
752 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
753 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
754 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
755 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
759 /* aess master ports */
760 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
761 &omap44xx_aess__l4_abe,
764 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
766 .pa_start = 0x401f1000,
767 .pa_end = 0x401f13ff,
768 .flags = ADDR_TYPE_RT
774 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
775 .master = &omap44xx_l4_abe_hwmod,
776 .slave = &omap44xx_aess_hwmod,
777 .clk = "ocp_abe_iclk",
778 .addr = omap44xx_aess_addrs,
779 .user = OCP_USER_MPU,
782 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
784 .pa_start = 0x490f1000,
785 .pa_end = 0x490f13ff,
786 .flags = ADDR_TYPE_RT
791 /* l4_abe -> aess (dma) */
792 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
793 .master = &omap44xx_l4_abe_hwmod,
794 .slave = &omap44xx_aess_hwmod,
795 .clk = "ocp_abe_iclk",
796 .addr = omap44xx_aess_dma_addrs,
797 .user = OCP_USER_SDMA,
800 /* aess slave ports */
801 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
802 &omap44xx_l4_abe__aess,
803 &omap44xx_l4_abe__aess_dma,
806 static struct omap_hwmod omap44xx_aess_hwmod = {
808 .class = &omap44xx_aess_hwmod_class,
809 .clkdm_name = "abe_clkdm",
810 .mpu_irqs = omap44xx_aess_irqs,
811 .sdma_reqs = omap44xx_aess_sdma_reqs,
812 .main_clk = "aess_fck",
815 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
816 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
817 .modulemode = MODULEMODE_SWCTRL,
820 .slaves = omap44xx_aess_slaves,
821 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
822 .masters = omap44xx_aess_masters,
823 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
828 * bangap reference for ldo regulators
831 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
836 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
837 { .role = "fclk", .clk = "bandgap_fclk" },
840 static struct omap_hwmod omap44xx_bandgap_hwmod = {
842 .class = &omap44xx_bandgap_hwmod_class,
843 .clkdm_name = "l4_wkup_clkdm",
846 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
849 .opt_clks = bandgap_opt_clks,
850 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
855 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
858 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
861 .sysc_flags = SYSC_HAS_SIDLEMODE,
862 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
864 .sysc_fields = &omap_hwmod_sysc_type1,
867 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
869 .sysc = &omap44xx_counter_sysc,
873 static struct omap_hwmod omap44xx_counter_32k_hwmod;
874 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
876 .pa_start = 0x4a304000,
877 .pa_end = 0x4a30401f,
878 .flags = ADDR_TYPE_RT
883 /* l4_wkup -> counter_32k */
884 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
885 .master = &omap44xx_l4_wkup_hwmod,
886 .slave = &omap44xx_counter_32k_hwmod,
887 .clk = "l4_wkup_clk_mux_ck",
888 .addr = omap44xx_counter_32k_addrs,
889 .user = OCP_USER_MPU | OCP_USER_SDMA,
892 /* counter_32k slave ports */
893 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
894 &omap44xx_l4_wkup__counter_32k,
897 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
898 .name = "counter_32k",
899 .class = &omap44xx_counter_hwmod_class,
900 .clkdm_name = "l4_wkup_clkdm",
901 .flags = HWMOD_SWSUP_SIDLE,
902 .main_clk = "sys_32k_ck",
905 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
906 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
909 .slaves = omap44xx_counter_32k_slaves,
910 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
915 * dma controller for data exchange between memory to memory (i.e. internal or
916 * external memory) and gp peripherals to memory or memory to gp peripherals
919 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
923 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
924 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
925 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
926 SYSS_HAS_RESET_STATUS),
927 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
928 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
929 .sysc_fields = &omap_hwmod_sysc_type1,
932 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
934 .sysc = &omap44xx_dma_sysc,
938 static struct omap_dma_dev_attr dma_dev_attr = {
939 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
940 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
945 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
946 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
947 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
948 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
949 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
953 /* dma_system master ports */
954 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
955 &omap44xx_dma_system__l3_main_2,
958 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
960 .pa_start = 0x4a056000,
961 .pa_end = 0x4a056fff,
962 .flags = ADDR_TYPE_RT
967 /* l4_cfg -> dma_system */
968 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
969 .master = &omap44xx_l4_cfg_hwmod,
970 .slave = &omap44xx_dma_system_hwmod,
972 .addr = omap44xx_dma_system_addrs,
973 .user = OCP_USER_MPU | OCP_USER_SDMA,
976 /* dma_system slave ports */
977 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
978 &omap44xx_l4_cfg__dma_system,
981 static struct omap_hwmod omap44xx_dma_system_hwmod = {
982 .name = "dma_system",
983 .class = &omap44xx_dma_hwmod_class,
984 .clkdm_name = "l3_dma_clkdm",
985 .mpu_irqs = omap44xx_dma_system_irqs,
986 .main_clk = "l3_div_ck",
989 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
990 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
993 .dev_attr = &dma_dev_attr,
994 .slaves = omap44xx_dma_system_slaves,
995 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
996 .masters = omap44xx_dma_system_masters,
997 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
1002 * digital microphone controller
1005 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1007 .sysc_offs = 0x0010,
1008 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1009 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1010 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1012 .sysc_fields = &omap_hwmod_sysc_type2,
1015 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1017 .sysc = &omap44xx_dmic_sysc,
1021 static struct omap_hwmod omap44xx_dmic_hwmod;
1022 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1023 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1027 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1028 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1032 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1035 .pa_start = 0x4012e000,
1036 .pa_end = 0x4012e07f,
1037 .flags = ADDR_TYPE_RT
1042 /* l4_abe -> dmic */
1043 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1044 .master = &omap44xx_l4_abe_hwmod,
1045 .slave = &omap44xx_dmic_hwmod,
1046 .clk = "ocp_abe_iclk",
1047 .addr = omap44xx_dmic_addrs,
1048 .user = OCP_USER_MPU,
1051 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1054 .pa_start = 0x4902e000,
1055 .pa_end = 0x4902e07f,
1056 .flags = ADDR_TYPE_RT
1061 /* l4_abe -> dmic (dma) */
1062 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1063 .master = &omap44xx_l4_abe_hwmod,
1064 .slave = &omap44xx_dmic_hwmod,
1065 .clk = "ocp_abe_iclk",
1066 .addr = omap44xx_dmic_dma_addrs,
1067 .user = OCP_USER_SDMA,
1070 /* dmic slave ports */
1071 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1072 &omap44xx_l4_abe__dmic,
1073 &omap44xx_l4_abe__dmic_dma,
1076 static struct omap_hwmod omap44xx_dmic_hwmod = {
1078 .class = &omap44xx_dmic_hwmod_class,
1079 .clkdm_name = "abe_clkdm",
1080 .mpu_irqs = omap44xx_dmic_irqs,
1081 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1082 .main_clk = "dmic_fck",
1085 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1086 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1090 .slaves = omap44xx_dmic_slaves,
1091 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1099 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1104 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1105 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1109 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1110 { .name = "mmu_cache", .rst_shift = 1 },
1113 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1114 { .name = "dsp", .rst_shift = 0 },
1118 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1119 .master = &omap44xx_dsp_hwmod,
1120 .slave = &omap44xx_iva_hwmod,
1121 .clk = "dpll_iva_m5x2_ck",
1124 /* dsp master ports */
1125 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1126 &omap44xx_dsp__l3_main_1,
1127 &omap44xx_dsp__l4_abe,
1132 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1133 .master = &omap44xx_l4_cfg_hwmod,
1134 .slave = &omap44xx_dsp_hwmod,
1136 .user = OCP_USER_MPU | OCP_USER_SDMA,
1139 /* dsp slave ports */
1140 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1141 &omap44xx_l4_cfg__dsp,
1144 /* Pseudo hwmod for reset control purpose only */
1145 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1147 .class = &omap44xx_dsp_hwmod_class,
1148 .clkdm_name = "tesla_clkdm",
1149 .flags = HWMOD_INIT_NO_RESET,
1150 .rst_lines = omap44xx_dsp_c0_resets,
1151 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1154 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1159 static struct omap_hwmod omap44xx_dsp_hwmod = {
1161 .class = &omap44xx_dsp_hwmod_class,
1162 .clkdm_name = "tesla_clkdm",
1163 .mpu_irqs = omap44xx_dsp_irqs,
1164 .rst_lines = omap44xx_dsp_resets,
1165 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1166 .main_clk = "dsp_fck",
1169 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1170 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1171 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1172 .modulemode = MODULEMODE_HWCTRL,
1175 .slaves = omap44xx_dsp_slaves,
1176 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1177 .masters = omap44xx_dsp_masters,
1178 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1183 * display sub-system
1186 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1188 .syss_offs = 0x0014,
1189 .sysc_flags = SYSS_HAS_RESET_STATUS,
1192 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1194 .sysc = &omap44xx_dss_sysc,
1195 .reset = omap_dss_reset,
1199 /* dss master ports */
1200 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1201 &omap44xx_dss__l3_main_1,
1204 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1206 .pa_start = 0x58000000,
1207 .pa_end = 0x5800007f,
1208 .flags = ADDR_TYPE_RT
1213 /* l3_main_2 -> dss */
1214 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1215 .master = &omap44xx_l3_main_2_hwmod,
1216 .slave = &omap44xx_dss_hwmod,
1218 .addr = omap44xx_dss_dma_addrs,
1219 .user = OCP_USER_SDMA,
1222 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1224 .pa_start = 0x48040000,
1225 .pa_end = 0x4804007f,
1226 .flags = ADDR_TYPE_RT
1232 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1233 .master = &omap44xx_l4_per_hwmod,
1234 .slave = &omap44xx_dss_hwmod,
1236 .addr = omap44xx_dss_addrs,
1237 .user = OCP_USER_MPU,
1240 /* dss slave ports */
1241 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1242 &omap44xx_l3_main_2__dss,
1243 &omap44xx_l4_per__dss,
1246 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1247 { .role = "sys_clk", .clk = "dss_sys_clk" },
1248 { .role = "tv_clk", .clk = "dss_tv_clk" },
1249 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1252 static struct omap_hwmod omap44xx_dss_hwmod = {
1254 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1255 .class = &omap44xx_dss_hwmod_class,
1256 .clkdm_name = "l3_dss_clkdm",
1257 .main_clk = "dss_dss_clk",
1260 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1261 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1264 .opt_clks = dss_opt_clks,
1265 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1266 .slaves = omap44xx_dss_slaves,
1267 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1268 .masters = omap44xx_dss_masters,
1269 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1274 * display controller
1277 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1279 .sysc_offs = 0x0010,
1280 .syss_offs = 0x0014,
1281 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1282 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1283 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1284 SYSS_HAS_RESET_STATUS),
1285 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1286 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1287 .sysc_fields = &omap_hwmod_sysc_type1,
1290 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1292 .sysc = &omap44xx_dispc_sysc,
1296 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1297 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1298 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1302 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1303 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1307 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1309 .pa_start = 0x58001000,
1310 .pa_end = 0x58001fff,
1311 .flags = ADDR_TYPE_RT
1316 /* l3_main_2 -> dss_dispc */
1317 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1318 .master = &omap44xx_l3_main_2_hwmod,
1319 .slave = &omap44xx_dss_dispc_hwmod,
1321 .addr = omap44xx_dss_dispc_dma_addrs,
1322 .user = OCP_USER_SDMA,
1325 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1327 .pa_start = 0x48041000,
1328 .pa_end = 0x48041fff,
1329 .flags = ADDR_TYPE_RT
1334 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1336 .has_framedonetv_irq = 1
1339 /* l4_per -> dss_dispc */
1340 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1341 .master = &omap44xx_l4_per_hwmod,
1342 .slave = &omap44xx_dss_dispc_hwmod,
1344 .addr = omap44xx_dss_dispc_addrs,
1345 .user = OCP_USER_MPU,
1348 /* dss_dispc slave ports */
1349 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1350 &omap44xx_l3_main_2__dss_dispc,
1351 &omap44xx_l4_per__dss_dispc,
1354 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1355 .name = "dss_dispc",
1356 .class = &omap44xx_dispc_hwmod_class,
1357 .clkdm_name = "l3_dss_clkdm",
1358 .mpu_irqs = omap44xx_dss_dispc_irqs,
1359 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1360 .main_clk = "dss_dss_clk",
1363 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1364 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1367 .slaves = omap44xx_dss_dispc_slaves,
1368 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1369 .dev_attr = &omap44xx_dss_dispc_dev_attr
1374 * display serial interface controller
1377 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1379 .sysc_offs = 0x0010,
1380 .syss_offs = 0x0014,
1381 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1382 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1383 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1384 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1385 .sysc_fields = &omap_hwmod_sysc_type1,
1388 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1390 .sysc = &omap44xx_dsi_sysc,
1394 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1395 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1396 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1400 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1401 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1405 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1407 .pa_start = 0x58004000,
1408 .pa_end = 0x580041ff,
1409 .flags = ADDR_TYPE_RT
1414 /* l3_main_2 -> dss_dsi1 */
1415 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1416 .master = &omap44xx_l3_main_2_hwmod,
1417 .slave = &omap44xx_dss_dsi1_hwmod,
1419 .addr = omap44xx_dss_dsi1_dma_addrs,
1420 .user = OCP_USER_SDMA,
1423 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1425 .pa_start = 0x48044000,
1426 .pa_end = 0x480441ff,
1427 .flags = ADDR_TYPE_RT
1432 /* l4_per -> dss_dsi1 */
1433 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1434 .master = &omap44xx_l4_per_hwmod,
1435 .slave = &omap44xx_dss_dsi1_hwmod,
1437 .addr = omap44xx_dss_dsi1_addrs,
1438 .user = OCP_USER_MPU,
1441 /* dss_dsi1 slave ports */
1442 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1443 &omap44xx_l3_main_2__dss_dsi1,
1444 &omap44xx_l4_per__dss_dsi1,
1447 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1448 { .role = "sys_clk", .clk = "dss_sys_clk" },
1451 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1453 .class = &omap44xx_dsi_hwmod_class,
1454 .clkdm_name = "l3_dss_clkdm",
1455 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1456 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1457 .main_clk = "dss_dss_clk",
1460 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1461 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1464 .opt_clks = dss_dsi1_opt_clks,
1465 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1466 .slaves = omap44xx_dss_dsi1_slaves,
1467 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1471 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1472 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1473 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1477 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1478 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1482 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1484 .pa_start = 0x58005000,
1485 .pa_end = 0x580051ff,
1486 .flags = ADDR_TYPE_RT
1491 /* l3_main_2 -> dss_dsi2 */
1492 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1493 .master = &omap44xx_l3_main_2_hwmod,
1494 .slave = &omap44xx_dss_dsi2_hwmod,
1496 .addr = omap44xx_dss_dsi2_dma_addrs,
1497 .user = OCP_USER_SDMA,
1500 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1502 .pa_start = 0x48045000,
1503 .pa_end = 0x480451ff,
1504 .flags = ADDR_TYPE_RT
1509 /* l4_per -> dss_dsi2 */
1510 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1511 .master = &omap44xx_l4_per_hwmod,
1512 .slave = &omap44xx_dss_dsi2_hwmod,
1514 .addr = omap44xx_dss_dsi2_addrs,
1515 .user = OCP_USER_MPU,
1518 /* dss_dsi2 slave ports */
1519 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1520 &omap44xx_l3_main_2__dss_dsi2,
1521 &omap44xx_l4_per__dss_dsi2,
1524 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1525 { .role = "sys_clk", .clk = "dss_sys_clk" },
1528 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1530 .class = &omap44xx_dsi_hwmod_class,
1531 .clkdm_name = "l3_dss_clkdm",
1532 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1533 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1534 .main_clk = "dss_dss_clk",
1537 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1538 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1541 .opt_clks = dss_dsi2_opt_clks,
1542 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1543 .slaves = omap44xx_dss_dsi2_slaves,
1544 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1552 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1554 .sysc_offs = 0x0010,
1555 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1556 SYSC_HAS_SOFTRESET),
1557 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1559 .sysc_fields = &omap_hwmod_sysc_type2,
1562 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1564 .sysc = &omap44xx_hdmi_sysc,
1568 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1569 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1570 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1574 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1575 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1579 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1581 .pa_start = 0x58006000,
1582 .pa_end = 0x58006fff,
1583 .flags = ADDR_TYPE_RT
1588 /* l3_main_2 -> dss_hdmi */
1589 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1590 .master = &omap44xx_l3_main_2_hwmod,
1591 .slave = &omap44xx_dss_hdmi_hwmod,
1593 .addr = omap44xx_dss_hdmi_dma_addrs,
1594 .user = OCP_USER_SDMA,
1597 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1599 .pa_start = 0x48046000,
1600 .pa_end = 0x48046fff,
1601 .flags = ADDR_TYPE_RT
1606 /* l4_per -> dss_hdmi */
1607 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1608 .master = &omap44xx_l4_per_hwmod,
1609 .slave = &omap44xx_dss_hdmi_hwmod,
1611 .addr = omap44xx_dss_hdmi_addrs,
1612 .user = OCP_USER_MPU,
1615 /* dss_hdmi slave ports */
1616 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1617 &omap44xx_l3_main_2__dss_hdmi,
1618 &omap44xx_l4_per__dss_hdmi,
1621 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1622 { .role = "sys_clk", .clk = "dss_sys_clk" },
1625 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1627 .class = &omap44xx_hdmi_hwmod_class,
1628 .clkdm_name = "l3_dss_clkdm",
1629 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1630 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1631 .main_clk = "dss_48mhz_clk",
1634 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1635 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1638 .opt_clks = dss_hdmi_opt_clks,
1639 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1640 .slaves = omap44xx_dss_hdmi_slaves,
1641 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1646 * remote frame buffer interface
1649 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1651 .sysc_offs = 0x0010,
1652 .syss_offs = 0x0014,
1653 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1654 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1656 .sysc_fields = &omap_hwmod_sysc_type1,
1659 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1661 .sysc = &omap44xx_rfbi_sysc,
1665 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1666 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1667 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1671 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1673 .pa_start = 0x58002000,
1674 .pa_end = 0x580020ff,
1675 .flags = ADDR_TYPE_RT
1680 /* l3_main_2 -> dss_rfbi */
1681 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1682 .master = &omap44xx_l3_main_2_hwmod,
1683 .slave = &omap44xx_dss_rfbi_hwmod,
1685 .addr = omap44xx_dss_rfbi_dma_addrs,
1686 .user = OCP_USER_SDMA,
1689 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1691 .pa_start = 0x48042000,
1692 .pa_end = 0x480420ff,
1693 .flags = ADDR_TYPE_RT
1698 /* l4_per -> dss_rfbi */
1699 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1700 .master = &omap44xx_l4_per_hwmod,
1701 .slave = &omap44xx_dss_rfbi_hwmod,
1703 .addr = omap44xx_dss_rfbi_addrs,
1704 .user = OCP_USER_MPU,
1707 /* dss_rfbi slave ports */
1708 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1709 &omap44xx_l3_main_2__dss_rfbi,
1710 &omap44xx_l4_per__dss_rfbi,
1713 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1714 { .role = "ick", .clk = "dss_fck" },
1717 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1719 .class = &omap44xx_rfbi_hwmod_class,
1720 .clkdm_name = "l3_dss_clkdm",
1721 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1722 .main_clk = "dss_dss_clk",
1725 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1726 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1729 .opt_clks = dss_rfbi_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1731 .slaves = omap44xx_dss_rfbi_slaves,
1732 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1740 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1745 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1746 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1748 .pa_start = 0x58003000,
1749 .pa_end = 0x580030ff,
1750 .flags = ADDR_TYPE_RT
1755 /* l3_main_2 -> dss_venc */
1756 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1757 .master = &omap44xx_l3_main_2_hwmod,
1758 .slave = &omap44xx_dss_venc_hwmod,
1760 .addr = omap44xx_dss_venc_dma_addrs,
1761 .user = OCP_USER_SDMA,
1764 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1766 .pa_start = 0x48043000,
1767 .pa_end = 0x480430ff,
1768 .flags = ADDR_TYPE_RT
1773 /* l4_per -> dss_venc */
1774 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1775 .master = &omap44xx_l4_per_hwmod,
1776 .slave = &omap44xx_dss_venc_hwmod,
1778 .addr = omap44xx_dss_venc_addrs,
1779 .user = OCP_USER_MPU,
1782 /* dss_venc slave ports */
1783 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1784 &omap44xx_l3_main_2__dss_venc,
1785 &omap44xx_l4_per__dss_venc,
1788 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1790 .class = &omap44xx_venc_hwmod_class,
1791 .clkdm_name = "l3_dss_clkdm",
1792 .main_clk = "dss_tv_clk",
1795 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1796 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1799 .slaves = omap44xx_dss_venc_slaves,
1800 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1805 * general purpose io module
1808 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1810 .sysc_offs = 0x0010,
1811 .syss_offs = 0x0114,
1812 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1813 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1814 SYSS_HAS_RESET_STATUS),
1815 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1817 .sysc_fields = &omap_hwmod_sysc_type1,
1820 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1822 .sysc = &omap44xx_gpio_sysc,
1827 static struct omap_gpio_dev_attr gpio_dev_attr = {
1833 static struct omap_hwmod omap44xx_gpio1_hwmod;
1834 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1835 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1839 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1841 .pa_start = 0x4a310000,
1842 .pa_end = 0x4a3101ff,
1843 .flags = ADDR_TYPE_RT
1848 /* l4_wkup -> gpio1 */
1849 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1850 .master = &omap44xx_l4_wkup_hwmod,
1851 .slave = &omap44xx_gpio1_hwmod,
1852 .clk = "l4_wkup_clk_mux_ck",
1853 .addr = omap44xx_gpio1_addrs,
1854 .user = OCP_USER_MPU | OCP_USER_SDMA,
1857 /* gpio1 slave ports */
1858 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1859 &omap44xx_l4_wkup__gpio1,
1862 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1863 { .role = "dbclk", .clk = "gpio1_dbclk" },
1866 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1868 .class = &omap44xx_gpio_hwmod_class,
1869 .clkdm_name = "l4_wkup_clkdm",
1870 .mpu_irqs = omap44xx_gpio1_irqs,
1871 .main_clk = "gpio1_ick",
1874 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1875 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1876 .modulemode = MODULEMODE_HWCTRL,
1879 .opt_clks = gpio1_opt_clks,
1880 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1881 .dev_attr = &gpio_dev_attr,
1882 .slaves = omap44xx_gpio1_slaves,
1883 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1887 static struct omap_hwmod omap44xx_gpio2_hwmod;
1888 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1889 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1893 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1895 .pa_start = 0x48055000,
1896 .pa_end = 0x480551ff,
1897 .flags = ADDR_TYPE_RT
1902 /* l4_per -> gpio2 */
1903 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1904 .master = &omap44xx_l4_per_hwmod,
1905 .slave = &omap44xx_gpio2_hwmod,
1907 .addr = omap44xx_gpio2_addrs,
1908 .user = OCP_USER_MPU | OCP_USER_SDMA,
1911 /* gpio2 slave ports */
1912 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1913 &omap44xx_l4_per__gpio2,
1916 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1917 { .role = "dbclk", .clk = "gpio2_dbclk" },
1920 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1922 .class = &omap44xx_gpio_hwmod_class,
1923 .clkdm_name = "l4_per_clkdm",
1924 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1925 .mpu_irqs = omap44xx_gpio2_irqs,
1926 .main_clk = "gpio2_ick",
1929 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1930 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1931 .modulemode = MODULEMODE_HWCTRL,
1934 .opt_clks = gpio2_opt_clks,
1935 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1936 .dev_attr = &gpio_dev_attr,
1937 .slaves = omap44xx_gpio2_slaves,
1938 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1942 static struct omap_hwmod omap44xx_gpio3_hwmod;
1943 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1944 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1948 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1950 .pa_start = 0x48057000,
1951 .pa_end = 0x480571ff,
1952 .flags = ADDR_TYPE_RT
1957 /* l4_per -> gpio3 */
1958 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1959 .master = &omap44xx_l4_per_hwmod,
1960 .slave = &omap44xx_gpio3_hwmod,
1962 .addr = omap44xx_gpio3_addrs,
1963 .user = OCP_USER_MPU | OCP_USER_SDMA,
1966 /* gpio3 slave ports */
1967 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1968 &omap44xx_l4_per__gpio3,
1971 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1972 { .role = "dbclk", .clk = "gpio3_dbclk" },
1975 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1977 .class = &omap44xx_gpio_hwmod_class,
1978 .clkdm_name = "l4_per_clkdm",
1979 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1980 .mpu_irqs = omap44xx_gpio3_irqs,
1981 .main_clk = "gpio3_ick",
1984 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1985 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1986 .modulemode = MODULEMODE_HWCTRL,
1989 .opt_clks = gpio3_opt_clks,
1990 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1991 .dev_attr = &gpio_dev_attr,
1992 .slaves = omap44xx_gpio3_slaves,
1993 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1997 static struct omap_hwmod omap44xx_gpio4_hwmod;
1998 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1999 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2003 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2005 .pa_start = 0x48059000,
2006 .pa_end = 0x480591ff,
2007 .flags = ADDR_TYPE_RT
2012 /* l4_per -> gpio4 */
2013 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2014 .master = &omap44xx_l4_per_hwmod,
2015 .slave = &omap44xx_gpio4_hwmod,
2017 .addr = omap44xx_gpio4_addrs,
2018 .user = OCP_USER_MPU | OCP_USER_SDMA,
2021 /* gpio4 slave ports */
2022 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2023 &omap44xx_l4_per__gpio4,
2026 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2027 { .role = "dbclk", .clk = "gpio4_dbclk" },
2030 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2032 .class = &omap44xx_gpio_hwmod_class,
2033 .clkdm_name = "l4_per_clkdm",
2034 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2035 .mpu_irqs = omap44xx_gpio4_irqs,
2036 .main_clk = "gpio4_ick",
2039 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2040 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2041 .modulemode = MODULEMODE_HWCTRL,
2044 .opt_clks = gpio4_opt_clks,
2045 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2046 .dev_attr = &gpio_dev_attr,
2047 .slaves = omap44xx_gpio4_slaves,
2048 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
2052 static struct omap_hwmod omap44xx_gpio5_hwmod;
2053 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2054 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2058 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2060 .pa_start = 0x4805b000,
2061 .pa_end = 0x4805b1ff,
2062 .flags = ADDR_TYPE_RT
2067 /* l4_per -> gpio5 */
2068 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2069 .master = &omap44xx_l4_per_hwmod,
2070 .slave = &omap44xx_gpio5_hwmod,
2072 .addr = omap44xx_gpio5_addrs,
2073 .user = OCP_USER_MPU | OCP_USER_SDMA,
2076 /* gpio5 slave ports */
2077 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2078 &omap44xx_l4_per__gpio5,
2081 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2082 { .role = "dbclk", .clk = "gpio5_dbclk" },
2085 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2087 .class = &omap44xx_gpio_hwmod_class,
2088 .clkdm_name = "l4_per_clkdm",
2089 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2090 .mpu_irqs = omap44xx_gpio5_irqs,
2091 .main_clk = "gpio5_ick",
2094 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2095 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2096 .modulemode = MODULEMODE_HWCTRL,
2099 .opt_clks = gpio5_opt_clks,
2100 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2101 .dev_attr = &gpio_dev_attr,
2102 .slaves = omap44xx_gpio5_slaves,
2103 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
2107 static struct omap_hwmod omap44xx_gpio6_hwmod;
2108 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2109 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2113 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2115 .pa_start = 0x4805d000,
2116 .pa_end = 0x4805d1ff,
2117 .flags = ADDR_TYPE_RT
2122 /* l4_per -> gpio6 */
2123 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2124 .master = &omap44xx_l4_per_hwmod,
2125 .slave = &omap44xx_gpio6_hwmod,
2127 .addr = omap44xx_gpio6_addrs,
2128 .user = OCP_USER_MPU | OCP_USER_SDMA,
2131 /* gpio6 slave ports */
2132 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2133 &omap44xx_l4_per__gpio6,
2136 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2137 { .role = "dbclk", .clk = "gpio6_dbclk" },
2140 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2142 .class = &omap44xx_gpio_hwmod_class,
2143 .clkdm_name = "l4_per_clkdm",
2144 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2145 .mpu_irqs = omap44xx_gpio6_irqs,
2146 .main_clk = "gpio6_ick",
2149 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2150 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2151 .modulemode = MODULEMODE_HWCTRL,
2154 .opt_clks = gpio6_opt_clks,
2155 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2156 .dev_attr = &gpio_dev_attr,
2157 .slaves = omap44xx_gpio6_slaves,
2158 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2163 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2167 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2169 .sysc_offs = 0x0010,
2170 .syss_offs = 0x0014,
2171 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2172 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2173 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2174 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2175 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2176 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2177 .sysc_fields = &omap_hwmod_sysc_type1,
2180 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2182 .sysc = &omap44xx_hsi_sysc,
2186 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2187 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2188 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2189 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2193 /* hsi master ports */
2194 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2195 &omap44xx_hsi__l3_main_2,
2198 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2200 .pa_start = 0x4a058000,
2201 .pa_end = 0x4a05bfff,
2202 .flags = ADDR_TYPE_RT
2208 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2209 .master = &omap44xx_l4_cfg_hwmod,
2210 .slave = &omap44xx_hsi_hwmod,
2212 .addr = omap44xx_hsi_addrs,
2213 .user = OCP_USER_MPU | OCP_USER_SDMA,
2216 /* hsi slave ports */
2217 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2218 &omap44xx_l4_cfg__hsi,
2221 static struct omap_hwmod omap44xx_hsi_hwmod = {
2223 .class = &omap44xx_hsi_hwmod_class,
2224 .clkdm_name = "l3_init_clkdm",
2225 .mpu_irqs = omap44xx_hsi_irqs,
2226 .main_clk = "hsi_fck",
2229 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2230 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2231 .modulemode = MODULEMODE_HWCTRL,
2234 .slaves = omap44xx_hsi_slaves,
2235 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2236 .masters = omap44xx_hsi_masters,
2237 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2242 * multimaster high-speed i2c controller
2245 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2246 .sysc_offs = 0x0010,
2247 .syss_offs = 0x0090,
2248 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2249 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2250 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2253 .clockact = CLOCKACT_TEST_ICLK,
2254 .sysc_fields = &omap_hwmod_sysc_type1,
2257 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2259 .sysc = &omap44xx_i2c_sysc,
2260 .rev = OMAP_I2C_IP_VERSION_2,
2261 .reset = &omap_i2c_reset,
2264 static struct omap_i2c_dev_attr i2c_dev_attr = {
2265 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2269 static struct omap_hwmod omap44xx_i2c1_hwmod;
2270 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2271 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2275 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2276 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2277 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2281 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2283 .pa_start = 0x48070000,
2284 .pa_end = 0x480700ff,
2285 .flags = ADDR_TYPE_RT
2290 /* l4_per -> i2c1 */
2291 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2292 .master = &omap44xx_l4_per_hwmod,
2293 .slave = &omap44xx_i2c1_hwmod,
2295 .addr = omap44xx_i2c1_addrs,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2299 /* i2c1 slave ports */
2300 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2301 &omap44xx_l4_per__i2c1,
2304 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2306 .class = &omap44xx_i2c_hwmod_class,
2307 .clkdm_name = "l4_per_clkdm",
2308 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2309 .mpu_irqs = omap44xx_i2c1_irqs,
2310 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2311 .main_clk = "i2c1_fck",
2314 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2315 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2316 .modulemode = MODULEMODE_SWCTRL,
2319 .slaves = omap44xx_i2c1_slaves,
2320 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2321 .dev_attr = &i2c_dev_attr,
2325 static struct omap_hwmod omap44xx_i2c2_hwmod;
2326 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2327 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2331 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2332 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2333 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2337 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2339 .pa_start = 0x48072000,
2340 .pa_end = 0x480720ff,
2341 .flags = ADDR_TYPE_RT
2346 /* l4_per -> i2c2 */
2347 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2348 .master = &omap44xx_l4_per_hwmod,
2349 .slave = &omap44xx_i2c2_hwmod,
2351 .addr = omap44xx_i2c2_addrs,
2352 .user = OCP_USER_MPU | OCP_USER_SDMA,
2355 /* i2c2 slave ports */
2356 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2357 &omap44xx_l4_per__i2c2,
2360 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2362 .class = &omap44xx_i2c_hwmod_class,
2363 .clkdm_name = "l4_per_clkdm",
2364 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2365 .mpu_irqs = omap44xx_i2c2_irqs,
2366 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2367 .main_clk = "i2c2_fck",
2370 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2371 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2372 .modulemode = MODULEMODE_SWCTRL,
2375 .slaves = omap44xx_i2c2_slaves,
2376 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2377 .dev_attr = &i2c_dev_attr,
2381 static struct omap_hwmod omap44xx_i2c3_hwmod;
2382 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2383 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2387 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2388 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2389 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2393 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2395 .pa_start = 0x48060000,
2396 .pa_end = 0x480600ff,
2397 .flags = ADDR_TYPE_RT
2402 /* l4_per -> i2c3 */
2403 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2404 .master = &omap44xx_l4_per_hwmod,
2405 .slave = &omap44xx_i2c3_hwmod,
2407 .addr = omap44xx_i2c3_addrs,
2408 .user = OCP_USER_MPU | OCP_USER_SDMA,
2411 /* i2c3 slave ports */
2412 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2413 &omap44xx_l4_per__i2c3,
2416 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2418 .class = &omap44xx_i2c_hwmod_class,
2419 .clkdm_name = "l4_per_clkdm",
2420 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2421 .mpu_irqs = omap44xx_i2c3_irqs,
2422 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2423 .main_clk = "i2c3_fck",
2426 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2427 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2428 .modulemode = MODULEMODE_SWCTRL,
2431 .slaves = omap44xx_i2c3_slaves,
2432 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2433 .dev_attr = &i2c_dev_attr,
2437 static struct omap_hwmod omap44xx_i2c4_hwmod;
2438 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2439 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2443 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2444 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2445 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2449 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2451 .pa_start = 0x48350000,
2452 .pa_end = 0x483500ff,
2453 .flags = ADDR_TYPE_RT
2458 /* l4_per -> i2c4 */
2459 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2460 .master = &omap44xx_l4_per_hwmod,
2461 .slave = &omap44xx_i2c4_hwmod,
2463 .addr = omap44xx_i2c4_addrs,
2464 .user = OCP_USER_MPU | OCP_USER_SDMA,
2467 /* i2c4 slave ports */
2468 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2469 &omap44xx_l4_per__i2c4,
2472 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2474 .class = &omap44xx_i2c_hwmod_class,
2475 .clkdm_name = "l4_per_clkdm",
2476 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2477 .mpu_irqs = omap44xx_i2c4_irqs,
2478 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2479 .main_clk = "i2c4_fck",
2482 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2483 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2484 .modulemode = MODULEMODE_SWCTRL,
2487 .slaves = omap44xx_i2c4_slaves,
2488 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2489 .dev_attr = &i2c_dev_attr,
2494 * imaging processor unit
2497 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2502 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2503 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2507 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2508 { .name = "cpu0", .rst_shift = 0 },
2511 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2512 { .name = "cpu1", .rst_shift = 1 },
2515 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2516 { .name = "mmu_cache", .rst_shift = 2 },
2519 /* ipu master ports */
2520 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2521 &omap44xx_ipu__l3_main_2,
2524 /* l3_main_2 -> ipu */
2525 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2526 .master = &omap44xx_l3_main_2_hwmod,
2527 .slave = &omap44xx_ipu_hwmod,
2529 .user = OCP_USER_MPU | OCP_USER_SDMA,
2532 /* ipu slave ports */
2533 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2534 &omap44xx_l3_main_2__ipu,
2537 /* Pseudo hwmod for reset control purpose only */
2538 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2540 .class = &omap44xx_ipu_hwmod_class,
2541 .clkdm_name = "ducati_clkdm",
2542 .flags = HWMOD_INIT_NO_RESET,
2543 .rst_lines = omap44xx_ipu_c0_resets,
2544 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2547 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2552 /* Pseudo hwmod for reset control purpose only */
2553 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2555 .class = &omap44xx_ipu_hwmod_class,
2556 .clkdm_name = "ducati_clkdm",
2557 .flags = HWMOD_INIT_NO_RESET,
2558 .rst_lines = omap44xx_ipu_c1_resets,
2559 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2562 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2567 static struct omap_hwmod omap44xx_ipu_hwmod = {
2569 .class = &omap44xx_ipu_hwmod_class,
2570 .clkdm_name = "ducati_clkdm",
2571 .mpu_irqs = omap44xx_ipu_irqs,
2572 .rst_lines = omap44xx_ipu_resets,
2573 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2574 .main_clk = "ipu_fck",
2577 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2578 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2579 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2580 .modulemode = MODULEMODE_HWCTRL,
2583 .slaves = omap44xx_ipu_slaves,
2584 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2585 .masters = omap44xx_ipu_masters,
2586 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2591 * external images sensor pixel data processor
2594 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2596 .sysc_offs = 0x0010,
2597 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2598 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2599 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2600 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2601 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2602 .sysc_fields = &omap_hwmod_sysc_type2,
2605 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2607 .sysc = &omap44xx_iss_sysc,
2611 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2612 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2616 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2617 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2618 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2619 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2620 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2624 /* iss master ports */
2625 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2626 &omap44xx_iss__l3_main_2,
2629 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2631 .pa_start = 0x52000000,
2632 .pa_end = 0x520000ff,
2633 .flags = ADDR_TYPE_RT
2638 /* l3_main_2 -> iss */
2639 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2640 .master = &omap44xx_l3_main_2_hwmod,
2641 .slave = &omap44xx_iss_hwmod,
2643 .addr = omap44xx_iss_addrs,
2644 .user = OCP_USER_MPU | OCP_USER_SDMA,
2647 /* iss slave ports */
2648 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2649 &omap44xx_l3_main_2__iss,
2652 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2653 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2656 static struct omap_hwmod omap44xx_iss_hwmod = {
2658 .class = &omap44xx_iss_hwmod_class,
2659 .clkdm_name = "iss_clkdm",
2660 .mpu_irqs = omap44xx_iss_irqs,
2661 .sdma_reqs = omap44xx_iss_sdma_reqs,
2662 .main_clk = "iss_fck",
2665 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2666 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2667 .modulemode = MODULEMODE_SWCTRL,
2670 .opt_clks = iss_opt_clks,
2671 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2672 .slaves = omap44xx_iss_slaves,
2673 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2674 .masters = omap44xx_iss_masters,
2675 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2680 * multi-standard video encoder/decoder hardware accelerator
2683 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2688 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2689 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2690 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2691 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2695 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2696 { .name = "logic", .rst_shift = 2 },
2699 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2700 { .name = "seq0", .rst_shift = 0 },
2703 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2704 { .name = "seq1", .rst_shift = 1 },
2707 /* iva master ports */
2708 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2709 &omap44xx_iva__l3_main_2,
2710 &omap44xx_iva__l3_instr,
2713 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2715 .pa_start = 0x5a000000,
2716 .pa_end = 0x5a07ffff,
2717 .flags = ADDR_TYPE_RT
2722 /* l3_main_2 -> iva */
2723 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2724 .master = &omap44xx_l3_main_2_hwmod,
2725 .slave = &omap44xx_iva_hwmod,
2727 .addr = omap44xx_iva_addrs,
2728 .user = OCP_USER_MPU,
2731 /* iva slave ports */
2732 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2734 &omap44xx_l3_main_2__iva,
2737 /* Pseudo hwmod for reset control purpose only */
2738 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2740 .class = &omap44xx_iva_hwmod_class,
2741 .clkdm_name = "ivahd_clkdm",
2742 .flags = HWMOD_INIT_NO_RESET,
2743 .rst_lines = omap44xx_iva_seq0_resets,
2744 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2747 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2752 /* Pseudo hwmod for reset control purpose only */
2753 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2755 .class = &omap44xx_iva_hwmod_class,
2756 .clkdm_name = "ivahd_clkdm",
2757 .flags = HWMOD_INIT_NO_RESET,
2758 .rst_lines = omap44xx_iva_seq1_resets,
2759 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2762 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2767 static struct omap_hwmod omap44xx_iva_hwmod = {
2769 .class = &omap44xx_iva_hwmod_class,
2770 .clkdm_name = "ivahd_clkdm",
2771 .mpu_irqs = omap44xx_iva_irqs,
2772 .rst_lines = omap44xx_iva_resets,
2773 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2774 .main_clk = "iva_fck",
2777 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2778 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2779 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2780 .modulemode = MODULEMODE_HWCTRL,
2783 .slaves = omap44xx_iva_slaves,
2784 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2785 .masters = omap44xx_iva_masters,
2786 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2791 * keyboard controller
2794 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2796 .sysc_offs = 0x0010,
2797 .syss_offs = 0x0014,
2798 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2799 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2800 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2801 SYSS_HAS_RESET_STATUS),
2802 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2803 .sysc_fields = &omap_hwmod_sysc_type1,
2806 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2808 .sysc = &omap44xx_kbd_sysc,
2812 static struct omap_hwmod omap44xx_kbd_hwmod;
2813 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2814 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2818 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2820 .pa_start = 0x4a31c000,
2821 .pa_end = 0x4a31c07f,
2822 .flags = ADDR_TYPE_RT
2827 /* l4_wkup -> kbd */
2828 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2829 .master = &omap44xx_l4_wkup_hwmod,
2830 .slave = &omap44xx_kbd_hwmod,
2831 .clk = "l4_wkup_clk_mux_ck",
2832 .addr = omap44xx_kbd_addrs,
2833 .user = OCP_USER_MPU | OCP_USER_SDMA,
2836 /* kbd slave ports */
2837 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2838 &omap44xx_l4_wkup__kbd,
2841 static struct omap_hwmod omap44xx_kbd_hwmod = {
2843 .class = &omap44xx_kbd_hwmod_class,
2844 .clkdm_name = "l4_wkup_clkdm",
2845 .mpu_irqs = omap44xx_kbd_irqs,
2846 .main_clk = "kbd_fck",
2849 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2850 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2851 .modulemode = MODULEMODE_SWCTRL,
2854 .slaves = omap44xx_kbd_slaves,
2855 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2860 * mailbox module allowing communication between the on-chip processors using a
2861 * queued mailbox-interrupt mechanism.
2864 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2866 .sysc_offs = 0x0010,
2867 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2868 SYSC_HAS_SOFTRESET),
2869 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2870 .sysc_fields = &omap_hwmod_sysc_type2,
2873 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2875 .sysc = &omap44xx_mailbox_sysc,
2879 static struct omap_hwmod omap44xx_mailbox_hwmod;
2880 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2881 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2885 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2887 .pa_start = 0x4a0f4000,
2888 .pa_end = 0x4a0f41ff,
2889 .flags = ADDR_TYPE_RT
2894 /* l4_cfg -> mailbox */
2895 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2896 .master = &omap44xx_l4_cfg_hwmod,
2897 .slave = &omap44xx_mailbox_hwmod,
2899 .addr = omap44xx_mailbox_addrs,
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2903 /* mailbox slave ports */
2904 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2905 &omap44xx_l4_cfg__mailbox,
2908 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2910 .class = &omap44xx_mailbox_hwmod_class,
2911 .clkdm_name = "l4_cfg_clkdm",
2912 .mpu_irqs = omap44xx_mailbox_irqs,
2915 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2916 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2919 .slaves = omap44xx_mailbox_slaves,
2920 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2925 * multi channel buffered serial port controller
2928 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2929 .sysc_offs = 0x008c,
2930 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2931 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2932 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2933 .sysc_fields = &omap_hwmod_sysc_type1,
2936 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2938 .sysc = &omap44xx_mcbsp_sysc,
2939 .rev = MCBSP_CONFIG_TYPE4,
2943 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2944 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2945 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2949 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2950 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2951 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2955 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2958 .pa_start = 0x40122000,
2959 .pa_end = 0x401220ff,
2960 .flags = ADDR_TYPE_RT
2965 /* l4_abe -> mcbsp1 */
2966 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2967 .master = &omap44xx_l4_abe_hwmod,
2968 .slave = &omap44xx_mcbsp1_hwmod,
2969 .clk = "ocp_abe_iclk",
2970 .addr = omap44xx_mcbsp1_addrs,
2971 .user = OCP_USER_MPU,
2974 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2977 .pa_start = 0x49022000,
2978 .pa_end = 0x490220ff,
2979 .flags = ADDR_TYPE_RT
2984 /* l4_abe -> mcbsp1 (dma) */
2985 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2986 .master = &omap44xx_l4_abe_hwmod,
2987 .slave = &omap44xx_mcbsp1_hwmod,
2988 .clk = "ocp_abe_iclk",
2989 .addr = omap44xx_mcbsp1_dma_addrs,
2990 .user = OCP_USER_SDMA,
2993 /* mcbsp1 slave ports */
2994 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2995 &omap44xx_l4_abe__mcbsp1,
2996 &omap44xx_l4_abe__mcbsp1_dma,
2999 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
3001 .class = &omap44xx_mcbsp_hwmod_class,
3002 .clkdm_name = "abe_clkdm",
3003 .mpu_irqs = omap44xx_mcbsp1_irqs,
3004 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
3005 .main_clk = "mcbsp1_fck",
3008 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3009 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3010 .modulemode = MODULEMODE_SWCTRL,
3013 .slaves = omap44xx_mcbsp1_slaves,
3014 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3018 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3019 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3020 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3024 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3025 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3026 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3030 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3033 .pa_start = 0x40124000,
3034 .pa_end = 0x401240ff,
3035 .flags = ADDR_TYPE_RT
3040 /* l4_abe -> mcbsp2 */
3041 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3042 .master = &omap44xx_l4_abe_hwmod,
3043 .slave = &omap44xx_mcbsp2_hwmod,
3044 .clk = "ocp_abe_iclk",
3045 .addr = omap44xx_mcbsp2_addrs,
3046 .user = OCP_USER_MPU,
3049 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3052 .pa_start = 0x49024000,
3053 .pa_end = 0x490240ff,
3054 .flags = ADDR_TYPE_RT
3059 /* l4_abe -> mcbsp2 (dma) */
3060 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3061 .master = &omap44xx_l4_abe_hwmod,
3062 .slave = &omap44xx_mcbsp2_hwmod,
3063 .clk = "ocp_abe_iclk",
3064 .addr = omap44xx_mcbsp2_dma_addrs,
3065 .user = OCP_USER_SDMA,
3068 /* mcbsp2 slave ports */
3069 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3070 &omap44xx_l4_abe__mcbsp2,
3071 &omap44xx_l4_abe__mcbsp2_dma,
3074 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3076 .class = &omap44xx_mcbsp_hwmod_class,
3077 .clkdm_name = "abe_clkdm",
3078 .mpu_irqs = omap44xx_mcbsp2_irqs,
3079 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
3080 .main_clk = "mcbsp2_fck",
3083 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3084 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3085 .modulemode = MODULEMODE_SWCTRL,
3088 .slaves = omap44xx_mcbsp2_slaves,
3089 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3093 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3094 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3095 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3099 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3100 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3101 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3105 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3108 .pa_start = 0x40126000,
3109 .pa_end = 0x401260ff,
3110 .flags = ADDR_TYPE_RT
3115 /* l4_abe -> mcbsp3 */
3116 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3117 .master = &omap44xx_l4_abe_hwmod,
3118 .slave = &omap44xx_mcbsp3_hwmod,
3119 .clk = "ocp_abe_iclk",
3120 .addr = omap44xx_mcbsp3_addrs,
3121 .user = OCP_USER_MPU,
3124 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3127 .pa_start = 0x49026000,
3128 .pa_end = 0x490260ff,
3129 .flags = ADDR_TYPE_RT
3134 /* l4_abe -> mcbsp3 (dma) */
3135 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3136 .master = &omap44xx_l4_abe_hwmod,
3137 .slave = &omap44xx_mcbsp3_hwmod,
3138 .clk = "ocp_abe_iclk",
3139 .addr = omap44xx_mcbsp3_dma_addrs,
3140 .user = OCP_USER_SDMA,
3143 /* mcbsp3 slave ports */
3144 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3145 &omap44xx_l4_abe__mcbsp3,
3146 &omap44xx_l4_abe__mcbsp3_dma,
3149 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3151 .class = &omap44xx_mcbsp_hwmod_class,
3152 .clkdm_name = "abe_clkdm",
3153 .mpu_irqs = omap44xx_mcbsp3_irqs,
3154 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
3155 .main_clk = "mcbsp3_fck",
3158 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3159 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3160 .modulemode = MODULEMODE_SWCTRL,
3163 .slaves = omap44xx_mcbsp3_slaves,
3164 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3168 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3169 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3170 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3174 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3175 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3176 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3180 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3182 .pa_start = 0x48096000,
3183 .pa_end = 0x480960ff,
3184 .flags = ADDR_TYPE_RT
3189 /* l4_per -> mcbsp4 */
3190 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3191 .master = &omap44xx_l4_per_hwmod,
3192 .slave = &omap44xx_mcbsp4_hwmod,
3194 .addr = omap44xx_mcbsp4_addrs,
3195 .user = OCP_USER_MPU | OCP_USER_SDMA,
3198 /* mcbsp4 slave ports */
3199 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3200 &omap44xx_l4_per__mcbsp4,
3203 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3205 .class = &omap44xx_mcbsp_hwmod_class,
3206 .clkdm_name = "l4_per_clkdm",
3207 .mpu_irqs = omap44xx_mcbsp4_irqs,
3208 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3209 .main_clk = "mcbsp4_fck",
3212 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3213 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3214 .modulemode = MODULEMODE_SWCTRL,
3217 .slaves = omap44xx_mcbsp4_slaves,
3218 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3223 * multi channel pdm controller (proprietary interface with phoenix power
3227 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3229 .sysc_offs = 0x0010,
3230 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3231 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3232 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3234 .sysc_fields = &omap_hwmod_sysc_type2,
3237 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3239 .sysc = &omap44xx_mcpdm_sysc,
3243 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3244 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3245 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3249 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3250 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3251 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3255 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3257 .pa_start = 0x40132000,
3258 .pa_end = 0x4013207f,
3259 .flags = ADDR_TYPE_RT
3264 /* l4_abe -> mcpdm */
3265 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3266 .master = &omap44xx_l4_abe_hwmod,
3267 .slave = &omap44xx_mcpdm_hwmod,
3268 .clk = "ocp_abe_iclk",
3269 .addr = omap44xx_mcpdm_addrs,
3270 .user = OCP_USER_MPU,
3273 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3275 .pa_start = 0x49032000,
3276 .pa_end = 0x4903207f,
3277 .flags = ADDR_TYPE_RT
3282 /* l4_abe -> mcpdm (dma) */
3283 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3284 .master = &omap44xx_l4_abe_hwmod,
3285 .slave = &omap44xx_mcpdm_hwmod,
3286 .clk = "ocp_abe_iclk",
3287 .addr = omap44xx_mcpdm_dma_addrs,
3288 .user = OCP_USER_SDMA,
3291 /* mcpdm slave ports */
3292 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3293 &omap44xx_l4_abe__mcpdm,
3294 &omap44xx_l4_abe__mcpdm_dma,
3297 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3299 .class = &omap44xx_mcpdm_hwmod_class,
3300 .clkdm_name = "abe_clkdm",
3301 .mpu_irqs = omap44xx_mcpdm_irqs,
3302 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3303 .main_clk = "mcpdm_fck",
3306 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3307 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3308 .modulemode = MODULEMODE_SWCTRL,
3311 .slaves = omap44xx_mcpdm_slaves,
3312 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3317 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3321 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3323 .sysc_offs = 0x0010,
3324 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3326 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3328 .sysc_fields = &omap_hwmod_sysc_type2,
3331 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3333 .sysc = &omap44xx_mcspi_sysc,
3334 .rev = OMAP4_MCSPI_REV,
3338 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3339 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3340 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3344 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3345 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3346 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3347 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3348 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3349 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3350 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3351 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3352 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3356 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3358 .pa_start = 0x48098000,
3359 .pa_end = 0x480981ff,
3360 .flags = ADDR_TYPE_RT
3365 /* l4_per -> mcspi1 */
3366 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3367 .master = &omap44xx_l4_per_hwmod,
3368 .slave = &omap44xx_mcspi1_hwmod,
3370 .addr = omap44xx_mcspi1_addrs,
3371 .user = OCP_USER_MPU | OCP_USER_SDMA,
3374 /* mcspi1 slave ports */
3375 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3376 &omap44xx_l4_per__mcspi1,
3379 /* mcspi1 dev_attr */
3380 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3381 .num_chipselect = 4,
3384 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3386 .class = &omap44xx_mcspi_hwmod_class,
3387 .clkdm_name = "l4_per_clkdm",
3388 .mpu_irqs = omap44xx_mcspi1_irqs,
3389 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3390 .main_clk = "mcspi1_fck",
3393 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3394 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3395 .modulemode = MODULEMODE_SWCTRL,
3398 .dev_attr = &mcspi1_dev_attr,
3399 .slaves = omap44xx_mcspi1_slaves,
3400 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3404 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3405 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3406 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3410 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3411 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3412 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3413 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3414 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3418 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3420 .pa_start = 0x4809a000,
3421 .pa_end = 0x4809a1ff,
3422 .flags = ADDR_TYPE_RT
3427 /* l4_per -> mcspi2 */
3428 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3429 .master = &omap44xx_l4_per_hwmod,
3430 .slave = &omap44xx_mcspi2_hwmod,
3432 .addr = omap44xx_mcspi2_addrs,
3433 .user = OCP_USER_MPU | OCP_USER_SDMA,
3436 /* mcspi2 slave ports */
3437 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3438 &omap44xx_l4_per__mcspi2,
3441 /* mcspi2 dev_attr */
3442 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3443 .num_chipselect = 2,
3446 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3448 .class = &omap44xx_mcspi_hwmod_class,
3449 .clkdm_name = "l4_per_clkdm",
3450 .mpu_irqs = omap44xx_mcspi2_irqs,
3451 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3452 .main_clk = "mcspi2_fck",
3455 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3456 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3457 .modulemode = MODULEMODE_SWCTRL,
3460 .dev_attr = &mcspi2_dev_attr,
3461 .slaves = omap44xx_mcspi2_slaves,
3462 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3466 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3467 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3468 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3472 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3473 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3474 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3475 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3476 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3480 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3482 .pa_start = 0x480b8000,
3483 .pa_end = 0x480b81ff,
3484 .flags = ADDR_TYPE_RT
3489 /* l4_per -> mcspi3 */
3490 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3491 .master = &omap44xx_l4_per_hwmod,
3492 .slave = &omap44xx_mcspi3_hwmod,
3494 .addr = omap44xx_mcspi3_addrs,
3495 .user = OCP_USER_MPU | OCP_USER_SDMA,
3498 /* mcspi3 slave ports */
3499 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3500 &omap44xx_l4_per__mcspi3,
3503 /* mcspi3 dev_attr */
3504 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3505 .num_chipselect = 2,
3508 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3510 .class = &omap44xx_mcspi_hwmod_class,
3511 .clkdm_name = "l4_per_clkdm",
3512 .mpu_irqs = omap44xx_mcspi3_irqs,
3513 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3514 .main_clk = "mcspi3_fck",
3517 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3518 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3519 .modulemode = MODULEMODE_SWCTRL,
3522 .dev_attr = &mcspi3_dev_attr,
3523 .slaves = omap44xx_mcspi3_slaves,
3524 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3528 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3529 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3530 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3534 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3535 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3536 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3540 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3542 .pa_start = 0x480ba000,
3543 .pa_end = 0x480ba1ff,
3544 .flags = ADDR_TYPE_RT
3549 /* l4_per -> mcspi4 */
3550 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3551 .master = &omap44xx_l4_per_hwmod,
3552 .slave = &omap44xx_mcspi4_hwmod,
3554 .addr = omap44xx_mcspi4_addrs,
3555 .user = OCP_USER_MPU | OCP_USER_SDMA,
3558 /* mcspi4 slave ports */
3559 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3560 &omap44xx_l4_per__mcspi4,
3563 /* mcspi4 dev_attr */
3564 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3565 .num_chipselect = 1,
3568 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3570 .class = &omap44xx_mcspi_hwmod_class,
3571 .clkdm_name = "l4_per_clkdm",
3572 .mpu_irqs = omap44xx_mcspi4_irqs,
3573 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3574 .main_clk = "mcspi4_fck",
3577 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3578 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3579 .modulemode = MODULEMODE_SWCTRL,
3582 .dev_attr = &mcspi4_dev_attr,
3583 .slaves = omap44xx_mcspi4_slaves,
3584 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3589 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3592 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3594 .sysc_offs = 0x0010,
3595 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3596 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3597 SYSC_HAS_SOFTRESET),
3598 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3599 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3600 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3601 .sysc_fields = &omap_hwmod_sysc_type2,
3604 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3606 .sysc = &omap44xx_mmc_sysc,
3610 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3611 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3615 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3616 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3617 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3621 /* mmc1 master ports */
3622 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3623 &omap44xx_mmc1__l3_main_1,
3626 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3628 .pa_start = 0x4809c000,
3629 .pa_end = 0x4809c3ff,
3630 .flags = ADDR_TYPE_RT
3635 /* l4_per -> mmc1 */
3636 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3637 .master = &omap44xx_l4_per_hwmod,
3638 .slave = &omap44xx_mmc1_hwmod,
3640 .addr = omap44xx_mmc1_addrs,
3641 .user = OCP_USER_MPU | OCP_USER_SDMA,
3644 /* mmc1 slave ports */
3645 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3646 &omap44xx_l4_per__mmc1,
3650 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3651 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3654 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3656 .class = &omap44xx_mmc_hwmod_class,
3657 .clkdm_name = "l3_init_clkdm",
3658 .mpu_irqs = omap44xx_mmc1_irqs,
3659 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3660 .main_clk = "mmc1_fck",
3663 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3664 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3665 .modulemode = MODULEMODE_SWCTRL,
3668 .dev_attr = &mmc1_dev_attr,
3669 .slaves = omap44xx_mmc1_slaves,
3670 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3671 .masters = omap44xx_mmc1_masters,
3672 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3676 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3677 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3681 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3682 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3683 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3687 /* mmc2 master ports */
3688 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3689 &omap44xx_mmc2__l3_main_1,
3692 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3694 .pa_start = 0x480b4000,
3695 .pa_end = 0x480b43ff,
3696 .flags = ADDR_TYPE_RT
3701 /* l4_per -> mmc2 */
3702 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3703 .master = &omap44xx_l4_per_hwmod,
3704 .slave = &omap44xx_mmc2_hwmod,
3706 .addr = omap44xx_mmc2_addrs,
3707 .user = OCP_USER_MPU | OCP_USER_SDMA,
3710 /* mmc2 slave ports */
3711 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3712 &omap44xx_l4_per__mmc2,
3715 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3717 .class = &omap44xx_mmc_hwmod_class,
3718 .clkdm_name = "l3_init_clkdm",
3719 .mpu_irqs = omap44xx_mmc2_irqs,
3720 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3721 .main_clk = "mmc2_fck",
3724 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3725 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3726 .modulemode = MODULEMODE_SWCTRL,
3729 .slaves = omap44xx_mmc2_slaves,
3730 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3731 .masters = omap44xx_mmc2_masters,
3732 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3736 static struct omap_hwmod omap44xx_mmc3_hwmod;
3737 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3738 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3742 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3743 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3744 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3748 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3750 .pa_start = 0x480ad000,
3751 .pa_end = 0x480ad3ff,
3752 .flags = ADDR_TYPE_RT
3757 /* l4_per -> mmc3 */
3758 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3759 .master = &omap44xx_l4_per_hwmod,
3760 .slave = &omap44xx_mmc3_hwmod,
3762 .addr = omap44xx_mmc3_addrs,
3763 .user = OCP_USER_MPU | OCP_USER_SDMA,
3766 /* mmc3 slave ports */
3767 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3768 &omap44xx_l4_per__mmc3,
3771 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3773 .class = &omap44xx_mmc_hwmod_class,
3774 .clkdm_name = "l4_per_clkdm",
3775 .mpu_irqs = omap44xx_mmc3_irqs,
3776 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3777 .main_clk = "mmc3_fck",
3780 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3781 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3782 .modulemode = MODULEMODE_SWCTRL,
3785 .slaves = omap44xx_mmc3_slaves,
3786 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3790 static struct omap_hwmod omap44xx_mmc4_hwmod;
3791 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3792 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3796 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3797 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3798 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3802 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3804 .pa_start = 0x480d1000,
3805 .pa_end = 0x480d13ff,
3806 .flags = ADDR_TYPE_RT
3811 /* l4_per -> mmc4 */
3812 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3813 .master = &omap44xx_l4_per_hwmod,
3814 .slave = &omap44xx_mmc4_hwmod,
3816 .addr = omap44xx_mmc4_addrs,
3817 .user = OCP_USER_MPU | OCP_USER_SDMA,
3820 /* mmc4 slave ports */
3821 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3822 &omap44xx_l4_per__mmc4,
3825 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3827 .class = &omap44xx_mmc_hwmod_class,
3828 .clkdm_name = "l4_per_clkdm",
3829 .mpu_irqs = omap44xx_mmc4_irqs,
3831 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3832 .main_clk = "mmc4_fck",
3835 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3836 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3837 .modulemode = MODULEMODE_SWCTRL,
3840 .slaves = omap44xx_mmc4_slaves,
3841 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3845 static struct omap_hwmod omap44xx_mmc5_hwmod;
3846 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3847 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3851 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3852 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3853 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3857 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3859 .pa_start = 0x480d5000,
3860 .pa_end = 0x480d53ff,
3861 .flags = ADDR_TYPE_RT
3866 /* l4_per -> mmc5 */
3867 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3868 .master = &omap44xx_l4_per_hwmod,
3869 .slave = &omap44xx_mmc5_hwmod,
3871 .addr = omap44xx_mmc5_addrs,
3872 .user = OCP_USER_MPU | OCP_USER_SDMA,
3875 /* mmc5 slave ports */
3876 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3877 &omap44xx_l4_per__mmc5,
3880 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3882 .class = &omap44xx_mmc_hwmod_class,
3883 .clkdm_name = "l4_per_clkdm",
3884 .mpu_irqs = omap44xx_mmc5_irqs,
3885 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3886 .main_clk = "mmc5_fck",
3889 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3890 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3891 .modulemode = MODULEMODE_SWCTRL,
3894 .slaves = omap44xx_mmc5_slaves,
3895 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3903 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3908 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3909 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3910 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3911 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3915 /* mpu master ports */
3916 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3917 &omap44xx_mpu__l3_main_1,
3918 &omap44xx_mpu__l4_abe,
3922 static struct omap_hwmod omap44xx_mpu_hwmod = {
3924 .class = &omap44xx_mpu_hwmod_class,
3925 .clkdm_name = "mpuss_clkdm",
3926 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3927 .mpu_irqs = omap44xx_mpu_irqs,
3928 .main_clk = "dpll_mpu_m2_ck",
3931 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3932 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3935 .masters = omap44xx_mpu_masters,
3936 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
3940 * 'smartreflex' class
3941 * smartreflex module (monitor silicon performance and outputs a measure of
3942 * performance error)
3945 /* The IP is not compliant to type1 / type2 scheme */
3946 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3951 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3952 .sysc_offs = 0x0038,
3953 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3954 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3956 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3959 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3960 .name = "smartreflex",
3961 .sysc = &omap44xx_smartreflex_sysc,
3965 /* smartreflex_core */
3966 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
3967 .sensor_voltdm_name = "core",
3970 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3971 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3972 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3976 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3978 .pa_start = 0x4a0dd000,
3979 .pa_end = 0x4a0dd03f,
3980 .flags = ADDR_TYPE_RT
3985 /* l4_cfg -> smartreflex_core */
3986 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3987 .master = &omap44xx_l4_cfg_hwmod,
3988 .slave = &omap44xx_smartreflex_core_hwmod,
3990 .addr = omap44xx_smartreflex_core_addrs,
3991 .user = OCP_USER_MPU | OCP_USER_SDMA,
3994 /* smartreflex_core slave ports */
3995 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3996 &omap44xx_l4_cfg__smartreflex_core,
3999 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
4000 .name = "smartreflex_core",
4001 .class = &omap44xx_smartreflex_hwmod_class,
4002 .clkdm_name = "l4_ao_clkdm",
4003 .mpu_irqs = omap44xx_smartreflex_core_irqs,
4005 .main_clk = "smartreflex_core_fck",
4008 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4009 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4010 .modulemode = MODULEMODE_SWCTRL,
4013 .slaves = omap44xx_smartreflex_core_slaves,
4014 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4015 .dev_attr = &smartreflex_core_dev_attr,
4018 /* smartreflex_iva */
4019 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
4020 .sensor_voltdm_name = "iva",
4023 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4024 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4025 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4029 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4031 .pa_start = 0x4a0db000,
4032 .pa_end = 0x4a0db03f,
4033 .flags = ADDR_TYPE_RT
4038 /* l4_cfg -> smartreflex_iva */
4039 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4040 .master = &omap44xx_l4_cfg_hwmod,
4041 .slave = &omap44xx_smartreflex_iva_hwmod,
4043 .addr = omap44xx_smartreflex_iva_addrs,
4044 .user = OCP_USER_MPU | OCP_USER_SDMA,
4047 /* smartreflex_iva slave ports */
4048 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4049 &omap44xx_l4_cfg__smartreflex_iva,
4052 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4053 .name = "smartreflex_iva",
4054 .class = &omap44xx_smartreflex_hwmod_class,
4055 .clkdm_name = "l4_ao_clkdm",
4056 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
4057 .main_clk = "smartreflex_iva_fck",
4060 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4061 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4062 .modulemode = MODULEMODE_SWCTRL,
4065 .slaves = omap44xx_smartreflex_iva_slaves,
4066 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4067 .dev_attr = &smartreflex_iva_dev_attr,
4070 /* smartreflex_mpu */
4071 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
4072 .sensor_voltdm_name = "mpu",
4075 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4076 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4077 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4081 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4083 .pa_start = 0x4a0d9000,
4084 .pa_end = 0x4a0d903f,
4085 .flags = ADDR_TYPE_RT
4090 /* l4_cfg -> smartreflex_mpu */
4091 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4092 .master = &omap44xx_l4_cfg_hwmod,
4093 .slave = &omap44xx_smartreflex_mpu_hwmod,
4095 .addr = omap44xx_smartreflex_mpu_addrs,
4096 .user = OCP_USER_MPU | OCP_USER_SDMA,
4099 /* smartreflex_mpu slave ports */
4100 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4101 &omap44xx_l4_cfg__smartreflex_mpu,
4104 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4105 .name = "smartreflex_mpu",
4106 .class = &omap44xx_smartreflex_hwmod_class,
4107 .clkdm_name = "l4_ao_clkdm",
4108 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
4109 .main_clk = "smartreflex_mpu_fck",
4112 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4113 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4114 .modulemode = MODULEMODE_SWCTRL,
4117 .slaves = omap44xx_smartreflex_mpu_slaves,
4118 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4119 .dev_attr = &smartreflex_mpu_dev_attr,
4124 * spinlock provides hardware assistance for synchronizing the processes
4125 * running on multiple processors
4128 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4130 .sysc_offs = 0x0010,
4131 .syss_offs = 0x0014,
4132 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4133 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4134 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4135 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4137 .sysc_fields = &omap_hwmod_sysc_type1,
4140 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4142 .sysc = &omap44xx_spinlock_sysc,
4146 static struct omap_hwmod omap44xx_spinlock_hwmod;
4147 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4149 .pa_start = 0x4a0f6000,
4150 .pa_end = 0x4a0f6fff,
4151 .flags = ADDR_TYPE_RT
4156 /* l4_cfg -> spinlock */
4157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4158 .master = &omap44xx_l4_cfg_hwmod,
4159 .slave = &omap44xx_spinlock_hwmod,
4161 .addr = omap44xx_spinlock_addrs,
4162 .user = OCP_USER_MPU | OCP_USER_SDMA,
4165 /* spinlock slave ports */
4166 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4167 &omap44xx_l4_cfg__spinlock,
4170 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4172 .class = &omap44xx_spinlock_hwmod_class,
4173 .clkdm_name = "l4_cfg_clkdm",
4176 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4177 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4180 .slaves = omap44xx_spinlock_slaves,
4181 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4186 * general purpose timer module with accurate 1ms tick
4187 * This class contains several variants: ['timer_1ms', 'timer']
4190 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4192 .sysc_offs = 0x0010,
4193 .syss_offs = 0x0014,
4194 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4195 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4196 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4197 SYSS_HAS_RESET_STATUS),
4198 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4199 .sysc_fields = &omap_hwmod_sysc_type1,
4202 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4204 .sysc = &omap44xx_timer_1ms_sysc,
4207 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4209 .sysc_offs = 0x0010,
4210 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4211 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4212 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4214 .sysc_fields = &omap_hwmod_sysc_type2,
4217 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4219 .sysc = &omap44xx_timer_sysc,
4222 /* always-on timers dev attribute */
4223 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4224 .timer_capability = OMAP_TIMER_ALWON,
4227 /* pwm timers dev attribute */
4228 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4229 .timer_capability = OMAP_TIMER_HAS_PWM,
4233 static struct omap_hwmod omap44xx_timer1_hwmod;
4234 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4235 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4239 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4241 .pa_start = 0x4a318000,
4242 .pa_end = 0x4a31807f,
4243 .flags = ADDR_TYPE_RT
4248 /* l4_wkup -> timer1 */
4249 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4250 .master = &omap44xx_l4_wkup_hwmod,
4251 .slave = &omap44xx_timer1_hwmod,
4252 .clk = "l4_wkup_clk_mux_ck",
4253 .addr = omap44xx_timer1_addrs,
4254 .user = OCP_USER_MPU | OCP_USER_SDMA,
4257 /* timer1 slave ports */
4258 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4259 &omap44xx_l4_wkup__timer1,
4262 static struct omap_hwmod omap44xx_timer1_hwmod = {
4264 .class = &omap44xx_timer_1ms_hwmod_class,
4265 .clkdm_name = "l4_wkup_clkdm",
4266 .mpu_irqs = omap44xx_timer1_irqs,
4267 .main_clk = "timer1_fck",
4270 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4271 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4272 .modulemode = MODULEMODE_SWCTRL,
4275 .dev_attr = &capability_alwon_dev_attr,
4276 .slaves = omap44xx_timer1_slaves,
4277 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4281 static struct omap_hwmod omap44xx_timer2_hwmod;
4282 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4283 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4287 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4289 .pa_start = 0x48032000,
4290 .pa_end = 0x4803207f,
4291 .flags = ADDR_TYPE_RT
4296 /* l4_per -> timer2 */
4297 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4298 .master = &omap44xx_l4_per_hwmod,
4299 .slave = &omap44xx_timer2_hwmod,
4301 .addr = omap44xx_timer2_addrs,
4302 .user = OCP_USER_MPU | OCP_USER_SDMA,
4305 /* timer2 slave ports */
4306 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4307 &omap44xx_l4_per__timer2,
4310 static struct omap_hwmod omap44xx_timer2_hwmod = {
4312 .class = &omap44xx_timer_1ms_hwmod_class,
4313 .clkdm_name = "l4_per_clkdm",
4314 .mpu_irqs = omap44xx_timer2_irqs,
4315 .main_clk = "timer2_fck",
4318 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4319 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4320 .modulemode = MODULEMODE_SWCTRL,
4323 .dev_attr = &capability_alwon_dev_attr,
4324 .slaves = omap44xx_timer2_slaves,
4325 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4329 static struct omap_hwmod omap44xx_timer3_hwmod;
4330 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4331 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4335 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4337 .pa_start = 0x48034000,
4338 .pa_end = 0x4803407f,
4339 .flags = ADDR_TYPE_RT
4344 /* l4_per -> timer3 */
4345 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4346 .master = &omap44xx_l4_per_hwmod,
4347 .slave = &omap44xx_timer3_hwmod,
4349 .addr = omap44xx_timer3_addrs,
4350 .user = OCP_USER_MPU | OCP_USER_SDMA,
4353 /* timer3 slave ports */
4354 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4355 &omap44xx_l4_per__timer3,
4358 static struct omap_hwmod omap44xx_timer3_hwmod = {
4360 .class = &omap44xx_timer_hwmod_class,
4361 .clkdm_name = "l4_per_clkdm",
4362 .mpu_irqs = omap44xx_timer3_irqs,
4363 .main_clk = "timer3_fck",
4366 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4367 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4368 .modulemode = MODULEMODE_SWCTRL,
4371 .dev_attr = &capability_alwon_dev_attr,
4372 .slaves = omap44xx_timer3_slaves,
4373 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4377 static struct omap_hwmod omap44xx_timer4_hwmod;
4378 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4379 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4383 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4385 .pa_start = 0x48036000,
4386 .pa_end = 0x4803607f,
4387 .flags = ADDR_TYPE_RT
4392 /* l4_per -> timer4 */
4393 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4394 .master = &omap44xx_l4_per_hwmod,
4395 .slave = &omap44xx_timer4_hwmod,
4397 .addr = omap44xx_timer4_addrs,
4398 .user = OCP_USER_MPU | OCP_USER_SDMA,
4401 /* timer4 slave ports */
4402 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4403 &omap44xx_l4_per__timer4,
4406 static struct omap_hwmod omap44xx_timer4_hwmod = {
4408 .class = &omap44xx_timer_hwmod_class,
4409 .clkdm_name = "l4_per_clkdm",
4410 .mpu_irqs = omap44xx_timer4_irqs,
4411 .main_clk = "timer4_fck",
4414 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4415 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4416 .modulemode = MODULEMODE_SWCTRL,
4419 .dev_attr = &capability_alwon_dev_attr,
4420 .slaves = omap44xx_timer4_slaves,
4421 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4425 static struct omap_hwmod omap44xx_timer5_hwmod;
4426 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4427 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4431 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4433 .pa_start = 0x40138000,
4434 .pa_end = 0x4013807f,
4435 .flags = ADDR_TYPE_RT
4440 /* l4_abe -> timer5 */
4441 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4442 .master = &omap44xx_l4_abe_hwmod,
4443 .slave = &omap44xx_timer5_hwmod,
4444 .clk = "ocp_abe_iclk",
4445 .addr = omap44xx_timer5_addrs,
4446 .user = OCP_USER_MPU,
4449 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4451 .pa_start = 0x49038000,
4452 .pa_end = 0x4903807f,
4453 .flags = ADDR_TYPE_RT
4458 /* l4_abe -> timer5 (dma) */
4459 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4460 .master = &omap44xx_l4_abe_hwmod,
4461 .slave = &omap44xx_timer5_hwmod,
4462 .clk = "ocp_abe_iclk",
4463 .addr = omap44xx_timer5_dma_addrs,
4464 .user = OCP_USER_SDMA,
4467 /* timer5 slave ports */
4468 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4469 &omap44xx_l4_abe__timer5,
4470 &omap44xx_l4_abe__timer5_dma,
4473 static struct omap_hwmod omap44xx_timer5_hwmod = {
4475 .class = &omap44xx_timer_hwmod_class,
4476 .clkdm_name = "abe_clkdm",
4477 .mpu_irqs = omap44xx_timer5_irqs,
4478 .main_clk = "timer5_fck",
4481 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4482 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4483 .modulemode = MODULEMODE_SWCTRL,
4486 .dev_attr = &capability_alwon_dev_attr,
4487 .slaves = omap44xx_timer5_slaves,
4488 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4492 static struct omap_hwmod omap44xx_timer6_hwmod;
4493 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4494 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4498 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4500 .pa_start = 0x4013a000,
4501 .pa_end = 0x4013a07f,
4502 .flags = ADDR_TYPE_RT
4507 /* l4_abe -> timer6 */
4508 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4509 .master = &omap44xx_l4_abe_hwmod,
4510 .slave = &omap44xx_timer6_hwmod,
4511 .clk = "ocp_abe_iclk",
4512 .addr = omap44xx_timer6_addrs,
4513 .user = OCP_USER_MPU,
4516 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4518 .pa_start = 0x4903a000,
4519 .pa_end = 0x4903a07f,
4520 .flags = ADDR_TYPE_RT
4525 /* l4_abe -> timer6 (dma) */
4526 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4527 .master = &omap44xx_l4_abe_hwmod,
4528 .slave = &omap44xx_timer6_hwmod,
4529 .clk = "ocp_abe_iclk",
4530 .addr = omap44xx_timer6_dma_addrs,
4531 .user = OCP_USER_SDMA,
4534 /* timer6 slave ports */
4535 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4536 &omap44xx_l4_abe__timer6,
4537 &omap44xx_l4_abe__timer6_dma,
4540 static struct omap_hwmod omap44xx_timer6_hwmod = {
4542 .class = &omap44xx_timer_hwmod_class,
4543 .clkdm_name = "abe_clkdm",
4544 .mpu_irqs = omap44xx_timer6_irqs,
4546 .main_clk = "timer6_fck",
4549 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4550 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4551 .modulemode = MODULEMODE_SWCTRL,
4554 .dev_attr = &capability_alwon_dev_attr,
4555 .slaves = omap44xx_timer6_slaves,
4556 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4560 static struct omap_hwmod omap44xx_timer7_hwmod;
4561 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4562 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4566 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4568 .pa_start = 0x4013c000,
4569 .pa_end = 0x4013c07f,
4570 .flags = ADDR_TYPE_RT
4575 /* l4_abe -> timer7 */
4576 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4577 .master = &omap44xx_l4_abe_hwmod,
4578 .slave = &omap44xx_timer7_hwmod,
4579 .clk = "ocp_abe_iclk",
4580 .addr = omap44xx_timer7_addrs,
4581 .user = OCP_USER_MPU,
4584 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4586 .pa_start = 0x4903c000,
4587 .pa_end = 0x4903c07f,
4588 .flags = ADDR_TYPE_RT
4593 /* l4_abe -> timer7 (dma) */
4594 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4595 .master = &omap44xx_l4_abe_hwmod,
4596 .slave = &omap44xx_timer7_hwmod,
4597 .clk = "ocp_abe_iclk",
4598 .addr = omap44xx_timer7_dma_addrs,
4599 .user = OCP_USER_SDMA,
4602 /* timer7 slave ports */
4603 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4604 &omap44xx_l4_abe__timer7,
4605 &omap44xx_l4_abe__timer7_dma,
4608 static struct omap_hwmod omap44xx_timer7_hwmod = {
4610 .class = &omap44xx_timer_hwmod_class,
4611 .clkdm_name = "abe_clkdm",
4612 .mpu_irqs = omap44xx_timer7_irqs,
4613 .main_clk = "timer7_fck",
4616 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4617 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4618 .modulemode = MODULEMODE_SWCTRL,
4621 .dev_attr = &capability_alwon_dev_attr,
4622 .slaves = omap44xx_timer7_slaves,
4623 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4627 static struct omap_hwmod omap44xx_timer8_hwmod;
4628 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4629 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4633 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4635 .pa_start = 0x4013e000,
4636 .pa_end = 0x4013e07f,
4637 .flags = ADDR_TYPE_RT
4642 /* l4_abe -> timer8 */
4643 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4644 .master = &omap44xx_l4_abe_hwmod,
4645 .slave = &omap44xx_timer8_hwmod,
4646 .clk = "ocp_abe_iclk",
4647 .addr = omap44xx_timer8_addrs,
4648 .user = OCP_USER_MPU,
4651 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4653 .pa_start = 0x4903e000,
4654 .pa_end = 0x4903e07f,
4655 .flags = ADDR_TYPE_RT
4660 /* l4_abe -> timer8 (dma) */
4661 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4662 .master = &omap44xx_l4_abe_hwmod,
4663 .slave = &omap44xx_timer8_hwmod,
4664 .clk = "ocp_abe_iclk",
4665 .addr = omap44xx_timer8_dma_addrs,
4666 .user = OCP_USER_SDMA,
4669 /* timer8 slave ports */
4670 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4671 &omap44xx_l4_abe__timer8,
4672 &omap44xx_l4_abe__timer8_dma,
4675 static struct omap_hwmod omap44xx_timer8_hwmod = {
4677 .class = &omap44xx_timer_hwmod_class,
4678 .clkdm_name = "abe_clkdm",
4679 .mpu_irqs = omap44xx_timer8_irqs,
4680 .main_clk = "timer8_fck",
4683 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4684 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4685 .modulemode = MODULEMODE_SWCTRL,
4688 .dev_attr = &capability_pwm_dev_attr,
4689 .slaves = omap44xx_timer8_slaves,
4690 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4694 static struct omap_hwmod omap44xx_timer9_hwmod;
4695 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4696 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4700 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4702 .pa_start = 0x4803e000,
4703 .pa_end = 0x4803e07f,
4704 .flags = ADDR_TYPE_RT
4709 /* l4_per -> timer9 */
4710 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4711 .master = &omap44xx_l4_per_hwmod,
4712 .slave = &omap44xx_timer9_hwmod,
4714 .addr = omap44xx_timer9_addrs,
4715 .user = OCP_USER_MPU | OCP_USER_SDMA,
4718 /* timer9 slave ports */
4719 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4720 &omap44xx_l4_per__timer9,
4723 static struct omap_hwmod omap44xx_timer9_hwmod = {
4725 .class = &omap44xx_timer_hwmod_class,
4726 .clkdm_name = "l4_per_clkdm",
4727 .mpu_irqs = omap44xx_timer9_irqs,
4728 .main_clk = "timer9_fck",
4731 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4732 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4733 .modulemode = MODULEMODE_SWCTRL,
4736 .dev_attr = &capability_pwm_dev_attr,
4737 .slaves = omap44xx_timer9_slaves,
4738 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4742 static struct omap_hwmod omap44xx_timer10_hwmod;
4743 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4744 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4748 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4750 .pa_start = 0x48086000,
4751 .pa_end = 0x4808607f,
4752 .flags = ADDR_TYPE_RT
4757 /* l4_per -> timer10 */
4758 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4759 .master = &omap44xx_l4_per_hwmod,
4760 .slave = &omap44xx_timer10_hwmod,
4762 .addr = omap44xx_timer10_addrs,
4763 .user = OCP_USER_MPU | OCP_USER_SDMA,
4766 /* timer10 slave ports */
4767 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4768 &omap44xx_l4_per__timer10,
4771 static struct omap_hwmod omap44xx_timer10_hwmod = {
4773 .class = &omap44xx_timer_1ms_hwmod_class,
4774 .clkdm_name = "l4_per_clkdm",
4775 .mpu_irqs = omap44xx_timer10_irqs,
4776 .main_clk = "timer10_fck",
4779 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4780 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4781 .modulemode = MODULEMODE_SWCTRL,
4784 .dev_attr = &capability_pwm_dev_attr,
4785 .slaves = omap44xx_timer10_slaves,
4786 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4790 static struct omap_hwmod omap44xx_timer11_hwmod;
4791 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4792 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4796 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4798 .pa_start = 0x48088000,
4799 .pa_end = 0x4808807f,
4800 .flags = ADDR_TYPE_RT
4805 /* l4_per -> timer11 */
4806 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4807 .master = &omap44xx_l4_per_hwmod,
4808 .slave = &omap44xx_timer11_hwmod,
4810 .addr = omap44xx_timer11_addrs,
4811 .user = OCP_USER_MPU | OCP_USER_SDMA,
4814 /* timer11 slave ports */
4815 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4816 &omap44xx_l4_per__timer11,
4819 static struct omap_hwmod omap44xx_timer11_hwmod = {
4821 .class = &omap44xx_timer_hwmod_class,
4822 .clkdm_name = "l4_per_clkdm",
4823 .mpu_irqs = omap44xx_timer11_irqs,
4824 .main_clk = "timer11_fck",
4827 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4828 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4829 .modulemode = MODULEMODE_SWCTRL,
4832 .dev_attr = &capability_pwm_dev_attr,
4833 .slaves = omap44xx_timer11_slaves,
4834 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4839 * universal asynchronous receiver/transmitter (uart)
4842 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4844 .sysc_offs = 0x0054,
4845 .syss_offs = 0x0058,
4846 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4847 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4848 SYSS_HAS_RESET_STATUS),
4849 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4851 .sysc_fields = &omap_hwmod_sysc_type1,
4854 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4856 .sysc = &omap44xx_uart_sysc,
4860 static struct omap_hwmod omap44xx_uart1_hwmod;
4861 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4862 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4866 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4867 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4868 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4872 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4874 .pa_start = 0x4806a000,
4875 .pa_end = 0x4806a0ff,
4876 .flags = ADDR_TYPE_RT
4881 /* l4_per -> uart1 */
4882 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4883 .master = &omap44xx_l4_per_hwmod,
4884 .slave = &omap44xx_uart1_hwmod,
4886 .addr = omap44xx_uart1_addrs,
4887 .user = OCP_USER_MPU | OCP_USER_SDMA,
4890 /* uart1 slave ports */
4891 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4892 &omap44xx_l4_per__uart1,
4895 static struct omap_hwmod omap44xx_uart1_hwmod = {
4897 .class = &omap44xx_uart_hwmod_class,
4898 .clkdm_name = "l4_per_clkdm",
4899 .mpu_irqs = omap44xx_uart1_irqs,
4900 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4901 .main_clk = "uart1_fck",
4904 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4905 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4906 .modulemode = MODULEMODE_SWCTRL,
4909 .slaves = omap44xx_uart1_slaves,
4910 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4914 static struct omap_hwmod omap44xx_uart2_hwmod;
4915 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4916 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4920 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4921 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4922 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4926 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4928 .pa_start = 0x4806c000,
4929 .pa_end = 0x4806c0ff,
4930 .flags = ADDR_TYPE_RT
4935 /* l4_per -> uart2 */
4936 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4937 .master = &omap44xx_l4_per_hwmod,
4938 .slave = &omap44xx_uart2_hwmod,
4940 .addr = omap44xx_uart2_addrs,
4941 .user = OCP_USER_MPU | OCP_USER_SDMA,
4944 /* uart2 slave ports */
4945 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4946 &omap44xx_l4_per__uart2,
4949 static struct omap_hwmod omap44xx_uart2_hwmod = {
4951 .class = &omap44xx_uart_hwmod_class,
4952 .clkdm_name = "l4_per_clkdm",
4953 .mpu_irqs = omap44xx_uart2_irqs,
4954 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4955 .main_clk = "uart2_fck",
4958 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4959 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4960 .modulemode = MODULEMODE_SWCTRL,
4963 .slaves = omap44xx_uart2_slaves,
4964 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
4968 static struct omap_hwmod omap44xx_uart3_hwmod;
4969 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4970 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4974 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4975 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4976 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4980 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4982 .pa_start = 0x48020000,
4983 .pa_end = 0x480200ff,
4984 .flags = ADDR_TYPE_RT
4989 /* l4_per -> uart3 */
4990 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4991 .master = &omap44xx_l4_per_hwmod,
4992 .slave = &omap44xx_uart3_hwmod,
4994 .addr = omap44xx_uart3_addrs,
4995 .user = OCP_USER_MPU | OCP_USER_SDMA,
4998 /* uart3 slave ports */
4999 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
5000 &omap44xx_l4_per__uart3,
5003 static struct omap_hwmod omap44xx_uart3_hwmod = {
5005 .class = &omap44xx_uart_hwmod_class,
5006 .clkdm_name = "l4_per_clkdm",
5007 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
5008 .mpu_irqs = omap44xx_uart3_irqs,
5009 .sdma_reqs = omap44xx_uart3_sdma_reqs,
5010 .main_clk = "uart3_fck",
5013 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5014 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5015 .modulemode = MODULEMODE_SWCTRL,
5018 .slaves = omap44xx_uart3_slaves,
5019 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
5023 static struct omap_hwmod omap44xx_uart4_hwmod;
5024 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5025 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5029 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5030 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5031 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5035 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5037 .pa_start = 0x4806e000,
5038 .pa_end = 0x4806e0ff,
5039 .flags = ADDR_TYPE_RT
5044 /* l4_per -> uart4 */
5045 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5046 .master = &omap44xx_l4_per_hwmod,
5047 .slave = &omap44xx_uart4_hwmod,
5049 .addr = omap44xx_uart4_addrs,
5050 .user = OCP_USER_MPU | OCP_USER_SDMA,
5053 /* uart4 slave ports */
5054 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5055 &omap44xx_l4_per__uart4,
5058 static struct omap_hwmod omap44xx_uart4_hwmod = {
5060 .class = &omap44xx_uart_hwmod_class,
5061 .clkdm_name = "l4_per_clkdm",
5062 .mpu_irqs = omap44xx_uart4_irqs,
5063 .sdma_reqs = omap44xx_uart4_sdma_reqs,
5064 .main_clk = "uart4_fck",
5067 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5068 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5069 .modulemode = MODULEMODE_SWCTRL,
5072 .slaves = omap44xx_uart4_slaves,
5073 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
5077 * 'usb_otg_hs' class
5078 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5081 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5083 .sysc_offs = 0x0404,
5084 .syss_offs = 0x0408,
5085 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5086 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5087 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5088 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5089 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5091 .sysc_fields = &omap_hwmod_sysc_type1,
5094 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5095 .name = "usb_otg_hs",
5096 .sysc = &omap44xx_usb_otg_hs_sysc,
5100 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5101 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5102 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5106 /* usb_otg_hs master ports */
5107 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5108 &omap44xx_usb_otg_hs__l3_main_2,
5111 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5113 .pa_start = 0x4a0ab000,
5114 .pa_end = 0x4a0ab003,
5115 .flags = ADDR_TYPE_RT
5120 /* l4_cfg -> usb_otg_hs */
5121 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5122 .master = &omap44xx_l4_cfg_hwmod,
5123 .slave = &omap44xx_usb_otg_hs_hwmod,
5125 .addr = omap44xx_usb_otg_hs_addrs,
5126 .user = OCP_USER_MPU | OCP_USER_SDMA,
5129 /* usb_otg_hs slave ports */
5130 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5131 &omap44xx_l4_cfg__usb_otg_hs,
5134 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5135 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5138 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5139 .name = "usb_otg_hs",
5140 .class = &omap44xx_usb_otg_hs_hwmod_class,
5141 .clkdm_name = "l3_init_clkdm",
5142 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5143 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5144 .main_clk = "usb_otg_hs_ick",
5147 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5148 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5149 .modulemode = MODULEMODE_HWCTRL,
5152 .opt_clks = usb_otg_hs_opt_clks,
5153 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5154 .slaves = omap44xx_usb_otg_hs_slaves,
5155 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5156 .masters = omap44xx_usb_otg_hs_masters,
5157 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5162 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5163 * overflow condition
5166 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5168 .sysc_offs = 0x0010,
5169 .syss_offs = 0x0014,
5170 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5171 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5172 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5174 .sysc_fields = &omap_hwmod_sysc_type1,
5177 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5179 .sysc = &omap44xx_wd_timer_sysc,
5180 .pre_shutdown = &omap2_wd_timer_disable,
5184 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5185 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5186 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5190 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5192 .pa_start = 0x4a314000,
5193 .pa_end = 0x4a31407f,
5194 .flags = ADDR_TYPE_RT
5199 /* l4_wkup -> wd_timer2 */
5200 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5201 .master = &omap44xx_l4_wkup_hwmod,
5202 .slave = &omap44xx_wd_timer2_hwmod,
5203 .clk = "l4_wkup_clk_mux_ck",
5204 .addr = omap44xx_wd_timer2_addrs,
5205 .user = OCP_USER_MPU | OCP_USER_SDMA,
5208 /* wd_timer2 slave ports */
5209 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5210 &omap44xx_l4_wkup__wd_timer2,
5213 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5214 .name = "wd_timer2",
5215 .class = &omap44xx_wd_timer_hwmod_class,
5216 .clkdm_name = "l4_wkup_clkdm",
5217 .mpu_irqs = omap44xx_wd_timer2_irqs,
5218 .main_clk = "wd_timer2_fck",
5221 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5222 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5223 .modulemode = MODULEMODE_SWCTRL,
5226 .slaves = omap44xx_wd_timer2_slaves,
5227 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5231 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5232 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5233 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5237 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5239 .pa_start = 0x40130000,
5240 .pa_end = 0x4013007f,
5241 .flags = ADDR_TYPE_RT
5246 /* l4_abe -> wd_timer3 */
5247 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5248 .master = &omap44xx_l4_abe_hwmod,
5249 .slave = &omap44xx_wd_timer3_hwmod,
5250 .clk = "ocp_abe_iclk",
5251 .addr = omap44xx_wd_timer3_addrs,
5252 .user = OCP_USER_MPU,
5255 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5257 .pa_start = 0x49030000,
5258 .pa_end = 0x4903007f,
5259 .flags = ADDR_TYPE_RT
5264 /* l4_abe -> wd_timer3 (dma) */
5265 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5266 .master = &omap44xx_l4_abe_hwmod,
5267 .slave = &omap44xx_wd_timer3_hwmod,
5268 .clk = "ocp_abe_iclk",
5269 .addr = omap44xx_wd_timer3_dma_addrs,
5270 .user = OCP_USER_SDMA,
5273 /* wd_timer3 slave ports */
5274 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5275 &omap44xx_l4_abe__wd_timer3,
5276 &omap44xx_l4_abe__wd_timer3_dma,
5279 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5280 .name = "wd_timer3",
5281 .class = &omap44xx_wd_timer_hwmod_class,
5282 .clkdm_name = "abe_clkdm",
5283 .mpu_irqs = omap44xx_wd_timer3_irqs,
5284 .main_clk = "wd_timer3_fck",
5287 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5288 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5289 .modulemode = MODULEMODE_SWCTRL,
5292 .slaves = omap44xx_wd_timer3_slaves,
5293 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5297 * 'usb_host_hs' class
5298 * high-speed multi-port usb host controller
5300 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
5301 .master = &omap44xx_usb_host_hs_hwmod,
5302 .slave = &omap44xx_l3_main_2_hwmod,
5304 .user = OCP_USER_MPU | OCP_USER_SDMA,
5307 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
5309 .sysc_offs = 0x0010,
5310 .syss_offs = 0x0014,
5311 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5312 SYSC_HAS_SOFTRESET),
5313 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5314 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5315 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5316 .sysc_fields = &omap_hwmod_sysc_type2,
5319 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
5320 .name = "usb_host_hs",
5321 .sysc = &omap44xx_usb_host_hs_sysc,
5324 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
5325 &omap44xx_usb_host_hs__l3_main_2,
5328 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5331 .pa_start = 0x4a064000,
5332 .pa_end = 0x4a0647ff,
5333 .flags = ADDR_TYPE_RT
5337 .pa_start = 0x4a064800,
5338 .pa_end = 0x4a064bff,
5342 .pa_start = 0x4a064c00,
5343 .pa_end = 0x4a064fff,
5348 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
5349 { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5350 { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5354 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5355 .master = &omap44xx_l4_cfg_hwmod,
5356 .slave = &omap44xx_usb_host_hs_hwmod,
5358 .addr = omap44xx_usb_host_hs_addrs,
5359 .user = OCP_USER_MPU | OCP_USER_SDMA,
5362 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
5363 &omap44xx_l4_cfg__usb_host_hs,
5366 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
5367 .name = "usb_host_hs",
5368 .class = &omap44xx_usb_host_hs_hwmod_class,
5369 .clkdm_name = "l3_init_clkdm",
5370 .main_clk = "usb_host_hs_fck",
5373 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5374 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5375 .modulemode = MODULEMODE_SWCTRL,
5378 .mpu_irqs = omap44xx_usb_host_hs_irqs,
5379 .slaves = omap44xx_usb_host_hs_slaves,
5380 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5381 .masters = omap44xx_usb_host_hs_masters,
5382 .masters_cnt = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5385 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5389 * In the following configuration :
5390 * - USBHOST module is set to smart-idle mode
5391 * - PRCM asserts idle_req to the USBHOST module ( This typically
5392 * happens when the system is going to a low power mode : all ports
5393 * have been suspended, the master part of the USBHOST module has
5394 * entered the standby state, and SW has cut the functional clocks)
5395 * - an USBHOST interrupt occurs before the module is able to answer
5396 * idle_ack, typically a remote wakeup IRQ.
5397 * Then the USB HOST module will enter a deadlock situation where it
5398 * is no more accessible nor functional.
5401 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5405 * Errata: USB host EHCI may stall when entering smart-standby mode
5409 * When the USBHOST module is set to smart-standby mode, and when it is
5410 * ready to enter the standby state (i.e. all ports are suspended and
5411 * all attached devices are in suspend mode), then it can wrongly assert
5412 * the Mstandby signal too early while there are still some residual OCP
5413 * transactions ongoing. If this condition occurs, the internal state
5414 * machine may go to an undefined state and the USB link may be stuck
5415 * upon the next resume.
5418 * Don't use smart standby; use only force standby,
5419 * hence HWMOD_SWSUP_MSTANDBY
5423 * During system boot; If the hwmod framework resets the module
5424 * the module will have smart idle settings; which can lead to deadlock
5425 * (above Errata Id:i660); so, dont reset the module during boot;
5426 * Use HWMOD_INIT_NO_RESET.
5429 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5430 HWMOD_INIT_NO_RESET,
5434 * 'usb_tll_hs' class
5435 * usb_tll_hs module is the adapter on the usb_host_hs ports
5437 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5439 .sysc_offs = 0x0010,
5440 .syss_offs = 0x0014,
5441 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5442 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5444 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5445 .sysc_fields = &omap_hwmod_sysc_type1,
5448 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5449 .name = "usb_tll_hs",
5450 .sysc = &omap44xx_usb_tll_hs_sysc,
5453 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
5454 { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
5458 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5461 .pa_start = 0x4a062000,
5462 .pa_end = 0x4a063fff,
5463 .flags = ADDR_TYPE_RT
5468 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5469 .master = &omap44xx_l4_cfg_hwmod,
5470 .slave = &omap44xx_usb_tll_hs_hwmod,
5472 .addr = omap44xx_usb_tll_hs_addrs,
5473 .user = OCP_USER_MPU | OCP_USER_SDMA,
5476 static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
5477 &omap44xx_l4_cfg__usb_tll_hs,
5480 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
5481 .name = "usb_tll_hs",
5482 .class = &omap44xx_usb_tll_hs_hwmod_class,
5483 .clkdm_name = "l3_init_clkdm",
5484 .main_clk = "usb_tll_hs_ick",
5487 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
5488 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
5489 .modulemode = MODULEMODE_HWCTRL,
5492 .mpu_irqs = omap44xx_usb_tll_hs_irqs,
5493 .slaves = omap44xx_usb_tll_hs_slaves,
5494 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5497 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5500 &omap44xx_dmm_hwmod,
5503 &omap44xx_emif_fw_hwmod,
5506 &omap44xx_l3_instr_hwmod,
5507 &omap44xx_l3_main_1_hwmod,
5508 &omap44xx_l3_main_2_hwmod,
5509 &omap44xx_l3_main_3_hwmod,
5512 &omap44xx_l4_abe_hwmod,
5513 &omap44xx_l4_cfg_hwmod,
5514 &omap44xx_l4_per_hwmod,
5515 &omap44xx_l4_wkup_hwmod,
5518 &omap44xx_mpu_private_hwmod,
5521 /* &omap44xx_aess_hwmod, */
5524 &omap44xx_bandgap_hwmod,
5527 /* &omap44xx_counter_32k_hwmod, */
5530 &omap44xx_dma_system_hwmod,
5533 &omap44xx_dmic_hwmod,
5536 &omap44xx_dsp_hwmod,
5537 &omap44xx_dsp_c0_hwmod,
5540 &omap44xx_dss_hwmod,
5541 &omap44xx_dss_dispc_hwmod,
5542 &omap44xx_dss_dsi1_hwmod,
5543 &omap44xx_dss_dsi2_hwmod,
5544 &omap44xx_dss_hdmi_hwmod,
5545 &omap44xx_dss_rfbi_hwmod,
5546 &omap44xx_dss_venc_hwmod,
5549 &omap44xx_gpio1_hwmod,
5550 &omap44xx_gpio2_hwmod,
5551 &omap44xx_gpio3_hwmod,
5552 &omap44xx_gpio4_hwmod,
5553 &omap44xx_gpio5_hwmod,
5554 &omap44xx_gpio6_hwmod,
5557 /* &omap44xx_hsi_hwmod, */
5560 &omap44xx_i2c1_hwmod,
5561 &omap44xx_i2c2_hwmod,
5562 &omap44xx_i2c3_hwmod,
5563 &omap44xx_i2c4_hwmod,
5566 &omap44xx_ipu_hwmod,
5567 &omap44xx_ipu_c0_hwmod,
5568 &omap44xx_ipu_c1_hwmod,
5571 /* &omap44xx_iss_hwmod, */
5574 &omap44xx_iva_hwmod,
5575 &omap44xx_iva_seq0_hwmod,
5576 &omap44xx_iva_seq1_hwmod,
5579 &omap44xx_kbd_hwmod,
5582 &omap44xx_mailbox_hwmod,
5585 &omap44xx_mcbsp1_hwmod,
5586 &omap44xx_mcbsp2_hwmod,
5587 &omap44xx_mcbsp3_hwmod,
5588 &omap44xx_mcbsp4_hwmod,
5591 &omap44xx_mcpdm_hwmod,
5594 &omap44xx_mcspi1_hwmod,
5595 &omap44xx_mcspi2_hwmod,
5596 &omap44xx_mcspi3_hwmod,
5597 &omap44xx_mcspi4_hwmod,
5600 &omap44xx_mmc1_hwmod,
5601 &omap44xx_mmc2_hwmod,
5602 &omap44xx_mmc3_hwmod,
5603 &omap44xx_mmc4_hwmod,
5604 &omap44xx_mmc5_hwmod,
5607 &omap44xx_mpu_hwmod,
5609 /* smartreflex class */
5610 &omap44xx_smartreflex_core_hwmod,
5611 &omap44xx_smartreflex_iva_hwmod,
5612 &omap44xx_smartreflex_mpu_hwmod,
5614 /* spinlock class */
5615 &omap44xx_spinlock_hwmod,
5618 &omap44xx_timer1_hwmod,
5619 &omap44xx_timer2_hwmod,
5620 &omap44xx_timer3_hwmod,
5621 &omap44xx_timer4_hwmod,
5622 &omap44xx_timer5_hwmod,
5623 &omap44xx_timer6_hwmod,
5624 &omap44xx_timer7_hwmod,
5625 &omap44xx_timer8_hwmod,
5626 &omap44xx_timer9_hwmod,
5627 &omap44xx_timer10_hwmod,
5628 &omap44xx_timer11_hwmod,
5631 &omap44xx_uart1_hwmod,
5632 &omap44xx_uart2_hwmod,
5633 &omap44xx_uart3_hwmod,
5634 &omap44xx_uart4_hwmod,
5636 /* usb host class */
5637 &omap44xx_usb_host_hs_hwmod,
5638 &omap44xx_usb_tll_hs_hwmod,
5640 /* usb_otg_hs class */
5641 &omap44xx_usb_otg_hs_hwmod,
5643 /* wd_timer class */
5644 &omap44xx_wd_timer2_hwmod,
5645 &omap44xx_wd_timer3_hwmod,
5649 int __init omap44xx_hwmod_init(void)
5651 return omap_hwmod_register(omap44xx_hwmods);