arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/i2c.h>
  32 #include <plat/dmtimer.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "wd_timer.h"
  41
  42 /* Base offset for all OMAP4 interrupts external to MPUSS */
  43 #define OMAP44XX_IRQ_GIC_START  32
  44
  45 /* Base offset for all OMAP4 dma requests */
  46 #define OMAP44XX_DMA_REQ_START  1
  47
  48 /* Backward references (IPs with Bus Master capability) */
  49 static struct omap_hwmod omap44xx_aess_hwmod;
  50 static struct omap_hwmod omap44xx_dma_system_hwmod;
  51 static struct omap_hwmod omap44xx_dmm_hwmod;
  52 static struct omap_hwmod omap44xx_dsp_hwmod;
  53 static struct omap_hwmod omap44xx_dss_hwmod;
  54 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  55 static struct omap_hwmod omap44xx_hsi_hwmod;
  56 static struct omap_hwmod omap44xx_ipu_hwmod;
  57 static struct omap_hwmod omap44xx_iss_hwmod;
  58 static struct omap_hwmod omap44xx_iva_hwmod;
  59 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  60 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  62 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  63 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  64 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  65 static struct omap_hwmod omap44xx_l4_per_hwmod;
  66 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  67 static struct omap_hwmod omap44xx_mmc1_hwmod;
  68 static struct omap_hwmod omap44xx_mmc2_hwmod;
  69 static struct omap_hwmod omap44xx_mpu_hwmod;
  70 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  71 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  72
  73 /*
  74  * Interconnects omap_hwmod structures
  75  * hwmods that compose the global OMAP interconnect
  76  */
  77
  78 /*
  79  * 'dmm' class
  80  * instance(s): dmm
  81  */
  82 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  83         .name   = "dmm",
  84 };
  85
  86 /* dmm */
  87 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  88         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  89         { .irq = -1 }
  90 };
  91
  92 /* l3_main_1 -> dmm */
  93 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  94         .master         = &omap44xx_l3_main_1_hwmod,
  95         .slave          = &omap44xx_dmm_hwmod,
  96         .clk            = "l3_div_ck",
  97         .user           = OCP_USER_SDMA,
  98 };
  99
 100 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 101         {
 102                 .pa_start       = 0x4e000000,
 103                 .pa_end         = 0x4e0007ff,
 104                 .flags          = ADDR_TYPE_RT
 105         },
 106         { }
 107 };
 108
 109 /* mpu -> dmm */
 110 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 111         .master         = &omap44xx_mpu_hwmod,
 112         .slave          = &omap44xx_dmm_hwmod,
 113         .clk            = "l3_div_ck",
 114         .addr           = omap44xx_dmm_addrs,
 115         .user           = OCP_USER_MPU,
 116 };
 117
 118 /* dmm slave ports */
 119 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 120         &omap44xx_l3_main_1__dmm,
 121         &omap44xx_mpu__dmm,
 122 };
 123
 124 static struct omap_hwmod omap44xx_dmm_hwmod = {
 125         .name           = "dmm",
 126         .class          = &omap44xx_dmm_hwmod_class,
 127         .clkdm_name     = "l3_emif_clkdm",
 128         .prcm = {
 129                 .omap4 = {
 130                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
 131                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 132                 },
 133         },
 134         .slaves         = omap44xx_dmm_slaves,
 135         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 136         .mpu_irqs       = omap44xx_dmm_irqs,
 137 };
 138
 139 /*
 140  * 'emif_fw' class
 141  * instance(s): emif_fw
 142  */
 143 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 144         .name   = "emif_fw",
 145 };
 146
 147 /* emif_fw */
 148 /* dmm -> emif_fw */
 149 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 150         .master         = &omap44xx_dmm_hwmod,
 151         .slave          = &omap44xx_emif_fw_hwmod,
 152         .clk            = "l3_div_ck",
 153         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 154 };
 155
 156 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 157         {
 158                 .pa_start       = 0x4a20c000,
 159                 .pa_end         = 0x4a20c0ff,
 160                 .flags          = ADDR_TYPE_RT
 161         },
 162         { }
 163 };
 164
 165 /* l4_cfg -> emif_fw */
 166 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 167         .master         = &omap44xx_l4_cfg_hwmod,
 168         .slave          = &omap44xx_emif_fw_hwmod,
 169         .clk            = "l4_div_ck",
 170         .addr           = omap44xx_emif_fw_addrs,
 171         .user           = OCP_USER_MPU,
 172 };
 173
 174 /* emif_fw slave ports */
 175 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 176         &omap44xx_dmm__emif_fw,
 177         &omap44xx_l4_cfg__emif_fw,
 178 };
 179
 180 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 181         .name           = "emif_fw",
 182         .class          = &omap44xx_emif_fw_hwmod_class,
 183         .clkdm_name     = "l3_emif_clkdm",
 184         .prcm = {
 185                 .omap4 = {
 186                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 187                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 188                 },
 189         },
 190         .slaves         = omap44xx_emif_fw_slaves,
 191         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 192 };
 193
 194 /*
 195  * 'l3' class
 196  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 197  */
 198 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 199         .name   = "l3",
 200 };
 201
 202 /* l3_instr */
 203 /* iva -> l3_instr */
 204 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 205         .master         = &omap44xx_iva_hwmod,
 206         .slave          = &omap44xx_l3_instr_hwmod,
 207         .clk            = "l3_div_ck",
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209 };
 210
 211 /* l3_main_3 -> l3_instr */
 212 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 213         .master         = &omap44xx_l3_main_3_hwmod,
 214         .slave          = &omap44xx_l3_instr_hwmod,
 215         .clk            = "l3_div_ck",
 216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 217 };
 218
 219 /* l3_instr slave ports */
 220 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 221         &omap44xx_iva__l3_instr,
 222         &omap44xx_l3_main_3__l3_instr,
 223 };
 224
 225 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 226         .name           = "l3_instr",
 227         .class          = &omap44xx_l3_hwmod_class,
 228         .clkdm_name     = "l3_instr_clkdm",
 229         .prcm = {
 230                 .omap4 = {
 231                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 232                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 233                         .modulemode   = MODULEMODE_HWCTRL,
 234                 },
 235         },
 236         .slaves         = omap44xx_l3_instr_slaves,
 237         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 238 };
 239
 240 /* l3_main_1 */
 241 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 242         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 243         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 244         { .irq = -1 }
 245 };
 246
 247 /* dsp -> l3_main_1 */
 248 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 249         .master         = &omap44xx_dsp_hwmod,
 250         .slave          = &omap44xx_l3_main_1_hwmod,
 251         .clk            = "l3_div_ck",
 252         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 253 };
 254
 255 /* dss -> l3_main_1 */
 256 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 257         .master         = &omap44xx_dss_hwmod,
 258         .slave          = &omap44xx_l3_main_1_hwmod,
 259         .clk            = "l3_div_ck",
 260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 261 };
 262
 263 /* l3_main_2 -> l3_main_1 */
 264 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 265         .master         = &omap44xx_l3_main_2_hwmod,
 266         .slave          = &omap44xx_l3_main_1_hwmod,
 267         .clk            = "l3_div_ck",
 268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 269 };
 270
 271 /* l4_cfg -> l3_main_1 */
 272 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 273         .master         = &omap44xx_l4_cfg_hwmod,
 274         .slave          = &omap44xx_l3_main_1_hwmod,
 275         .clk            = "l4_div_ck",
 276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 277 };
 278
 279 /* mmc1 -> l3_main_1 */
 280 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 281         .master         = &omap44xx_mmc1_hwmod,
 282         .slave          = &omap44xx_l3_main_1_hwmod,
 283         .clk            = "l3_div_ck",
 284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 285 };
 286
 287 /* mmc2 -> l3_main_1 */
 288 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 289         .master         = &omap44xx_mmc2_hwmod,
 290         .slave          = &omap44xx_l3_main_1_hwmod,
 291         .clk            = "l3_div_ck",
 292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 293 };
 294
 295 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 296         {
 297                 .pa_start       = 0x44000000,
 298                 .pa_end         = 0x44000fff,
 299                 .flags          = ADDR_TYPE_RT
 300         },
 301         { }
 302 };
 303
 304 /* mpu -> l3_main_1 */
 305 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 306         .master         = &omap44xx_mpu_hwmod,
 307         .slave          = &omap44xx_l3_main_1_hwmod,
 308         .clk            = "l3_div_ck",
 309         .addr           = omap44xx_l3_main_1_addrs,
 310         .user           = OCP_USER_MPU,
 311 };
 312
 313 /* l3_main_1 slave ports */
 314 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 315         &omap44xx_dsp__l3_main_1,
 316         &omap44xx_dss__l3_main_1,
 317         &omap44xx_l3_main_2__l3_main_1,
 318         &omap44xx_l4_cfg__l3_main_1,
 319         &omap44xx_mmc1__l3_main_1,
 320         &omap44xx_mmc2__l3_main_1,
 321         &omap44xx_mpu__l3_main_1,
 322 };
 323
 324 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 325         .name           = "l3_main_1",
 326         .class          = &omap44xx_l3_hwmod_class,
 327         .clkdm_name     = "l3_1_clkdm",
 328         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 329         .prcm = {
 330                 .omap4 = {
 331                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 332                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 333                 },
 334         },
 335         .slaves         = omap44xx_l3_main_1_slaves,
 336         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 337 };
 338
 339 /* l3_main_2 */
 340 /* dma_system -> l3_main_2 */
 341 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 342         .master         = &omap44xx_dma_system_hwmod,
 343         .slave          = &omap44xx_l3_main_2_hwmod,
 344         .clk            = "l3_div_ck",
 345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 346 };
 347
 348 /* hsi -> l3_main_2 */
 349 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 350         .master         = &omap44xx_hsi_hwmod,
 351         .slave          = &omap44xx_l3_main_2_hwmod,
 352         .clk            = "l3_div_ck",
 353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 354 };
 355
 356 /* ipu -> l3_main_2 */
 357 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 358         .master         = &omap44xx_ipu_hwmod,
 359         .slave          = &omap44xx_l3_main_2_hwmod,
 360         .clk            = "l3_div_ck",
 361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 362 };
 363
 364 /* iss -> l3_main_2 */
 365 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 366         .master         = &omap44xx_iss_hwmod,
 367         .slave          = &omap44xx_l3_main_2_hwmod,
 368         .clk            = "l3_div_ck",
 369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 370 };
 371
 372 /* iva -> l3_main_2 */
 373 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 374         .master         = &omap44xx_iva_hwmod,
 375         .slave          = &omap44xx_l3_main_2_hwmod,
 376         .clk            = "l3_div_ck",
 377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 378 };
 379
 380 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 381         {
 382                 .pa_start       = 0x44800000,
 383                 .pa_end         = 0x44801fff,
 384                 .flags          = ADDR_TYPE_RT
 385         },
 386         { }
 387 };
 388
 389 /* l3_main_1 -> l3_main_2 */
 390 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 391         .master         = &omap44xx_l3_main_1_hwmod,
 392         .slave          = &omap44xx_l3_main_2_hwmod,
 393         .clk            = "l3_div_ck",
 394         .addr           = omap44xx_l3_main_2_addrs,
 395         .user           = OCP_USER_MPU,
 396 };
 397
 398 /* l4_cfg -> l3_main_2 */
 399 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 400         .master         = &omap44xx_l4_cfg_hwmod,
 401         .slave          = &omap44xx_l3_main_2_hwmod,
 402         .clk            = "l4_div_ck",
 403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 404 };
 405
 406 /* usb_otg_hs -> l3_main_2 */
 407 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 408         .master         = &omap44xx_usb_otg_hs_hwmod,
 409         .slave          = &omap44xx_l3_main_2_hwmod,
 410         .clk            = "l3_div_ck",
 411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 412 };
 413
 414 /* l3_main_2 slave ports */
 415 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 416         &omap44xx_dma_system__l3_main_2,
 417         &omap44xx_hsi__l3_main_2,
 418         &omap44xx_ipu__l3_main_2,
 419         &omap44xx_iss__l3_main_2,
 420         &omap44xx_iva__l3_main_2,
 421         &omap44xx_l3_main_1__l3_main_2,
 422         &omap44xx_l4_cfg__l3_main_2,
 423         &omap44xx_usb_otg_hs__l3_main_2,
 424 };
 425
 426 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 427         .name           = "l3_main_2",
 428         .class          = &omap44xx_l3_hwmod_class,
 429         .clkdm_name     = "l3_2_clkdm",
 430         .prcm = {
 431                 .omap4 = {
 432                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 433                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 434                 },
 435         },
 436         .slaves         = omap44xx_l3_main_2_slaves,
 437         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 438 };
 439
 440 /* l3_main_3 */
 441 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 442         {
 443                 .pa_start       = 0x45000000,
 444                 .pa_end         = 0x45000fff,
 445                 .flags          = ADDR_TYPE_RT
 446         },
 447         { }
 448 };
 449
 450 /* l3_main_1 -> l3_main_3 */
 451 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 452         .master         = &omap44xx_l3_main_1_hwmod,
 453         .slave          = &omap44xx_l3_main_3_hwmod,
 454         .clk            = "l3_div_ck",
 455         .addr           = omap44xx_l3_main_3_addrs,
 456         .user           = OCP_USER_MPU,
 457 };
 458
 459 /* l3_main_2 -> l3_main_3 */
 460 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 461         .master         = &omap44xx_l3_main_2_hwmod,
 462         .slave          = &omap44xx_l3_main_3_hwmod,
 463         .clk            = "l3_div_ck",
 464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 465 };
 466
 467 /* l4_cfg -> l3_main_3 */
 468 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 469         .master         = &omap44xx_l4_cfg_hwmod,
 470         .slave          = &omap44xx_l3_main_3_hwmod,
 471         .clk            = "l4_div_ck",
 472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 473 };
 474
 475 /* l3_main_3 slave ports */
 476 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 477         &omap44xx_l3_main_1__l3_main_3,
 478         &omap44xx_l3_main_2__l3_main_3,
 479         &omap44xx_l4_cfg__l3_main_3,
 480 };
 481
 482 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 483         .name           = "l3_main_3",
 484         .class          = &omap44xx_l3_hwmod_class,
 485         .clkdm_name     = "l3_instr_clkdm",
 486         .prcm = {
 487                 .omap4 = {
 488                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 489                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 490                         .modulemode   = MODULEMODE_HWCTRL,
 491                 },
 492         },
 493         .slaves         = omap44xx_l3_main_3_slaves,
 494         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 495 };
 496
 497 /*
 498  * 'l4' class
 499  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 500  */
 501 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 502         .name   = "l4",
 503 };
 504
 505 /* l4_abe */
 506 /* aess -> l4_abe */
 507 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 508         .master         = &omap44xx_aess_hwmod,
 509         .slave          = &omap44xx_l4_abe_hwmod,
 510         .clk            = "ocp_abe_iclk",
 511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 512 };
 513
 514 /* dsp -> l4_abe */
 515 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 516         .master         = &omap44xx_dsp_hwmod,
 517         .slave          = &omap44xx_l4_abe_hwmod,
 518         .clk            = "ocp_abe_iclk",
 519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 520 };
 521
 522 /* l3_main_1 -> l4_abe */
 523 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 524         .master         = &omap44xx_l3_main_1_hwmod,
 525         .slave          = &omap44xx_l4_abe_hwmod,
 526         .clk            = "l3_div_ck",
 527         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 528 };
 529
 530 /* mpu -> l4_abe */
 531 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 532         .master         = &omap44xx_mpu_hwmod,
 533         .slave          = &omap44xx_l4_abe_hwmod,
 534         .clk            = "ocp_abe_iclk",
 535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 536 };
 537
 538 /* l4_abe slave ports */
 539 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 540         &omap44xx_aess__l4_abe,
 541         &omap44xx_dsp__l4_abe,
 542         &omap44xx_l3_main_1__l4_abe,
 543         &omap44xx_mpu__l4_abe,
 544 };
 545
 546 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 547         .name           = "l4_abe",
 548         .class          = &omap44xx_l4_hwmod_class,
 549         .clkdm_name     = "abe_clkdm",
 550         .prcm = {
 551                 .omap4 = {
 552                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 553                 },
 554         },
 555         .slaves         = omap44xx_l4_abe_slaves,
 556         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 557 };
 558
 559 /* l4_cfg */
 560 /* l3_main_1 -> l4_cfg */
 561 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 562         .master         = &omap44xx_l3_main_1_hwmod,
 563         .slave          = &omap44xx_l4_cfg_hwmod,
 564         .clk            = "l3_div_ck",
 565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 566 };
 567
 568 /* l4_cfg slave ports */
 569 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 570         &omap44xx_l3_main_1__l4_cfg,
 571 };
 572
 573 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 574         .name           = "l4_cfg",
 575         .class          = &omap44xx_l4_hwmod_class,
 576         .clkdm_name     = "l4_cfg_clkdm",
 577         .prcm = {
 578                 .omap4 = {
 579                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 580                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 581                 },
 582         },
 583         .slaves         = omap44xx_l4_cfg_slaves,
 584         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 585 };
 586
 587 /* l4_per */
 588 /* l3_main_2 -> l4_per */
 589 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 590         .master         = &omap44xx_l3_main_2_hwmod,
 591         .slave          = &omap44xx_l4_per_hwmod,
 592         .clk            = "l3_div_ck",
 593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 594 };
 595
 596 /* l4_per slave ports */
 597 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 598         &omap44xx_l3_main_2__l4_per,
 599 };
 600
 601 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 602         .name           = "l4_per",
 603         .class          = &omap44xx_l4_hwmod_class,
 604         .clkdm_name     = "l4_per_clkdm",
 605         .prcm = {
 606                 .omap4 = {
 607                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 608                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 609                 },
 610         },
 611         .slaves         = omap44xx_l4_per_slaves,
 612         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 613 };
 614
 615 /* l4_wkup */
 616 /* l4_cfg -> l4_wkup */
 617 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 618         .master         = &omap44xx_l4_cfg_hwmod,
 619         .slave          = &omap44xx_l4_wkup_hwmod,
 620         .clk            = "l4_div_ck",
 621         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 622 };
 623
 624 /* l4_wkup slave ports */
 625 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 626         &omap44xx_l4_cfg__l4_wkup,
 627 };
 628
 629 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 630         .name           = "l4_wkup",
 631         .class          = &omap44xx_l4_hwmod_class,
 632         .clkdm_name     = "l4_wkup_clkdm",
 633         .prcm = {
 634                 .omap4 = {
 635                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 636                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 637                 },
 638         },
 639         .slaves         = omap44xx_l4_wkup_slaves,
 640         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 641 };
 642
 643 /*
 644  * 'mpu_bus' class
 645  * instance(s): mpu_private
 646  */
 647 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 648         .name   = "mpu_bus",
 649 };
 650
 651 /* mpu_private */
 652 /* mpu -> mpu_private */
 653 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 654         .master         = &omap44xx_mpu_hwmod,
 655         .slave          = &omap44xx_mpu_private_hwmod,
 656         .clk            = "l3_div_ck",
 657         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 658 };
 659
 660 /* mpu_private slave ports */
 661 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 662         &omap44xx_mpu__mpu_private,
 663 };
 664
 665 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 666         .name           = "mpu_private",
 667         .class          = &omap44xx_mpu_bus_hwmod_class,
 668         .clkdm_name     = "mpuss_clkdm",
 669         .slaves         = omap44xx_mpu_private_slaves,
 670         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 671 };
 672
 673 /*
 674  * Modules omap_hwmod structures
 675  *
 676  * The following IPs are excluded for the moment because:
 677  * - They do not need an explicit SW control using omap_hwmod API.
 678  * - They still need to be validated with the driver
 679  *   properly adapted to omap_hwmod / omap_device
 680  *
 681  *  c2c
 682  *  c2c_target_fw
 683  *  cm_core
 684  *  cm_core_aon
 685  *  ctrl_module_core
 686  *  ctrl_module_pad_core
 687  *  ctrl_module_pad_wkup
 688  *  ctrl_module_wkup
 689  *  debugss
 690  *  efuse_ctrl_cust
 691  *  efuse_ctrl_std
 692  *  elm
 693  *  emif1
 694  *  emif2
 695  *  fdif
 696  *  gpmc
 697  *  gpu
 698  *  hdq1w
 699  *  mcasp
 700  *  mpu_c0
 701  *  mpu_c1
 702  *  ocmc_ram
 703  *  ocp2scp_usb_phy
 704  *  ocp_wp_noc
 705  *  prcm_mpu
 706  *  prm
 707  *  scrm
 708  *  sl2if
 709  *  slimbus1
 710  *  slimbus2
 711  *  usb_host_fs
 712  *  usb_host_hs
 713  *  usb_phy_cm
 714  *  usb_tll_hs
 715  *  usim
 716  */
 717
 718 /*
 719  * 'aess' class
 720  * audio engine sub system
 721  */
 722
 723 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 724         .rev_offs       = 0x0000,
 725         .sysc_offs      = 0x0010,
 726         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 727         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 728                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 729                            MSTANDBY_SMART_WKUP),
 730         .sysc_fields    = &omap_hwmod_sysc_type2,
 731 };
 732
 733 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 734         .name   = "aess",
 735         .sysc   = &omap44xx_aess_sysc,
 736 };
 737
 738 /* aess */
 739 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 740         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 741         { .irq = -1 }
 742 };
 743
 744 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 745         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 746         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 747         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 748         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 749         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 750         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 751         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 752         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 753         { .dma_req = -1 }
 754 };
 755
 756 /* aess master ports */
 757 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 758         &omap44xx_aess__l4_abe,
 759 };
 760
 761 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 762         {
 763                 .pa_start       = 0x401f1000,
 764                 .pa_end         = 0x401f13ff,
 765                 .flags          = ADDR_TYPE_RT
 766         },
 767         { }
 768 };
 769
 770 /* l4_abe -> aess */
 771 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 772         .master         = &omap44xx_l4_abe_hwmod,
 773         .slave          = &omap44xx_aess_hwmod,
 774         .clk            = "ocp_abe_iclk",
 775         .addr           = omap44xx_aess_addrs,
 776         .user           = OCP_USER_MPU,
 777 };
 778
 779 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 780         {
 781                 .pa_start       = 0x490f1000,
 782                 .pa_end         = 0x490f13ff,
 783                 .flags          = ADDR_TYPE_RT
 784         },
 785         { }
 786 };
 787
 788 /* l4_abe -> aess (dma) */
 789 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 790         .master         = &omap44xx_l4_abe_hwmod,
 791         .slave          = &omap44xx_aess_hwmod,
 792         .clk            = "ocp_abe_iclk",
 793         .addr           = omap44xx_aess_dma_addrs,
 794         .user           = OCP_USER_SDMA,
 795 };
 796
 797 /* aess slave ports */
 798 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 799         &omap44xx_l4_abe__aess,
 800         &omap44xx_l4_abe__aess_dma,
 801 };
 802
 803 static struct omap_hwmod omap44xx_aess_hwmod = {
 804         .name           = "aess",
 805         .class          = &omap44xx_aess_hwmod_class,
 806         .clkdm_name     = "abe_clkdm",
 807         .mpu_irqs       = omap44xx_aess_irqs,
 808         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 809         .main_clk       = "aess_fck",
 810         .prcm = {
 811                 .omap4 = {
 812                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 813                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 814                         .modulemode   = MODULEMODE_SWCTRL,
 815                 },
 816         },
 817         .slaves         = omap44xx_aess_slaves,
 818         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 819         .masters        = omap44xx_aess_masters,
 820         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 821 };
 822
 823 /*
 824  * 'bandgap' class
 825  * bangap reference for ldo regulators
 826  */
 827
 828 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 829         .name   = "bandgap",
 830 };
 831
 832 /* bandgap */
 833 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 834         { .role = "fclk", .clk = "bandgap_fclk" },
 835 };
 836
 837 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 838         .name           = "bandgap",
 839         .class          = &omap44xx_bandgap_hwmod_class,
 840         .clkdm_name     = "l4_wkup_clkdm",
 841         .prcm = {
 842                 .omap4 = {
 843                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
 844                 },
 845         },
 846         .opt_clks       = bandgap_opt_clks,
 847         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 848 };
 849
 850 /*
 851  * 'counter' class
 852  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 853  */
 854
 855 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 856         .rev_offs       = 0x0000,
 857         .sysc_offs      = 0x0004,
 858         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 860                            SIDLE_SMART_WKUP),
 861         .sysc_fields    = &omap_hwmod_sysc_type1,
 862 };
 863
 864 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 865         .name   = "counter",
 866         .sysc   = &omap44xx_counter_sysc,
 867 };
 868
 869 /* counter_32k */
 870 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 871 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 872         {
 873                 .pa_start       = 0x4a304000,
 874                 .pa_end         = 0x4a30401f,
 875                 .flags          = ADDR_TYPE_RT
 876         },
 877         { }
 878 };
 879
 880 /* l4_wkup -> counter_32k */
 881 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 882         .master         = &omap44xx_l4_wkup_hwmod,
 883         .slave          = &omap44xx_counter_32k_hwmod,
 884         .clk            = "l4_wkup_clk_mux_ck",
 885         .addr           = omap44xx_counter_32k_addrs,
 886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 887 };
 888
 889 /* counter_32k slave ports */
 890 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 891         &omap44xx_l4_wkup__counter_32k,
 892 };
 893
 894 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 895         .name           = "counter_32k",
 896         .class          = &omap44xx_counter_hwmod_class,
 897         .clkdm_name     = "l4_wkup_clkdm",
 898         .flags          = HWMOD_SWSUP_SIDLE,
 899         .main_clk       = "sys_32k_ck",
 900         .prcm = {
 901                 .omap4 = {
 902                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 903                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 904                 },
 905         },
 906         .slaves         = omap44xx_counter_32k_slaves,
 907         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 908 };
 909
 910 /*
 911  * 'dma' class
 912  * dma controller for data exchange between memory to memory (i.e. internal or
 913  * external memory) and gp peripherals to memory or memory to gp peripherals
 914  */
 915
 916 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 917         .rev_offs       = 0x0000,
 918         .sysc_offs      = 0x002c,
 919         .syss_offs      = 0x0028,
 920         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 921                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 922                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 923                            SYSS_HAS_RESET_STATUS),
 924         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 925                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 926         .sysc_fields    = &omap_hwmod_sysc_type1,
 927 };
 928
 929 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 930         .name   = "dma",
 931         .sysc   = &omap44xx_dma_sysc,
 932 };
 933
 934 /* dma dev_attr */
 935 static struct omap_dma_dev_attr dma_dev_attr = {
 936         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 937                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 938         .lch_count      = 32,
 939 };
 940
 941 /* dma_system */
 942 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 943         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 944         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 945         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 946         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 947         { .irq = -1 }
 948 };
 949
 950 /* dma_system master ports */
 951 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 952         &omap44xx_dma_system__l3_main_2,
 953 };
 954
 955 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 956         {
 957                 .pa_start       = 0x4a056000,
 958                 .pa_end         = 0x4a056fff,
 959                 .flags          = ADDR_TYPE_RT
 960         },
 961         { }
 962 };
 963
 964 /* l4_cfg -> dma_system */
 965 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 966         .master         = &omap44xx_l4_cfg_hwmod,
 967         .slave          = &omap44xx_dma_system_hwmod,
 968         .clk            = "l4_div_ck",
 969         .addr           = omap44xx_dma_system_addrs,
 970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 971 };
 972
 973 /* dma_system slave ports */
 974 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 975         &omap44xx_l4_cfg__dma_system,
 976 };
 977
 978 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 979         .name           = "dma_system",
 980         .class          = &omap44xx_dma_hwmod_class,
 981         .clkdm_name     = "l3_dma_clkdm",
 982         .mpu_irqs       = omap44xx_dma_system_irqs,
 983         .main_clk       = "l3_div_ck",
 984         .prcm = {
 985                 .omap4 = {
 986                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 987                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 988                 },
 989         },
 990         .dev_attr       = &dma_dev_attr,
 991         .slaves         = omap44xx_dma_system_slaves,
 992         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 993         .masters        = omap44xx_dma_system_masters,
 994         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 995 };
 996
 997 /*
 998  * 'dmic' class
 999  * digital microphone controller
1000  */
1001
1002 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1003         .rev_offs       = 0x0000,
1004         .sysc_offs      = 0x0010,
1005         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1006                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1007         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1008                            SIDLE_SMART_WKUP),
1009         .sysc_fields    = &omap_hwmod_sysc_type2,
1010 };
1011
1012 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1013         .name   = "dmic",
1014         .sysc   = &omap44xx_dmic_sysc,
1015 };
1016
1017 /* dmic */
1018 static struct omap_hwmod omap44xx_dmic_hwmod;
1019 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1020         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1021         { .irq = -1 }
1022 };
1023
1024 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1025         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1026         { .dma_req = -1 }
1027 };
1028
1029 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1030         {
1031                 .pa_start       = 0x4012e000,
1032                 .pa_end         = 0x4012e07f,
1033                 .flags          = ADDR_TYPE_RT
1034         },
1035         { }
1036 };
1037
1038 /* l4_abe -> dmic */
1039 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1040         .master         = &omap44xx_l4_abe_hwmod,
1041         .slave          = &omap44xx_dmic_hwmod,
1042         .clk            = "ocp_abe_iclk",
1043         .addr           = omap44xx_dmic_addrs,
1044         .user           = OCP_USER_MPU,
1045 };
1046
1047 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1048         {
1049                 .pa_start       = 0x4902e000,
1050                 .pa_end         = 0x4902e07f,
1051                 .flags          = ADDR_TYPE_RT
1052         },
1053         { }
1054 };
1055
1056 /* l4_abe -> dmic (dma) */
1057 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1058         .master         = &omap44xx_l4_abe_hwmod,
1059         .slave          = &omap44xx_dmic_hwmod,
1060         .clk            = "ocp_abe_iclk",
1061         .addr           = omap44xx_dmic_dma_addrs,
1062         .user           = OCP_USER_SDMA,
1063 };
1064
1065 /* dmic slave ports */
1066 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1067         &omap44xx_l4_abe__dmic,
1068         &omap44xx_l4_abe__dmic_dma,
1069 };
1070
1071 static struct omap_hwmod omap44xx_dmic_hwmod = {
1072         .name           = "dmic",
1073         .class          = &omap44xx_dmic_hwmod_class,
1074         .clkdm_name     = "abe_clkdm",
1075         .mpu_irqs       = omap44xx_dmic_irqs,
1076         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1077         .main_clk       = "dmic_fck",
1078         .prcm = {
1079                 .omap4 = {
1080                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1081                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1082                         .modulemode   = MODULEMODE_SWCTRL,
1083                 },
1084         },
1085         .slaves         = omap44xx_dmic_slaves,
1086         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1087 };
1088
1089 /*
1090  * 'dsp' class
1091  * dsp sub-system
1092  */
1093
1094 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1095         .name   = "dsp",
1096 };
1097
1098 /* dsp */
1099 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1100         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1101         { .irq = -1 }
1102 };
1103
1104 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1105         { .name = "mmu_cache", .rst_shift = 1 },
1106 };
1107
1108 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1109         { .name = "dsp", .rst_shift = 0 },
1110 };
1111
1112 /* dsp -> iva */
1113 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1114         .master         = &omap44xx_dsp_hwmod,
1115         .slave          = &omap44xx_iva_hwmod,
1116         .clk            = "dpll_iva_m5x2_ck",
1117 };
1118
1119 /* dsp master ports */
1120 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1121         &omap44xx_dsp__l3_main_1,
1122         &omap44xx_dsp__l4_abe,
1123         &omap44xx_dsp__iva,
1124 };
1125
1126 /* l4_cfg -> dsp */
1127 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1128         .master         = &omap44xx_l4_cfg_hwmod,
1129         .slave          = &omap44xx_dsp_hwmod,
1130         .clk            = "l4_div_ck",
1131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1132 };
1133
1134 /* dsp slave ports */
1135 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1136         &omap44xx_l4_cfg__dsp,
1137 };
1138
1139 /* Pseudo hwmod for reset control purpose only */
1140 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1141         .name           = "dsp_c0",
1142         .class          = &omap44xx_dsp_hwmod_class,
1143         .clkdm_name     = "tesla_clkdm",
1144         .flags          = HWMOD_INIT_NO_RESET,
1145         .rst_lines      = omap44xx_dsp_c0_resets,
1146         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1147         .prcm = {
1148                 .omap4 = {
1149                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1150                 },
1151         },
1152 };
1153
1154 static struct omap_hwmod omap44xx_dsp_hwmod = {
1155         .name           = "dsp",
1156         .class          = &omap44xx_dsp_hwmod_class,
1157         .clkdm_name     = "tesla_clkdm",
1158         .mpu_irqs       = omap44xx_dsp_irqs,
1159         .rst_lines      = omap44xx_dsp_resets,
1160         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1161         .main_clk       = "dsp_fck",
1162         .prcm = {
1163                 .omap4 = {
1164                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1165                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1166                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1167                         .modulemode   = MODULEMODE_HWCTRL,
1168                 },
1169         },
1170         .slaves         = omap44xx_dsp_slaves,
1171         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1172         .masters        = omap44xx_dsp_masters,
1173         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1174 };
1175
1176 /*
1177  * 'dss' class
1178  * display sub-system
1179  */
1180
1181 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1182         .rev_offs       = 0x0000,
1183         .syss_offs      = 0x0014,
1184         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1185 };
1186
1187 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1188         .name   = "dss",
1189         .sysc   = &omap44xx_dss_sysc,
1190 };
1191
1192 /* dss */
1193 /* dss master ports */
1194 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1195         &omap44xx_dss__l3_main_1,
1196 };
1197
1198 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1199         {
1200                 .pa_start       = 0x58000000,
1201                 .pa_end         = 0x5800007f,
1202                 .flags          = ADDR_TYPE_RT
1203         },
1204         { }
1205 };
1206
1207 /* l3_main_2 -> dss */
1208 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1209         .master         = &omap44xx_l3_main_2_hwmod,
1210         .slave          = &omap44xx_dss_hwmod,
1211         .clk            = "dss_fck",
1212         .addr           = omap44xx_dss_dma_addrs,
1213         .user           = OCP_USER_SDMA,
1214 };
1215
1216 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1217         {
1218                 .pa_start       = 0x48040000,
1219                 .pa_end         = 0x4804007f,
1220                 .flags          = ADDR_TYPE_RT
1221         },
1222         { }
1223 };
1224
1225 /* l4_per -> dss */
1226 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1227         .master         = &omap44xx_l4_per_hwmod,
1228         .slave          = &omap44xx_dss_hwmod,
1229         .clk            = "l4_div_ck",
1230         .addr           = omap44xx_dss_addrs,
1231         .user           = OCP_USER_MPU,
1232 };
1233
1234 /* dss slave ports */
1235 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1236         &omap44xx_l3_main_2__dss,
1237         &omap44xx_l4_per__dss,
1238 };
1239
1240 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1241         { .role = "sys_clk", .clk = "dss_sys_clk" },
1242         { .role = "tv_clk", .clk = "dss_tv_clk" },
1243         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1244 };
1245
1246 static struct omap_hwmod omap44xx_dss_hwmod = {
1247         .name           = "dss_core",
1248         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1249         .class          = &omap44xx_dss_hwmod_class,
1250         .clkdm_name     = "l3_dss_clkdm",
1251         .main_clk       = "dss_dss_clk",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1256                 },
1257         },
1258         .opt_clks       = dss_opt_clks,
1259         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1260         .slaves         = omap44xx_dss_slaves,
1261         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1262         .masters        = omap44xx_dss_masters,
1263         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1264 };
1265
1266 /*
1267  * 'dispc' class
1268  * display controller
1269  */
1270
1271 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1272         .rev_offs       = 0x0000,
1273         .sysc_offs      = 0x0010,
1274         .syss_offs      = 0x0014,
1275         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1276                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1277                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1278                            SYSS_HAS_RESET_STATUS),
1279         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1280                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1281         .sysc_fields    = &omap_hwmod_sysc_type1,
1282 };
1283
1284 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1285         .name   = "dispc",
1286         .sysc   = &omap44xx_dispc_sysc,
1287 };
1288
1289 /* dss_dispc */
1290 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1291 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1292         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1293         { .irq = -1 }
1294 };
1295
1296 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1297         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1298         { .dma_req = -1 }
1299 };
1300
1301 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1302         {
1303                 .pa_start       = 0x58001000,
1304                 .pa_end         = 0x58001fff,
1305                 .flags          = ADDR_TYPE_RT
1306         },
1307         { }
1308 };
1309
1310 /* l3_main_2 -> dss_dispc */
1311 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1312         .master         = &omap44xx_l3_main_2_hwmod,
1313         .slave          = &omap44xx_dss_dispc_hwmod,
1314         .clk            = "dss_fck",
1315         .addr           = omap44xx_dss_dispc_dma_addrs,
1316         .user           = OCP_USER_SDMA,
1317 };
1318
1319 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1320         {
1321                 .pa_start       = 0x48041000,
1322                 .pa_end         = 0x48041fff,
1323                 .flags          = ADDR_TYPE_RT
1324         },
1325         { }
1326 };
1327
1328 /* l4_per -> dss_dispc */
1329 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1330         .master         = &omap44xx_l4_per_hwmod,
1331         .slave          = &omap44xx_dss_dispc_hwmod,
1332         .clk            = "l4_div_ck",
1333         .addr           = omap44xx_dss_dispc_addrs,
1334         .user           = OCP_USER_MPU,
1335 };
1336
1337 /* dss_dispc slave ports */
1338 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1339         &omap44xx_l3_main_2__dss_dispc,
1340         &omap44xx_l4_per__dss_dispc,
1341 };
1342
1343 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1344         .name           = "dss_dispc",
1345         .class          = &omap44xx_dispc_hwmod_class,
1346         .clkdm_name     = "l3_dss_clkdm",
1347         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1348         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1349         .main_clk       = "dss_dss_clk",
1350         .prcm = {
1351                 .omap4 = {
1352                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1353                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1354                 },
1355         },
1356         .slaves         = omap44xx_dss_dispc_slaves,
1357         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1358 };
1359
1360 /*
1361  * 'dsi' class
1362  * display serial interface controller
1363  */
1364
1365 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1366         .rev_offs       = 0x0000,
1367         .sysc_offs      = 0x0010,
1368         .syss_offs      = 0x0014,
1369         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1370                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1371                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1372         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1373         .sysc_fields    = &omap_hwmod_sysc_type1,
1374 };
1375
1376 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1377         .name   = "dsi",
1378         .sysc   = &omap44xx_dsi_sysc,
1379 };
1380
1381 /* dss_dsi1 */
1382 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1383 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1384         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1385         { .irq = -1 }
1386 };
1387
1388 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1389         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1390         { .dma_req = -1 }
1391 };
1392
1393 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1394         {
1395                 .pa_start       = 0x58004000,
1396                 .pa_end         = 0x580041ff,
1397                 .flags          = ADDR_TYPE_RT
1398         },
1399         { }
1400 };
1401
1402 /* l3_main_2 -> dss_dsi1 */
1403 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1404         .master         = &omap44xx_l3_main_2_hwmod,
1405         .slave          = &omap44xx_dss_dsi1_hwmod,
1406         .clk            = "dss_fck",
1407         .addr           = omap44xx_dss_dsi1_dma_addrs,
1408         .user           = OCP_USER_SDMA,
1409 };
1410
1411 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1412         {
1413                 .pa_start       = 0x48044000,
1414                 .pa_end         = 0x480441ff,
1415                 .flags          = ADDR_TYPE_RT
1416         },
1417         { }
1418 };
1419
1420 /* l4_per -> dss_dsi1 */
1421 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1422         .master         = &omap44xx_l4_per_hwmod,
1423         .slave          = &omap44xx_dss_dsi1_hwmod,
1424         .clk            = "l4_div_ck",
1425         .addr           = omap44xx_dss_dsi1_addrs,
1426         .user           = OCP_USER_MPU,
1427 };
1428
1429 /* dss_dsi1 slave ports */
1430 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1431         &omap44xx_l3_main_2__dss_dsi1,
1432         &omap44xx_l4_per__dss_dsi1,
1433 };
1434
1435 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1436         { .role = "sys_clk", .clk = "dss_sys_clk" },
1437 };
1438
1439 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1440         .name           = "dss_dsi1",
1441         .class          = &omap44xx_dsi_hwmod_class,
1442         .clkdm_name     = "l3_dss_clkdm",
1443         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1444         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1445         .main_clk       = "dss_dss_clk",
1446         .prcm = {
1447                 .omap4 = {
1448                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1449                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1450                 },
1451         },
1452         .opt_clks       = dss_dsi1_opt_clks,
1453         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1454         .slaves         = omap44xx_dss_dsi1_slaves,
1455         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1456 };
1457
1458 /* dss_dsi2 */
1459 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1460 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1461         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1462         { .irq = -1 }
1463 };
1464
1465 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1466         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1467         { .dma_req = -1 }
1468 };
1469
1470 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1471         {
1472                 .pa_start       = 0x58005000,
1473                 .pa_end         = 0x580051ff,
1474                 .flags          = ADDR_TYPE_RT
1475         },
1476         { }
1477 };
1478
1479 /* l3_main_2 -> dss_dsi2 */
1480 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1481         .master         = &omap44xx_l3_main_2_hwmod,
1482         .slave          = &omap44xx_dss_dsi2_hwmod,
1483         .clk            = "dss_fck",
1484         .addr           = omap44xx_dss_dsi2_dma_addrs,
1485         .user           = OCP_USER_SDMA,
1486 };
1487
1488 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1489         {
1490                 .pa_start       = 0x48045000,
1491                 .pa_end         = 0x480451ff,
1492                 .flags          = ADDR_TYPE_RT
1493         },
1494         { }
1495 };
1496
1497 /* l4_per -> dss_dsi2 */
1498 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1499         .master         = &omap44xx_l4_per_hwmod,
1500         .slave          = &omap44xx_dss_dsi2_hwmod,
1501         .clk            = "l4_div_ck",
1502         .addr           = omap44xx_dss_dsi2_addrs,
1503         .user           = OCP_USER_MPU,
1504 };
1505
1506 /* dss_dsi2 slave ports */
1507 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1508         &omap44xx_l3_main_2__dss_dsi2,
1509         &omap44xx_l4_per__dss_dsi2,
1510 };
1511
1512 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1513         { .role = "sys_clk", .clk = "dss_sys_clk" },
1514 };
1515
1516 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1517         .name           = "dss_dsi2",
1518         .class          = &omap44xx_dsi_hwmod_class,
1519         .clkdm_name     = "l3_dss_clkdm",
1520         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1521         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1522         .main_clk       = "dss_dss_clk",
1523         .prcm = {
1524                 .omap4 = {
1525                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1526                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1527                 },
1528         },
1529         .opt_clks       = dss_dsi2_opt_clks,
1530         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1531         .slaves         = omap44xx_dss_dsi2_slaves,
1532         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1533 };
1534
1535 /*
1536  * 'hdmi' class
1537  * hdmi controller
1538  */
1539
1540 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1541         .rev_offs       = 0x0000,
1542         .sysc_offs      = 0x0010,
1543         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1544                            SYSC_HAS_SOFTRESET),
1545         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1546                            SIDLE_SMART_WKUP),
1547         .sysc_fields    = &omap_hwmod_sysc_type2,
1548 };
1549
1550 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1551         .name   = "hdmi",
1552         .sysc   = &omap44xx_hdmi_sysc,
1553 };
1554
1555 /* dss_hdmi */
1556 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1557 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1558         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1559         { .irq = -1 }
1560 };
1561
1562 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1563         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1564         { .dma_req = -1 }
1565 };
1566
1567 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1568         {
1569                 .pa_start       = 0x58006000,
1570                 .pa_end         = 0x58006fff,
1571                 .flags          = ADDR_TYPE_RT
1572         },
1573         { }
1574 };
1575
1576 /* l3_main_2 -> dss_hdmi */
1577 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1578         .master         = &omap44xx_l3_main_2_hwmod,
1579         .slave          = &omap44xx_dss_hdmi_hwmod,
1580         .clk            = "dss_fck",
1581         .addr           = omap44xx_dss_hdmi_dma_addrs,
1582         .user           = OCP_USER_SDMA,
1583 };
1584
1585 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1586         {
1587                 .pa_start       = 0x48046000,
1588                 .pa_end         = 0x48046fff,
1589                 .flags          = ADDR_TYPE_RT
1590         },
1591         { }
1592 };
1593
1594 /* l4_per -> dss_hdmi */
1595 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1596         .master         = &omap44xx_l4_per_hwmod,
1597         .slave          = &omap44xx_dss_hdmi_hwmod,
1598         .clk            = "l4_div_ck",
1599         .addr           = omap44xx_dss_hdmi_addrs,
1600         .user           = OCP_USER_MPU,
1601 };
1602
1603 /* dss_hdmi slave ports */
1604 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1605         &omap44xx_l3_main_2__dss_hdmi,
1606         &omap44xx_l4_per__dss_hdmi,
1607 };
1608
1609 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1610         { .role = "sys_clk", .clk = "dss_sys_clk" },
1611 };
1612
1613 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1614         .name           = "dss_hdmi",
1615         .class          = &omap44xx_hdmi_hwmod_class,
1616         .clkdm_name     = "l3_dss_clkdm",
1617         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1618         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1619         .main_clk       = "dss_48mhz_clk",
1620         .prcm = {
1621                 .omap4 = {
1622                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1623                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1624                 },
1625         },
1626         .opt_clks       = dss_hdmi_opt_clks,
1627         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1628         .slaves         = omap44xx_dss_hdmi_slaves,
1629         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1630 };
1631
1632 /*
1633  * 'rfbi' class
1634  * remote frame buffer interface
1635  */
1636
1637 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1638         .rev_offs       = 0x0000,
1639         .sysc_offs      = 0x0010,
1640         .syss_offs      = 0x0014,
1641         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1642                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1643         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1644         .sysc_fields    = &omap_hwmod_sysc_type1,
1645 };
1646
1647 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1648         .name   = "rfbi",
1649         .sysc   = &omap44xx_rfbi_sysc,
1650 };
1651
1652 /* dss_rfbi */
1653 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1654 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1655         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1656         { .dma_req = -1 }
1657 };
1658
1659 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1660         {
1661                 .pa_start       = 0x58002000,
1662                 .pa_end         = 0x580020ff,
1663                 .flags          = ADDR_TYPE_RT
1664         },
1665         { }
1666 };
1667
1668 /* l3_main_2 -> dss_rfbi */
1669 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1670         .master         = &omap44xx_l3_main_2_hwmod,
1671         .slave          = &omap44xx_dss_rfbi_hwmod,
1672         .clk            = "dss_fck",
1673         .addr           = omap44xx_dss_rfbi_dma_addrs,
1674         .user           = OCP_USER_SDMA,
1675 };
1676
1677 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1678         {
1679                 .pa_start       = 0x48042000,
1680                 .pa_end         = 0x480420ff,
1681                 .flags          = ADDR_TYPE_RT
1682         },
1683         { }
1684 };
1685
1686 /* l4_per -> dss_rfbi */
1687 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1688         .master         = &omap44xx_l4_per_hwmod,
1689         .slave          = &omap44xx_dss_rfbi_hwmod,
1690         .clk            = "l4_div_ck",
1691         .addr           = omap44xx_dss_rfbi_addrs,
1692         .user           = OCP_USER_MPU,
1693 };
1694
1695 /* dss_rfbi slave ports */
1696 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1697         &omap44xx_l3_main_2__dss_rfbi,
1698         &omap44xx_l4_per__dss_rfbi,
1699 };
1700
1701 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1702         { .role = "ick", .clk = "dss_fck" },
1703 };
1704
1705 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1706         .name           = "dss_rfbi",
1707         .class          = &omap44xx_rfbi_hwmod_class,
1708         .clkdm_name     = "l3_dss_clkdm",
1709         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1710         .main_clk       = "dss_dss_clk",
1711         .prcm = {
1712                 .omap4 = {
1713                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1714                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1715                 },
1716         },
1717         .opt_clks       = dss_rfbi_opt_clks,
1718         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1719         .slaves         = omap44xx_dss_rfbi_slaves,
1720         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1721 };
1722
1723 /*
1724  * 'venc' class
1725  * video encoder
1726  */
1727
1728 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1729         .name   = "venc",
1730 };
1731
1732 /* dss_venc */
1733 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1734 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1735         {
1736                 .pa_start       = 0x58003000,
1737                 .pa_end         = 0x580030ff,
1738                 .flags          = ADDR_TYPE_RT
1739         },
1740         { }
1741 };
1742
1743 /* l3_main_2 -> dss_venc */
1744 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1745         .master         = &omap44xx_l3_main_2_hwmod,
1746         .slave          = &omap44xx_dss_venc_hwmod,
1747         .clk            = "dss_fck",
1748         .addr           = omap44xx_dss_venc_dma_addrs,
1749         .user           = OCP_USER_SDMA,
1750 };
1751
1752 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1753         {
1754                 .pa_start       = 0x48043000,
1755                 .pa_end         = 0x480430ff,
1756                 .flags          = ADDR_TYPE_RT
1757         },
1758         { }
1759 };
1760
1761 /* l4_per -> dss_venc */
1762 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1763         .master         = &omap44xx_l4_per_hwmod,
1764         .slave          = &omap44xx_dss_venc_hwmod,
1765         .clk            = "l4_div_ck",
1766         .addr           = omap44xx_dss_venc_addrs,
1767         .user           = OCP_USER_MPU,
1768 };
1769
1770 /* dss_venc slave ports */
1771 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1772         &omap44xx_l3_main_2__dss_venc,
1773         &omap44xx_l4_per__dss_venc,
1774 };
1775
1776 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1777         .name           = "dss_venc",
1778         .class          = &omap44xx_venc_hwmod_class,
1779         .clkdm_name     = "l3_dss_clkdm",
1780         .main_clk       = "dss_tv_clk",
1781         .prcm = {
1782                 .omap4 = {
1783                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1784                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1785                 },
1786         },
1787         .slaves         = omap44xx_dss_venc_slaves,
1788         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1789 };
1790
1791 /*
1792  * 'gpio' class
1793  * general purpose io module
1794  */
1795
1796 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1797         .rev_offs       = 0x0000,
1798         .sysc_offs      = 0x0010,
1799         .syss_offs      = 0x0114,
1800         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1801                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1802                            SYSS_HAS_RESET_STATUS),
1803         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1804                            SIDLE_SMART_WKUP),
1805         .sysc_fields    = &omap_hwmod_sysc_type1,
1806 };
1807
1808 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1809         .name   = "gpio",
1810         .sysc   = &omap44xx_gpio_sysc,
1811         .rev    = 2,
1812 };
1813
1814 /* gpio dev_attr */
1815 static struct omap_gpio_dev_attr gpio_dev_attr = {
1816         .bank_width     = 32,
1817         .dbck_flag      = true,
1818 };
1819
1820 /* gpio1 */
1821 static struct omap_hwmod omap44xx_gpio1_hwmod;
1822 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1823         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1824         { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1828         {
1829                 .pa_start       = 0x4a310000,
1830                 .pa_end         = 0x4a3101ff,
1831                 .flags          = ADDR_TYPE_RT
1832         },
1833         { }
1834 };
1835
1836 /* l4_wkup -> gpio1 */
1837 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1838         .master         = &omap44xx_l4_wkup_hwmod,
1839         .slave          = &omap44xx_gpio1_hwmod,
1840         .clk            = "l4_wkup_clk_mux_ck",
1841         .addr           = omap44xx_gpio1_addrs,
1842         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1843 };
1844
1845 /* gpio1 slave ports */
1846 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1847         &omap44xx_l4_wkup__gpio1,
1848 };
1849
1850 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1851         { .role = "dbclk", .clk = "gpio1_dbclk" },
1852 };
1853
1854 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1855         .name           = "gpio1",
1856         .class          = &omap44xx_gpio_hwmod_class,
1857         .clkdm_name     = "l4_wkup_clkdm",
1858         .mpu_irqs       = omap44xx_gpio1_irqs,
1859         .main_clk       = "gpio1_ick",
1860         .prcm = {
1861                 .omap4 = {
1862                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1863                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1864                         .modulemode   = MODULEMODE_HWCTRL,
1865                 },
1866         },
1867         .opt_clks       = gpio1_opt_clks,
1868         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1869         .dev_attr       = &gpio_dev_attr,
1870         .slaves         = omap44xx_gpio1_slaves,
1871         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1872 };
1873
1874 /* gpio2 */
1875 static struct omap_hwmod omap44xx_gpio2_hwmod;
1876 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1877         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1878         { .irq = -1 }
1879 };
1880
1881 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1882         {
1883                 .pa_start       = 0x48055000,
1884                 .pa_end         = 0x480551ff,
1885                 .flags          = ADDR_TYPE_RT
1886         },
1887         { }
1888 };
1889
1890 /* l4_per -> gpio2 */
1891 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1892         .master         = &omap44xx_l4_per_hwmod,
1893         .slave          = &omap44xx_gpio2_hwmod,
1894         .clk            = "l4_div_ck",
1895         .addr           = omap44xx_gpio2_addrs,
1896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1897 };
1898
1899 /* gpio2 slave ports */
1900 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1901         &omap44xx_l4_per__gpio2,
1902 };
1903
1904 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1905         { .role = "dbclk", .clk = "gpio2_dbclk" },
1906 };
1907
1908 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1909         .name           = "gpio2",
1910         .class          = &omap44xx_gpio_hwmod_class,
1911         .clkdm_name     = "l4_per_clkdm",
1912         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1913         .mpu_irqs       = omap44xx_gpio2_irqs,
1914         .main_clk       = "gpio2_ick",
1915         .prcm = {
1916                 .omap4 = {
1917                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1918                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1919                         .modulemode   = MODULEMODE_HWCTRL,
1920                 },
1921         },
1922         .opt_clks       = gpio2_opt_clks,
1923         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1924         .dev_attr       = &gpio_dev_attr,
1925         .slaves         = omap44xx_gpio2_slaves,
1926         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1927 };
1928
1929 /* gpio3 */
1930 static struct omap_hwmod omap44xx_gpio3_hwmod;
1931 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1932         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1933         { .irq = -1 }
1934 };
1935
1936 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1937         {
1938                 .pa_start       = 0x48057000,
1939                 .pa_end         = 0x480571ff,
1940                 .flags          = ADDR_TYPE_RT
1941         },
1942         { }
1943 };
1944
1945 /* l4_per -> gpio3 */
1946 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1947         .master         = &omap44xx_l4_per_hwmod,
1948         .slave          = &omap44xx_gpio3_hwmod,
1949         .clk            = "l4_div_ck",
1950         .addr           = omap44xx_gpio3_addrs,
1951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1952 };
1953
1954 /* gpio3 slave ports */
1955 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1956         &omap44xx_l4_per__gpio3,
1957 };
1958
1959 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1960         { .role = "dbclk", .clk = "gpio3_dbclk" },
1961 };
1962
1963 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1964         .name           = "gpio3",
1965         .class          = &omap44xx_gpio_hwmod_class,
1966         .clkdm_name     = "l4_per_clkdm",
1967         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1968         .mpu_irqs       = omap44xx_gpio3_irqs,
1969         .main_clk       = "gpio3_ick",
1970         .prcm = {
1971                 .omap4 = {
1972                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1973                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1974                         .modulemode   = MODULEMODE_HWCTRL,
1975                 },
1976         },
1977         .opt_clks       = gpio3_opt_clks,
1978         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1979         .dev_attr       = &gpio_dev_attr,
1980         .slaves         = omap44xx_gpio3_slaves,
1981         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1982 };
1983
1984 /* gpio4 */
1985 static struct omap_hwmod omap44xx_gpio4_hwmod;
1986 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1987         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1988         { .irq = -1 }
1989 };
1990
1991 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1992         {
1993                 .pa_start       = 0x48059000,
1994                 .pa_end         = 0x480591ff,
1995                 .flags          = ADDR_TYPE_RT
1996         },
1997         { }
1998 };
1999
2000 /* l4_per -> gpio4 */
2001 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2002         .master         = &omap44xx_l4_per_hwmod,
2003         .slave          = &omap44xx_gpio4_hwmod,
2004         .clk            = "l4_div_ck",
2005         .addr           = omap44xx_gpio4_addrs,
2006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2007 };
2008
2009 /* gpio4 slave ports */
2010 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2011         &omap44xx_l4_per__gpio4,
2012 };
2013
2014 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2015         { .role = "dbclk", .clk = "gpio4_dbclk" },
2016 };
2017
2018 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2019         .name           = "gpio4",
2020         .class          = &omap44xx_gpio_hwmod_class,
2021         .clkdm_name     = "l4_per_clkdm",
2022         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2023         .mpu_irqs       = omap44xx_gpio4_irqs,
2024         .main_clk       = "gpio4_ick",
2025         .prcm = {
2026                 .omap4 = {
2027                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2028                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2029                         .modulemode   = MODULEMODE_HWCTRL,
2030                 },
2031         },
2032         .opt_clks       = gpio4_opt_clks,
2033         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2034         .dev_attr       = &gpio_dev_attr,
2035         .slaves         = omap44xx_gpio4_slaves,
2036         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2037 };
2038
2039 /* gpio5 */
2040 static struct omap_hwmod omap44xx_gpio5_hwmod;
2041 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2042         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2043         { .irq = -1 }
2044 };
2045
2046 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2047         {
2048                 .pa_start       = 0x4805b000,
2049                 .pa_end         = 0x4805b1ff,
2050                 .flags          = ADDR_TYPE_RT
2051         },
2052         { }
2053 };
2054
2055 /* l4_per -> gpio5 */
2056 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2057         .master         = &omap44xx_l4_per_hwmod,
2058         .slave          = &omap44xx_gpio5_hwmod,
2059         .clk            = "l4_div_ck",
2060         .addr           = omap44xx_gpio5_addrs,
2061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2062 };
2063
2064 /* gpio5 slave ports */
2065 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2066         &omap44xx_l4_per__gpio5,
2067 };
2068
2069 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2070         { .role = "dbclk", .clk = "gpio5_dbclk" },
2071 };
2072
2073 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2074         .name           = "gpio5",
2075         .class          = &omap44xx_gpio_hwmod_class,
2076         .clkdm_name     = "l4_per_clkdm",
2077         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2078         .mpu_irqs       = omap44xx_gpio5_irqs,
2079         .main_clk       = "gpio5_ick",
2080         .prcm = {
2081                 .omap4 = {
2082                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2083                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2084                         .modulemode   = MODULEMODE_HWCTRL,
2085                 },
2086         },
2087         .opt_clks       = gpio5_opt_clks,
2088         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2089         .dev_attr       = &gpio_dev_attr,
2090         .slaves         = omap44xx_gpio5_slaves,
2091         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2092 };
2093
2094 /* gpio6 */
2095 static struct omap_hwmod omap44xx_gpio6_hwmod;
2096 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2097         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2098         { .irq = -1 }
2099 };
2100
2101 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2102         {
2103                 .pa_start       = 0x4805d000,
2104                 .pa_end         = 0x4805d1ff,
2105                 .flags          = ADDR_TYPE_RT
2106         },
2107         { }
2108 };
2109
2110 /* l4_per -> gpio6 */
2111 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2112         .master         = &omap44xx_l4_per_hwmod,
2113         .slave          = &omap44xx_gpio6_hwmod,
2114         .clk            = "l4_div_ck",
2115         .addr           = omap44xx_gpio6_addrs,
2116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2117 };
2118
2119 /* gpio6 slave ports */
2120 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2121         &omap44xx_l4_per__gpio6,
2122 };
2123
2124 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2125         { .role = "dbclk", .clk = "gpio6_dbclk" },
2126 };
2127
2128 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2129         .name           = "gpio6",
2130         .class          = &omap44xx_gpio_hwmod_class,
2131         .clkdm_name     = "l4_per_clkdm",
2132         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2133         .mpu_irqs       = omap44xx_gpio6_irqs,
2134         .main_clk       = "gpio6_ick",
2135         .prcm = {
2136                 .omap4 = {
2137                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2138                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2139                         .modulemode   = MODULEMODE_HWCTRL,
2140                 },
2141         },
2142         .opt_clks       = gpio6_opt_clks,
2143         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2144         .dev_attr       = &gpio_dev_attr,
2145         .slaves         = omap44xx_gpio6_slaves,
2146         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2147 };
2148
2149 /*
2150  * 'hsi' class
2151  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2152  * serial if)
2153  */
2154
2155 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2156         .rev_offs       = 0x0000,
2157         .sysc_offs      = 0x0010,
2158         .syss_offs      = 0x0014,
2159         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2160                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2161                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2162         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2163                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2164                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2165         .sysc_fields    = &omap_hwmod_sysc_type1,
2166 };
2167
2168 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2169         .name   = "hsi",
2170         .sysc   = &omap44xx_hsi_sysc,
2171 };
2172
2173 /* hsi */
2174 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2175         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2176         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2177         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2178         { .irq = -1 }
2179 };
2180
2181 /* hsi master ports */
2182 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2183         &omap44xx_hsi__l3_main_2,
2184 };
2185
2186 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2187         {
2188                 .pa_start       = 0x4a058000,
2189                 .pa_end         = 0x4a05bfff,
2190                 .flags          = ADDR_TYPE_RT
2191         },
2192         { }
2193 };
2194
2195 /* l4_cfg -> hsi */
2196 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2197         .master         = &omap44xx_l4_cfg_hwmod,
2198         .slave          = &omap44xx_hsi_hwmod,
2199         .clk            = "l4_div_ck",
2200         .addr           = omap44xx_hsi_addrs,
2201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2202 };
2203
2204 /* hsi slave ports */
2205 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2206         &omap44xx_l4_cfg__hsi,
2207 };
2208
2209 static struct omap_hwmod omap44xx_hsi_hwmod = {
2210         .name           = "hsi",
2211         .class          = &omap44xx_hsi_hwmod_class,
2212         .clkdm_name     = "l3_init_clkdm",
2213         .mpu_irqs       = omap44xx_hsi_irqs,
2214         .main_clk       = "hsi_fck",
2215         .prcm = {
2216                 .omap4 = {
2217                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2218                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2219                         .modulemode   = MODULEMODE_HWCTRL,
2220                 },
2221         },
2222         .slaves         = omap44xx_hsi_slaves,
2223         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2224         .masters        = omap44xx_hsi_masters,
2225         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2226 };
2227
2228 /*
2229  * 'i2c' class
2230  * multimaster high-speed i2c controller
2231  */
2232
2233 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2234         .sysc_offs      = 0x0010,
2235         .syss_offs      = 0x0090,
2236         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2237                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2238                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2239         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2240                            SIDLE_SMART_WKUP),
2241         .sysc_fields    = &omap_hwmod_sysc_type1,
2242 };
2243
2244 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2245         .name   = "i2c",
2246         .sysc   = &omap44xx_i2c_sysc,
2247         .rev    = OMAP_I2C_IP_VERSION_2,
2248         .reset  = &omap_i2c_reset,
2249 };
2250
2251 static struct omap_i2c_dev_attr i2c_dev_attr = {
2252         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2253 };
2254
2255 /* i2c1 */
2256 static struct omap_hwmod omap44xx_i2c1_hwmod;
2257 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2258         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2259         { .irq = -1 }
2260 };
2261
2262 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2263         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2264         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2265         { .dma_req = -1 }
2266 };
2267
2268 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2269         {
2270                 .pa_start       = 0x48070000,
2271                 .pa_end         = 0x480700ff,
2272                 .flags          = ADDR_TYPE_RT
2273         },
2274         { }
2275 };
2276
2277 /* l4_per -> i2c1 */
2278 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2279         .master         = &omap44xx_l4_per_hwmod,
2280         .slave          = &omap44xx_i2c1_hwmod,
2281         .clk            = "l4_div_ck",
2282         .addr           = omap44xx_i2c1_addrs,
2283         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2284 };
2285
2286 /* i2c1 slave ports */
2287 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2288         &omap44xx_l4_per__i2c1,
2289 };
2290
2291 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2292         .name           = "i2c1",
2293         .class          = &omap44xx_i2c_hwmod_class,
2294         .clkdm_name     = "l4_per_clkdm",
2295         .flags          = HWMOD_16BIT_REG,
2296         .mpu_irqs       = omap44xx_i2c1_irqs,
2297         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2298         .main_clk       = "i2c1_fck",
2299         .prcm = {
2300                 .omap4 = {
2301                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2302                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2303                         .modulemode   = MODULEMODE_SWCTRL,
2304                 },
2305         },
2306         .slaves         = omap44xx_i2c1_slaves,
2307         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2308         .dev_attr       = &i2c_dev_attr,
2309 };
2310
2311 /* i2c2 */
2312 static struct omap_hwmod omap44xx_i2c2_hwmod;
2313 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2314         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2315         { .irq = -1 }
2316 };
2317
2318 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2319         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2320         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2321         { .dma_req = -1 }
2322 };
2323
2324 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2325         {
2326                 .pa_start       = 0x48072000,
2327                 .pa_end         = 0x480720ff,
2328                 .flags          = ADDR_TYPE_RT
2329         },
2330         { }
2331 };
2332
2333 /* l4_per -> i2c2 */
2334 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2335         .master         = &omap44xx_l4_per_hwmod,
2336         .slave          = &omap44xx_i2c2_hwmod,
2337         .clk            = "l4_div_ck",
2338         .addr           = omap44xx_i2c2_addrs,
2339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2340 };
2341
2342 /* i2c2 slave ports */
2343 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2344         &omap44xx_l4_per__i2c2,
2345 };
2346
2347 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2348         .name           = "i2c2",
2349         .class          = &omap44xx_i2c_hwmod_class,
2350         .clkdm_name     = "l4_per_clkdm",
2351         .flags          = HWMOD_16BIT_REG,
2352         .mpu_irqs       = omap44xx_i2c2_irqs,
2353         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2354         .main_clk       = "i2c2_fck",
2355         .prcm = {
2356                 .omap4 = {
2357                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2358                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2359                         .modulemode   = MODULEMODE_SWCTRL,
2360                 },
2361         },
2362         .slaves         = omap44xx_i2c2_slaves,
2363         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2364         .dev_attr       = &i2c_dev_attr,
2365 };
2366
2367 /* i2c3 */
2368 static struct omap_hwmod omap44xx_i2c3_hwmod;
2369 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2370         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2371         { .irq = -1 }
2372 };
2373
2374 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2375         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2376         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2377         { .dma_req = -1 }
2378 };
2379
2380 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2381         {
2382                 .pa_start       = 0x48060000,
2383                 .pa_end         = 0x480600ff,
2384                 .flags          = ADDR_TYPE_RT
2385         },
2386         { }
2387 };
2388
2389 /* l4_per -> i2c3 */
2390 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2391         .master         = &omap44xx_l4_per_hwmod,
2392         .slave          = &omap44xx_i2c3_hwmod,
2393         .clk            = "l4_div_ck",
2394         .addr           = omap44xx_i2c3_addrs,
2395         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2396 };
2397
2398 /* i2c3 slave ports */
2399 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2400         &omap44xx_l4_per__i2c3,
2401 };
2402
2403 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2404         .name           = "i2c3",
2405         .class          = &omap44xx_i2c_hwmod_class,
2406         .clkdm_name     = "l4_per_clkdm",
2407         .flags          = HWMOD_16BIT_REG,
2408         .mpu_irqs       = omap44xx_i2c3_irqs,
2409         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2410         .main_clk       = "i2c3_fck",
2411         .prcm = {
2412                 .omap4 = {
2413                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2414                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2415                         .modulemode   = MODULEMODE_SWCTRL,
2416                 },
2417         },
2418         .slaves         = omap44xx_i2c3_slaves,
2419         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2420         .dev_attr       = &i2c_dev_attr,
2421 };
2422
2423 /* i2c4 */
2424 static struct omap_hwmod omap44xx_i2c4_hwmod;
2425 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2426         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2427         { .irq = -1 }
2428 };
2429
2430 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2431         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2432         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2433         { .dma_req = -1 }
2434 };
2435
2436 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2437         {
2438                 .pa_start       = 0x48350000,
2439                 .pa_end         = 0x483500ff,
2440                 .flags          = ADDR_TYPE_RT
2441         },
2442         { }
2443 };
2444
2445 /* l4_per -> i2c4 */
2446 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2447         .master         = &omap44xx_l4_per_hwmod,
2448         .slave          = &omap44xx_i2c4_hwmod,
2449         .clk            = "l4_div_ck",
2450         .addr           = omap44xx_i2c4_addrs,
2451         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2452 };
2453
2454 /* i2c4 slave ports */
2455 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2456         &omap44xx_l4_per__i2c4,
2457 };
2458
2459 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2460         .name           = "i2c4",
2461         .class          = &omap44xx_i2c_hwmod_class,
2462         .clkdm_name     = "l4_per_clkdm",
2463         .flags          = HWMOD_16BIT_REG,
2464         .mpu_irqs       = omap44xx_i2c4_irqs,
2465         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2466         .main_clk       = "i2c4_fck",
2467         .prcm = {
2468                 .omap4 = {
2469                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2470                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2471                         .modulemode   = MODULEMODE_SWCTRL,
2472                 },
2473         },
2474         .slaves         = omap44xx_i2c4_slaves,
2475         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2476         .dev_attr       = &i2c_dev_attr,
2477 };
2478
2479 /*
2480  * 'ipu' class
2481  * imaging processor unit
2482  */
2483
2484 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2485         .name   = "ipu",
2486 };
2487
2488 /* ipu */
2489 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2490         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2491         { .irq = -1 }
2492 };
2493
2494 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2495         { .name = "cpu0", .rst_shift = 0 },
2496 };
2497
2498 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2499         { .name = "cpu1", .rst_shift = 1 },
2500 };
2501
2502 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2503         { .name = "mmu_cache", .rst_shift = 2 },
2504 };
2505
2506 /* ipu master ports */
2507 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2508         &omap44xx_ipu__l3_main_2,
2509 };
2510
2511 /* l3_main_2 -> ipu */
2512 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2513         .master         = &omap44xx_l3_main_2_hwmod,
2514         .slave          = &omap44xx_ipu_hwmod,
2515         .clk            = "l3_div_ck",
2516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2517 };
2518
2519 /* ipu slave ports */
2520 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2521         &omap44xx_l3_main_2__ipu,
2522 };
2523
2524 /* Pseudo hwmod for reset control purpose only */
2525 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2526         .name           = "ipu_c0",
2527         .class          = &omap44xx_ipu_hwmod_class,
2528         .clkdm_name     = "ducati_clkdm",
2529         .flags          = HWMOD_INIT_NO_RESET,
2530         .rst_lines      = omap44xx_ipu_c0_resets,
2531         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2532         .prcm = {
2533                 .omap4 = {
2534                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2535                 },
2536         },
2537 };
2538
2539 /* Pseudo hwmod for reset control purpose only */
2540 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2541         .name           = "ipu_c1",
2542         .class          = &omap44xx_ipu_hwmod_class,
2543         .clkdm_name     = "ducati_clkdm",
2544         .flags          = HWMOD_INIT_NO_RESET,
2545         .rst_lines      = omap44xx_ipu_c1_resets,
2546         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2547         .prcm = {
2548                 .omap4 = {
2549                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2550                 },
2551         },
2552 };
2553
2554 static struct omap_hwmod omap44xx_ipu_hwmod = {
2555         .name           = "ipu",
2556         .class          = &omap44xx_ipu_hwmod_class,
2557         .clkdm_name     = "ducati_clkdm",
2558         .mpu_irqs       = omap44xx_ipu_irqs,
2559         .rst_lines      = omap44xx_ipu_resets,
2560         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2561         .main_clk       = "ipu_fck",
2562         .prcm = {
2563                 .omap4 = {
2564                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2565                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2566                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2567                         .modulemode   = MODULEMODE_HWCTRL,
2568                 },
2569         },
2570         .slaves         = omap44xx_ipu_slaves,
2571         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2572         .masters        = omap44xx_ipu_masters,
2573         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2574 };
2575
2576 /*
2577  * 'iss' class
2578  * external images sensor pixel data processor
2579  */
2580
2581 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2582         .rev_offs       = 0x0000,
2583         .sysc_offs      = 0x0010,
2584         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2585                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2586         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2587                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2588                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2589         .sysc_fields    = &omap_hwmod_sysc_type2,
2590 };
2591
2592 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2593         .name   = "iss",
2594         .sysc   = &omap44xx_iss_sysc,
2595 };
2596
2597 /* iss */
2598 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2599         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2600         { .irq = -1 }
2601 };
2602
2603 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2604         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2605         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2606         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2607         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2608         { .dma_req = -1 }
2609 };
2610
2611 /* iss master ports */
2612 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2613         &omap44xx_iss__l3_main_2,
2614 };
2615
2616 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2617         {
2618                 .pa_start       = 0x52000000,
2619                 .pa_end         = 0x520000ff,
2620                 .flags          = ADDR_TYPE_RT
2621         },
2622         { }
2623 };
2624
2625 /* l3_main_2 -> iss */
2626 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2627         .master         = &omap44xx_l3_main_2_hwmod,
2628         .slave          = &omap44xx_iss_hwmod,
2629         .clk            = "l3_div_ck",
2630         .addr           = omap44xx_iss_addrs,
2631         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2632 };
2633
2634 /* iss slave ports */
2635 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2636         &omap44xx_l3_main_2__iss,
2637 };
2638
2639 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2640         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2641 };
2642
2643 static struct omap_hwmod omap44xx_iss_hwmod = {
2644         .name           = "iss",
2645         .class          = &omap44xx_iss_hwmod_class,
2646         .clkdm_name     = "iss_clkdm",
2647         .mpu_irqs       = omap44xx_iss_irqs,
2648         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2649         .main_clk       = "iss_fck",
2650         .prcm = {
2651                 .omap4 = {
2652                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2653                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2654                         .modulemode   = MODULEMODE_SWCTRL,
2655                 },
2656         },
2657         .opt_clks       = iss_opt_clks,
2658         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2659         .slaves         = omap44xx_iss_slaves,
2660         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2661         .masters        = omap44xx_iss_masters,
2662         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2663 };
2664
2665 /*
2666  * 'iva' class
2667  * multi-standard video encoder/decoder hardware accelerator
2668  */
2669
2670 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2671         .name   = "iva",
2672 };
2673
2674 /* iva */
2675 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2676         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2677         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2678         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2679         { .irq = -1 }
2680 };
2681
2682 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2683         { .name = "logic", .rst_shift = 2 },
2684 };
2685
2686 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2687         { .name = "seq0", .rst_shift = 0 },
2688 };
2689
2690 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2691         { .name = "seq1", .rst_shift = 1 },
2692 };
2693
2694 /* iva master ports */
2695 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2696         &omap44xx_iva__l3_main_2,
2697         &omap44xx_iva__l3_instr,
2698 };
2699
2700 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2701         {
2702                 .pa_start       = 0x5a000000,
2703                 .pa_end         = 0x5a07ffff,
2704                 .flags          = ADDR_TYPE_RT
2705         },
2706         { }
2707 };
2708
2709 /* l3_main_2 -> iva */
2710 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2711         .master         = &omap44xx_l3_main_2_hwmod,
2712         .slave          = &omap44xx_iva_hwmod,
2713         .clk            = "l3_div_ck",
2714         .addr           = omap44xx_iva_addrs,
2715         .user           = OCP_USER_MPU,
2716 };
2717
2718 /* iva slave ports */
2719 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2720         &omap44xx_dsp__iva,
2721         &omap44xx_l3_main_2__iva,
2722 };
2723
2724 /* Pseudo hwmod for reset control purpose only */
2725 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2726         .name           = "iva_seq0",
2727         .class          = &omap44xx_iva_hwmod_class,
2728         .clkdm_name     = "ivahd_clkdm",
2729         .flags          = HWMOD_INIT_NO_RESET,
2730         .rst_lines      = omap44xx_iva_seq0_resets,
2731         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2732         .prcm = {
2733                 .omap4 = {
2734                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2735                 },
2736         },
2737 };
2738
2739 /* Pseudo hwmod for reset control purpose only */
2740 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2741         .name           = "iva_seq1",
2742         .class          = &omap44xx_iva_hwmod_class,
2743         .clkdm_name     = "ivahd_clkdm",
2744         .flags          = HWMOD_INIT_NO_RESET,
2745         .rst_lines      = omap44xx_iva_seq1_resets,
2746         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2747         .prcm = {
2748                 .omap4 = {
2749                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2750                 },
2751         },
2752 };
2753
2754 static struct omap_hwmod omap44xx_iva_hwmod = {
2755         .name           = "iva",
2756         .class          = &omap44xx_iva_hwmod_class,
2757         .clkdm_name     = "ivahd_clkdm",
2758         .mpu_irqs       = omap44xx_iva_irqs,
2759         .rst_lines      = omap44xx_iva_resets,
2760         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2761         .main_clk       = "iva_fck",
2762         .prcm = {
2763                 .omap4 = {
2764                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2765                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2766                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2767                         .modulemode   = MODULEMODE_HWCTRL,
2768                 },
2769         },
2770         .slaves         = omap44xx_iva_slaves,
2771         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2772         .masters        = omap44xx_iva_masters,
2773         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2774 };
2775
2776 /*
2777  * 'kbd' class
2778  * keyboard controller
2779  */
2780
2781 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2782         .rev_offs       = 0x0000,
2783         .sysc_offs      = 0x0010,
2784         .syss_offs      = 0x0014,
2785         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2786                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2787                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2788                            SYSS_HAS_RESET_STATUS),
2789         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2790         .sysc_fields    = &omap_hwmod_sysc_type1,
2791 };
2792
2793 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2794         .name   = "kbd",
2795         .sysc   = &omap44xx_kbd_sysc,
2796 };
2797
2798 /* kbd */
2799 static struct omap_hwmod omap44xx_kbd_hwmod;
2800 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2801         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2802         { .irq = -1 }
2803 };
2804
2805 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2806         {
2807                 .pa_start       = 0x4a31c000,
2808                 .pa_end         = 0x4a31c07f,
2809                 .flags          = ADDR_TYPE_RT
2810         },
2811         { }
2812 };
2813
2814 /* l4_wkup -> kbd */
2815 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2816         .master         = &omap44xx_l4_wkup_hwmod,
2817         .slave          = &omap44xx_kbd_hwmod,
2818         .clk            = "l4_wkup_clk_mux_ck",
2819         .addr           = omap44xx_kbd_addrs,
2820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2821 };
2822
2823 /* kbd slave ports */
2824 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2825         &omap44xx_l4_wkup__kbd,
2826 };
2827
2828 static struct omap_hwmod omap44xx_kbd_hwmod = {
2829         .name           = "kbd",
2830         .class          = &omap44xx_kbd_hwmod_class,
2831         .clkdm_name     = "l4_wkup_clkdm",
2832         .mpu_irqs       = omap44xx_kbd_irqs,
2833         .main_clk       = "kbd_fck",
2834         .prcm = {
2835                 .omap4 = {
2836                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2837                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2838                         .modulemode   = MODULEMODE_SWCTRL,
2839                 },
2840         },
2841         .slaves         = omap44xx_kbd_slaves,
2842         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2843 };
2844
2845 /*
2846  * 'mailbox' class
2847  * mailbox module allowing communication between the on-chip processors using a
2848  * queued mailbox-interrupt mechanism.
2849  */
2850
2851 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2852         .rev_offs       = 0x0000,
2853         .sysc_offs      = 0x0010,
2854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2855                            SYSC_HAS_SOFTRESET),
2856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2857         .sysc_fields    = &omap_hwmod_sysc_type2,
2858 };
2859
2860 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2861         .name   = "mailbox",
2862         .sysc   = &omap44xx_mailbox_sysc,
2863 };
2864
2865 /* mailbox */
2866 static struct omap_hwmod omap44xx_mailbox_hwmod;
2867 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2868         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2869         { .irq = -1 }
2870 };
2871
2872 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2873         {
2874                 .pa_start       = 0x4a0f4000,
2875                 .pa_end         = 0x4a0f41ff,
2876                 .flags          = ADDR_TYPE_RT
2877         },
2878         { }
2879 };
2880
2881 /* l4_cfg -> mailbox */
2882 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2883         .master         = &omap44xx_l4_cfg_hwmod,
2884         .slave          = &omap44xx_mailbox_hwmod,
2885         .clk            = "l4_div_ck",
2886         .addr           = omap44xx_mailbox_addrs,
2887         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2888 };
2889
2890 /* mailbox slave ports */
2891 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2892         &omap44xx_l4_cfg__mailbox,
2893 };
2894
2895 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2896         .name           = "mailbox",
2897         .class          = &omap44xx_mailbox_hwmod_class,
2898         .clkdm_name     = "l4_cfg_clkdm",
2899         .mpu_irqs       = omap44xx_mailbox_irqs,
2900         .prcm = {
2901                 .omap4 = {
2902                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2903                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2904                 },
2905         },
2906         .slaves         = omap44xx_mailbox_slaves,
2907         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2908 };
2909
2910 /*
2911  * 'mcbsp' class
2912  * multi channel buffered serial port controller
2913  */
2914
2915 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2916         .sysc_offs      = 0x008c,
2917         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2918                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2919         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2920         .sysc_fields    = &omap_hwmod_sysc_type1,
2921 };
2922
2923 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2924         .name   = "mcbsp",
2925         .sysc   = &omap44xx_mcbsp_sysc,
2926         .rev    = MCBSP_CONFIG_TYPE4,
2927 };
2928
2929 /* mcbsp1 */
2930 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2931 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2932         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2933         { .irq = -1 }
2934 };
2935
2936 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2937         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2938         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2939         { .dma_req = -1 }
2940 };
2941
2942 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2943         {
2944                 .name           = "mpu",
2945                 .pa_start       = 0x40122000,
2946                 .pa_end         = 0x401220ff,
2947                 .flags          = ADDR_TYPE_RT
2948         },
2949         { }
2950 };
2951
2952 /* l4_abe -> mcbsp1 */
2953 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2954         .master         = &omap44xx_l4_abe_hwmod,
2955         .slave          = &omap44xx_mcbsp1_hwmod,
2956         .clk            = "ocp_abe_iclk",
2957         .addr           = omap44xx_mcbsp1_addrs,
2958         .user           = OCP_USER_MPU,
2959 };
2960
2961 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2962         {
2963                 .name           = "dma",
2964                 .pa_start       = 0x49022000,
2965                 .pa_end         = 0x490220ff,
2966                 .flags          = ADDR_TYPE_RT
2967         },
2968         { }
2969 };
2970
2971 /* l4_abe -> mcbsp1 (dma) */
2972 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2973         .master         = &omap44xx_l4_abe_hwmod,
2974         .slave          = &omap44xx_mcbsp1_hwmod,
2975         .clk            = "ocp_abe_iclk",
2976         .addr           = omap44xx_mcbsp1_dma_addrs,
2977         .user           = OCP_USER_SDMA,
2978 };
2979
2980 /* mcbsp1 slave ports */
2981 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2982         &omap44xx_l4_abe__mcbsp1,
2983         &omap44xx_l4_abe__mcbsp1_dma,
2984 };
2985
2986 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2987         .name           = "mcbsp1",
2988         .class          = &omap44xx_mcbsp_hwmod_class,
2989         .clkdm_name     = "abe_clkdm",
2990         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2991         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2992         .main_clk       = "mcbsp1_fck",
2993         .prcm = {
2994                 .omap4 = {
2995                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
2996                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
2997                         .modulemode   = MODULEMODE_SWCTRL,
2998                 },
2999         },
3000         .slaves         = omap44xx_mcbsp1_slaves,
3001         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3002 };
3003
3004 /* mcbsp2 */
3005 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3006 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3007         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3008         { .irq = -1 }
3009 };
3010
3011 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3012         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3013         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3014         { .dma_req = -1 }
3015 };
3016
3017 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3018         {
3019                 .name           = "mpu",
3020                 .pa_start       = 0x40124000,
3021                 .pa_end         = 0x401240ff,
3022                 .flags          = ADDR_TYPE_RT
3023         },
3024         { }
3025 };
3026
3027 /* l4_abe -> mcbsp2 */
3028 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3029         .master         = &omap44xx_l4_abe_hwmod,
3030         .slave          = &omap44xx_mcbsp2_hwmod,
3031         .clk            = "ocp_abe_iclk",
3032         .addr           = omap44xx_mcbsp2_addrs,
3033         .user           = OCP_USER_MPU,
3034 };
3035
3036 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3037         {
3038                 .name           = "dma",
3039                 .pa_start       = 0x49024000,
3040                 .pa_end         = 0x490240ff,
3041                 .flags          = ADDR_TYPE_RT
3042         },
3043         { }
3044 };
3045
3046 /* l4_abe -> mcbsp2 (dma) */
3047 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3048         .master         = &omap44xx_l4_abe_hwmod,
3049         .slave          = &omap44xx_mcbsp2_hwmod,
3050         .clk            = "ocp_abe_iclk",
3051         .addr           = omap44xx_mcbsp2_dma_addrs,
3052         .user           = OCP_USER_SDMA,
3053 };
3054
3055 /* mcbsp2 slave ports */
3056 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3057         &omap44xx_l4_abe__mcbsp2,
3058         &omap44xx_l4_abe__mcbsp2_dma,
3059 };
3060
3061 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3062         .name           = "mcbsp2",
3063         .class          = &omap44xx_mcbsp_hwmod_class,
3064         .clkdm_name     = "abe_clkdm",
3065         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3066         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3067         .main_clk       = "mcbsp2_fck",
3068         .prcm = {
3069                 .omap4 = {
3070                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3071                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3072                         .modulemode   = MODULEMODE_SWCTRL,
3073                 },
3074         },
3075         .slaves         = omap44xx_mcbsp2_slaves,
3076         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3077 };
3078
3079 /* mcbsp3 */
3080 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3081 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3082         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3083         { .irq = -1 }
3084 };
3085
3086 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3087         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3088         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3089         { .dma_req = -1 }
3090 };
3091
3092 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3093         {
3094                 .name           = "mpu",
3095                 .pa_start       = 0x40126000,
3096                 .pa_end         = 0x401260ff,
3097                 .flags          = ADDR_TYPE_RT
3098         },
3099         { }
3100 };
3101
3102 /* l4_abe -> mcbsp3 */
3103 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3104         .master         = &omap44xx_l4_abe_hwmod,
3105         .slave          = &omap44xx_mcbsp3_hwmod,
3106         .clk            = "ocp_abe_iclk",
3107         .addr           = omap44xx_mcbsp3_addrs,
3108         .user           = OCP_USER_MPU,
3109 };
3110
3111 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3112         {
3113                 .name           = "dma",
3114                 .pa_start       = 0x49026000,
3115                 .pa_end         = 0x490260ff,
3116                 .flags          = ADDR_TYPE_RT
3117         },
3118         { }
3119 };
3120
3121 /* l4_abe -> mcbsp3 (dma) */
3122 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3123         .master         = &omap44xx_l4_abe_hwmod,
3124         .slave          = &omap44xx_mcbsp3_hwmod,
3125         .clk            = "ocp_abe_iclk",
3126         .addr           = omap44xx_mcbsp3_dma_addrs,
3127         .user           = OCP_USER_SDMA,
3128 };
3129
3130 /* mcbsp3 slave ports */
3131 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3132         &omap44xx_l4_abe__mcbsp3,
3133         &omap44xx_l4_abe__mcbsp3_dma,
3134 };
3135
3136 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3137         .name           = "mcbsp3",
3138         .class          = &omap44xx_mcbsp_hwmod_class,
3139         .clkdm_name     = "abe_clkdm",
3140         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3141         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3142         .main_clk       = "mcbsp3_fck",
3143         .prcm = {
3144                 .omap4 = {
3145                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3146                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3147                         .modulemode   = MODULEMODE_SWCTRL,
3148                 },
3149         },
3150         .slaves         = omap44xx_mcbsp3_slaves,
3151         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3152 };
3153
3154 /* mcbsp4 */
3155 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3156 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3157         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3158         { .irq = -1 }
3159 };
3160
3161 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3162         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3163         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3164         { .dma_req = -1 }
3165 };
3166
3167 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3168         {
3169                 .pa_start       = 0x48096000,
3170                 .pa_end         = 0x480960ff,
3171                 .flags          = ADDR_TYPE_RT
3172         },
3173         { }
3174 };
3175
3176 /* l4_per -> mcbsp4 */
3177 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3178         .master         = &omap44xx_l4_per_hwmod,
3179         .slave          = &omap44xx_mcbsp4_hwmod,
3180         .clk            = "l4_div_ck",
3181         .addr           = omap44xx_mcbsp4_addrs,
3182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3183 };
3184
3185 /* mcbsp4 slave ports */
3186 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3187         &omap44xx_l4_per__mcbsp4,
3188 };
3189
3190 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3191         .name           = "mcbsp4",
3192         .class          = &omap44xx_mcbsp_hwmod_class,
3193         .clkdm_name     = "l4_per_clkdm",
3194         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3195         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3196         .main_clk       = "mcbsp4_fck",
3197         .prcm = {
3198                 .omap4 = {
3199                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3200                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3201                         .modulemode   = MODULEMODE_SWCTRL,
3202                 },
3203         },
3204         .slaves         = omap44xx_mcbsp4_slaves,
3205         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3206 };
3207
3208 /*
3209  * 'mcpdm' class
3210  * multi channel pdm controller (proprietary interface with phoenix power
3211  * ic)
3212  */
3213
3214 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3215         .rev_offs       = 0x0000,
3216         .sysc_offs      = 0x0010,
3217         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3218                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3219         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3220                            SIDLE_SMART_WKUP),
3221         .sysc_fields    = &omap_hwmod_sysc_type2,
3222 };
3223
3224 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3225         .name   = "mcpdm",
3226         .sysc   = &omap44xx_mcpdm_sysc,
3227 };
3228
3229 /* mcpdm */
3230 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3231 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3232         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3233         { .irq = -1 }
3234 };
3235
3236 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3237         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3238         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3239         { .dma_req = -1 }
3240 };
3241
3242 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3243         {
3244                 .pa_start       = 0x40132000,
3245                 .pa_end         = 0x4013207f,
3246                 .flags          = ADDR_TYPE_RT
3247         },
3248         { }
3249 };
3250
3251 /* l4_abe -> mcpdm */
3252 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3253         .master         = &omap44xx_l4_abe_hwmod,
3254         .slave          = &omap44xx_mcpdm_hwmod,
3255         .clk            = "ocp_abe_iclk",
3256         .addr           = omap44xx_mcpdm_addrs,
3257         .user           = OCP_USER_MPU,
3258 };
3259
3260 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3261         {
3262                 .pa_start       = 0x49032000,
3263                 .pa_end         = 0x4903207f,
3264                 .flags          = ADDR_TYPE_RT
3265         },
3266         { }
3267 };
3268
3269 /* l4_abe -> mcpdm (dma) */
3270 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3271         .master         = &omap44xx_l4_abe_hwmod,
3272         .slave          = &omap44xx_mcpdm_hwmod,
3273         .clk            = "ocp_abe_iclk",
3274         .addr           = omap44xx_mcpdm_dma_addrs,
3275         .user           = OCP_USER_SDMA,
3276 };
3277
3278 /* mcpdm slave ports */
3279 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3280         &omap44xx_l4_abe__mcpdm,
3281         &omap44xx_l4_abe__mcpdm_dma,
3282 };
3283
3284 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3285         .name           = "mcpdm",
3286         .class          = &omap44xx_mcpdm_hwmod_class,
3287         .clkdm_name     = "abe_clkdm",
3288         .mpu_irqs       = omap44xx_mcpdm_irqs,
3289         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3290         .main_clk       = "mcpdm_fck",
3291         .prcm = {
3292                 .omap4 = {
3293                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3294                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3295                         .modulemode   = MODULEMODE_SWCTRL,
3296                 },
3297         },
3298         .slaves         = omap44xx_mcpdm_slaves,
3299         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3300 };
3301
3302 /*
3303  * 'mcspi' class
3304  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3305  * bus
3306  */
3307
3308 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3309         .rev_offs       = 0x0000,
3310         .sysc_offs      = 0x0010,
3311         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3312                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3313         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3314                            SIDLE_SMART_WKUP),
3315         .sysc_fields    = &omap_hwmod_sysc_type2,
3316 };
3317
3318 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3319         .name   = "mcspi",
3320         .sysc   = &omap44xx_mcspi_sysc,
3321         .rev    = OMAP4_MCSPI_REV,
3322 };
3323
3324 /* mcspi1 */
3325 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3326 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3327         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3328         { .irq = -1 }
3329 };
3330
3331 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3332         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3333         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3334         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3335         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3336         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3337         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3338         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3339         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3340         { .dma_req = -1 }
3341 };
3342
3343 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3344         {
3345                 .pa_start       = 0x48098000,
3346                 .pa_end         = 0x480981ff,
3347                 .flags          = ADDR_TYPE_RT
3348         },
3349         { }
3350 };
3351
3352 /* l4_per -> mcspi1 */
3353 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3354         .master         = &omap44xx_l4_per_hwmod,
3355         .slave          = &omap44xx_mcspi1_hwmod,
3356         .clk            = "l4_div_ck",
3357         .addr           = omap44xx_mcspi1_addrs,
3358         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3359 };
3360
3361 /* mcspi1 slave ports */
3362 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3363         &omap44xx_l4_per__mcspi1,
3364 };
3365
3366 /* mcspi1 dev_attr */
3367 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3368         .num_chipselect = 4,
3369 };
3370
3371 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3372         .name           = "mcspi1",
3373         .class          = &omap44xx_mcspi_hwmod_class,
3374         .clkdm_name     = "l4_per_clkdm",
3375         .mpu_irqs       = omap44xx_mcspi1_irqs,
3376         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3377         .main_clk       = "mcspi1_fck",
3378         .prcm = {
3379                 .omap4 = {
3380                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3381                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3382                         .modulemode   = MODULEMODE_SWCTRL,
3383                 },
3384         },
3385         .dev_attr       = &mcspi1_dev_attr,
3386         .slaves         = omap44xx_mcspi1_slaves,
3387         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3388 };
3389
3390 /* mcspi2 */
3391 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3392 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3393         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3394         { .irq = -1 }
3395 };
3396
3397 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3398         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3399         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3400         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3401         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3402         { .dma_req = -1 }
3403 };
3404
3405 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3406         {
3407                 .pa_start       = 0x4809a000,
3408                 .pa_end         = 0x4809a1ff,
3409                 .flags          = ADDR_TYPE_RT
3410         },
3411         { }
3412 };
3413
3414 /* l4_per -> mcspi2 */
3415 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3416         .master         = &omap44xx_l4_per_hwmod,
3417         .slave          = &omap44xx_mcspi2_hwmod,
3418         .clk            = "l4_div_ck",
3419         .addr           = omap44xx_mcspi2_addrs,
3420         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3421 };
3422
3423 /* mcspi2 slave ports */
3424 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3425         &omap44xx_l4_per__mcspi2,
3426 };
3427
3428 /* mcspi2 dev_attr */
3429 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3430         .num_chipselect = 2,
3431 };
3432
3433 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3434         .name           = "mcspi2",
3435         .class          = &omap44xx_mcspi_hwmod_class,
3436         .clkdm_name     = "l4_per_clkdm",
3437         .mpu_irqs       = omap44xx_mcspi2_irqs,
3438         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3439         .main_clk       = "mcspi2_fck",
3440         .prcm = {
3441                 .omap4 = {
3442                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3443                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3444                         .modulemode   = MODULEMODE_SWCTRL,
3445                 },
3446         },
3447         .dev_attr       = &mcspi2_dev_attr,
3448         .slaves         = omap44xx_mcspi2_slaves,
3449         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3450 };
3451
3452 /* mcspi3 */
3453 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3454 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3455         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3456         { .irq = -1 }
3457 };
3458
3459 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3460         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3461         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3462         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3463         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3464         { .dma_req = -1 }
3465 };
3466
3467 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3468         {
3469                 .pa_start       = 0x480b8000,
3470                 .pa_end         = 0x480b81ff,
3471                 .flags          = ADDR_TYPE_RT
3472         },
3473         { }
3474 };
3475
3476 /* l4_per -> mcspi3 */
3477 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3478         .master         = &omap44xx_l4_per_hwmod,
3479         .slave          = &omap44xx_mcspi3_hwmod,
3480         .clk            = "l4_div_ck",
3481         .addr           = omap44xx_mcspi3_addrs,
3482         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3483 };
3484
3485 /* mcspi3 slave ports */
3486 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3487         &omap44xx_l4_per__mcspi3,
3488 };
3489
3490 /* mcspi3 dev_attr */
3491 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3492         .num_chipselect = 2,
3493 };
3494
3495 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3496         .name           = "mcspi3",
3497         .class          = &omap44xx_mcspi_hwmod_class,
3498         .clkdm_name     = "l4_per_clkdm",
3499         .mpu_irqs       = omap44xx_mcspi3_irqs,
3500         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3501         .main_clk       = "mcspi3_fck",
3502         .prcm = {
3503                 .omap4 = {
3504                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3505                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3506                         .modulemode   = MODULEMODE_SWCTRL,
3507                 },
3508         },
3509         .dev_attr       = &mcspi3_dev_attr,
3510         .slaves         = omap44xx_mcspi3_slaves,
3511         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3512 };
3513
3514 /* mcspi4 */
3515 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3516 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3517         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3518         { .irq = -1 }
3519 };
3520
3521 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3522         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3523         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3524         { .dma_req = -1 }
3525 };
3526
3527 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3528         {
3529                 .pa_start       = 0x480ba000,
3530                 .pa_end         = 0x480ba1ff,
3531                 .flags          = ADDR_TYPE_RT
3532         },
3533         { }
3534 };
3535
3536 /* l4_per -> mcspi4 */
3537 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3538         .master         = &omap44xx_l4_per_hwmod,
3539         .slave          = &omap44xx_mcspi4_hwmod,
3540         .clk            = "l4_div_ck",
3541         .addr           = omap44xx_mcspi4_addrs,
3542         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3543 };
3544
3545 /* mcspi4 slave ports */
3546 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3547         &omap44xx_l4_per__mcspi4,
3548 };
3549
3550 /* mcspi4 dev_attr */
3551 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3552         .num_chipselect = 1,
3553 };
3554
3555 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3556         .name           = "mcspi4",
3557         .class          = &omap44xx_mcspi_hwmod_class,
3558         .clkdm_name     = "l4_per_clkdm",
3559         .mpu_irqs       = omap44xx_mcspi4_irqs,
3560         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3561         .main_clk       = "mcspi4_fck",
3562         .prcm = {
3563                 .omap4 = {
3564                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3565                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3566                         .modulemode   = MODULEMODE_SWCTRL,
3567                 },
3568         },
3569         .dev_attr       = &mcspi4_dev_attr,
3570         .slaves         = omap44xx_mcspi4_slaves,
3571         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3572 };
3573
3574 /*
3575  * 'mmc' class
3576  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3577  */
3578
3579 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3580         .rev_offs       = 0x0000,
3581         .sysc_offs      = 0x0010,
3582         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3583                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3584                            SYSC_HAS_SOFTRESET),
3585         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3586                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3587                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3588         .sysc_fields    = &omap_hwmod_sysc_type2,
3589 };
3590
3591 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3592         .name   = "mmc",
3593         .sysc   = &omap44xx_mmc_sysc,
3594 };
3595
3596 /* mmc1 */
3597 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3598         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3599         { .irq = -1 }
3600 };
3601
3602 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3603         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3604         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3605         { .dma_req = -1 }
3606 };
3607
3608 /* mmc1 master ports */
3609 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3610         &omap44xx_mmc1__l3_main_1,
3611 };
3612
3613 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3614         {
3615                 .pa_start       = 0x4809c000,
3616                 .pa_end         = 0x4809c3ff,
3617                 .flags          = ADDR_TYPE_RT
3618         },
3619         { }
3620 };
3621
3622 /* l4_per -> mmc1 */
3623 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3624         .master         = &omap44xx_l4_per_hwmod,
3625         .slave          = &omap44xx_mmc1_hwmod,
3626         .clk            = "l4_div_ck",
3627         .addr           = omap44xx_mmc1_addrs,
3628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3629 };
3630
3631 /* mmc1 slave ports */
3632 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3633         &omap44xx_l4_per__mmc1,
3634 };
3635
3636 /* mmc1 dev_attr */
3637 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3638         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3639 };
3640
3641 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3642         .name           = "mmc1",
3643         .class          = &omap44xx_mmc_hwmod_class,
3644         .clkdm_name     = "l3_init_clkdm",
3645         .mpu_irqs       = omap44xx_mmc1_irqs,
3646         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3647         .main_clk       = "mmc1_fck",
3648         .prcm = {
3649                 .omap4 = {
3650                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3651                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3652                         .modulemode   = MODULEMODE_SWCTRL,
3653                 },
3654         },
3655         .dev_attr       = &mmc1_dev_attr,
3656         .slaves         = omap44xx_mmc1_slaves,
3657         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3658         .masters        = omap44xx_mmc1_masters,
3659         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3660 };
3661
3662 /* mmc2 */
3663 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3664         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3665         { .irq = -1 }
3666 };
3667
3668 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3669         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3670         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3671         { .dma_req = -1 }
3672 };
3673
3674 /* mmc2 master ports */
3675 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3676         &omap44xx_mmc2__l3_main_1,
3677 };
3678
3679 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3680         {
3681                 .pa_start       = 0x480b4000,
3682                 .pa_end         = 0x480b43ff,
3683                 .flags          = ADDR_TYPE_RT
3684         },
3685         { }
3686 };
3687
3688 /* l4_per -> mmc2 */
3689 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3690         .master         = &omap44xx_l4_per_hwmod,
3691         .slave          = &omap44xx_mmc2_hwmod,
3692         .clk            = "l4_div_ck",
3693         .addr           = omap44xx_mmc2_addrs,
3694         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3695 };
3696
3697 /* mmc2 slave ports */
3698 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3699         &omap44xx_l4_per__mmc2,
3700 };
3701
3702 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3703         .name           = "mmc2",
3704         .class          = &omap44xx_mmc_hwmod_class,
3705         .clkdm_name     = "l3_init_clkdm",
3706         .mpu_irqs       = omap44xx_mmc2_irqs,
3707         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3708         .main_clk       = "mmc2_fck",
3709         .prcm = {
3710                 .omap4 = {
3711                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3712                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3713                         .modulemode   = MODULEMODE_SWCTRL,
3714                 },
3715         },
3716         .slaves         = omap44xx_mmc2_slaves,
3717         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3718         .masters        = omap44xx_mmc2_masters,
3719         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3720 };
3721
3722 /* mmc3 */
3723 static struct omap_hwmod omap44xx_mmc3_hwmod;
3724 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3725         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3726         { .irq = -1 }
3727 };
3728
3729 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3730         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3731         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3732         { .dma_req = -1 }
3733 };
3734
3735 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3736         {
3737                 .pa_start       = 0x480ad000,
3738                 .pa_end         = 0x480ad3ff,
3739                 .flags          = ADDR_TYPE_RT
3740         },
3741         { }
3742 };
3743
3744 /* l4_per -> mmc3 */
3745 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3746         .master         = &omap44xx_l4_per_hwmod,
3747         .slave          = &omap44xx_mmc3_hwmod,
3748         .clk            = "l4_div_ck",
3749         .addr           = omap44xx_mmc3_addrs,
3750         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3751 };
3752
3753 /* mmc3 slave ports */
3754 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3755         &omap44xx_l4_per__mmc3,
3756 };
3757
3758 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3759         .name           = "mmc3",
3760         .class          = &omap44xx_mmc_hwmod_class,
3761         .clkdm_name     = "l4_per_clkdm",
3762         .mpu_irqs       = omap44xx_mmc3_irqs,
3763         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3764         .main_clk       = "mmc3_fck",
3765         .prcm = {
3766                 .omap4 = {
3767                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3768                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3769                         .modulemode   = MODULEMODE_SWCTRL,
3770                 },
3771         },
3772         .slaves         = omap44xx_mmc3_slaves,
3773         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3774 };
3775
3776 /* mmc4 */
3777 static struct omap_hwmod omap44xx_mmc4_hwmod;
3778 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3779         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3780         { .irq = -1 }
3781 };
3782
3783 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3784         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3785         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3786         { .dma_req = -1 }
3787 };
3788
3789 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3790         {
3791                 .pa_start       = 0x480d1000,
3792                 .pa_end         = 0x480d13ff,
3793                 .flags          = ADDR_TYPE_RT
3794         },
3795         { }
3796 };
3797
3798 /* l4_per -> mmc4 */
3799 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3800         .master         = &omap44xx_l4_per_hwmod,
3801         .slave          = &omap44xx_mmc4_hwmod,
3802         .clk            = "l4_div_ck",
3803         .addr           = omap44xx_mmc4_addrs,
3804         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3805 };
3806
3807 /* mmc4 slave ports */
3808 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3809         &omap44xx_l4_per__mmc4,
3810 };
3811
3812 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3813         .name           = "mmc4",
3814         .class          = &omap44xx_mmc_hwmod_class,
3815         .clkdm_name     = "l4_per_clkdm",
3816         .mpu_irqs       = omap44xx_mmc4_irqs,
3817
3818         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3819         .main_clk       = "mmc4_fck",
3820         .prcm = {
3821                 .omap4 = {
3822                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3823                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3824                         .modulemode   = MODULEMODE_SWCTRL,
3825                 },
3826         },
3827         .slaves         = omap44xx_mmc4_slaves,
3828         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3829 };
3830
3831 /* mmc5 */
3832 static struct omap_hwmod omap44xx_mmc5_hwmod;
3833 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3834         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3835         { .irq = -1 }
3836 };
3837
3838 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3839         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3840         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3841         { .dma_req = -1 }
3842 };
3843
3844 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3845         {
3846                 .pa_start       = 0x480d5000,
3847                 .pa_end         = 0x480d53ff,
3848                 .flags          = ADDR_TYPE_RT
3849         },
3850         { }
3851 };
3852
3853 /* l4_per -> mmc5 */
3854 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3855         .master         = &omap44xx_l4_per_hwmod,
3856         .slave          = &omap44xx_mmc5_hwmod,
3857         .clk            = "l4_div_ck",
3858         .addr           = omap44xx_mmc5_addrs,
3859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3860 };
3861
3862 /* mmc5 slave ports */
3863 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3864         &omap44xx_l4_per__mmc5,
3865 };
3866
3867 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3868         .name           = "mmc5",
3869         .class          = &omap44xx_mmc_hwmod_class,
3870         .clkdm_name     = "l4_per_clkdm",
3871         .mpu_irqs       = omap44xx_mmc5_irqs,
3872         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3873         .main_clk       = "mmc5_fck",
3874         .prcm = {
3875                 .omap4 = {
3876                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3877                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3878                         .modulemode   = MODULEMODE_SWCTRL,
3879                 },
3880         },
3881         .slaves         = omap44xx_mmc5_slaves,
3882         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3883 };
3884
3885 /*
3886  * 'mpu' class
3887  * mpu sub-system
3888  */
3889
3890 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3891         .name   = "mpu",
3892 };
3893
3894 /* mpu */
3895 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3896         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3897         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3898         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3899         { .irq = -1 }
3900 };
3901
3902 /* mpu master ports */
3903 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3904         &omap44xx_mpu__l3_main_1,
3905         &omap44xx_mpu__l4_abe,
3906         &omap44xx_mpu__dmm,
3907 };
3908
3909 static struct omap_hwmod omap44xx_mpu_hwmod = {
3910         .name           = "mpu",
3911         .class          = &omap44xx_mpu_hwmod_class,
3912         .clkdm_name     = "mpuss_clkdm",
3913         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3914         .mpu_irqs       = omap44xx_mpu_irqs,
3915         .main_clk       = "dpll_mpu_m2_ck",
3916         .prcm = {
3917                 .omap4 = {
3918                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3919                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3920                 },
3921         },
3922         .masters        = omap44xx_mpu_masters,
3923         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3924 };
3925
3926 /*
3927  * 'smartreflex' class
3928  * smartreflex module (monitor silicon performance and outputs a measure of
3929  * performance error)
3930  */
3931
3932 /* The IP is not compliant to type1 / type2 scheme */
3933 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3934         .sidle_shift    = 24,
3935         .enwkup_shift   = 26,
3936 };
3937
3938 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3939         .sysc_offs      = 0x0038,
3940         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3941         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3942                            SIDLE_SMART_WKUP),
3943         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3944 };
3945
3946 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3947         .name   = "smartreflex",
3948         .sysc   = &omap44xx_smartreflex_sysc,
3949         .rev    = 2,
3950 };
3951
3952 /* smartreflex_core */
3953 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3954 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3955         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3956         { .irq = -1 }
3957 };
3958
3959 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3960         {
3961                 .pa_start       = 0x4a0dd000,
3962                 .pa_end         = 0x4a0dd03f,
3963                 .flags          = ADDR_TYPE_RT
3964         },
3965         { }
3966 };
3967
3968 /* l4_cfg -> smartreflex_core */
3969 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3970         .master         = &omap44xx_l4_cfg_hwmod,
3971         .slave          = &omap44xx_smartreflex_core_hwmod,
3972         .clk            = "l4_div_ck",
3973         .addr           = omap44xx_smartreflex_core_addrs,
3974         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3975 };
3976
3977 /* smartreflex_core slave ports */
3978 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3979         &omap44xx_l4_cfg__smartreflex_core,
3980 };
3981
3982 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3983         .name           = "smartreflex_core",
3984         .class          = &omap44xx_smartreflex_hwmod_class,
3985         .clkdm_name     = "l4_ao_clkdm",
3986         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3987
3988         .main_clk       = "smartreflex_core_fck",
3989         .vdd_name       = "core",
3990         .prcm = {
3991                 .omap4 = {
3992                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
3993                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
3994                         .modulemode   = MODULEMODE_SWCTRL,
3995                 },
3996         },
3997         .slaves         = omap44xx_smartreflex_core_slaves,
3998         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3999 };
4000
4001 /* smartreflex_iva */
4002 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4003 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4004         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4005         { .irq = -1 }
4006 };
4007
4008 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4009         {
4010                 .pa_start       = 0x4a0db000,
4011                 .pa_end         = 0x4a0db03f,
4012                 .flags          = ADDR_TYPE_RT
4013         },
4014         { }
4015 };
4016
4017 /* l4_cfg -> smartreflex_iva */
4018 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4019         .master         = &omap44xx_l4_cfg_hwmod,
4020         .slave          = &omap44xx_smartreflex_iva_hwmod,
4021         .clk            = "l4_div_ck",
4022         .addr           = omap44xx_smartreflex_iva_addrs,
4023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4024 };
4025
4026 /* smartreflex_iva slave ports */
4027 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4028         &omap44xx_l4_cfg__smartreflex_iva,
4029 };
4030
4031 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4032         .name           = "smartreflex_iva",
4033         .class          = &omap44xx_smartreflex_hwmod_class,
4034         .clkdm_name     = "l4_ao_clkdm",
4035         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
4036         .main_clk       = "smartreflex_iva_fck",
4037         .vdd_name       = "iva",
4038         .prcm = {
4039                 .omap4 = {
4040                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4041                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4042                         .modulemode   = MODULEMODE_SWCTRL,
4043                 },
4044         },
4045         .slaves         = omap44xx_smartreflex_iva_slaves,
4046         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4047 };
4048
4049 /* smartreflex_mpu */
4050 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4051 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4052         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4053         { .irq = -1 }
4054 };
4055
4056 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4057         {
4058                 .pa_start       = 0x4a0d9000,
4059                 .pa_end         = 0x4a0d903f,
4060                 .flags          = ADDR_TYPE_RT
4061         },
4062         { }
4063 };
4064
4065 /* l4_cfg -> smartreflex_mpu */
4066 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4067         .master         = &omap44xx_l4_cfg_hwmod,
4068         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4069         .clk            = "l4_div_ck",
4070         .addr           = omap44xx_smartreflex_mpu_addrs,
4071         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4072 };
4073
4074 /* smartreflex_mpu slave ports */
4075 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4076         &omap44xx_l4_cfg__smartreflex_mpu,
4077 };
4078
4079 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4080         .name           = "smartreflex_mpu",
4081         .class          = &omap44xx_smartreflex_hwmod_class,
4082         .clkdm_name     = "l4_ao_clkdm",
4083         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
4084         .main_clk       = "smartreflex_mpu_fck",
4085         .vdd_name       = "mpu",
4086         .prcm = {
4087                 .omap4 = {
4088                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4089                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4090                         .modulemode   = MODULEMODE_SWCTRL,
4091                 },
4092         },
4093         .slaves         = omap44xx_smartreflex_mpu_slaves,
4094         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4095 };
4096
4097 /*
4098  * 'spinlock' class
4099  * spinlock provides hardware assistance for synchronizing the processes
4100  * running on multiple processors
4101  */
4102
4103 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4104         .rev_offs       = 0x0000,
4105         .sysc_offs      = 0x0010,
4106         .syss_offs      = 0x0014,
4107         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4108                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4109                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4110         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4111                            SIDLE_SMART_WKUP),
4112         .sysc_fields    = &omap_hwmod_sysc_type1,
4113 };
4114
4115 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4116         .name   = "spinlock",
4117         .sysc   = &omap44xx_spinlock_sysc,
4118 };
4119
4120 /* spinlock */
4121 static struct omap_hwmod omap44xx_spinlock_hwmod;
4122 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4123         {
4124                 .pa_start       = 0x4a0f6000,
4125                 .pa_end         = 0x4a0f6fff,
4126                 .flags          = ADDR_TYPE_RT
4127         },
4128         { }
4129 };
4130
4131 /* l4_cfg -> spinlock */
4132 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4133         .master         = &omap44xx_l4_cfg_hwmod,
4134         .slave          = &omap44xx_spinlock_hwmod,
4135         .clk            = "l4_div_ck",
4136         .addr           = omap44xx_spinlock_addrs,
4137         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4138 };
4139
4140 /* spinlock slave ports */
4141 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4142         &omap44xx_l4_cfg__spinlock,
4143 };
4144
4145 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4146         .name           = "spinlock",
4147         .class          = &omap44xx_spinlock_hwmod_class,
4148         .clkdm_name     = "l4_cfg_clkdm",
4149         .prcm = {
4150                 .omap4 = {
4151                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4152                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4153                 },
4154         },
4155         .slaves         = omap44xx_spinlock_slaves,
4156         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4157 };
4158
4159 /*
4160  * 'timer' class
4161  * general purpose timer module with accurate 1ms tick
4162  * This class contains several variants: ['timer_1ms', 'timer']
4163  */
4164
4165 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4166         .rev_offs       = 0x0000,
4167         .sysc_offs      = 0x0010,
4168         .syss_offs      = 0x0014,
4169         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4170                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4171                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4172                            SYSS_HAS_RESET_STATUS),
4173         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4174         .sysc_fields    = &omap_hwmod_sysc_type1,
4175 };
4176
4177 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4178         .name   = "timer",
4179         .sysc   = &omap44xx_timer_1ms_sysc,
4180 };
4181
4182 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4183         .rev_offs       = 0x0000,
4184         .sysc_offs      = 0x0010,
4185         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4186                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4187         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4188                            SIDLE_SMART_WKUP),
4189         .sysc_fields    = &omap_hwmod_sysc_type2,
4190 };
4191
4192 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4193         .name   = "timer",
4194         .sysc   = &omap44xx_timer_sysc,
4195 };
4196
4197 /* always-on timers dev attribute */
4198 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4199         .timer_capability       = OMAP_TIMER_ALWON,
4200 };
4201
4202 /* pwm timers dev attribute */
4203 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4204         .timer_capability       = OMAP_TIMER_HAS_PWM,
4205 };
4206
4207 /* timer1 */
4208 static struct omap_hwmod omap44xx_timer1_hwmod;
4209 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4210         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4211         { .irq = -1 }
4212 };
4213
4214 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4215         {
4216                 .pa_start       = 0x4a318000,
4217                 .pa_end         = 0x4a31807f,
4218                 .flags          = ADDR_TYPE_RT
4219         },
4220         { }
4221 };
4222
4223 /* l4_wkup -> timer1 */
4224 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4225         .master         = &omap44xx_l4_wkup_hwmod,
4226         .slave          = &omap44xx_timer1_hwmod,
4227         .clk            = "l4_wkup_clk_mux_ck",
4228         .addr           = omap44xx_timer1_addrs,
4229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4230 };
4231
4232 /* timer1 slave ports */
4233 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4234         &omap44xx_l4_wkup__timer1,
4235 };
4236
4237 static struct omap_hwmod omap44xx_timer1_hwmod = {
4238         .name           = "timer1",
4239         .class          = &omap44xx_timer_1ms_hwmod_class,
4240         .clkdm_name     = "l4_wkup_clkdm",
4241         .mpu_irqs       = omap44xx_timer1_irqs,
4242         .main_clk       = "timer1_fck",
4243         .prcm = {
4244                 .omap4 = {
4245                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4246                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4247                         .modulemode   = MODULEMODE_SWCTRL,
4248                 },
4249         },
4250         .dev_attr       = &capability_alwon_dev_attr,
4251         .slaves         = omap44xx_timer1_slaves,
4252         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4253 };
4254
4255 /* timer2 */
4256 static struct omap_hwmod omap44xx_timer2_hwmod;
4257 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4258         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4259         { .irq = -1 }
4260 };
4261
4262 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4263         {
4264                 .pa_start       = 0x48032000,
4265                 .pa_end         = 0x4803207f,
4266                 .flags          = ADDR_TYPE_RT
4267         },
4268         { }
4269 };
4270
4271 /* l4_per -> timer2 */
4272 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4273         .master         = &omap44xx_l4_per_hwmod,
4274         .slave          = &omap44xx_timer2_hwmod,
4275         .clk            = "l4_div_ck",
4276         .addr           = omap44xx_timer2_addrs,
4277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4278 };
4279
4280 /* timer2 slave ports */
4281 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4282         &omap44xx_l4_per__timer2,
4283 };
4284
4285 static struct omap_hwmod omap44xx_timer2_hwmod = {
4286         .name           = "timer2",
4287         .class          = &omap44xx_timer_1ms_hwmod_class,
4288         .clkdm_name     = "l4_per_clkdm",
4289         .mpu_irqs       = omap44xx_timer2_irqs,
4290         .main_clk       = "timer2_fck",
4291         .prcm = {
4292                 .omap4 = {
4293                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4294                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4295                         .modulemode   = MODULEMODE_SWCTRL,
4296                 },
4297         },
4298         .dev_attr       = &capability_alwon_dev_attr,
4299         .slaves         = omap44xx_timer2_slaves,
4300         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4301 };
4302
4303 /* timer3 */
4304 static struct omap_hwmod omap44xx_timer3_hwmod;
4305 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4306         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4307         { .irq = -1 }
4308 };
4309
4310 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4311         {
4312                 .pa_start       = 0x48034000,
4313                 .pa_end         = 0x4803407f,
4314                 .flags          = ADDR_TYPE_RT
4315         },
4316         { }
4317 };
4318
4319 /* l4_per -> timer3 */
4320 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4321         .master         = &omap44xx_l4_per_hwmod,
4322         .slave          = &omap44xx_timer3_hwmod,
4323         .clk            = "l4_div_ck",
4324         .addr           = omap44xx_timer3_addrs,
4325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4326 };
4327
4328 /* timer3 slave ports */
4329 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4330         &omap44xx_l4_per__timer3,
4331 };
4332
4333 static struct omap_hwmod omap44xx_timer3_hwmod = {
4334         .name           = "timer3",
4335         .class          = &omap44xx_timer_hwmod_class,
4336         .clkdm_name     = "l4_per_clkdm",
4337         .mpu_irqs       = omap44xx_timer3_irqs,
4338         .main_clk       = "timer3_fck",
4339         .prcm = {
4340                 .omap4 = {
4341                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4342                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4343                         .modulemode   = MODULEMODE_SWCTRL,
4344                 },
4345         },
4346         .dev_attr       = &capability_alwon_dev_attr,
4347         .slaves         = omap44xx_timer3_slaves,
4348         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4349 };
4350
4351 /* timer4 */
4352 static struct omap_hwmod omap44xx_timer4_hwmod;
4353 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4354         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4355         { .irq = -1 }
4356 };
4357
4358 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4359         {
4360                 .pa_start       = 0x48036000,
4361                 .pa_end         = 0x4803607f,
4362                 .flags          = ADDR_TYPE_RT
4363         },
4364         { }
4365 };
4366
4367 /* l4_per -> timer4 */
4368 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4369         .master         = &omap44xx_l4_per_hwmod,
4370         .slave          = &omap44xx_timer4_hwmod,
4371         .clk            = "l4_div_ck",
4372         .addr           = omap44xx_timer4_addrs,
4373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4374 };
4375
4376 /* timer4 slave ports */
4377 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4378         &omap44xx_l4_per__timer4,
4379 };
4380
4381 static struct omap_hwmod omap44xx_timer4_hwmod = {
4382         .name           = "timer4",
4383         .class          = &omap44xx_timer_hwmod_class,
4384         .clkdm_name     = "l4_per_clkdm",
4385         .mpu_irqs       = omap44xx_timer4_irqs,
4386         .main_clk       = "timer4_fck",
4387         .prcm = {
4388                 .omap4 = {
4389                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4390                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4391                         .modulemode   = MODULEMODE_SWCTRL,
4392                 },
4393         },
4394         .dev_attr       = &capability_alwon_dev_attr,
4395         .slaves         = omap44xx_timer4_slaves,
4396         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4397 };
4398
4399 /* timer5 */
4400 static struct omap_hwmod omap44xx_timer5_hwmod;
4401 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4402         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4403         { .irq = -1 }
4404 };
4405
4406 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4407         {
4408                 .pa_start       = 0x40138000,
4409                 .pa_end         = 0x4013807f,
4410                 .flags          = ADDR_TYPE_RT
4411         },
4412         { }
4413 };
4414
4415 /* l4_abe -> timer5 */
4416 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4417         .master         = &omap44xx_l4_abe_hwmod,
4418         .slave          = &omap44xx_timer5_hwmod,
4419         .clk            = "ocp_abe_iclk",
4420         .addr           = omap44xx_timer5_addrs,
4421         .user           = OCP_USER_MPU,
4422 };
4423
4424 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4425         {
4426                 .pa_start       = 0x49038000,
4427                 .pa_end         = 0x4903807f,
4428                 .flags          = ADDR_TYPE_RT
4429         },
4430         { }
4431 };
4432
4433 /* l4_abe -> timer5 (dma) */
4434 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4435         .master         = &omap44xx_l4_abe_hwmod,
4436         .slave          = &omap44xx_timer5_hwmod,
4437         .clk            = "ocp_abe_iclk",
4438         .addr           = omap44xx_timer5_dma_addrs,
4439         .user           = OCP_USER_SDMA,
4440 };
4441
4442 /* timer5 slave ports */
4443 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4444         &omap44xx_l4_abe__timer5,
4445         &omap44xx_l4_abe__timer5_dma,
4446 };
4447
4448 static struct omap_hwmod omap44xx_timer5_hwmod = {
4449         .name           = "timer5",
4450         .class          = &omap44xx_timer_hwmod_class,
4451         .clkdm_name     = "abe_clkdm",
4452         .mpu_irqs       = omap44xx_timer5_irqs,
4453         .main_clk       = "timer5_fck",
4454         .prcm = {
4455                 .omap4 = {
4456                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4457                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4458                         .modulemode   = MODULEMODE_SWCTRL,
4459                 },
4460         },
4461         .dev_attr       = &capability_alwon_dev_attr,
4462         .slaves         = omap44xx_timer5_slaves,
4463         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4464 };
4465
4466 /* timer6 */
4467 static struct omap_hwmod omap44xx_timer6_hwmod;
4468 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4469         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4470         { .irq = -1 }
4471 };
4472
4473 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4474         {
4475                 .pa_start       = 0x4013a000,
4476                 .pa_end         = 0x4013a07f,
4477                 .flags          = ADDR_TYPE_RT
4478         },
4479         { }
4480 };
4481
4482 /* l4_abe -> timer6 */
4483 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4484         .master         = &omap44xx_l4_abe_hwmod,
4485         .slave          = &omap44xx_timer6_hwmod,
4486         .clk            = "ocp_abe_iclk",
4487         .addr           = omap44xx_timer6_addrs,
4488         .user           = OCP_USER_MPU,
4489 };
4490
4491 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4492         {
4493                 .pa_start       = 0x4903a000,
4494                 .pa_end         = 0x4903a07f,
4495                 .flags          = ADDR_TYPE_RT
4496         },
4497         { }
4498 };
4499
4500 /* l4_abe -> timer6 (dma) */
4501 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4502         .master         = &omap44xx_l4_abe_hwmod,
4503         .slave          = &omap44xx_timer6_hwmod,
4504         .clk            = "ocp_abe_iclk",
4505         .addr           = omap44xx_timer6_dma_addrs,
4506         .user           = OCP_USER_SDMA,
4507 };
4508
4509 /* timer6 slave ports */
4510 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4511         &omap44xx_l4_abe__timer6,
4512         &omap44xx_l4_abe__timer6_dma,
4513 };
4514
4515 static struct omap_hwmod omap44xx_timer6_hwmod = {
4516         .name           = "timer6",
4517         .class          = &omap44xx_timer_hwmod_class,
4518         .clkdm_name     = "abe_clkdm",
4519         .mpu_irqs       = omap44xx_timer6_irqs,
4520
4521         .main_clk       = "timer6_fck",
4522         .prcm = {
4523                 .omap4 = {
4524                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4525                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4526                         .modulemode   = MODULEMODE_SWCTRL,
4527                 },
4528         },
4529         .dev_attr       = &capability_alwon_dev_attr,
4530         .slaves         = omap44xx_timer6_slaves,
4531         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4532 };
4533
4534 /* timer7 */
4535 static struct omap_hwmod omap44xx_timer7_hwmod;
4536 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4537         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4538         { .irq = -1 }
4539 };
4540
4541 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4542         {
4543                 .pa_start       = 0x4013c000,
4544                 .pa_end         = 0x4013c07f,
4545                 .flags          = ADDR_TYPE_RT
4546         },
4547         { }
4548 };
4549
4550 /* l4_abe -> timer7 */
4551 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4552         .master         = &omap44xx_l4_abe_hwmod,
4553         .slave          = &omap44xx_timer7_hwmod,
4554         .clk            = "ocp_abe_iclk",
4555         .addr           = omap44xx_timer7_addrs,
4556         .user           = OCP_USER_MPU,
4557 };
4558
4559 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4560         {
4561                 .pa_start       = 0x4903c000,
4562                 .pa_end         = 0x4903c07f,
4563                 .flags          = ADDR_TYPE_RT
4564         },
4565         { }
4566 };
4567
4568 /* l4_abe -> timer7 (dma) */
4569 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4570         .master         = &omap44xx_l4_abe_hwmod,
4571         .slave          = &omap44xx_timer7_hwmod,
4572         .clk            = "ocp_abe_iclk",
4573         .addr           = omap44xx_timer7_dma_addrs,
4574         .user           = OCP_USER_SDMA,
4575 };
4576
4577 /* timer7 slave ports */
4578 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4579         &omap44xx_l4_abe__timer7,
4580         &omap44xx_l4_abe__timer7_dma,
4581 };
4582
4583 static struct omap_hwmod omap44xx_timer7_hwmod = {
4584         .name           = "timer7",
4585         .class          = &omap44xx_timer_hwmod_class,
4586         .clkdm_name     = "abe_clkdm",
4587         .mpu_irqs       = omap44xx_timer7_irqs,
4588         .main_clk       = "timer7_fck",
4589         .prcm = {
4590                 .omap4 = {
4591                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4592                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4593                         .modulemode   = MODULEMODE_SWCTRL,
4594                 },
4595         },
4596         .dev_attr       = &capability_alwon_dev_attr,
4597         .slaves         = omap44xx_timer7_slaves,
4598         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4599 };
4600
4601 /* timer8 */
4602 static struct omap_hwmod omap44xx_timer8_hwmod;
4603 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4604         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4605         { .irq = -1 }
4606 };
4607
4608 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4609         {
4610                 .pa_start       = 0x4013e000,
4611                 .pa_end         = 0x4013e07f,
4612                 .flags          = ADDR_TYPE_RT
4613         },
4614         { }
4615 };
4616
4617 /* l4_abe -> timer8 */
4618 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4619         .master         = &omap44xx_l4_abe_hwmod,
4620         .slave          = &omap44xx_timer8_hwmod,
4621         .clk            = "ocp_abe_iclk",
4622         .addr           = omap44xx_timer8_addrs,
4623         .user           = OCP_USER_MPU,
4624 };
4625
4626 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4627         {
4628                 .pa_start       = 0x4903e000,
4629                 .pa_end         = 0x4903e07f,
4630                 .flags          = ADDR_TYPE_RT
4631         },
4632         { }
4633 };
4634
4635 /* l4_abe -> timer8 (dma) */
4636 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4637         .master         = &omap44xx_l4_abe_hwmod,
4638         .slave          = &omap44xx_timer8_hwmod,
4639         .clk            = "ocp_abe_iclk",
4640         .addr           = omap44xx_timer8_dma_addrs,
4641         .user           = OCP_USER_SDMA,
4642 };
4643
4644 /* timer8 slave ports */
4645 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4646         &omap44xx_l4_abe__timer8,
4647         &omap44xx_l4_abe__timer8_dma,
4648 };
4649
4650 static struct omap_hwmod omap44xx_timer8_hwmod = {
4651         .name           = "timer8",
4652         .class          = &omap44xx_timer_hwmod_class,
4653         .clkdm_name     = "abe_clkdm",
4654         .mpu_irqs       = omap44xx_timer8_irqs,
4655         .main_clk       = "timer8_fck",
4656         .prcm = {
4657                 .omap4 = {
4658                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4659                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4660                         .modulemode   = MODULEMODE_SWCTRL,
4661                 },
4662         },
4663         .dev_attr       = &capability_pwm_dev_attr,
4664         .slaves         = omap44xx_timer8_slaves,
4665         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4666 };
4667
4668 /* timer9 */
4669 static struct omap_hwmod omap44xx_timer9_hwmod;
4670 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4671         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4672         { .irq = -1 }
4673 };
4674
4675 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4676         {
4677                 .pa_start       = 0x4803e000,
4678                 .pa_end         = 0x4803e07f,
4679                 .flags          = ADDR_TYPE_RT
4680         },
4681         { }
4682 };
4683
4684 /* l4_per -> timer9 */
4685 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4686         .master         = &omap44xx_l4_per_hwmod,
4687         .slave          = &omap44xx_timer9_hwmod,
4688         .clk            = "l4_div_ck",
4689         .addr           = omap44xx_timer9_addrs,
4690         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4691 };
4692
4693 /* timer9 slave ports */
4694 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4695         &omap44xx_l4_per__timer9,
4696 };
4697
4698 static struct omap_hwmod omap44xx_timer9_hwmod = {
4699         .name           = "timer9",
4700         .class          = &omap44xx_timer_hwmod_class,
4701         .clkdm_name     = "l4_per_clkdm",
4702         .mpu_irqs       = omap44xx_timer9_irqs,
4703         .main_clk       = "timer9_fck",
4704         .prcm = {
4705                 .omap4 = {
4706                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4707                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4708                         .modulemode   = MODULEMODE_SWCTRL,
4709                 },
4710         },
4711         .dev_attr       = &capability_pwm_dev_attr,
4712         .slaves         = omap44xx_timer9_slaves,
4713         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4714 };
4715
4716 /* timer10 */
4717 static struct omap_hwmod omap44xx_timer10_hwmod;
4718 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4719         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4720         { .irq = -1 }
4721 };
4722
4723 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4724         {
4725                 .pa_start       = 0x48086000,
4726                 .pa_end         = 0x4808607f,
4727                 .flags          = ADDR_TYPE_RT
4728         },
4729         { }
4730 };
4731
4732 /* l4_per -> timer10 */
4733 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4734         .master         = &omap44xx_l4_per_hwmod,
4735         .slave          = &omap44xx_timer10_hwmod,
4736         .clk            = "l4_div_ck",
4737         .addr           = omap44xx_timer10_addrs,
4738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4739 };
4740
4741 /* timer10 slave ports */
4742 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4743         &omap44xx_l4_per__timer10,
4744 };
4745
4746 static struct omap_hwmod omap44xx_timer10_hwmod = {
4747         .name           = "timer10",
4748         .class          = &omap44xx_timer_1ms_hwmod_class,
4749         .clkdm_name     = "l4_per_clkdm",
4750         .mpu_irqs       = omap44xx_timer10_irqs,
4751         .main_clk       = "timer10_fck",
4752         .prcm = {
4753                 .omap4 = {
4754                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4755                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4756                         .modulemode   = MODULEMODE_SWCTRL,
4757                 },
4758         },
4759         .dev_attr       = &capability_pwm_dev_attr,
4760         .slaves         = omap44xx_timer10_slaves,
4761         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4762 };
4763
4764 /* timer11 */
4765 static struct omap_hwmod omap44xx_timer11_hwmod;
4766 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4767         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4768         { .irq = -1 }
4769 };
4770
4771 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4772         {
4773                 .pa_start       = 0x48088000,
4774                 .pa_end         = 0x4808807f,
4775                 .flags          = ADDR_TYPE_RT
4776         },
4777         { }
4778 };
4779
4780 /* l4_per -> timer11 */
4781 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4782         .master         = &omap44xx_l4_per_hwmod,
4783         .slave          = &omap44xx_timer11_hwmod,
4784         .clk            = "l4_div_ck",
4785         .addr           = omap44xx_timer11_addrs,
4786         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4787 };
4788
4789 /* timer11 slave ports */
4790 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4791         &omap44xx_l4_per__timer11,
4792 };
4793
4794 static struct omap_hwmod omap44xx_timer11_hwmod = {
4795         .name           = "timer11",
4796         .class          = &omap44xx_timer_hwmod_class,
4797         .clkdm_name     = "l4_per_clkdm",
4798         .mpu_irqs       = omap44xx_timer11_irqs,
4799         .main_clk       = "timer11_fck",
4800         .prcm = {
4801                 .omap4 = {
4802                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4803                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4804                         .modulemode   = MODULEMODE_SWCTRL,
4805                 },
4806         },
4807         .dev_attr       = &capability_pwm_dev_attr,
4808         .slaves         = omap44xx_timer11_slaves,
4809         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4810 };
4811
4812 /*
4813  * 'uart' class
4814  * universal asynchronous receiver/transmitter (uart)
4815  */
4816
4817 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4818         .rev_offs       = 0x0050,
4819         .sysc_offs      = 0x0054,
4820         .syss_offs      = 0x0058,
4821         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4822                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4823                            SYSS_HAS_RESET_STATUS),
4824         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4825                            SIDLE_SMART_WKUP),
4826         .sysc_fields    = &omap_hwmod_sysc_type1,
4827 };
4828
4829 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4830         .name   = "uart",
4831         .sysc   = &omap44xx_uart_sysc,
4832 };
4833
4834 /* uart1 */
4835 static struct omap_hwmod omap44xx_uart1_hwmod;
4836 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4837         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4838         { .irq = -1 }
4839 };
4840
4841 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4842         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4843         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4844         { .dma_req = -1 }
4845 };
4846
4847 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4848         {
4849                 .pa_start       = 0x4806a000,
4850                 .pa_end         = 0x4806a0ff,
4851                 .flags          = ADDR_TYPE_RT
4852         },
4853         { }
4854 };
4855
4856 /* l4_per -> uart1 */
4857 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4858         .master         = &omap44xx_l4_per_hwmod,
4859         .slave          = &omap44xx_uart1_hwmod,
4860         .clk            = "l4_div_ck",
4861         .addr           = omap44xx_uart1_addrs,
4862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4863 };
4864
4865 /* uart1 slave ports */
4866 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4867         &omap44xx_l4_per__uart1,
4868 };
4869
4870 static struct omap_hwmod omap44xx_uart1_hwmod = {
4871         .name           = "uart1",
4872         .class          = &omap44xx_uart_hwmod_class,
4873         .clkdm_name     = "l4_per_clkdm",
4874         .mpu_irqs       = omap44xx_uart1_irqs,
4875         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4876         .main_clk       = "uart1_fck",
4877         .prcm = {
4878                 .omap4 = {
4879                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4880                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4881                         .modulemode   = MODULEMODE_SWCTRL,
4882                 },
4883         },
4884         .slaves         = omap44xx_uart1_slaves,
4885         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4886 };
4887
4888 /* uart2 */
4889 static struct omap_hwmod omap44xx_uart2_hwmod;
4890 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4891         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4892         { .irq = -1 }
4893 };
4894
4895 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4896         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4897         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4898         { .dma_req = -1 }
4899 };
4900
4901 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4902         {
4903                 .pa_start       = 0x4806c000,
4904                 .pa_end         = 0x4806c0ff,
4905                 .flags          = ADDR_TYPE_RT
4906         },
4907         { }
4908 };
4909
4910 /* l4_per -> uart2 */
4911 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4912         .master         = &omap44xx_l4_per_hwmod,
4913         .slave          = &omap44xx_uart2_hwmod,
4914         .clk            = "l4_div_ck",
4915         .addr           = omap44xx_uart2_addrs,
4916         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4917 };
4918
4919 /* uart2 slave ports */
4920 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4921         &omap44xx_l4_per__uart2,
4922 };
4923
4924 static struct omap_hwmod omap44xx_uart2_hwmod = {
4925         .name           = "uart2",
4926         .class          = &omap44xx_uart_hwmod_class,
4927         .clkdm_name     = "l4_per_clkdm",
4928         .mpu_irqs       = omap44xx_uart2_irqs,
4929         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4930         .main_clk       = "uart2_fck",
4931         .prcm = {
4932                 .omap4 = {
4933                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4934                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4935                         .modulemode   = MODULEMODE_SWCTRL,
4936                 },
4937         },
4938         .slaves         = omap44xx_uart2_slaves,
4939         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4940 };
4941
4942 /* uart3 */
4943 static struct omap_hwmod omap44xx_uart3_hwmod;
4944 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4945         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4946         { .irq = -1 }
4947 };
4948
4949 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4950         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4951         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4952         { .dma_req = -1 }
4953 };
4954
4955 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4956         {
4957                 .pa_start       = 0x48020000,
4958                 .pa_end         = 0x480200ff,
4959                 .flags          = ADDR_TYPE_RT
4960         },
4961         { }
4962 };
4963
4964 /* l4_per -> uart3 */
4965 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4966         .master         = &omap44xx_l4_per_hwmod,
4967         .slave          = &omap44xx_uart3_hwmod,
4968         .clk            = "l4_div_ck",
4969         .addr           = omap44xx_uart3_addrs,
4970         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4971 };
4972
4973 /* uart3 slave ports */
4974 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4975         &omap44xx_l4_per__uart3,
4976 };
4977
4978 static struct omap_hwmod omap44xx_uart3_hwmod = {
4979         .name           = "uart3",
4980         .class          = &omap44xx_uart_hwmod_class,
4981         .clkdm_name     = "l4_per_clkdm",
4982         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4983         .mpu_irqs       = omap44xx_uart3_irqs,
4984         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4985         .main_clk       = "uart3_fck",
4986         .prcm = {
4987                 .omap4 = {
4988                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
4989                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
4990                         .modulemode   = MODULEMODE_SWCTRL,
4991                 },
4992         },
4993         .slaves         = omap44xx_uart3_slaves,
4994         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4995 };
4996
4997 /* uart4 */
4998 static struct omap_hwmod omap44xx_uart4_hwmod;
4999 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5000         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5001         { .irq = -1 }
5002 };
5003
5004 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5005         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5006         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5007         { .dma_req = -1 }
5008 };
5009
5010 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5011         {
5012                 .pa_start       = 0x4806e000,
5013                 .pa_end         = 0x4806e0ff,
5014                 .flags          = ADDR_TYPE_RT
5015         },
5016         { }
5017 };
5018
5019 /* l4_per -> uart4 */
5020 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5021         .master         = &omap44xx_l4_per_hwmod,
5022         .slave          = &omap44xx_uart4_hwmod,
5023         .clk            = "l4_div_ck",
5024         .addr           = omap44xx_uart4_addrs,
5025         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5026 };
5027
5028 /* uart4 slave ports */
5029 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5030         &omap44xx_l4_per__uart4,
5031 };
5032
5033 static struct omap_hwmod omap44xx_uart4_hwmod = {
5034         .name           = "uart4",
5035         .class          = &omap44xx_uart_hwmod_class,
5036         .clkdm_name     = "l4_per_clkdm",
5037         .mpu_irqs       = omap44xx_uart4_irqs,
5038         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
5039         .main_clk       = "uart4_fck",
5040         .prcm = {
5041                 .omap4 = {
5042                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5043                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5044                         .modulemode   = MODULEMODE_SWCTRL,
5045                 },
5046         },
5047         .slaves         = omap44xx_uart4_slaves,
5048         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
5049 };
5050
5051 /*
5052  * 'usb_otg_hs' class
5053  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5054  */
5055
5056 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5057         .rev_offs       = 0x0400,
5058         .sysc_offs      = 0x0404,
5059         .syss_offs      = 0x0408,
5060         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5061                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5062                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5063         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5064                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5065                            MSTANDBY_SMART),
5066         .sysc_fields    = &omap_hwmod_sysc_type1,
5067 };
5068
5069 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5070         .name   = "usb_otg_hs",
5071         .sysc   = &omap44xx_usb_otg_hs_sysc,
5072 };
5073
5074 /* usb_otg_hs */
5075 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5076         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5077         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5078         { .irq = -1 }
5079 };
5080
5081 /* usb_otg_hs master ports */
5082 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5083         &omap44xx_usb_otg_hs__l3_main_2,
5084 };
5085
5086 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5087         {
5088                 .pa_start       = 0x4a0ab000,
5089                 .pa_end         = 0x4a0ab003,
5090                 .flags          = ADDR_TYPE_RT
5091         },
5092         { }
5093 };
5094
5095 /* l4_cfg -> usb_otg_hs */
5096 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5097         .master         = &omap44xx_l4_cfg_hwmod,
5098         .slave          = &omap44xx_usb_otg_hs_hwmod,
5099         .clk            = "l4_div_ck",
5100         .addr           = omap44xx_usb_otg_hs_addrs,
5101         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5102 };
5103
5104 /* usb_otg_hs slave ports */
5105 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5106         &omap44xx_l4_cfg__usb_otg_hs,
5107 };
5108
5109 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5110         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5111 };
5112
5113 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5114         .name           = "usb_otg_hs",
5115         .class          = &omap44xx_usb_otg_hs_hwmod_class,
5116         .clkdm_name     = "l3_init_clkdm",
5117         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5118         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
5119         .main_clk       = "usb_otg_hs_ick",
5120         .prcm = {
5121                 .omap4 = {
5122                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5123                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5124                         .modulemode   = MODULEMODE_HWCTRL,
5125                 },
5126         },
5127         .opt_clks       = usb_otg_hs_opt_clks,
5128         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
5129         .slaves         = omap44xx_usb_otg_hs_slaves,
5130         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5131         .masters        = omap44xx_usb_otg_hs_masters,
5132         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5133 };
5134
5135 /*
5136  * 'wd_timer' class
5137  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5138  * overflow condition
5139  */
5140
5141 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5142         .rev_offs       = 0x0000,
5143         .sysc_offs      = 0x0010,
5144         .syss_offs      = 0x0014,
5145         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5146                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5147         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5148                            SIDLE_SMART_WKUP),
5149         .sysc_fields    = &omap_hwmod_sysc_type1,
5150 };
5151
5152 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5153         .name           = "wd_timer",
5154         .sysc           = &omap44xx_wd_timer_sysc,
5155         .pre_shutdown   = &omap2_wd_timer_disable,
5156 };
5157
5158 /* wd_timer2 */
5159 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5160 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5161         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5162         { .irq = -1 }
5163 };
5164
5165 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5166         {
5167                 .pa_start       = 0x4a314000,
5168                 .pa_end         = 0x4a31407f,
5169                 .flags          = ADDR_TYPE_RT
5170         },
5171         { }
5172 };
5173
5174 /* l4_wkup -> wd_timer2 */
5175 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5176         .master         = &omap44xx_l4_wkup_hwmod,
5177         .slave          = &omap44xx_wd_timer2_hwmod,
5178         .clk            = "l4_wkup_clk_mux_ck",
5179         .addr           = omap44xx_wd_timer2_addrs,
5180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5181 };
5182
5183 /* wd_timer2 slave ports */
5184 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5185         &omap44xx_l4_wkup__wd_timer2,
5186 };
5187
5188 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5189         .name           = "wd_timer2",
5190         .class          = &omap44xx_wd_timer_hwmod_class,
5191         .clkdm_name     = "l4_wkup_clkdm",
5192         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5193         .main_clk       = "wd_timer2_fck",
5194         .prcm = {
5195                 .omap4 = {
5196                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5197                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5198                         .modulemode   = MODULEMODE_SWCTRL,
5199                 },
5200         },
5201         .slaves         = omap44xx_wd_timer2_slaves,
5202         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5203 };
5204
5205 /* wd_timer3 */
5206 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5207 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5208         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5209         { .irq = -1 }
5210 };
5211
5212 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5213         {
5214                 .pa_start       = 0x40130000,
5215                 .pa_end         = 0x4013007f,
5216                 .flags          = ADDR_TYPE_RT
5217         },
5218         { }
5219 };
5220
5221 /* l4_abe -> wd_timer3 */
5222 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5223         .master         = &omap44xx_l4_abe_hwmod,
5224         .slave          = &omap44xx_wd_timer3_hwmod,
5225         .clk            = "ocp_abe_iclk",
5226         .addr           = omap44xx_wd_timer3_addrs,
5227         .user           = OCP_USER_MPU,
5228 };
5229
5230 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5231         {
5232                 .pa_start       = 0x49030000,
5233                 .pa_end         = 0x4903007f,
5234                 .flags          = ADDR_TYPE_RT
5235         },
5236         { }
5237 };
5238
5239 /* l4_abe -> wd_timer3 (dma) */
5240 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5241         .master         = &omap44xx_l4_abe_hwmod,
5242         .slave          = &omap44xx_wd_timer3_hwmod,
5243         .clk            = "ocp_abe_iclk",
5244         .addr           = omap44xx_wd_timer3_dma_addrs,
5245         .user           = OCP_USER_SDMA,
5246 };
5247
5248 /* wd_timer3 slave ports */
5249 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5250         &omap44xx_l4_abe__wd_timer3,
5251         &omap44xx_l4_abe__wd_timer3_dma,
5252 };
5253
5254 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5255         .name           = "wd_timer3",
5256         .class          = &omap44xx_wd_timer_hwmod_class,
5257         .clkdm_name     = "abe_clkdm",
5258         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5259         .main_clk       = "wd_timer3_fck",
5260         .prcm = {
5261                 .omap4 = {
5262                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5263                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5264                         .modulemode   = MODULEMODE_SWCTRL,
5265                 },
5266         },
5267         .slaves         = omap44xx_wd_timer3_slaves,
5268         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5269 };
5270
5271 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5272
5273         /* dmm class */
5274         &omap44xx_dmm_hwmod,
5275
5276         /* emif_fw class */
5277         &omap44xx_emif_fw_hwmod,
5278
5279         /* l3 class */
5280         &omap44xx_l3_instr_hwmod,
5281         &omap44xx_l3_main_1_hwmod,
5282         &omap44xx_l3_main_2_hwmod,
5283         &omap44xx_l3_main_3_hwmod,
5284
5285         /* l4 class */
5286         &omap44xx_l4_abe_hwmod,
5287         &omap44xx_l4_cfg_hwmod,
5288         &omap44xx_l4_per_hwmod,
5289         &omap44xx_l4_wkup_hwmod,
5290
5291         /* mpu_bus class */
5292         &omap44xx_mpu_private_hwmod,
5293
5294         /* aess class */
5295 /*      &omap44xx_aess_hwmod, */
5296
5297         /* bandgap class */
5298         &omap44xx_bandgap_hwmod,
5299
5300         /* counter class */
5301 /*      &omap44xx_counter_32k_hwmod, */
5302
5303         /* dma class */
5304         &omap44xx_dma_system_hwmod,
5305
5306         /* dmic class */
5307         &omap44xx_dmic_hwmod,
5308
5309         /* dsp class */
5310         &omap44xx_dsp_hwmod,
5311         &omap44xx_dsp_c0_hwmod,
5312
5313         /* dss class */
5314         &omap44xx_dss_hwmod,
5315         &omap44xx_dss_dispc_hwmod,
5316         &omap44xx_dss_dsi1_hwmod,
5317         &omap44xx_dss_dsi2_hwmod,
5318         &omap44xx_dss_hdmi_hwmod,
5319         &omap44xx_dss_rfbi_hwmod,
5320         &omap44xx_dss_venc_hwmod,
5321
5322         /* gpio class */
5323         &omap44xx_gpio1_hwmod,
5324         &omap44xx_gpio2_hwmod,
5325         &omap44xx_gpio3_hwmod,
5326         &omap44xx_gpio4_hwmod,
5327         &omap44xx_gpio5_hwmod,
5328         &omap44xx_gpio6_hwmod,
5329
5330         /* hsi class */
5331 /*      &omap44xx_hsi_hwmod, */
5332
5333         /* i2c class */
5334         &omap44xx_i2c1_hwmod,
5335         &omap44xx_i2c2_hwmod,
5336         &omap44xx_i2c3_hwmod,
5337         &omap44xx_i2c4_hwmod,
5338
5339         /* ipu class */
5340         &omap44xx_ipu_hwmod,
5341         &omap44xx_ipu_c0_hwmod,
5342         &omap44xx_ipu_c1_hwmod,
5343
5344         /* iss class */
5345 /*      &omap44xx_iss_hwmod, */
5346
5347         /* iva class */
5348         &omap44xx_iva_hwmod,
5349         &omap44xx_iva_seq0_hwmod,
5350         &omap44xx_iva_seq1_hwmod,
5351
5352         /* kbd class */
5353         &omap44xx_kbd_hwmod,
5354
5355         /* mailbox class */
5356         &omap44xx_mailbox_hwmod,
5357
5358         /* mcbsp class */
5359         &omap44xx_mcbsp1_hwmod,
5360         &omap44xx_mcbsp2_hwmod,
5361         &omap44xx_mcbsp3_hwmod,
5362         &omap44xx_mcbsp4_hwmod,
5363
5364         /* mcpdm class */
5365         &omap44xx_mcpdm_hwmod,
5366
5367         /* mcspi class */
5368         &omap44xx_mcspi1_hwmod,
5369         &omap44xx_mcspi2_hwmod,
5370         &omap44xx_mcspi3_hwmod,
5371         &omap44xx_mcspi4_hwmod,
5372
5373         /* mmc class */
5374         &omap44xx_mmc1_hwmod,
5375         &omap44xx_mmc2_hwmod,
5376         &omap44xx_mmc3_hwmod,
5377         &omap44xx_mmc4_hwmod,
5378         &omap44xx_mmc5_hwmod,
5379
5380         /* mpu class */
5381         &omap44xx_mpu_hwmod,
5382
5383         /* smartreflex class */
5384         &omap44xx_smartreflex_core_hwmod,
5385         &omap44xx_smartreflex_iva_hwmod,
5386         &omap44xx_smartreflex_mpu_hwmod,
5387
5388         /* spinlock class */
5389         &omap44xx_spinlock_hwmod,
5390
5391         /* timer class */
5392         &omap44xx_timer1_hwmod,
5393         &omap44xx_timer2_hwmod,
5394         &omap44xx_timer3_hwmod,
5395         &omap44xx_timer4_hwmod,
5396         &omap44xx_timer5_hwmod,
5397         &omap44xx_timer6_hwmod,
5398         &omap44xx_timer7_hwmod,
5399         &omap44xx_timer8_hwmod,
5400         &omap44xx_timer9_hwmod,
5401         &omap44xx_timer10_hwmod,
5402         &omap44xx_timer11_hwmod,
5403
5404         /* uart class */
5405         &omap44xx_uart1_hwmod,
5406         &omap44xx_uart2_hwmod,
5407         &omap44xx_uart3_hwmod,
5408         &omap44xx_uart4_hwmod,
5409
5410         /* usb_otg_hs class */
5411         &omap44xx_usb_otg_hs_hwmod,
5412
5413         /* wd_timer class */
5414         &omap44xx_wd_timer2_hwmod,
5415         &omap44xx_wd_timer3_hwmod,
5416
5417         NULL,
5418 };
5419
5420 int __init omap44xx_hwmod_init(void)
5421 {
5422         return omap_hwmod_register(omap44xx_hwmods);
5423 }
5424