arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22 #include <linux/platform_data/gpio-omap.h>
  23 #include <linux/power/smartreflex.h>
  24 #include <linux/platform_data/omap_ocp2scp.h>
  25 #include <linux/i2c-omap.h>
  26
  27 #include <linux/omap-dma.h>
  28
  29 #include <linux/platform_data/spi-omap2-mcspi.h>
  30 #include <linux/platform_data/asoc-ti-mcbsp.h>
  31 #include <linux/platform_data/iommu-omap.h>
  32 #include <plat/dmtimer.h>
  33
  34 #include "omap_hwmod.h"
  35 #include "omap_hwmod_common_data.h"
  36 #include "cm1_44xx.h"
  37 #include "cm2_44xx.h"
  38 #include "prm44xx.h"
  39 #include "prm-regbits-44xx.h"
  40 #include "i2c.h"
  41 #include "mmc.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /*
  51  * IP blocks
  52  */
  53
  54 /*
  55  * 'c2c_target_fw' class
  56  * instance(s): c2c_target_fw
  57  */
  58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
  59         .name   = "c2c_target_fw",
  60 };
  61
  62 /* c2c_target_fw */
  63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
  64         .name           = "c2c_target_fw",
  65         .class          = &omap44xx_c2c_target_fw_hwmod_class,
  66         .clkdm_name     = "d2d_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
  70                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
  71                 },
  72         },
  73 };
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm */
  84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  86         { .irq = -1 }
  87 };
  88
  89 static struct omap_hwmod omap44xx_dmm_hwmod = {
  90         .name           = "dmm",
  91         .class          = &omap44xx_dmm_hwmod_class,
  92         .clkdm_name     = "l3_emif_clkdm",
  93         .mpu_irqs       = omap44xx_dmm_irqs,
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  97                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  98                 },
  99         },
 100 };
 101
 102 /*
 103  * 'emif_fw' class
 104  * instance(s): emif_fw
 105  */
 106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 107         .name   = "emif_fw",
 108 };
 109
 110 /* emif_fw */
 111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 112         .name           = "emif_fw",
 113         .class          = &omap44xx_emif_fw_hwmod_class,
 114         .clkdm_name     = "l3_emif_clkdm",
 115         .prcm = {
 116                 .omap4 = {
 117                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 118                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 119                 },
 120         },
 121 };
 122
 123 /*
 124  * 'l3' class
 125  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 126  */
 127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 128         .name   = "l3",
 129 };
 130
 131 /* l3_instr */
 132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 133         .name           = "l3_instr",
 134         .class          = &omap44xx_l3_hwmod_class,
 135         .clkdm_name     = "l3_instr_clkdm",
 136         .prcm = {
 137                 .omap4 = {
 138                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 139                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 140                         .modulemode   = MODULEMODE_HWCTRL,
 141                 },
 142         },
 143 };
 144
 145 /* l3_main_1 */
 146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 147         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 148         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 149         { .irq = -1 }
 150 };
 151
 152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 153         .name           = "l3_main_1",
 154         .class          = &omap44xx_l3_hwmod_class,
 155         .clkdm_name     = "l3_1_clkdm",
 156         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 157         .prcm = {
 158                 .omap4 = {
 159                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 160                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 161                 },
 162         },
 163 };
 164
 165 /* l3_main_2 */
 166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 167         .name           = "l3_main_2",
 168         .class          = &omap44xx_l3_hwmod_class,
 169         .clkdm_name     = "l3_2_clkdm",
 170         .prcm = {
 171                 .omap4 = {
 172                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 173                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 174                 },
 175         },
 176 };
 177
 178 /* l3_main_3 */
 179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 180         .name           = "l3_main_3",
 181         .class          = &omap44xx_l3_hwmod_class,
 182         .clkdm_name     = "l3_instr_clkdm",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 186                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 187                         .modulemode   = MODULEMODE_HWCTRL,
 188                 },
 189         },
 190 };
 191
 192 /*
 193  * 'l4' class
 194  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 195  */
 196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 197         .name   = "l4",
 198 };
 199
 200 /* l4_abe */
 201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 202         .name           = "l4_abe",
 203         .class          = &omap44xx_l4_hwmod_class,
 204         .clkdm_name     = "abe_clkdm",
 205         .prcm = {
 206                 .omap4 = {
 207                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 208                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 209                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 210                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 211                 },
 212         },
 213 };
 214
 215 /* l4_cfg */
 216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 217         .name           = "l4_cfg",
 218         .class          = &omap44xx_l4_hwmod_class,
 219         .clkdm_name     = "l4_cfg_clkdm",
 220         .prcm = {
 221                 .omap4 = {
 222                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 223                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 224                 },
 225         },
 226 };
 227
 228 /* l4_per */
 229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 230         .name           = "l4_per",
 231         .class          = &omap44xx_l4_hwmod_class,
 232         .clkdm_name     = "l4_per_clkdm",
 233         .prcm = {
 234                 .omap4 = {
 235                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 236                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 237                 },
 238         },
 239 };
 240
 241 /* l4_wkup */
 242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 243         .name           = "l4_wkup",
 244         .class          = &omap44xx_l4_hwmod_class,
 245         .clkdm_name     = "l4_wkup_clkdm",
 246         .prcm = {
 247                 .omap4 = {
 248                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 249                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 250                 },
 251         },
 252 };
 253
 254 /*
 255  * 'mpu_bus' class
 256  * instance(s): mpu_private
 257  */
 258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 259         .name   = "mpu_bus",
 260 };
 261
 262 /* mpu_private */
 263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 264         .name           = "mpu_private",
 265         .class          = &omap44xx_mpu_bus_hwmod_class,
 266         .clkdm_name     = "mpuss_clkdm",
 267         .prcm = {
 268                 .omap4 = {
 269                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 270                 },
 271         },
 272 };
 273
 274 /*
 275  * 'ocp_wp_noc' class
 276  * instance(s): ocp_wp_noc
 277  */
 278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 279         .name   = "ocp_wp_noc",
 280 };
 281
 282 /* ocp_wp_noc */
 283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 284         .name           = "ocp_wp_noc",
 285         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 286         .clkdm_name     = "l3_instr_clkdm",
 287         .prcm = {
 288                 .omap4 = {
 289                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 290                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 291                         .modulemode   = MODULEMODE_HWCTRL,
 292                 },
 293         },
 294 };
 295
 296 /*
 297  * Modules omap_hwmod structures
 298  *
 299  * The following IPs are excluded for the moment because:
 300  * - They do not need an explicit SW control using omap_hwmod API.
 301  * - They still need to be validated with the driver
 302  *   properly adapted to omap_hwmod / omap_device
 303  *
 304  * usim
 305  */
 306
 307 /*
 308  * 'aess' class
 309  * audio engine sub system
 310  */
 311
 312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 313         .rev_offs       = 0x0000,
 314         .sysc_offs      = 0x0010,
 315         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 317                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 318                            MSTANDBY_SMART_WKUP),
 319         .sysc_fields    = &omap_hwmod_sysc_type2,
 320 };
 321
 322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 323         .name   = "aess",
 324         .sysc   = &omap44xx_aess_sysc,
 325 };
 326
 327 /* aess */
 328 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 329         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 330         { .irq = -1 }
 331 };
 332
 333 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 334         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 335         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 336         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 337         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 338         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 339         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 340         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 341         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 342         { .dma_req = -1 }
 343 };
 344
 345 static struct omap_hwmod omap44xx_aess_hwmod = {
 346         .name           = "aess",
 347         .class          = &omap44xx_aess_hwmod_class,
 348         .clkdm_name     = "abe_clkdm",
 349         .mpu_irqs       = omap44xx_aess_irqs,
 350         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 351         .main_clk       = "aess_fck",
 352         .prcm = {
 353                 .omap4 = {
 354                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 355                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 356                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 357                         .modulemode   = MODULEMODE_SWCTRL,
 358                 },
 359         },
 360 };
 361
 362 /*
 363  * 'c2c' class
 364  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 365  * soc
 366  */
 367
 368 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 369         .name   = "c2c",
 370 };
 371
 372 /* c2c */
 373 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
 374         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
 375         { .irq = -1 }
 376 };
 377
 378 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
 379         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
 380         { .dma_req = -1 }
 381 };
 382
 383 static struct omap_hwmod omap44xx_c2c_hwmod = {
 384         .name           = "c2c",
 385         .class          = &omap44xx_c2c_hwmod_class,
 386         .clkdm_name     = "d2d_clkdm",
 387         .mpu_irqs       = omap44xx_c2c_irqs,
 388         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
 389         .prcm = {
 390                 .omap4 = {
 391                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 392                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 393                 },
 394         },
 395 };
 396
 397 /*
 398  * 'counter' class
 399  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 400  */
 401
 402 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 403         .rev_offs       = 0x0000,
 404         .sysc_offs      = 0x0004,
 405         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
 407         .sysc_fields    = &omap_hwmod_sysc_type1,
 408 };
 409
 410 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 411         .name   = "counter",
 412         .sysc   = &omap44xx_counter_sysc,
 413 };
 414
 415 /* counter_32k */
 416 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 417         .name           = "counter_32k",
 418         .class          = &omap44xx_counter_hwmod_class,
 419         .clkdm_name     = "l4_wkup_clkdm",
 420         .flags          = HWMOD_SWSUP_SIDLE,
 421         .main_clk       = "sys_32k_ck",
 422         .prcm = {
 423                 .omap4 = {
 424                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 425                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 426                 },
 427         },
 428 };
 429
 430 /*
 431  * 'ctrl_module' class
 432  * attila core control module + core pad control module + wkup pad control
 433  * module + attila wkup control module
 434  */
 435
 436 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 437         .rev_offs       = 0x0000,
 438         .sysc_offs      = 0x0010,
 439         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 441                            SIDLE_SMART_WKUP),
 442         .sysc_fields    = &omap_hwmod_sysc_type2,
 443 };
 444
 445 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 446         .name   = "ctrl_module",
 447         .sysc   = &omap44xx_ctrl_module_sysc,
 448 };
 449
 450 /* ctrl_module_core */
 451 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
 452         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
 453         { .irq = -1 }
 454 };
 455
 456 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 457         .name           = "ctrl_module_core",
 458         .class          = &omap44xx_ctrl_module_hwmod_class,
 459         .clkdm_name     = "l4_cfg_clkdm",
 460         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
 461         .prcm = {
 462                 .omap4 = {
 463                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 464                 },
 465         },
 466 };
 467
 468 /* ctrl_module_pad_core */
 469 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 470         .name           = "ctrl_module_pad_core",
 471         .class          = &omap44xx_ctrl_module_hwmod_class,
 472         .clkdm_name     = "l4_cfg_clkdm",
 473         .prcm = {
 474                 .omap4 = {
 475                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 476                 },
 477         },
 478 };
 479
 480 /* ctrl_module_wkup */
 481 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 482         .name           = "ctrl_module_wkup",
 483         .class          = &omap44xx_ctrl_module_hwmod_class,
 484         .clkdm_name     = "l4_wkup_clkdm",
 485         .prcm = {
 486                 .omap4 = {
 487                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 488                 },
 489         },
 490 };
 491
 492 /* ctrl_module_pad_wkup */
 493 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 494         .name           = "ctrl_module_pad_wkup",
 495         .class          = &omap44xx_ctrl_module_hwmod_class,
 496         .clkdm_name     = "l4_wkup_clkdm",
 497         .prcm = {
 498                 .omap4 = {
 499                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 500                 },
 501         },
 502 };
 503
 504 /*
 505  * 'debugss' class
 506  * debug and emulation sub system
 507  */
 508
 509 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 510         .name   = "debugss",
 511 };
 512
 513 /* debugss */
 514 static struct omap_hwmod omap44xx_debugss_hwmod = {
 515         .name           = "debugss",
 516         .class          = &omap44xx_debugss_hwmod_class,
 517         .clkdm_name     = "emu_sys_clkdm",
 518         .main_clk       = "trace_clk_div_ck",
 519         .prcm = {
 520                 .omap4 = {
 521                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 522                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 523                 },
 524         },
 525 };
 526
 527 /*
 528  * 'dma' class
 529  * dma controller for data exchange between memory to memory (i.e. internal or
 530  * external memory) and gp peripherals to memory or memory to gp peripherals
 531  */
 532
 533 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 534         .rev_offs       = 0x0000,
 535         .sysc_offs      = 0x002c,
 536         .syss_offs      = 0x0028,
 537         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 538                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 539                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 540                            SYSS_HAS_RESET_STATUS),
 541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 542                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 543         .sysc_fields    = &omap_hwmod_sysc_type1,
 544 };
 545
 546 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 547         .name   = "dma",
 548         .sysc   = &omap44xx_dma_sysc,
 549 };
 550
 551 /* dma dev_attr */
 552 static struct omap_dma_dev_attr dma_dev_attr = {
 553         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 554                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 555         .lch_count      = 32,
 556 };
 557
 558 /* dma_system */
 559 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 560         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 561         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 562         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 563         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 564         { .irq = -1 }
 565 };
 566
 567 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 568         .name           = "dma_system",
 569         .class          = &omap44xx_dma_hwmod_class,
 570         .clkdm_name     = "l3_dma_clkdm",
 571         .mpu_irqs       = omap44xx_dma_system_irqs,
 572         .main_clk       = "l3_div_ck",
 573         .prcm = {
 574                 .omap4 = {
 575                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 576                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 577                 },
 578         },
 579         .dev_attr       = &dma_dev_attr,
 580 };
 581
 582 /*
 583  * 'dmic' class
 584  * digital microphone controller
 585  */
 586
 587 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 588         .rev_offs       = 0x0000,
 589         .sysc_offs      = 0x0010,
 590         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 591                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 592         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 593                            SIDLE_SMART_WKUP),
 594         .sysc_fields    = &omap_hwmod_sysc_type2,
 595 };
 596
 597 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 598         .name   = "dmic",
 599         .sysc   = &omap44xx_dmic_sysc,
 600 };
 601
 602 /* dmic */
 603 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 604         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 605         { .irq = -1 }
 606 };
 607
 608 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 609         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 610         { .dma_req = -1 }
 611 };
 612
 613 static struct omap_hwmod omap44xx_dmic_hwmod = {
 614         .name           = "dmic",
 615         .class          = &omap44xx_dmic_hwmod_class,
 616         .clkdm_name     = "abe_clkdm",
 617         .mpu_irqs       = omap44xx_dmic_irqs,
 618         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 619         .main_clk       = "dmic_fck",
 620         .prcm = {
 621                 .omap4 = {
 622                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 623                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 624                         .modulemode   = MODULEMODE_SWCTRL,
 625                 },
 626         },
 627 };
 628
 629 /*
 630  * 'dsp' class
 631  * dsp sub-system
 632  */
 633
 634 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 635         .name   = "dsp",
 636 };
 637
 638 /* dsp */
 639 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 640         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 641         { .irq = -1 }
 642 };
 643
 644 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 645         { .name = "dsp", .rst_shift = 0 },
 646 };
 647
 648 static struct omap_hwmod omap44xx_dsp_hwmod = {
 649         .name           = "dsp",
 650         .class          = &omap44xx_dsp_hwmod_class,
 651         .clkdm_name     = "tesla_clkdm",
 652         .mpu_irqs       = omap44xx_dsp_irqs,
 653         .rst_lines      = omap44xx_dsp_resets,
 654         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 655         .main_clk       = "dpll_iva_m4x2_ck",
 656         .prcm = {
 657                 .omap4 = {
 658                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 659                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 660                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 661                         .modulemode   = MODULEMODE_HWCTRL,
 662                 },
 663         },
 664 };
 665
 666 /*
 667  * 'dss' class
 668  * display sub-system
 669  */
 670
 671 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 672         .rev_offs       = 0x0000,
 673         .syss_offs      = 0x0014,
 674         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 675 };
 676
 677 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 678         .name   = "dss",
 679         .sysc   = &omap44xx_dss_sysc,
 680         .reset  = omap_dss_reset,
 681 };
 682
 683 /* dss */
 684 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 685         { .role = "sys_clk", .clk = "dss_sys_clk" },
 686         { .role = "tv_clk", .clk = "dss_tv_clk" },
 687         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 688 };
 689
 690 static struct omap_hwmod omap44xx_dss_hwmod = {
 691         .name           = "dss_core",
 692         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 693         .class          = &omap44xx_dss_hwmod_class,
 694         .clkdm_name     = "l3_dss_clkdm",
 695         .main_clk       = "dss_dss_clk",
 696         .prcm = {
 697                 .omap4 = {
 698                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 699                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 700                 },
 701         },
 702         .opt_clks       = dss_opt_clks,
 703         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
 704 };
 705
 706 /*
 707  * 'dispc' class
 708  * display controller
 709  */
 710
 711 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 712         .rev_offs       = 0x0000,
 713         .sysc_offs      = 0x0010,
 714         .syss_offs      = 0x0014,
 715         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 716                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 717                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 718                            SYSS_HAS_RESET_STATUS),
 719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 720                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 721         .sysc_fields    = &omap_hwmod_sysc_type1,
 722 };
 723
 724 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 725         .name   = "dispc",
 726         .sysc   = &omap44xx_dispc_sysc,
 727 };
 728
 729 /* dss_dispc */
 730 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
 731         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
 732         { .irq = -1 }
 733 };
 734
 735 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
 736         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
 737         { .dma_req = -1 }
 738 };
 739
 740 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 741         .manager_count          = 3,
 742         .has_framedonetv_irq    = 1
 743 };
 744
 745 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 746         .name           = "dss_dispc",
 747         .class          = &omap44xx_dispc_hwmod_class,
 748         .clkdm_name     = "l3_dss_clkdm",
 749         .mpu_irqs       = omap44xx_dss_dispc_irqs,
 750         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
 751         .main_clk       = "dss_dss_clk",
 752         .prcm = {
 753                 .omap4 = {
 754                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 755                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 756                 },
 757         },
 758         .dev_attr       = &omap44xx_dss_dispc_dev_attr
 759 };
 760
 761 /*
 762  * 'dsi' class
 763  * display serial interface controller
 764  */
 765
 766 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 767         .rev_offs       = 0x0000,
 768         .sysc_offs      = 0x0010,
 769         .syss_offs      = 0x0014,
 770         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 771                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 772                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 774         .sysc_fields    = &omap_hwmod_sysc_type1,
 775 };
 776
 777 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 778         .name   = "dsi",
 779         .sysc   = &omap44xx_dsi_sysc,
 780 };
 781
 782 /* dss_dsi1 */
 783 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
 784         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
 785         { .irq = -1 }
 786 };
 787
 788 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
 789         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
 790         { .dma_req = -1 }
 791 };
 792
 793 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 794         { .role = "sys_clk", .clk = "dss_sys_clk" },
 795 };
 796
 797 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 798         .name           = "dss_dsi1",
 799         .class          = &omap44xx_dsi_hwmod_class,
 800         .clkdm_name     = "l3_dss_clkdm",
 801         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
 802         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
 803         .main_clk       = "dss_dss_clk",
 804         .prcm = {
 805                 .omap4 = {
 806                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 807                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 808                 },
 809         },
 810         .opt_clks       = dss_dsi1_opt_clks,
 811         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 812 };
 813
 814 /* dss_dsi2 */
 815 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
 816         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
 817         { .irq = -1 }
 818 };
 819
 820 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
 821         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
 822         { .dma_req = -1 }
 823 };
 824
 825 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 826         { .role = "sys_clk", .clk = "dss_sys_clk" },
 827 };
 828
 829 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 830         .name           = "dss_dsi2",
 831         .class          = &omap44xx_dsi_hwmod_class,
 832         .clkdm_name     = "l3_dss_clkdm",
 833         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
 834         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
 835         .main_clk       = "dss_dss_clk",
 836         .prcm = {
 837                 .omap4 = {
 838                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 839                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 840                 },
 841         },
 842         .opt_clks       = dss_dsi2_opt_clks,
 843         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
 844 };
 845
 846 /*
 847  * 'hdmi' class
 848  * hdmi controller
 849  */
 850
 851 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 852         .rev_offs       = 0x0000,
 853         .sysc_offs      = 0x0010,
 854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 855                            SYSC_HAS_SOFTRESET),
 856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 857                            SIDLE_SMART_WKUP),
 858         .sysc_fields    = &omap_hwmod_sysc_type2,
 859 };
 860
 861 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 862         .name   = "hdmi",
 863         .sysc   = &omap44xx_hdmi_sysc,
 864 };
 865
 866 /* dss_hdmi */
 867 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
 868         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
 869         { .irq = -1 }
 870 };
 871
 872 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
 873         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
 874         { .dma_req = -1 }
 875 };
 876
 877 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 878         { .role = "sys_clk", .clk = "dss_sys_clk" },
 879 };
 880
 881 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 882         .name           = "dss_hdmi",
 883         .class          = &omap44xx_hdmi_hwmod_class,
 884         .clkdm_name     = "l3_dss_clkdm",
 885         /*
 886          * HDMI audio requires to use no-idle mode. Hence,
 887          * set idle mode by software.
 888          */
 889         .flags          = HWMOD_SWSUP_SIDLE,
 890         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
 891         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
 892         .main_clk       = "dss_48mhz_clk",
 893         .prcm = {
 894                 .omap4 = {
 895                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 896                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 897                 },
 898         },
 899         .opt_clks       = dss_hdmi_opt_clks,
 900         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
 901 };
 902
 903 /*
 904  * 'rfbi' class
 905  * remote frame buffer interface
 906  */
 907
 908 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 909         .rev_offs       = 0x0000,
 910         .sysc_offs      = 0x0010,
 911         .syss_offs      = 0x0014,
 912         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 913                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 914         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 915         .sysc_fields    = &omap_hwmod_sysc_type1,
 916 };
 917
 918 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 919         .name   = "rfbi",
 920         .sysc   = &omap44xx_rfbi_sysc,
 921 };
 922
 923 /* dss_rfbi */
 924 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
 925         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
 926         { .dma_req = -1 }
 927 };
 928
 929 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 930         { .role = "ick", .clk = "dss_fck" },
 931 };
 932
 933 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 934         .name           = "dss_rfbi",
 935         .class          = &omap44xx_rfbi_hwmod_class,
 936         .clkdm_name     = "l3_dss_clkdm",
 937         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
 938         .main_clk       = "dss_dss_clk",
 939         .prcm = {
 940                 .omap4 = {
 941                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 942                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 943                 },
 944         },
 945         .opt_clks       = dss_rfbi_opt_clks,
 946         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 947 };
 948
 949 /*
 950  * 'venc' class
 951  * video encoder
 952  */
 953
 954 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 955         .name   = "venc",
 956 };
 957
 958 /* dss_venc */
 959 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 960         .name           = "dss_venc",
 961         .class          = &omap44xx_venc_hwmod_class,
 962         .clkdm_name     = "l3_dss_clkdm",
 963         .main_clk       = "dss_tv_clk",
 964         .prcm = {
 965                 .omap4 = {
 966                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 967                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 968                 },
 969         },
 970 };
 971
 972 /*
 973  * 'elm' class
 974  * bch error location module
 975  */
 976
 977 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 978         .rev_offs       = 0x0000,
 979         .sysc_offs      = 0x0010,
 980         .syss_offs      = 0x0014,
 981         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 982                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 983                            SYSS_HAS_RESET_STATUS),
 984         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 985         .sysc_fields    = &omap_hwmod_sysc_type1,
 986 };
 987
 988 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 989         .name   = "elm",
 990         .sysc   = &omap44xx_elm_sysc,
 991 };
 992
 993 /* elm */
 994 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
 995         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
 996         { .irq = -1 }
 997 };
 998
 999 static struct omap_hwmod omap44xx_elm_hwmod = {
1000         .name           = "elm",
1001         .class          = &omap44xx_elm_hwmod_class,
1002         .clkdm_name     = "l4_per_clkdm",
1003         .mpu_irqs       = omap44xx_elm_irqs,
1004         .prcm = {
1005                 .omap4 = {
1006                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1007                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1008                 },
1009         },
1010 };
1011
1012 /*
1013  * 'emif' class
1014  * external memory interface no1
1015  */
1016
1017 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1018         .rev_offs       = 0x0000,
1019 };
1020
1021 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1022         .name   = "emif",
1023         .sysc   = &omap44xx_emif_sysc,
1024 };
1025
1026 /* emif1 */
1027 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1028         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1029         { .irq = -1 }
1030 };
1031
1032 static struct omap_hwmod omap44xx_emif1_hwmod = {
1033         .name           = "emif1",
1034         .class          = &omap44xx_emif_hwmod_class,
1035         .clkdm_name     = "l3_emif_clkdm",
1036         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1037         .mpu_irqs       = omap44xx_emif1_irqs,
1038         .main_clk       = "ddrphy_ck",
1039         .prcm = {
1040                 .omap4 = {
1041                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1042                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1043                         .modulemode   = MODULEMODE_HWCTRL,
1044                 },
1045         },
1046 };
1047
1048 /* emif2 */
1049 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1050         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1051         { .irq = -1 }
1052 };
1053
1054 static struct omap_hwmod omap44xx_emif2_hwmod = {
1055         .name           = "emif2",
1056         .class          = &omap44xx_emif_hwmod_class,
1057         .clkdm_name     = "l3_emif_clkdm",
1058         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1059         .mpu_irqs       = omap44xx_emif2_irqs,
1060         .main_clk       = "ddrphy_ck",
1061         .prcm = {
1062                 .omap4 = {
1063                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1064                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1065                         .modulemode   = MODULEMODE_HWCTRL,
1066                 },
1067         },
1068 };
1069
1070 /*
1071  * 'fdif' class
1072  * face detection hw accelerator module
1073  */
1074
1075 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1076         .rev_offs       = 0x0000,
1077         .sysc_offs      = 0x0010,
1078         /*
1079          * FDIF needs 100 OCP clk cycles delay after a softreset before
1080          * accessing sysconfig again.
1081          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1082          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1083          *
1084          * TODO: Indicate errata when available.
1085          */
1086         .srst_udelay    = 2,
1087         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1088                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1089         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1091         .sysc_fields    = &omap_hwmod_sysc_type2,
1092 };
1093
1094 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1095         .name   = "fdif",
1096         .sysc   = &omap44xx_fdif_sysc,
1097 };
1098
1099 /* fdif */
1100 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1101         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1102         { .irq = -1 }
1103 };
1104
1105 static struct omap_hwmod omap44xx_fdif_hwmod = {
1106         .name           = "fdif",
1107         .class          = &omap44xx_fdif_hwmod_class,
1108         .clkdm_name     = "iss_clkdm",
1109         .mpu_irqs       = omap44xx_fdif_irqs,
1110         .main_clk       = "fdif_fck",
1111         .prcm = {
1112                 .omap4 = {
1113                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1114                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1115                         .modulemode   = MODULEMODE_SWCTRL,
1116                 },
1117         },
1118 };
1119
1120 /*
1121  * 'gpio' class
1122  * general purpose io module
1123  */
1124
1125 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1126         .rev_offs       = 0x0000,
1127         .sysc_offs      = 0x0010,
1128         .syss_offs      = 0x0114,
1129         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1130                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1131                            SYSS_HAS_RESET_STATUS),
1132         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1133                            SIDLE_SMART_WKUP),
1134         .sysc_fields    = &omap_hwmod_sysc_type1,
1135 };
1136
1137 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1138         .name   = "gpio",
1139         .sysc   = &omap44xx_gpio_sysc,
1140         .rev    = 2,
1141 };
1142
1143 /* gpio dev_attr */
1144 static struct omap_gpio_dev_attr gpio_dev_attr = {
1145         .bank_width     = 32,
1146         .dbck_flag      = true,
1147 };
1148
1149 /* gpio1 */
1150 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1151         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1152         { .irq = -1 }
1153 };
1154
1155 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1156         { .role = "dbclk", .clk = "gpio1_dbclk" },
1157 };
1158
1159 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1160         .name           = "gpio1",
1161         .class          = &omap44xx_gpio_hwmod_class,
1162         .clkdm_name     = "l4_wkup_clkdm",
1163         .mpu_irqs       = omap44xx_gpio1_irqs,
1164         .main_clk       = "gpio1_ick",
1165         .prcm = {
1166                 .omap4 = {
1167                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1168                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1169                         .modulemode   = MODULEMODE_HWCTRL,
1170                 },
1171         },
1172         .opt_clks       = gpio1_opt_clks,
1173         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1174         .dev_attr       = &gpio_dev_attr,
1175 };
1176
1177 /* gpio2 */
1178 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1179         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1180         { .irq = -1 }
1181 };
1182
1183 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1184         { .role = "dbclk", .clk = "gpio2_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1188         .name           = "gpio2",
1189         .class          = &omap44xx_gpio_hwmod_class,
1190         .clkdm_name     = "l4_per_clkdm",
1191         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192         .mpu_irqs       = omap44xx_gpio2_irqs,
1193         .main_clk       = "gpio2_ick",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201         .opt_clks       = gpio2_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1203         .dev_attr       = &gpio_dev_attr,
1204 };
1205
1206 /* gpio3 */
1207 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1208         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1209         { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1213         { .role = "dbclk", .clk = "gpio3_dbclk" },
1214 };
1215
1216 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1217         .name           = "gpio3",
1218         .class          = &omap44xx_gpio_hwmod_class,
1219         .clkdm_name     = "l4_per_clkdm",
1220         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221         .mpu_irqs       = omap44xx_gpio3_irqs,
1222         .main_clk       = "gpio3_ick",
1223         .prcm = {
1224                 .omap4 = {
1225                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1226                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1227                         .modulemode   = MODULEMODE_HWCTRL,
1228                 },
1229         },
1230         .opt_clks       = gpio3_opt_clks,
1231         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1232         .dev_attr       = &gpio_dev_attr,
1233 };
1234
1235 /* gpio4 */
1236 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1237         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1238         { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1242         { .role = "dbclk", .clk = "gpio4_dbclk" },
1243 };
1244
1245 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1246         .name           = "gpio4",
1247         .class          = &omap44xx_gpio_hwmod_class,
1248         .clkdm_name     = "l4_per_clkdm",
1249         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250         .mpu_irqs       = omap44xx_gpio4_irqs,
1251         .main_clk       = "gpio4_ick",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1256                         .modulemode   = MODULEMODE_HWCTRL,
1257                 },
1258         },
1259         .opt_clks       = gpio4_opt_clks,
1260         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1261         .dev_attr       = &gpio_dev_attr,
1262 };
1263
1264 /* gpio5 */
1265 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1266         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1267         { .irq = -1 }
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1271         { .role = "dbclk", .clk = "gpio5_dbclk" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1275         .name           = "gpio5",
1276         .class          = &omap44xx_gpio_hwmod_class,
1277         .clkdm_name     = "l4_per_clkdm",
1278         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279         .mpu_irqs       = omap44xx_gpio5_irqs,
1280         .main_clk       = "gpio5_ick",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_HWCTRL,
1286                 },
1287         },
1288         .opt_clks       = gpio5_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1290         .dev_attr       = &gpio_dev_attr,
1291 };
1292
1293 /* gpio6 */
1294 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1295         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1296         { .irq = -1 }
1297 };
1298
1299 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1300         { .role = "dbclk", .clk = "gpio6_dbclk" },
1301 };
1302
1303 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1304         .name           = "gpio6",
1305         .class          = &omap44xx_gpio_hwmod_class,
1306         .clkdm_name     = "l4_per_clkdm",
1307         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1308         .mpu_irqs       = omap44xx_gpio6_irqs,
1309         .main_clk       = "gpio6_ick",
1310         .prcm = {
1311                 .omap4 = {
1312                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1313                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1314                         .modulemode   = MODULEMODE_HWCTRL,
1315                 },
1316         },
1317         .opt_clks       = gpio6_opt_clks,
1318         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1319         .dev_attr       = &gpio_dev_attr,
1320 };
1321
1322 /*
1323  * 'gpmc' class
1324  * general purpose memory controller
1325  */
1326
1327 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1328         .rev_offs       = 0x0000,
1329         .sysc_offs      = 0x0010,
1330         .syss_offs      = 0x0014,
1331         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1332                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1334         .sysc_fields    = &omap_hwmod_sysc_type1,
1335 };
1336
1337 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1338         .name   = "gpmc",
1339         .sysc   = &omap44xx_gpmc_sysc,
1340 };
1341
1342 /* gpmc */
1343 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1344         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1345         { .irq = -1 }
1346 };
1347
1348 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1349         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1350         { .dma_req = -1 }
1351 };
1352
1353 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1354         .name           = "gpmc",
1355         .class          = &omap44xx_gpmc_hwmod_class,
1356         .clkdm_name     = "l3_2_clkdm",
1357         /*
1358          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1359          * block.  It is not being added due to any known bugs with
1360          * resetting the GPMC IP block, but rather because any timings
1361          * set by the bootloader are not being correctly programmed by
1362          * the kernel from the board file or DT data.
1363          * HWMOD_INIT_NO_RESET should be removed ASAP.
1364          */
1365         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1366         .mpu_irqs       = omap44xx_gpmc_irqs,
1367         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1371                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1372                         .modulemode   = MODULEMODE_HWCTRL,
1373                 },
1374         },
1375 };
1376
1377 /*
1378  * 'gpu' class
1379  * 2d/3d graphics accelerator
1380  */
1381
1382 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1383         .rev_offs       = 0x1fc00,
1384         .sysc_offs      = 0x1fc10,
1385         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1386         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1387                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1388                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1389         .sysc_fields    = &omap_hwmod_sysc_type2,
1390 };
1391
1392 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1393         .name   = "gpu",
1394         .sysc   = &omap44xx_gpu_sysc,
1395 };
1396
1397 /* gpu */
1398 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1399         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1400         { .irq = -1 }
1401 };
1402
1403 static struct omap_hwmod omap44xx_gpu_hwmod = {
1404         .name           = "gpu",
1405         .class          = &omap44xx_gpu_hwmod_class,
1406         .clkdm_name     = "l3_gfx_clkdm",
1407         .mpu_irqs       = omap44xx_gpu_irqs,
1408         .main_clk       = "gpu_fck",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'hdq1w' class
1420  * hdq / 1-wire serial interface controller
1421  */
1422
1423 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1424         .rev_offs       = 0x0000,
1425         .sysc_offs      = 0x0014,
1426         .syss_offs      = 0x0018,
1427         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1428                            SYSS_HAS_RESET_STATUS),
1429         .sysc_fields    = &omap_hwmod_sysc_type1,
1430 };
1431
1432 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1433         .name   = "hdq1w",
1434         .sysc   = &omap44xx_hdq1w_sysc,
1435 };
1436
1437 /* hdq1w */
1438 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1439         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1440         { .irq = -1 }
1441 };
1442
1443 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1444         .name           = "hdq1w",
1445         .class          = &omap44xx_hdq1w_hwmod_class,
1446         .clkdm_name     = "l4_per_clkdm",
1447         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1448         .mpu_irqs       = omap44xx_hdq1w_irqs,
1449         .main_clk       = "hdq1w_fck",
1450         .prcm = {
1451                 .omap4 = {
1452                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1453                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1454                         .modulemode   = MODULEMODE_SWCTRL,
1455                 },
1456         },
1457 };
1458
1459 /*
1460  * 'hsi' class
1461  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1462  * serial if)
1463  */
1464
1465 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1466         .rev_offs       = 0x0000,
1467         .sysc_offs      = 0x0010,
1468         .syss_offs      = 0x0014,
1469         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1470                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1471                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1472         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1473                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1474                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1475         .sysc_fields    = &omap_hwmod_sysc_type1,
1476 };
1477
1478 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1479         .name   = "hsi",
1480         .sysc   = &omap44xx_hsi_sysc,
1481 };
1482
1483 /* hsi */
1484 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1485         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1486         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1488         { .irq = -1 }
1489 };
1490
1491 static struct omap_hwmod omap44xx_hsi_hwmod = {
1492         .name           = "hsi",
1493         .class          = &omap44xx_hsi_hwmod_class,
1494         .clkdm_name     = "l3_init_clkdm",
1495         .mpu_irqs       = omap44xx_hsi_irqs,
1496         .main_clk       = "hsi_fck",
1497         .prcm = {
1498                 .omap4 = {
1499                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1500                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1501                         .modulemode   = MODULEMODE_HWCTRL,
1502                 },
1503         },
1504 };
1505
1506 /*
1507  * 'i2c' class
1508  * multimaster high-speed i2c controller
1509  */
1510
1511 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1512         .sysc_offs      = 0x0010,
1513         .syss_offs      = 0x0090,
1514         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1515                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1516                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1517         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1518                            SIDLE_SMART_WKUP),
1519         .clockact       = CLOCKACT_TEST_ICLK,
1520         .sysc_fields    = &omap_hwmod_sysc_type1,
1521 };
1522
1523 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1524         .name   = "i2c",
1525         .sysc   = &omap44xx_i2c_sysc,
1526         .rev    = OMAP_I2C_IP_VERSION_2,
1527         .reset  = &omap_i2c_reset,
1528 };
1529
1530 static struct omap_i2c_dev_attr i2c_dev_attr = {
1531         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1532 };
1533
1534 /* i2c1 */
1535 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1536         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1537         { .irq = -1 }
1538 };
1539
1540 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1541         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1542         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1543         { .dma_req = -1 }
1544 };
1545
1546 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1547         .name           = "i2c1",
1548         .class          = &omap44xx_i2c_hwmod_class,
1549         .clkdm_name     = "l4_per_clkdm",
1550         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1551         .mpu_irqs       = omap44xx_i2c1_irqs,
1552         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1553         .main_clk       = "i2c1_fck",
1554         .prcm = {
1555                 .omap4 = {
1556                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1557                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1558                         .modulemode   = MODULEMODE_SWCTRL,
1559                 },
1560         },
1561         .dev_attr       = &i2c_dev_attr,
1562 };
1563
1564 /* i2c2 */
1565 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1566         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1567         { .irq = -1 }
1568 };
1569
1570 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1571         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1572         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1573         { .dma_req = -1 }
1574 };
1575
1576 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1577         .name           = "i2c2",
1578         .class          = &omap44xx_i2c_hwmod_class,
1579         .clkdm_name     = "l4_per_clkdm",
1580         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1581         .mpu_irqs       = omap44xx_i2c2_irqs,
1582         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1583         .main_clk       = "i2c2_fck",
1584         .prcm = {
1585                 .omap4 = {
1586                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1587                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1588                         .modulemode   = MODULEMODE_SWCTRL,
1589                 },
1590         },
1591         .dev_attr       = &i2c_dev_attr,
1592 };
1593
1594 /* i2c3 */
1595 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1596         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1597         { .irq = -1 }
1598 };
1599
1600 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1601         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1602         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1603         { .dma_req = -1 }
1604 };
1605
1606 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1607         .name           = "i2c3",
1608         .class          = &omap44xx_i2c_hwmod_class,
1609         .clkdm_name     = "l4_per_clkdm",
1610         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1611         .mpu_irqs       = omap44xx_i2c3_irqs,
1612         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1613         .main_clk       = "i2c3_fck",
1614         .prcm = {
1615                 .omap4 = {
1616                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1617                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1618                         .modulemode   = MODULEMODE_SWCTRL,
1619                 },
1620         },
1621         .dev_attr       = &i2c_dev_attr,
1622 };
1623
1624 /* i2c4 */
1625 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1626         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1627         { .irq = -1 }
1628 };
1629
1630 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1631         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1632         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1633         { .dma_req = -1 }
1634 };
1635
1636 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1637         .name           = "i2c4",
1638         .class          = &omap44xx_i2c_hwmod_class,
1639         .clkdm_name     = "l4_per_clkdm",
1640         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1641         .mpu_irqs       = omap44xx_i2c4_irqs,
1642         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1643         .main_clk       = "i2c4_fck",
1644         .prcm = {
1645                 .omap4 = {
1646                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1647                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1648                         .modulemode   = MODULEMODE_SWCTRL,
1649                 },
1650         },
1651         .dev_attr       = &i2c_dev_attr,
1652 };
1653
1654 /*
1655  * 'ipu' class
1656  * imaging processor unit
1657  */
1658
1659 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1660         .name   = "ipu",
1661 };
1662
1663 /* ipu */
1664 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1665         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1666         { .irq = -1 }
1667 };
1668
1669 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1670         { .name = "cpu0", .rst_shift = 0 },
1671         { .name = "cpu1", .rst_shift = 1 },
1672 };
1673
1674 static struct omap_hwmod omap44xx_ipu_hwmod = {
1675         .name           = "ipu",
1676         .class          = &omap44xx_ipu_hwmod_class,
1677         .clkdm_name     = "ducati_clkdm",
1678         .mpu_irqs       = omap44xx_ipu_irqs,
1679         .rst_lines      = omap44xx_ipu_resets,
1680         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1681         .main_clk       = "ducati_clk_mux_ck",
1682         .prcm = {
1683                 .omap4 = {
1684                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1685                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1686                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1687                         .modulemode   = MODULEMODE_HWCTRL,
1688                 },
1689         },
1690 };
1691
1692 /*
1693  * 'iss' class
1694  * external images sensor pixel data processor
1695  */
1696
1697 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1698         .rev_offs       = 0x0000,
1699         .sysc_offs      = 0x0010,
1700         /*
1701          * ISS needs 100 OCP clk cycles delay after a softreset before
1702          * accessing sysconfig again.
1703          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1704          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1705          *
1706          * TODO: Indicate errata when available.
1707          */
1708         .srst_udelay    = 2,
1709         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1710                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1711         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1712                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1713                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1714         .sysc_fields    = &omap_hwmod_sysc_type2,
1715 };
1716
1717 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1718         .name   = "iss",
1719         .sysc   = &omap44xx_iss_sysc,
1720 };
1721
1722 /* iss */
1723 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1724         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1725         { .irq = -1 }
1726 };
1727
1728 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1729         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1730         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1731         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1732         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1733         { .dma_req = -1 }
1734 };
1735
1736 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1737         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1738 };
1739
1740 static struct omap_hwmod omap44xx_iss_hwmod = {
1741         .name           = "iss",
1742         .class          = &omap44xx_iss_hwmod_class,
1743         .clkdm_name     = "iss_clkdm",
1744         .mpu_irqs       = omap44xx_iss_irqs,
1745         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1746         .main_clk       = "iss_fck",
1747         .prcm = {
1748                 .omap4 = {
1749                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1750                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1751                         .modulemode   = MODULEMODE_SWCTRL,
1752                 },
1753         },
1754         .opt_clks       = iss_opt_clks,
1755         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1756 };
1757
1758 /*
1759  * 'iva' class
1760  * multi-standard video encoder/decoder hardware accelerator
1761  */
1762
1763 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1764         .name   = "iva",
1765 };
1766
1767 /* iva */
1768 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1769         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1770         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1772         { .irq = -1 }
1773 };
1774
1775 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1776         { .name = "seq0", .rst_shift = 0 },
1777         { .name = "seq1", .rst_shift = 1 },
1778         { .name = "logic", .rst_shift = 2 },
1779 };
1780
1781 static struct omap_hwmod omap44xx_iva_hwmod = {
1782         .name           = "iva",
1783         .class          = &omap44xx_iva_hwmod_class,
1784         .clkdm_name     = "ivahd_clkdm",
1785         .mpu_irqs       = omap44xx_iva_irqs,
1786         .rst_lines      = omap44xx_iva_resets,
1787         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1788         .main_clk       = "iva_fck",
1789         .prcm = {
1790                 .omap4 = {
1791                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1792                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1793                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1794                         .modulemode   = MODULEMODE_HWCTRL,
1795                 },
1796         },
1797 };
1798
1799 /*
1800  * 'kbd' class
1801  * keyboard controller
1802  */
1803
1804 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1805         .rev_offs       = 0x0000,
1806         .sysc_offs      = 0x0010,
1807         .syss_offs      = 0x0014,
1808         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1809                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1810                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811                            SYSS_HAS_RESET_STATUS),
1812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1813         .sysc_fields    = &omap_hwmod_sysc_type1,
1814 };
1815
1816 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1817         .name   = "kbd",
1818         .sysc   = &omap44xx_kbd_sysc,
1819 };
1820
1821 /* kbd */
1822 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1823         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1824         { .irq = -1 }
1825 };
1826
1827 static struct omap_hwmod omap44xx_kbd_hwmod = {
1828         .name           = "kbd",
1829         .class          = &omap44xx_kbd_hwmod_class,
1830         .clkdm_name     = "l4_wkup_clkdm",
1831         .mpu_irqs       = omap44xx_kbd_irqs,
1832         .main_clk       = "kbd_fck",
1833         .prcm = {
1834                 .omap4 = {
1835                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1836                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1837                         .modulemode   = MODULEMODE_SWCTRL,
1838                 },
1839         },
1840 };
1841
1842 /*
1843  * 'mailbox' class
1844  * mailbox module allowing communication between the on-chip processors using a
1845  * queued mailbox-interrupt mechanism.
1846  */
1847
1848 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1849         .rev_offs       = 0x0000,
1850         .sysc_offs      = 0x0010,
1851         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1852                            SYSC_HAS_SOFTRESET),
1853         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1854         .sysc_fields    = &omap_hwmod_sysc_type2,
1855 };
1856
1857 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1858         .name   = "mailbox",
1859         .sysc   = &omap44xx_mailbox_sysc,
1860 };
1861
1862 /* mailbox */
1863 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1864         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1865         { .irq = -1 }
1866 };
1867
1868 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1869         .name           = "mailbox",
1870         .class          = &omap44xx_mailbox_hwmod_class,
1871         .clkdm_name     = "l4_cfg_clkdm",
1872         .mpu_irqs       = omap44xx_mailbox_irqs,
1873         .prcm = {
1874                 .omap4 = {
1875                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1876                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1877                 },
1878         },
1879 };
1880
1881 /*
1882  * 'mcasp' class
1883  * multi-channel audio serial port controller
1884  */
1885
1886 /* The IP is not compliant to type1 / type2 scheme */
1887 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1888         .sidle_shift    = 0,
1889 };
1890
1891 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1892         .sysc_offs      = 0x0004,
1893         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1894         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1895                            SIDLE_SMART_WKUP),
1896         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1897 };
1898
1899 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1900         .name   = "mcasp",
1901         .sysc   = &omap44xx_mcasp_sysc,
1902 };
1903
1904 /* mcasp */
1905 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1906         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1907         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1908         { .irq = -1 }
1909 };
1910
1911 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1912         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1913         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1914         { .dma_req = -1 }
1915 };
1916
1917 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1918         .name           = "mcasp",
1919         .class          = &omap44xx_mcasp_hwmod_class,
1920         .clkdm_name     = "abe_clkdm",
1921         .mpu_irqs       = omap44xx_mcasp_irqs,
1922         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1923         .main_clk       = "mcasp_fck",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1927                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_SWCTRL,
1929                 },
1930         },
1931 };
1932
1933 /*
1934  * 'mcbsp' class
1935  * multi channel buffered serial port controller
1936  */
1937
1938 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1939         .sysc_offs      = 0x008c,
1940         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1941                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1942         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1943         .sysc_fields    = &omap_hwmod_sysc_type1,
1944 };
1945
1946 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1947         .name   = "mcbsp",
1948         .sysc   = &omap44xx_mcbsp_sysc,
1949         .rev    = MCBSP_CONFIG_TYPE4,
1950 };
1951
1952 /* mcbsp1 */
1953 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1954         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1955         { .irq = -1 }
1956 };
1957
1958 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1959         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1960         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1961         { .dma_req = -1 }
1962 };
1963
1964 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1965         { .role = "pad_fck", .clk = "pad_clks_ck" },
1966         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1967 };
1968
1969 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1970         .name           = "mcbsp1",
1971         .class          = &omap44xx_mcbsp_hwmod_class,
1972         .clkdm_name     = "abe_clkdm",
1973         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1974         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1975         .main_clk       = "mcbsp1_fck",
1976         .prcm = {
1977                 .omap4 = {
1978                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1979                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1980                         .modulemode   = MODULEMODE_SWCTRL,
1981                 },
1982         },
1983         .opt_clks       = mcbsp1_opt_clks,
1984         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1985 };
1986
1987 /* mcbsp2 */
1988 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1989         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1990         { .irq = -1 }
1991 };
1992
1993 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1994         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1995         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1996         { .dma_req = -1 }
1997 };
1998
1999 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2000         { .role = "pad_fck", .clk = "pad_clks_ck" },
2001         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2002 };
2003
2004 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2005         .name           = "mcbsp2",
2006         .class          = &omap44xx_mcbsp_hwmod_class,
2007         .clkdm_name     = "abe_clkdm",
2008         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2009         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2010         .main_clk       = "mcbsp2_fck",
2011         .prcm = {
2012                 .omap4 = {
2013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2014                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2015                         .modulemode   = MODULEMODE_SWCTRL,
2016                 },
2017         },
2018         .opt_clks       = mcbsp2_opt_clks,
2019         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2020 };
2021
2022 /* mcbsp3 */
2023 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2024         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2025         { .irq = -1 }
2026 };
2027
2028 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2029         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2030         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2031         { .dma_req = -1 }
2032 };
2033
2034 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2035         { .role = "pad_fck", .clk = "pad_clks_ck" },
2036         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2037 };
2038
2039 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2040         .name           = "mcbsp3",
2041         .class          = &omap44xx_mcbsp_hwmod_class,
2042         .clkdm_name     = "abe_clkdm",
2043         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2044         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2045         .main_clk       = "mcbsp3_fck",
2046         .prcm = {
2047                 .omap4 = {
2048                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2049                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2050                         .modulemode   = MODULEMODE_SWCTRL,
2051                 },
2052         },
2053         .opt_clks       = mcbsp3_opt_clks,
2054         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2055 };
2056
2057 /* mcbsp4 */
2058 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2059         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2060         { .irq = -1 }
2061 };
2062
2063 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2064         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2065         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2066         { .dma_req = -1 }
2067 };
2068
2069 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2070         { .role = "pad_fck", .clk = "pad_clks_ck" },
2071         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2072 };
2073
2074 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2075         .name           = "mcbsp4",
2076         .class          = &omap44xx_mcbsp_hwmod_class,
2077         .clkdm_name     = "l4_per_clkdm",
2078         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2079         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2080         .main_clk       = "mcbsp4_fck",
2081         .prcm = {
2082                 .omap4 = {
2083                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2084                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2085                         .modulemode   = MODULEMODE_SWCTRL,
2086                 },
2087         },
2088         .opt_clks       = mcbsp4_opt_clks,
2089         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2090 };
2091
2092 /*
2093  * 'mcpdm' class
2094  * multi channel pdm controller (proprietary interface with phoenix power
2095  * ic)
2096  */
2097
2098 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2099         .rev_offs       = 0x0000,
2100         .sysc_offs      = 0x0010,
2101         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2102                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2103         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2104                            SIDLE_SMART_WKUP),
2105         .sysc_fields    = &omap_hwmod_sysc_type2,
2106 };
2107
2108 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2109         .name   = "mcpdm",
2110         .sysc   = &omap44xx_mcpdm_sysc,
2111 };
2112
2113 /* mcpdm */
2114 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2115         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2116         { .irq = -1 }
2117 };
2118
2119 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2120         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2121         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2122         { .dma_req = -1 }
2123 };
2124
2125 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2126         .name           = "mcpdm",
2127         .class          = &omap44xx_mcpdm_hwmod_class,
2128         .clkdm_name     = "abe_clkdm",
2129         /*
2130          * It's suspected that the McPDM requires an off-chip main
2131          * functional clock, controlled via I2C.  This IP block is
2132          * currently reset very early during boot, before I2C is
2133          * available, so it doesn't seem that we have any choice in
2134          * the kernel other than to avoid resetting it.
2135          *
2136          * Also, McPDM needs to be configured to NO_IDLE mode when it
2137          * is in used otherwise vital clocks will be gated which
2138          * results 'slow motion' audio playback.
2139          */
2140         .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
2141         .mpu_irqs       = omap44xx_mcpdm_irqs,
2142         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2143         .main_clk       = "mcpdm_fck",
2144         .prcm = {
2145                 .omap4 = {
2146                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2147                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2148                         .modulemode   = MODULEMODE_SWCTRL,
2149                 },
2150         },
2151 };
2152
2153 /*
2154  * 'mcspi' class
2155  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2156  * bus
2157  */
2158
2159 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2160         .rev_offs       = 0x0000,
2161         .sysc_offs      = 0x0010,
2162         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2163                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2165                            SIDLE_SMART_WKUP),
2166         .sysc_fields    = &omap_hwmod_sysc_type2,
2167 };
2168
2169 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2170         .name   = "mcspi",
2171         .sysc   = &omap44xx_mcspi_sysc,
2172         .rev    = OMAP4_MCSPI_REV,
2173 };
2174
2175 /* mcspi1 */
2176 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2177         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2178         { .irq = -1 }
2179 };
2180
2181 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2182         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2183         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2184         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2185         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2186         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2187         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2188         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2189         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2190         { .dma_req = -1 }
2191 };
2192
2193 /* mcspi1 dev_attr */
2194 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2195         .num_chipselect = 4,
2196 };
2197
2198 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2199         .name           = "mcspi1",
2200         .class          = &omap44xx_mcspi_hwmod_class,
2201         .clkdm_name     = "l4_per_clkdm",
2202         .mpu_irqs       = omap44xx_mcspi1_irqs,
2203         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2204         .main_clk       = "mcspi1_fck",
2205         .prcm = {
2206                 .omap4 = {
2207                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2208                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2209                         .modulemode   = MODULEMODE_SWCTRL,
2210                 },
2211         },
2212         .dev_attr       = &mcspi1_dev_attr,
2213 };
2214
2215 /* mcspi2 */
2216 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2217         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2218         { .irq = -1 }
2219 };
2220
2221 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2222         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2223         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2224         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2225         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2226         { .dma_req = -1 }
2227 };
2228
2229 /* mcspi2 dev_attr */
2230 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2231         .num_chipselect = 2,
2232 };
2233
2234 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2235         .name           = "mcspi2",
2236         .class          = &omap44xx_mcspi_hwmod_class,
2237         .clkdm_name     = "l4_per_clkdm",
2238         .mpu_irqs       = omap44xx_mcspi2_irqs,
2239         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2240         .main_clk       = "mcspi2_fck",
2241         .prcm = {
2242                 .omap4 = {
2243                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2244                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2245                         .modulemode   = MODULEMODE_SWCTRL,
2246                 },
2247         },
2248         .dev_attr       = &mcspi2_dev_attr,
2249 };
2250
2251 /* mcspi3 */
2252 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2253         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2254         { .irq = -1 }
2255 };
2256
2257 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2258         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2259         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2260         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2261         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2262         { .dma_req = -1 }
2263 };
2264
2265 /* mcspi3 dev_attr */
2266 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2267         .num_chipselect = 2,
2268 };
2269
2270 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2271         .name           = "mcspi3",
2272         .class          = &omap44xx_mcspi_hwmod_class,
2273         .clkdm_name     = "l4_per_clkdm",
2274         .mpu_irqs       = omap44xx_mcspi3_irqs,
2275         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2276         .main_clk       = "mcspi3_fck",
2277         .prcm = {
2278                 .omap4 = {
2279                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2280                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2281                         .modulemode   = MODULEMODE_SWCTRL,
2282                 },
2283         },
2284         .dev_attr       = &mcspi3_dev_attr,
2285 };
2286
2287 /* mcspi4 */
2288 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2289         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2290         { .irq = -1 }
2291 };
2292
2293 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2294         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2295         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2296         { .dma_req = -1 }
2297 };
2298
2299 /* mcspi4 dev_attr */
2300 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2301         .num_chipselect = 1,
2302 };
2303
2304 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2305         .name           = "mcspi4",
2306         .class          = &omap44xx_mcspi_hwmod_class,
2307         .clkdm_name     = "l4_per_clkdm",
2308         .mpu_irqs       = omap44xx_mcspi4_irqs,
2309         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2310         .main_clk       = "mcspi4_fck",
2311         .prcm = {
2312                 .omap4 = {
2313                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2314                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2315                         .modulemode   = MODULEMODE_SWCTRL,
2316                 },
2317         },
2318         .dev_attr       = &mcspi4_dev_attr,
2319 };
2320
2321 /*
2322  * 'mmc' class
2323  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2324  */
2325
2326 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2327         .rev_offs       = 0x0000,
2328         .sysc_offs      = 0x0010,
2329         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2330                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2331                            SYSC_HAS_SOFTRESET),
2332         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2333                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2334                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2335         .sysc_fields    = &omap_hwmod_sysc_type2,
2336 };
2337
2338 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2339         .name   = "mmc",
2340         .sysc   = &omap44xx_mmc_sysc,
2341 };
2342
2343 /* mmc1 */
2344 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2345         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2346         { .irq = -1 }
2347 };
2348
2349 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2350         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2351         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2352         { .dma_req = -1 }
2353 };
2354
2355 /* mmc1 dev_attr */
2356 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2357         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2358 };
2359
2360 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2361         .name           = "mmc1",
2362         .class          = &omap44xx_mmc_hwmod_class,
2363         .clkdm_name     = "l3_init_clkdm",
2364         .mpu_irqs       = omap44xx_mmc1_irqs,
2365         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2366         .main_clk       = "mmc1_fck",
2367         .prcm = {
2368                 .omap4 = {
2369                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2370                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2371                         .modulemode   = MODULEMODE_SWCTRL,
2372                 },
2373         },
2374         .dev_attr       = &mmc1_dev_attr,
2375 };
2376
2377 /* mmc2 */
2378 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2379         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2380         { .irq = -1 }
2381 };
2382
2383 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2384         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2385         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2386         { .dma_req = -1 }
2387 };
2388
2389 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2390         .name           = "mmc2",
2391         .class          = &omap44xx_mmc_hwmod_class,
2392         .clkdm_name     = "l3_init_clkdm",
2393         .mpu_irqs       = omap44xx_mmc2_irqs,
2394         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2395         .main_clk       = "mmc2_fck",
2396         .prcm = {
2397                 .omap4 = {
2398                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2399                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2400                         .modulemode   = MODULEMODE_SWCTRL,
2401                 },
2402         },
2403 };
2404
2405 /* mmc3 */
2406 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2407         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2408         { .irq = -1 }
2409 };
2410
2411 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2412         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2413         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2414         { .dma_req = -1 }
2415 };
2416
2417 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2418         .name           = "mmc3",
2419         .class          = &omap44xx_mmc_hwmod_class,
2420         .clkdm_name     = "l4_per_clkdm",
2421         .mpu_irqs       = omap44xx_mmc3_irqs,
2422         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2423         .main_clk       = "mmc3_fck",
2424         .prcm = {
2425                 .omap4 = {
2426                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2427                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2428                         .modulemode   = MODULEMODE_SWCTRL,
2429                 },
2430         },
2431 };
2432
2433 /* mmc4 */
2434 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2435         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2436         { .irq = -1 }
2437 };
2438
2439 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2440         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2441         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2442         { .dma_req = -1 }
2443 };
2444
2445 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2446         .name           = "mmc4",
2447         .class          = &omap44xx_mmc_hwmod_class,
2448         .clkdm_name     = "l4_per_clkdm",
2449         .mpu_irqs       = omap44xx_mmc4_irqs,
2450         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2451         .main_clk       = "mmc4_fck",
2452         .prcm = {
2453                 .omap4 = {
2454                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2455                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2456                         .modulemode   = MODULEMODE_SWCTRL,
2457                 },
2458         },
2459 };
2460
2461 /* mmc5 */
2462 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2463         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2464         { .irq = -1 }
2465 };
2466
2467 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2468         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2469         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2470         { .dma_req = -1 }
2471 };
2472
2473 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2474         .name           = "mmc5",
2475         .class          = &omap44xx_mmc_hwmod_class,
2476         .clkdm_name     = "l4_per_clkdm",
2477         .mpu_irqs       = omap44xx_mmc5_irqs,
2478         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2479         .main_clk       = "mmc5_fck",
2480         .prcm = {
2481                 .omap4 = {
2482                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2483                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2484                         .modulemode   = MODULEMODE_SWCTRL,
2485                 },
2486         },
2487 };
2488
2489 /*
2490  * 'mmu' class
2491  * The memory management unit performs virtual to physical address translation
2492  * for its requestors.
2493  */
2494
2495 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2496         .rev_offs       = 0x000,
2497         .sysc_offs      = 0x010,
2498         .syss_offs      = 0x014,
2499         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2500                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2501         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2502         .sysc_fields    = &omap_hwmod_sysc_type1,
2503 };
2504
2505 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2506         .name = "mmu",
2507         .sysc = &mmu_sysc,
2508 };
2509
2510 /* mmu ipu */
2511
2512 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2513         .da_start       = 0x0,
2514         .da_end         = 0xfffff000,
2515         .nr_tlb_entries = 32,
2516 };
2517
2518 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2519 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2520         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2521         { .irq = -1 }
2522 };
2523
2524 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2525         { .name = "mmu_cache", .rst_shift = 2 },
2526 };
2527
2528 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2529         {
2530                 .pa_start       = 0x55082000,
2531                 .pa_end         = 0x550820ff,
2532                 .flags          = ADDR_TYPE_RT,
2533         },
2534         { }
2535 };
2536
2537 /* l3_main_2 -> mmu_ipu */
2538 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2539         .master         = &omap44xx_l3_main_2_hwmod,
2540         .slave          = &omap44xx_mmu_ipu_hwmod,
2541         .clk            = "l3_div_ck",
2542         .addr           = omap44xx_mmu_ipu_addrs,
2543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2544 };
2545
2546 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2547         .name           = "mmu_ipu",
2548         .class          = &omap44xx_mmu_hwmod_class,
2549         .clkdm_name     = "ducati_clkdm",
2550         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2551         .rst_lines      = omap44xx_mmu_ipu_resets,
2552         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2553         .main_clk       = "ducati_clk_mux_ck",
2554         .prcm = {
2555                 .omap4 = {
2556                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2557                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2558                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2559                         .modulemode   = MODULEMODE_HWCTRL,
2560                 },
2561         },
2562         .dev_attr       = &mmu_ipu_dev_attr,
2563 };
2564
2565 /* mmu dsp */
2566
2567 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2568         .da_start       = 0x0,
2569         .da_end         = 0xfffff000,
2570         .nr_tlb_entries = 32,
2571 };
2572
2573 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2574 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2575         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2576         { .irq = -1 }
2577 };
2578
2579 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2580         { .name = "mmu_cache", .rst_shift = 1 },
2581 };
2582
2583 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2584         {
2585                 .pa_start       = 0x4a066000,
2586                 .pa_end         = 0x4a0660ff,
2587                 .flags          = ADDR_TYPE_RT,
2588         },
2589         { }
2590 };
2591
2592 /* l4_cfg -> dsp */
2593 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2594         .master         = &omap44xx_l4_cfg_hwmod,
2595         .slave          = &omap44xx_mmu_dsp_hwmod,
2596         .clk            = "l4_div_ck",
2597         .addr           = omap44xx_mmu_dsp_addrs,
2598         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2599 };
2600
2601 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2602         .name           = "mmu_dsp",
2603         .class          = &omap44xx_mmu_hwmod_class,
2604         .clkdm_name     = "tesla_clkdm",
2605         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2606         .rst_lines      = omap44xx_mmu_dsp_resets,
2607         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2608         .main_clk       = "dpll_iva_m4x2_ck",
2609         .prcm = {
2610                 .omap4 = {
2611                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2612                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2613                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2614                         .modulemode   = MODULEMODE_HWCTRL,
2615                 },
2616         },
2617         .dev_attr       = &mmu_dsp_dev_attr,
2618 };
2619
2620 /*
2621  * 'mpu' class
2622  * mpu sub-system
2623  */
2624
2625 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2626         .name   = "mpu",
2627 };
2628
2629 /* mpu */
2630 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2631         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2632         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2633         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2634         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2635         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2636         { .irq = -1 }
2637 };
2638
2639 static struct omap_hwmod omap44xx_mpu_hwmod = {
2640         .name           = "mpu",
2641         .class          = &omap44xx_mpu_hwmod_class,
2642         .clkdm_name     = "mpuss_clkdm",
2643         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2644         .mpu_irqs       = omap44xx_mpu_irqs,
2645         .main_clk       = "dpll_mpu_m2_ck",
2646         .prcm = {
2647                 .omap4 = {
2648                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2649                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2650                 },
2651         },
2652 };
2653
2654 /*
2655  * 'ocmc_ram' class
2656  * top-level core on-chip ram
2657  */
2658
2659 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2660         .name   = "ocmc_ram",
2661 };
2662
2663 /* ocmc_ram */
2664 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2665         .name           = "ocmc_ram",
2666         .class          = &omap44xx_ocmc_ram_hwmod_class,
2667         .clkdm_name     = "l3_2_clkdm",
2668         .prcm = {
2669                 .omap4 = {
2670                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2671                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2672                 },
2673         },
2674 };
2675
2676 /*
2677  * 'ocp2scp' class
2678  * bridge to transform ocp interface protocol to scp (serial control port)
2679  * protocol
2680  */
2681
2682 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2683         .rev_offs       = 0x0000,
2684         .sysc_offs      = 0x0010,
2685         .syss_offs      = 0x0014,
2686         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2687                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2688         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2689         .sysc_fields    = &omap_hwmod_sysc_type1,
2690 };
2691
2692 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2693         .name   = "ocp2scp",
2694         .sysc   = &omap44xx_ocp2scp_sysc,
2695 };
2696
2697 /* ocp2scp dev_attr */
2698 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2699         {
2700                 .name           = "usb_phy",
2701                 .start          = 0x4a0ad080,
2702                 .end            = 0x4a0ae000,
2703                 .flags          = IORESOURCE_MEM,
2704         },
2705         {
2706                 /* XXX: Remove this once control module driver is in place */
2707                 .name           = "ctrl_dev",
2708                 .start          = 0x4a002300,
2709                 .end            = 0x4a002303,
2710                 .flags          = IORESOURCE_MEM,
2711         },
2712         { }
2713 };
2714
2715 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2716         {
2717                 .drv_name       = "omap-usb2",
2718                 .res            = omap44xx_usb_phy_and_pll_addrs,
2719         },
2720         { }
2721 };
2722
2723 /* ocp2scp_usb_phy */
2724 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2725         .name           = "ocp2scp_usb_phy",
2726         .class          = &omap44xx_ocp2scp_hwmod_class,
2727         .clkdm_name     = "l3_init_clkdm",
2728         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2729         .prcm = {
2730                 .omap4 = {
2731                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2732                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2733                         .modulemode   = MODULEMODE_HWCTRL,
2734                 },
2735         },
2736         .dev_attr       = ocp2scp_dev_attr,
2737 };
2738
2739 /*
2740  * 'prcm' class
2741  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2742  * + clock manager 1 (in always on power domain) + local prm in mpu
2743  */
2744
2745 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2746         .name   = "prcm",
2747 };
2748
2749 /* prcm_mpu */
2750 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2751         .name           = "prcm_mpu",
2752         .class          = &omap44xx_prcm_hwmod_class,
2753         .clkdm_name     = "l4_wkup_clkdm",
2754         .flags          = HWMOD_NO_IDLEST,
2755         .prcm = {
2756                 .omap4 = {
2757                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2758                 },
2759         },
2760 };
2761
2762 /* cm_core_aon */
2763 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2764         .name           = "cm_core_aon",
2765         .class          = &omap44xx_prcm_hwmod_class,
2766         .flags          = HWMOD_NO_IDLEST,
2767         .prcm = {
2768                 .omap4 = {
2769                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2770                 },
2771         },
2772 };
2773
2774 /* cm_core */
2775 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2776         .name           = "cm_core",
2777         .class          = &omap44xx_prcm_hwmod_class,
2778         .flags          = HWMOD_NO_IDLEST,
2779         .prcm = {
2780                 .omap4 = {
2781                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2782                 },
2783         },
2784 };
2785
2786 /* prm */
2787 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2788         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2789         { .irq = -1 }
2790 };
2791
2792 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2793         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2794         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2795 };
2796
2797 static struct omap_hwmod omap44xx_prm_hwmod = {
2798         .name           = "prm",
2799         .class          = &omap44xx_prcm_hwmod_class,
2800         .mpu_irqs       = omap44xx_prm_irqs,
2801         .rst_lines      = omap44xx_prm_resets,
2802         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2803 };
2804
2805 /*
2806  * 'scrm' class
2807  * system clock and reset manager
2808  */
2809
2810 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2811         .name   = "scrm",
2812 };
2813
2814 /* scrm */
2815 static struct omap_hwmod omap44xx_scrm_hwmod = {
2816         .name           = "scrm",
2817         .class          = &omap44xx_scrm_hwmod_class,
2818         .clkdm_name     = "l4_wkup_clkdm",
2819         .prcm = {
2820                 .omap4 = {
2821                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2822                 },
2823         },
2824 };
2825
2826 /*
2827  * 'sl2if' class
2828  * shared level 2 memory interface
2829  */
2830
2831 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2832         .name   = "sl2if",
2833 };
2834
2835 /* sl2if */
2836 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2837         .name           = "sl2if",
2838         .class          = &omap44xx_sl2if_hwmod_class,
2839         .clkdm_name     = "ivahd_clkdm",
2840         .prcm = {
2841                 .omap4 = {
2842                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2843                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2844                         .modulemode   = MODULEMODE_HWCTRL,
2845                 },
2846         },
2847 };
2848
2849 /*
2850  * 'slimbus' class
2851  * bidirectional, multi-drop, multi-channel two-line serial interface between
2852  * the device and external components
2853  */
2854
2855 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2856         .rev_offs       = 0x0000,
2857         .sysc_offs      = 0x0010,
2858         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2859                            SYSC_HAS_SOFTRESET),
2860         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2861                            SIDLE_SMART_WKUP),
2862         .sysc_fields    = &omap_hwmod_sysc_type2,
2863 };
2864
2865 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2866         .name   = "slimbus",
2867         .sysc   = &omap44xx_slimbus_sysc,
2868 };
2869
2870 /* slimbus1 */
2871 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2872         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2873         { .irq = -1 }
2874 };
2875
2876 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2877         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2878         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2879         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2880         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2881         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2882         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2883         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2884         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2885         { .dma_req = -1 }
2886 };
2887
2888 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2889         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2890         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2891         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2892         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2893 };
2894
2895 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2896         .name           = "slimbus1",
2897         .class          = &omap44xx_slimbus_hwmod_class,
2898         .clkdm_name     = "abe_clkdm",
2899         .mpu_irqs       = omap44xx_slimbus1_irqs,
2900         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2901         .prcm = {
2902                 .omap4 = {
2903                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2904                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2905                         .modulemode   = MODULEMODE_SWCTRL,
2906                 },
2907         },
2908         .opt_clks       = slimbus1_opt_clks,
2909         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2910 };
2911
2912 /* slimbus2 */
2913 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2914         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2915         { .irq = -1 }
2916 };
2917
2918 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2919         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2920         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2921         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2922         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2923         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2924         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2925         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2926         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2927         { .dma_req = -1 }
2928 };
2929
2930 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2931         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2932         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2933         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2934 };
2935
2936 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2937         .name           = "slimbus2",
2938         .class          = &omap44xx_slimbus_hwmod_class,
2939         .clkdm_name     = "l4_per_clkdm",
2940         .mpu_irqs       = omap44xx_slimbus2_irqs,
2941         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2942         .prcm = {
2943                 .omap4 = {
2944                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2945                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2946                         .modulemode   = MODULEMODE_SWCTRL,
2947                 },
2948         },
2949         .opt_clks       = slimbus2_opt_clks,
2950         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2951 };
2952
2953 /*
2954  * 'smartreflex' class
2955  * smartreflex module (monitor silicon performance and outputs a measure of
2956  * performance error)
2957  */
2958
2959 /* The IP is not compliant to type1 / type2 scheme */
2960 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2961         .sidle_shift    = 24,
2962         .enwkup_shift   = 26,
2963 };
2964
2965 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2966         .sysc_offs      = 0x0038,
2967         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2968         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2969                            SIDLE_SMART_WKUP),
2970         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2971 };
2972
2973 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2974         .name   = "smartreflex",
2975         .sysc   = &omap44xx_smartreflex_sysc,
2976         .rev    = 2,
2977 };
2978
2979 /* smartreflex_core */
2980 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2981         .sensor_voltdm_name   = "core",
2982 };
2983
2984 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2985         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2986         { .irq = -1 }
2987 };
2988
2989 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2990         .name           = "smartreflex_core",
2991         .class          = &omap44xx_smartreflex_hwmod_class,
2992         .clkdm_name     = "l4_ao_clkdm",
2993         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2994
2995         .main_clk       = "smartreflex_core_fck",
2996         .prcm = {
2997                 .omap4 = {
2998                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2999                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
3000                         .modulemode   = MODULEMODE_SWCTRL,
3001                 },
3002         },
3003         .dev_attr       = &smartreflex_core_dev_attr,
3004 };
3005
3006 /* smartreflex_iva */
3007 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3008         .sensor_voltdm_name     = "iva",
3009 };
3010
3011 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3012         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3013         { .irq = -1 }
3014 };
3015
3016 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3017         .name           = "smartreflex_iva",
3018         .class          = &omap44xx_smartreflex_hwmod_class,
3019         .clkdm_name     = "l4_ao_clkdm",
3020         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3021         .main_clk       = "smartreflex_iva_fck",
3022         .prcm = {
3023                 .omap4 = {
3024                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3025                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3026                         .modulemode   = MODULEMODE_SWCTRL,
3027                 },
3028         },
3029         .dev_attr       = &smartreflex_iva_dev_attr,
3030 };
3031
3032 /* smartreflex_mpu */
3033 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3034         .sensor_voltdm_name     = "mpu",
3035 };
3036
3037 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3038         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3039         { .irq = -1 }
3040 };
3041
3042 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3043         .name           = "smartreflex_mpu",
3044         .class          = &omap44xx_smartreflex_hwmod_class,
3045         .clkdm_name     = "l4_ao_clkdm",
3046         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3047         .main_clk       = "smartreflex_mpu_fck",
3048         .prcm = {
3049                 .omap4 = {
3050                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3051                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3052                         .modulemode   = MODULEMODE_SWCTRL,
3053                 },
3054         },
3055         .dev_attr       = &smartreflex_mpu_dev_attr,
3056 };
3057
3058 /*
3059  * 'spinlock' class
3060  * spinlock provides hardware assistance for synchronizing the processes
3061  * running on multiple processors
3062  */
3063
3064 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3065         .rev_offs       = 0x0000,
3066         .sysc_offs      = 0x0010,
3067         .syss_offs      = 0x0014,
3068         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3069                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3070                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3071         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3072                            SIDLE_SMART_WKUP),
3073         .sysc_fields    = &omap_hwmod_sysc_type1,
3074 };
3075
3076 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3077         .name   = "spinlock",
3078         .sysc   = &omap44xx_spinlock_sysc,
3079 };
3080
3081 /* spinlock */
3082 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3083         .name           = "spinlock",
3084         .class          = &omap44xx_spinlock_hwmod_class,
3085         .clkdm_name     = "l4_cfg_clkdm",
3086         .prcm = {
3087                 .omap4 = {
3088                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3089                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3090                 },
3091         },
3092 };
3093
3094 /*
3095  * 'timer' class
3096  * general purpose timer module with accurate 1ms tick
3097  * This class contains several variants: ['timer_1ms', 'timer']
3098  */
3099
3100 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3101         .rev_offs       = 0x0000,
3102         .sysc_offs      = 0x0010,
3103         .syss_offs      = 0x0014,
3104         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3105                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3106                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3107                            SYSS_HAS_RESET_STATUS),
3108         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3109         .clockact       = CLOCKACT_TEST_ICLK,
3110         .sysc_fields    = &omap_hwmod_sysc_type1,
3111 };
3112
3113 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3114         .name   = "timer",
3115         .sysc   = &omap44xx_timer_1ms_sysc,
3116 };
3117
3118 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3119         .rev_offs       = 0x0000,
3120         .sysc_offs      = 0x0010,
3121         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3122                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3123         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3124                            SIDLE_SMART_WKUP),
3125         .sysc_fields    = &omap_hwmod_sysc_type2,
3126 };
3127
3128 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3129         .name   = "timer",
3130         .sysc   = &omap44xx_timer_sysc,
3131 };
3132
3133 /* always-on timers dev attribute */
3134 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3135         .timer_capability       = OMAP_TIMER_ALWON,
3136 };
3137
3138 /* pwm timers dev attribute */
3139 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3140         .timer_capability       = OMAP_TIMER_HAS_PWM,
3141 };
3142
3143 /* timers with DSP interrupt dev attribute */
3144 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3145         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3146 };
3147
3148 /* pwm timers with DSP interrupt dev attribute */
3149 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3150         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3151 };
3152
3153 /* timer1 */
3154 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3155         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3156         { .irq = -1 }
3157 };
3158
3159 static struct omap_hwmod omap44xx_timer1_hwmod = {
3160         .name           = "timer1",
3161         .class          = &omap44xx_timer_1ms_hwmod_class,
3162         .clkdm_name     = "l4_wkup_clkdm",
3163         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3164         .mpu_irqs       = omap44xx_timer1_irqs,
3165         .main_clk       = "timer1_fck",
3166         .prcm = {
3167                 .omap4 = {
3168                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3169                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3170                         .modulemode   = MODULEMODE_SWCTRL,
3171                 },
3172         },
3173         .dev_attr       = &capability_alwon_dev_attr,
3174 };
3175
3176 /* timer2 */
3177 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3178         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3179         { .irq = -1 }
3180 };
3181
3182 static struct omap_hwmod omap44xx_timer2_hwmod = {
3183         .name           = "timer2",
3184         .class          = &omap44xx_timer_1ms_hwmod_class,
3185         .clkdm_name     = "l4_per_clkdm",
3186         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3187         .mpu_irqs       = omap44xx_timer2_irqs,
3188         .main_clk       = "timer2_fck",
3189         .prcm = {
3190                 .omap4 = {
3191                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3192                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3193                         .modulemode   = MODULEMODE_SWCTRL,
3194                 },
3195         },
3196 };
3197
3198 /* timer3 */
3199 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3200         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3201         { .irq = -1 }
3202 };
3203
3204 static struct omap_hwmod omap44xx_timer3_hwmod = {
3205         .name           = "timer3",
3206         .class          = &omap44xx_timer_hwmod_class,
3207         .clkdm_name     = "l4_per_clkdm",
3208         .mpu_irqs       = omap44xx_timer3_irqs,
3209         .main_clk       = "timer3_fck",
3210         .prcm = {
3211                 .omap4 = {
3212                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3213                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3214                         .modulemode   = MODULEMODE_SWCTRL,
3215                 },
3216         },
3217 };
3218
3219 /* timer4 */
3220 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3221         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3222         { .irq = -1 }
3223 };
3224
3225 static struct omap_hwmod omap44xx_timer4_hwmod = {
3226         .name           = "timer4",
3227         .class          = &omap44xx_timer_hwmod_class,
3228         .clkdm_name     = "l4_per_clkdm",
3229         .mpu_irqs       = omap44xx_timer4_irqs,
3230         .main_clk       = "timer4_fck",
3231         .prcm = {
3232                 .omap4 = {
3233                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3234                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3235                         .modulemode   = MODULEMODE_SWCTRL,
3236                 },
3237         },
3238 };
3239
3240 /* timer5 */
3241 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3242         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3243         { .irq = -1 }
3244 };
3245
3246 static struct omap_hwmod omap44xx_timer5_hwmod = {
3247         .name           = "timer5",
3248         .class          = &omap44xx_timer_hwmod_class,
3249         .clkdm_name     = "abe_clkdm",
3250         .mpu_irqs       = omap44xx_timer5_irqs,
3251         .main_clk       = "timer5_fck",
3252         .prcm = {
3253                 .omap4 = {
3254                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3255                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3256                         .modulemode   = MODULEMODE_SWCTRL,
3257                 },
3258         },
3259         .dev_attr       = &capability_dsp_dev_attr,
3260 };
3261
3262 /* timer6 */
3263 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3264         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3265         { .irq = -1 }
3266 };
3267
3268 static struct omap_hwmod omap44xx_timer6_hwmod = {
3269         .name           = "timer6",
3270         .class          = &omap44xx_timer_hwmod_class,
3271         .clkdm_name     = "abe_clkdm",
3272         .mpu_irqs       = omap44xx_timer6_irqs,
3273
3274         .main_clk       = "timer6_fck",
3275         .prcm = {
3276                 .omap4 = {
3277                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3278                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3279                         .modulemode   = MODULEMODE_SWCTRL,
3280                 },
3281         },
3282         .dev_attr       = &capability_dsp_dev_attr,
3283 };
3284
3285 /* timer7 */
3286 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3287         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3288         { .irq = -1 }
3289 };
3290
3291 static struct omap_hwmod omap44xx_timer7_hwmod = {
3292         .name           = "timer7",
3293         .class          = &omap44xx_timer_hwmod_class,
3294         .clkdm_name     = "abe_clkdm",
3295         .mpu_irqs       = omap44xx_timer7_irqs,
3296         .main_clk       = "timer7_fck",
3297         .prcm = {
3298                 .omap4 = {
3299                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3300                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3301                         .modulemode   = MODULEMODE_SWCTRL,
3302                 },
3303         },
3304         .dev_attr       = &capability_dsp_dev_attr,
3305 };
3306
3307 /* timer8 */
3308 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3309         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3310         { .irq = -1 }
3311 };
3312
3313 static struct omap_hwmod omap44xx_timer8_hwmod = {
3314         .name           = "timer8",
3315         .class          = &omap44xx_timer_hwmod_class,
3316         .clkdm_name     = "abe_clkdm",
3317         .mpu_irqs       = omap44xx_timer8_irqs,
3318         .main_clk       = "timer8_fck",
3319         .prcm = {
3320                 .omap4 = {
3321                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3322                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3323                         .modulemode   = MODULEMODE_SWCTRL,
3324                 },
3325         },
3326         .dev_attr       = &capability_dsp_pwm_dev_attr,
3327 };
3328
3329 /* timer9 */
3330 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3331         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3332         { .irq = -1 }
3333 };
3334
3335 static struct omap_hwmod omap44xx_timer9_hwmod = {
3336         .name           = "timer9",
3337         .class          = &omap44xx_timer_hwmod_class,
3338         .clkdm_name     = "l4_per_clkdm",
3339         .mpu_irqs       = omap44xx_timer9_irqs,
3340         .main_clk       = "timer9_fck",
3341         .prcm = {
3342                 .omap4 = {
3343                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3344                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3345                         .modulemode   = MODULEMODE_SWCTRL,
3346                 },
3347         },
3348         .dev_attr       = &capability_pwm_dev_attr,
3349 };
3350
3351 /* timer10 */
3352 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3353         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3354         { .irq = -1 }
3355 };
3356
3357 static struct omap_hwmod omap44xx_timer10_hwmod = {
3358         .name           = "timer10",
3359         .class          = &omap44xx_timer_1ms_hwmod_class,
3360         .clkdm_name     = "l4_per_clkdm",
3361         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
3362         .mpu_irqs       = omap44xx_timer10_irqs,
3363         .main_clk       = "timer10_fck",
3364         .prcm = {
3365                 .omap4 = {
3366                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3367                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3368                         .modulemode   = MODULEMODE_SWCTRL,
3369                 },
3370         },
3371         .dev_attr       = &capability_pwm_dev_attr,
3372 };
3373
3374 /* timer11 */
3375 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3376         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3377         { .irq = -1 }
3378 };
3379
3380 static struct omap_hwmod omap44xx_timer11_hwmod = {
3381         .name           = "timer11",
3382         .class          = &omap44xx_timer_hwmod_class,
3383         .clkdm_name     = "l4_per_clkdm",
3384         .mpu_irqs       = omap44xx_timer11_irqs,
3385         .main_clk       = "timer11_fck",
3386         .prcm = {
3387                 .omap4 = {
3388                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3389                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3390                         .modulemode   = MODULEMODE_SWCTRL,
3391                 },
3392         },
3393         .dev_attr       = &capability_pwm_dev_attr,
3394 };
3395
3396 /*
3397  * 'uart' class
3398  * universal asynchronous receiver/transmitter (uart)
3399  */
3400
3401 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3402         .rev_offs       = 0x0050,
3403         .sysc_offs      = 0x0054,
3404         .syss_offs      = 0x0058,
3405         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3406                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3407                            SYSS_HAS_RESET_STATUS),
3408         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3409                            SIDLE_SMART_WKUP),
3410         .sysc_fields    = &omap_hwmod_sysc_type1,
3411 };
3412
3413 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3414         .name   = "uart",
3415         .sysc   = &omap44xx_uart_sysc,
3416 };
3417
3418 /* uart1 */
3419 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3420         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3421         { .irq = -1 }
3422 };
3423
3424 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3425         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3426         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3427         { .dma_req = -1 }
3428 };
3429
3430 static struct omap_hwmod omap44xx_uart1_hwmod = {
3431         .name           = "uart1",
3432         .class          = &omap44xx_uart_hwmod_class,
3433         .clkdm_name     = "l4_per_clkdm",
3434         .mpu_irqs       = omap44xx_uart1_irqs,
3435         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3436         .main_clk       = "uart1_fck",
3437         .prcm = {
3438                 .omap4 = {
3439                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3440                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3441                         .modulemode   = MODULEMODE_SWCTRL,
3442                 },
3443         },
3444 };
3445
3446 /* uart2 */
3447 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3448         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3449         { .irq = -1 }
3450 };
3451
3452 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3453         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3454         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3455         { .dma_req = -1 }
3456 };
3457
3458 static struct omap_hwmod omap44xx_uart2_hwmod = {
3459         .name           = "uart2",
3460         .class          = &omap44xx_uart_hwmod_class,
3461         .clkdm_name     = "l4_per_clkdm",
3462         .mpu_irqs       = omap44xx_uart2_irqs,
3463         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3464         .main_clk       = "uart2_fck",
3465         .prcm = {
3466                 .omap4 = {
3467                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3468                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3469                         .modulemode   = MODULEMODE_SWCTRL,
3470                 },
3471         },
3472 };
3473
3474 /* uart3 */
3475 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3476         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3477         { .irq = -1 }
3478 };
3479
3480 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3481         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3482         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3483         { .dma_req = -1 }
3484 };
3485
3486 static struct omap_hwmod omap44xx_uart3_hwmod = {
3487         .name           = "uart3",
3488         .class          = &omap44xx_uart_hwmod_class,
3489         .clkdm_name     = "l4_per_clkdm",
3490         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3491         .mpu_irqs       = omap44xx_uart3_irqs,
3492         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3493         .main_clk       = "uart3_fck",
3494         .prcm = {
3495                 .omap4 = {
3496                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3497                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3498                         .modulemode   = MODULEMODE_SWCTRL,
3499                 },
3500         },
3501 };
3502
3503 /* uart4 */
3504 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3505         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3506         { .irq = -1 }
3507 };
3508
3509 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3510         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3511         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3512         { .dma_req = -1 }
3513 };
3514
3515 static struct omap_hwmod omap44xx_uart4_hwmod = {
3516         .name           = "uart4",
3517         .class          = &omap44xx_uart_hwmod_class,
3518         .clkdm_name     = "l4_per_clkdm",
3519         .mpu_irqs       = omap44xx_uart4_irqs,
3520         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3521         .main_clk       = "uart4_fck",
3522         .prcm = {
3523                 .omap4 = {
3524                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3525                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3526                         .modulemode   = MODULEMODE_SWCTRL,
3527                 },
3528         },
3529 };
3530
3531 /*
3532  * 'usb_host_fs' class
3533  * full-speed usb host controller
3534  */
3535
3536 /* The IP is not compliant to type1 / type2 scheme */
3537 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3538         .midle_shift    = 4,
3539         .sidle_shift    = 2,
3540         .srst_shift     = 1,
3541 };
3542
3543 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3544         .rev_offs       = 0x0000,
3545         .sysc_offs      = 0x0210,
3546         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3547                            SYSC_HAS_SOFTRESET),
3548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3549                            SIDLE_SMART_WKUP),
3550         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3551 };
3552
3553 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3554         .name   = "usb_host_fs",
3555         .sysc   = &omap44xx_usb_host_fs_sysc,
3556 };
3557
3558 /* usb_host_fs */
3559 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3560         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3561         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3562         { .irq = -1 }
3563 };
3564
3565 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3566         .name           = "usb_host_fs",
3567         .class          = &omap44xx_usb_host_fs_hwmod_class,
3568         .clkdm_name     = "l3_init_clkdm",
3569         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3570         .main_clk       = "usb_host_fs_fck",
3571         .prcm = {
3572                 .omap4 = {
3573                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3574                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3575                         .modulemode   = MODULEMODE_SWCTRL,
3576                 },
3577         },
3578 };
3579
3580 /*
3581  * 'usb_host_hs' class
3582  * high-speed multi-port usb host controller
3583  */
3584
3585 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3586         .rev_offs       = 0x0000,
3587         .sysc_offs      = 0x0010,
3588         .syss_offs      = 0x0014,
3589         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3590                            SYSC_HAS_SOFTRESET),
3591         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3592                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3593                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3594         .sysc_fields    = &omap_hwmod_sysc_type2,
3595 };
3596
3597 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3598         .name   = "usb_host_hs",
3599         .sysc   = &omap44xx_usb_host_hs_sysc,
3600 };
3601
3602 /* usb_host_hs */
3603 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3604         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3605         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3606         { .irq = -1 }
3607 };
3608
3609 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3610         .name           = "usb_host_hs",
3611         .class          = &omap44xx_usb_host_hs_hwmod_class,
3612         .clkdm_name     = "l3_init_clkdm",
3613         .main_clk       = "usb_host_hs_fck",
3614         .prcm = {
3615                 .omap4 = {
3616                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3617                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3618                         .modulemode   = MODULEMODE_SWCTRL,
3619                 },
3620         },
3621         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3622
3623         /*
3624          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3625          * id: i660
3626          *
3627          * Description:
3628          * In the following configuration :
3629          * - USBHOST module is set to smart-idle mode
3630          * - PRCM asserts idle_req to the USBHOST module ( This typically
3631          *   happens when the system is going to a low power mode : all ports
3632          *   have been suspended, the master part of the USBHOST module has
3633          *   entered the standby state, and SW has cut the functional clocks)
3634          * - an USBHOST interrupt occurs before the module is able to answer
3635          *   idle_ack, typically a remote wakeup IRQ.
3636          * Then the USB HOST module will enter a deadlock situation where it
3637          * is no more accessible nor functional.
3638          *
3639          * Workaround:
3640          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3641          */
3642
3643         /*
3644          * Errata: USB host EHCI may stall when entering smart-standby mode
3645          * Id: i571
3646          *
3647          * Description:
3648          * When the USBHOST module is set to smart-standby mode, and when it is
3649          * ready to enter the standby state (i.e. all ports are suspended and
3650          * all attached devices are in suspend mode), then it can wrongly assert
3651          * the Mstandby signal too early while there are still some residual OCP
3652          * transactions ongoing. If this condition occurs, the internal state
3653          * machine may go to an undefined state and the USB link may be stuck
3654          * upon the next resume.
3655          *
3656          * Workaround:
3657          * Don't use smart standby; use only force standby,
3658          * hence HWMOD_SWSUP_MSTANDBY
3659          */
3660
3661         /*
3662          * During system boot; If the hwmod framework resets the module
3663          * the module will have smart idle settings; which can lead to deadlock
3664          * (above Errata Id:i660); so, dont reset the module during boot;
3665          * Use HWMOD_INIT_NO_RESET.
3666          */
3667
3668         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3669                           HWMOD_INIT_NO_RESET,
3670 };
3671
3672 /*
3673  * 'usb_otg_hs' class
3674  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3675  */
3676
3677 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3678         .rev_offs       = 0x0400,
3679         .sysc_offs      = 0x0404,
3680         .syss_offs      = 0x0408,
3681         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3682                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3683                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3684         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3685                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3686                            MSTANDBY_SMART),
3687         .sysc_fields    = &omap_hwmod_sysc_type1,
3688 };
3689
3690 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3691         .name   = "usb_otg_hs",
3692         .sysc   = &omap44xx_usb_otg_hs_sysc,
3693 };
3694
3695 /* usb_otg_hs */
3696 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3697         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3698         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3699         { .irq = -1 }
3700 };
3701
3702 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3703         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3704 };
3705
3706 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3707         .name           = "usb_otg_hs",
3708         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3709         .clkdm_name     = "l3_init_clkdm",
3710         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3711         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3712         .main_clk       = "usb_otg_hs_ick",
3713         .prcm = {
3714                 .omap4 = {
3715                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3716                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3717                         .modulemode   = MODULEMODE_HWCTRL,
3718                 },
3719         },
3720         .opt_clks       = usb_otg_hs_opt_clks,
3721         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3722 };
3723
3724 /*
3725  * 'usb_tll_hs' class
3726  * usb_tll_hs module is the adapter on the usb_host_hs ports
3727  */
3728
3729 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3730         .rev_offs       = 0x0000,
3731         .sysc_offs      = 0x0010,
3732         .syss_offs      = 0x0014,
3733         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3734                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3735                            SYSC_HAS_AUTOIDLE),
3736         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3737         .sysc_fields    = &omap_hwmod_sysc_type1,
3738 };
3739
3740 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3741         .name   = "usb_tll_hs",
3742         .sysc   = &omap44xx_usb_tll_hs_sysc,
3743 };
3744
3745 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3746         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3747         { .irq = -1 }
3748 };
3749
3750 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3751         .name           = "usb_tll_hs",
3752         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3753         .clkdm_name     = "l3_init_clkdm",
3754         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3755         .main_clk       = "usb_tll_hs_ick",
3756         .prcm = {
3757                 .omap4 = {
3758                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3759                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3760                         .modulemode   = MODULEMODE_HWCTRL,
3761                 },
3762         },
3763 };
3764
3765 /*
3766  * 'wd_timer' class
3767  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3768  * overflow condition
3769  */
3770
3771 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3772         .rev_offs       = 0x0000,
3773         .sysc_offs      = 0x0010,
3774         .syss_offs      = 0x0014,
3775         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3776                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3777         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3778                            SIDLE_SMART_WKUP),
3779         .sysc_fields    = &omap_hwmod_sysc_type1,
3780 };
3781
3782 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3783         .name           = "wd_timer",
3784         .sysc           = &omap44xx_wd_timer_sysc,
3785         .pre_shutdown   = &omap2_wd_timer_disable,
3786         .reset          = &omap2_wd_timer_reset,
3787 };
3788
3789 /* wd_timer2 */
3790 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3791         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3792         { .irq = -1 }
3793 };
3794
3795 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3796         .name           = "wd_timer2",
3797         .class          = &omap44xx_wd_timer_hwmod_class,
3798         .clkdm_name     = "l4_wkup_clkdm",
3799         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3800         .main_clk       = "wd_timer2_fck",
3801         .prcm = {
3802                 .omap4 = {
3803                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3804                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3805                         .modulemode   = MODULEMODE_SWCTRL,
3806                 },
3807         },
3808 };
3809
3810 /* wd_timer3 */
3811 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3812         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3813         { .irq = -1 }
3814 };
3815
3816 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3817         .name           = "wd_timer3",
3818         .class          = &omap44xx_wd_timer_hwmod_class,
3819         .clkdm_name     = "abe_clkdm",
3820         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3821         .main_clk       = "wd_timer3_fck",
3822         .prcm = {
3823                 .omap4 = {
3824                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3825                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3826                         .modulemode   = MODULEMODE_SWCTRL,
3827                 },
3828         },
3829 };
3830
3831
3832 /*
3833  * interfaces
3834  */
3835
3836 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3837         {
3838                 .pa_start       = 0x4a204000,
3839                 .pa_end         = 0x4a2040ff,
3840                 .flags          = ADDR_TYPE_RT
3841         },
3842         { }
3843 };
3844
3845 /* c2c -> c2c_target_fw */
3846 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3847         .master         = &omap44xx_c2c_hwmod,
3848         .slave          = &omap44xx_c2c_target_fw_hwmod,
3849         .clk            = "div_core_ck",
3850         .addr           = omap44xx_c2c_target_fw_addrs,
3851         .user           = OCP_USER_MPU,
3852 };
3853
3854 /* l4_cfg -> c2c_target_fw */
3855 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3856         .master         = &omap44xx_l4_cfg_hwmod,
3857         .slave          = &omap44xx_c2c_target_fw_hwmod,
3858         .clk            = "l4_div_ck",
3859         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3860 };
3861
3862 /* l3_main_1 -> dmm */
3863 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3864         .master         = &omap44xx_l3_main_1_hwmod,
3865         .slave          = &omap44xx_dmm_hwmod,
3866         .clk            = "l3_div_ck",
3867         .user           = OCP_USER_SDMA,
3868 };
3869
3870 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3871         {
3872                 .pa_start       = 0x4e000000,
3873                 .pa_end         = 0x4e0007ff,
3874                 .flags          = ADDR_TYPE_RT
3875         },
3876         { }
3877 };
3878
3879 /* mpu -> dmm */
3880 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3881         .master         = &omap44xx_mpu_hwmod,
3882         .slave          = &omap44xx_dmm_hwmod,
3883         .clk            = "l3_div_ck",
3884         .addr           = omap44xx_dmm_addrs,
3885         .user           = OCP_USER_MPU,
3886 };
3887
3888 /* c2c -> emif_fw */
3889 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3890         .master         = &omap44xx_c2c_hwmod,
3891         .slave          = &omap44xx_emif_fw_hwmod,
3892         .clk            = "div_core_ck",
3893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3894 };
3895
3896 /* dmm -> emif_fw */
3897 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3898         .master         = &omap44xx_dmm_hwmod,
3899         .slave          = &omap44xx_emif_fw_hwmod,
3900         .clk            = "l3_div_ck",
3901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3902 };
3903
3904 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3905         {
3906                 .pa_start       = 0x4a20c000,
3907                 .pa_end         = 0x4a20c0ff,
3908                 .flags          = ADDR_TYPE_RT
3909         },
3910         { }
3911 };
3912
3913 /* l4_cfg -> emif_fw */
3914 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3915         .master         = &omap44xx_l4_cfg_hwmod,
3916         .slave          = &omap44xx_emif_fw_hwmod,
3917         .clk            = "l4_div_ck",
3918         .addr           = omap44xx_emif_fw_addrs,
3919         .user           = OCP_USER_MPU,
3920 };
3921
3922 /* iva -> l3_instr */
3923 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3924         .master         = &omap44xx_iva_hwmod,
3925         .slave          = &omap44xx_l3_instr_hwmod,
3926         .clk            = "l3_div_ck",
3927         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3928 };
3929
3930 /* l3_main_3 -> l3_instr */
3931 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3932         .master         = &omap44xx_l3_main_3_hwmod,
3933         .slave          = &omap44xx_l3_instr_hwmod,
3934         .clk            = "l3_div_ck",
3935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3936 };
3937
3938 /* ocp_wp_noc -> l3_instr */
3939 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3940         .master         = &omap44xx_ocp_wp_noc_hwmod,
3941         .slave          = &omap44xx_l3_instr_hwmod,
3942         .clk            = "l3_div_ck",
3943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3944 };
3945
3946 /* dsp -> l3_main_1 */
3947 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3948         .master         = &omap44xx_dsp_hwmod,
3949         .slave          = &omap44xx_l3_main_1_hwmod,
3950         .clk            = "l3_div_ck",
3951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3952 };
3953
3954 /* dss -> l3_main_1 */
3955 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3956         .master         = &omap44xx_dss_hwmod,
3957         .slave          = &omap44xx_l3_main_1_hwmod,
3958         .clk            = "l3_div_ck",
3959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3960 };
3961
3962 /* l3_main_2 -> l3_main_1 */
3963 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3964         .master         = &omap44xx_l3_main_2_hwmod,
3965         .slave          = &omap44xx_l3_main_1_hwmod,
3966         .clk            = "l3_div_ck",
3967         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3969
3970 /* l4_cfg -> l3_main_1 */
3971 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3972         .master         = &omap44xx_l4_cfg_hwmod,
3973         .slave          = &omap44xx_l3_main_1_hwmod,
3974         .clk            = "l4_div_ck",
3975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3977
3978 /* mmc1 -> l3_main_1 */
3979 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3980         .master         = &omap44xx_mmc1_hwmod,
3981         .slave          = &omap44xx_l3_main_1_hwmod,
3982         .clk            = "l3_div_ck",
3983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3984 };
3985
3986 /* mmc2 -> l3_main_1 */
3987 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3988         .master         = &omap44xx_mmc2_hwmod,
3989         .slave          = &omap44xx_l3_main_1_hwmod,
3990         .clk            = "l3_div_ck",
3991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3992 };
3993
3994 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3995         {
3996                 .pa_start       = 0x44000000,
3997                 .pa_end         = 0x44000fff,
3998                 .flags          = ADDR_TYPE_RT
3999         },
4000         { }
4001 };
4002
4003 /* mpu -> l3_main_1 */
4004 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
4005         .master         = &omap44xx_mpu_hwmod,
4006         .slave          = &omap44xx_l3_main_1_hwmod,
4007         .clk            = "l3_div_ck",
4008         .addr           = omap44xx_l3_main_1_addrs,
4009         .user           = OCP_USER_MPU,
4010 };
4011
4012 /* c2c_target_fw -> l3_main_2 */
4013 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4014         .master         = &omap44xx_c2c_target_fw_hwmod,
4015         .slave          = &omap44xx_l3_main_2_hwmod,
4016         .clk            = "l3_div_ck",
4017         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4018 };
4019
4020 /* debugss -> l3_main_2 */
4021 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4022         .master         = &omap44xx_debugss_hwmod,
4023         .slave          = &omap44xx_l3_main_2_hwmod,
4024         .clk            = "dbgclk_mux_ck",
4025         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4026 };
4027
4028 /* dma_system -> l3_main_2 */
4029 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4030         .master         = &omap44xx_dma_system_hwmod,
4031         .slave          = &omap44xx_l3_main_2_hwmod,
4032         .clk            = "l3_div_ck",
4033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4034 };
4035
4036 /* fdif -> l3_main_2 */
4037 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4038         .master         = &omap44xx_fdif_hwmod,
4039         .slave          = &omap44xx_l3_main_2_hwmod,
4040         .clk            = "l3_div_ck",
4041         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 /* gpu -> l3_main_2 */
4045 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4046         .master         = &omap44xx_gpu_hwmod,
4047         .slave          = &omap44xx_l3_main_2_hwmod,
4048         .clk            = "l3_div_ck",
4049         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4050 };
4051
4052 /* hsi -> l3_main_2 */
4053 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4054         .master         = &omap44xx_hsi_hwmod,
4055         .slave          = &omap44xx_l3_main_2_hwmod,
4056         .clk            = "l3_div_ck",
4057         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4058 };
4059
4060 /* ipu -> l3_main_2 */
4061 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4062         .master         = &omap44xx_ipu_hwmod,
4063         .slave          = &omap44xx_l3_main_2_hwmod,
4064         .clk            = "l3_div_ck",
4065         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4066 };
4067
4068 /* iss -> l3_main_2 */
4069 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4070         .master         = &omap44xx_iss_hwmod,
4071         .slave          = &omap44xx_l3_main_2_hwmod,
4072         .clk            = "l3_div_ck",
4073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4074 };
4075
4076 /* iva -> l3_main_2 */
4077 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4078         .master         = &omap44xx_iva_hwmod,
4079         .slave          = &omap44xx_l3_main_2_hwmod,
4080         .clk            = "l3_div_ck",
4081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4082 };
4083
4084 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4085         {
4086                 .pa_start       = 0x44800000,
4087                 .pa_end         = 0x44801fff,
4088                 .flags          = ADDR_TYPE_RT
4089         },
4090         { }
4091 };
4092
4093 /* l3_main_1 -> l3_main_2 */
4094 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4095         .master         = &omap44xx_l3_main_1_hwmod,
4096         .slave          = &omap44xx_l3_main_2_hwmod,
4097         .clk            = "l3_div_ck",
4098         .addr           = omap44xx_l3_main_2_addrs,
4099         .user           = OCP_USER_MPU,
4100 };
4101
4102 /* l4_cfg -> l3_main_2 */
4103 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4104         .master         = &omap44xx_l4_cfg_hwmod,
4105         .slave          = &omap44xx_l3_main_2_hwmod,
4106         .clk            = "l4_div_ck",
4107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4108 };
4109
4110 /* usb_host_fs -> l3_main_2 */
4111 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4112         .master         = &omap44xx_usb_host_fs_hwmod,
4113         .slave          = &omap44xx_l3_main_2_hwmod,
4114         .clk            = "l3_div_ck",
4115         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4116 };
4117
4118 /* usb_host_hs -> l3_main_2 */
4119 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4120         .master         = &omap44xx_usb_host_hs_hwmod,
4121         .slave          = &omap44xx_l3_main_2_hwmod,
4122         .clk            = "l3_div_ck",
4123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4124 };
4125
4126 /* usb_otg_hs -> l3_main_2 */
4127 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4128         .master         = &omap44xx_usb_otg_hs_hwmod,
4129         .slave          = &omap44xx_l3_main_2_hwmod,
4130         .clk            = "l3_div_ck",
4131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4132 };
4133
4134 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4135         {
4136                 .pa_start       = 0x45000000,
4137                 .pa_end         = 0x45000fff,
4138                 .flags          = ADDR_TYPE_RT
4139         },
4140         { }
4141 };
4142
4143 /* l3_main_1 -> l3_main_3 */
4144 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4145         .master         = &omap44xx_l3_main_1_hwmod,
4146         .slave          = &omap44xx_l3_main_3_hwmod,
4147         .clk            = "l3_div_ck",
4148         .addr           = omap44xx_l3_main_3_addrs,
4149         .user           = OCP_USER_MPU,
4150 };
4151
4152 /* l3_main_2 -> l3_main_3 */
4153 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4154         .master         = &omap44xx_l3_main_2_hwmod,
4155         .slave          = &omap44xx_l3_main_3_hwmod,
4156         .clk            = "l3_div_ck",
4157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4158 };
4159
4160 /* l4_cfg -> l3_main_3 */
4161 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4162         .master         = &omap44xx_l4_cfg_hwmod,
4163         .slave          = &omap44xx_l3_main_3_hwmod,
4164         .clk            = "l4_div_ck",
4165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4166 };
4167
4168 /* aess -> l4_abe */
4169 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4170         .master         = &omap44xx_aess_hwmod,
4171         .slave          = &omap44xx_l4_abe_hwmod,
4172         .clk            = "ocp_abe_iclk",
4173         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4174 };
4175
4176 /* dsp -> l4_abe */
4177 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4178         .master         = &omap44xx_dsp_hwmod,
4179         .slave          = &omap44xx_l4_abe_hwmod,
4180         .clk            = "ocp_abe_iclk",
4181         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4182 };
4183
4184 /* l3_main_1 -> l4_abe */
4185 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4186         .master         = &omap44xx_l3_main_1_hwmod,
4187         .slave          = &omap44xx_l4_abe_hwmod,
4188         .clk            = "l3_div_ck",
4189         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4190 };
4191
4192 /* mpu -> l4_abe */
4193 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4194         .master         = &omap44xx_mpu_hwmod,
4195         .slave          = &omap44xx_l4_abe_hwmod,
4196         .clk            = "ocp_abe_iclk",
4197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4198 };
4199
4200 /* l3_main_1 -> l4_cfg */
4201 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4202         .master         = &omap44xx_l3_main_1_hwmod,
4203         .slave          = &omap44xx_l4_cfg_hwmod,
4204         .clk            = "l3_div_ck",
4205         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4206 };
4207
4208 /* l3_main_2 -> l4_per */
4209 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4210         .master         = &omap44xx_l3_main_2_hwmod,
4211         .slave          = &omap44xx_l4_per_hwmod,
4212         .clk            = "l3_div_ck",
4213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4214 };
4215
4216 /* l4_cfg -> l4_wkup */
4217 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4218         .master         = &omap44xx_l4_cfg_hwmod,
4219         .slave          = &omap44xx_l4_wkup_hwmod,
4220         .clk            = "l4_div_ck",
4221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4222 };
4223
4224 /* mpu -> mpu_private */
4225 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4226         .master         = &omap44xx_mpu_hwmod,
4227         .slave          = &omap44xx_mpu_private_hwmod,
4228         .clk            = "l3_div_ck",
4229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4230 };
4231
4232 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4233         {
4234                 .pa_start       = 0x4a102000,
4235                 .pa_end         = 0x4a10207f,
4236                 .flags          = ADDR_TYPE_RT
4237         },
4238         { }
4239 };
4240
4241 /* l4_cfg -> ocp_wp_noc */
4242 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4243         .master         = &omap44xx_l4_cfg_hwmod,
4244         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4245         .clk            = "l4_div_ck",
4246         .addr           = omap44xx_ocp_wp_noc_addrs,
4247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4248 };
4249
4250 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4251         {
4252                 .pa_start       = 0x401f1000,
4253                 .pa_end         = 0x401f13ff,
4254                 .flags          = ADDR_TYPE_RT
4255         },
4256         { }
4257 };
4258
4259 /* l4_abe -> aess */
4260 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4261         .master         = &omap44xx_l4_abe_hwmod,
4262         .slave          = &omap44xx_aess_hwmod,
4263         .clk            = "ocp_abe_iclk",
4264         .addr           = omap44xx_aess_addrs,
4265         .user           = OCP_USER_MPU,
4266 };
4267
4268 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4269         {
4270                 .pa_start       = 0x490f1000,
4271                 .pa_end         = 0x490f13ff,
4272                 .flags          = ADDR_TYPE_RT
4273         },
4274         { }
4275 };
4276
4277 /* l4_abe -> aess (dma) */
4278 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4279         .master         = &omap44xx_l4_abe_hwmod,
4280         .slave          = &omap44xx_aess_hwmod,
4281         .clk            = "ocp_abe_iclk",
4282         .addr           = omap44xx_aess_dma_addrs,
4283         .user           = OCP_USER_SDMA,
4284 };
4285
4286 /* l3_main_2 -> c2c */
4287 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4288         .master         = &omap44xx_l3_main_2_hwmod,
4289         .slave          = &omap44xx_c2c_hwmod,
4290         .clk            = "l3_div_ck",
4291         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4292 };
4293
4294 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4295         {
4296                 .pa_start       = 0x4a304000,
4297                 .pa_end         = 0x4a30401f,
4298                 .flags          = ADDR_TYPE_RT
4299         },
4300         { }
4301 };
4302
4303 /* l4_wkup -> counter_32k */
4304 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4305         .master         = &omap44xx_l4_wkup_hwmod,
4306         .slave          = &omap44xx_counter_32k_hwmod,
4307         .clk            = "l4_wkup_clk_mux_ck",
4308         .addr           = omap44xx_counter_32k_addrs,
4309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4310 };
4311
4312 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4313         {
4314                 .pa_start       = 0x4a002000,
4315                 .pa_end         = 0x4a0027ff,
4316                 .flags          = ADDR_TYPE_RT
4317         },
4318         { }
4319 };
4320
4321 /* l4_cfg -> ctrl_module_core */
4322 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4323         .master         = &omap44xx_l4_cfg_hwmod,
4324         .slave          = &omap44xx_ctrl_module_core_hwmod,
4325         .clk            = "l4_div_ck",
4326         .addr           = omap44xx_ctrl_module_core_addrs,
4327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4328 };
4329
4330 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4331         {
4332                 .pa_start       = 0x4a100000,
4333                 .pa_end         = 0x4a1007ff,
4334                 .flags          = ADDR_TYPE_RT
4335         },
4336         { }
4337 };
4338
4339 /* l4_cfg -> ctrl_module_pad_core */
4340 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4341         .master         = &omap44xx_l4_cfg_hwmod,
4342         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4343         .clk            = "l4_div_ck",
4344         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4346 };
4347
4348 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4349         {
4350                 .pa_start       = 0x4a30c000,
4351                 .pa_end         = 0x4a30c7ff,
4352                 .flags          = ADDR_TYPE_RT
4353         },
4354         { }
4355 };
4356
4357 /* l4_wkup -> ctrl_module_wkup */
4358 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4359         .master         = &omap44xx_l4_wkup_hwmod,
4360         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4361         .clk            = "l4_wkup_clk_mux_ck",
4362         .addr           = omap44xx_ctrl_module_wkup_addrs,
4363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4364 };
4365
4366 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4367         {
4368                 .pa_start       = 0x4a31e000,
4369                 .pa_end         = 0x4a31e7ff,
4370                 .flags          = ADDR_TYPE_RT
4371         },
4372         { }
4373 };
4374
4375 /* l4_wkup -> ctrl_module_pad_wkup */
4376 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4377         .master         = &omap44xx_l4_wkup_hwmod,
4378         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4379         .clk            = "l4_wkup_clk_mux_ck",
4380         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4382 };
4383
4384 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4385         {
4386                 .pa_start       = 0x54160000,
4387                 .pa_end         = 0x54167fff,
4388                 .flags          = ADDR_TYPE_RT
4389         },
4390         { }
4391 };
4392
4393 /* l3_instr -> debugss */
4394 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4395         .master         = &omap44xx_l3_instr_hwmod,
4396         .slave          = &omap44xx_debugss_hwmod,
4397         .clk            = "l3_div_ck",
4398         .addr           = omap44xx_debugss_addrs,
4399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4400 };
4401
4402 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4403         {
4404                 .pa_start       = 0x4a056000,
4405                 .pa_end         = 0x4a056fff,
4406                 .flags          = ADDR_TYPE_RT
4407         },
4408         { }
4409 };
4410
4411 /* l4_cfg -> dma_system */
4412 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4413         .master         = &omap44xx_l4_cfg_hwmod,
4414         .slave          = &omap44xx_dma_system_hwmod,
4415         .clk            = "l4_div_ck",
4416         .addr           = omap44xx_dma_system_addrs,
4417         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4418 };
4419
4420 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4421         {
4422                 .name           = "mpu",
4423                 .pa_start       = 0x4012e000,
4424                 .pa_end         = 0x4012e07f,
4425                 .flags          = ADDR_TYPE_RT
4426         },
4427         { }
4428 };
4429
4430 /* l4_abe -> dmic */
4431 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4432         .master         = &omap44xx_l4_abe_hwmod,
4433         .slave          = &omap44xx_dmic_hwmod,
4434         .clk            = "ocp_abe_iclk",
4435         .addr           = omap44xx_dmic_addrs,
4436         .user           = OCP_USER_MPU,
4437 };
4438
4439 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4440         {
4441                 .name           = "dma",
4442                 .pa_start       = 0x4902e000,
4443                 .pa_end         = 0x4902e07f,
4444                 .flags          = ADDR_TYPE_RT
4445         },
4446         { }
4447 };
4448
4449 /* l4_abe -> dmic (dma) */
4450 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4451         .master         = &omap44xx_l4_abe_hwmod,
4452         .slave          = &omap44xx_dmic_hwmod,
4453         .clk            = "ocp_abe_iclk",
4454         .addr           = omap44xx_dmic_dma_addrs,
4455         .user           = OCP_USER_SDMA,
4456 };
4457
4458 /* dsp -> iva */
4459 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4460         .master         = &omap44xx_dsp_hwmod,
4461         .slave          = &omap44xx_iva_hwmod,
4462         .clk            = "dpll_iva_m5x2_ck",
4463         .user           = OCP_USER_DSP,
4464 };
4465
4466 /* dsp -> sl2if */
4467 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4468         .master         = &omap44xx_dsp_hwmod,
4469         .slave          = &omap44xx_sl2if_hwmod,
4470         .clk            = "dpll_iva_m5x2_ck",
4471         .user           = OCP_USER_DSP,
4472 };
4473
4474 /* l4_cfg -> dsp */
4475 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4476         .master         = &omap44xx_l4_cfg_hwmod,
4477         .slave          = &omap44xx_dsp_hwmod,
4478         .clk            = "l4_div_ck",
4479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4480 };
4481
4482 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4483         {
4484                 .pa_start       = 0x58000000,
4485                 .pa_end         = 0x5800007f,
4486                 .flags          = ADDR_TYPE_RT
4487         },
4488         { }
4489 };
4490
4491 /* l3_main_2 -> dss */
4492 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4493         .master         = &omap44xx_l3_main_2_hwmod,
4494         .slave          = &omap44xx_dss_hwmod,
4495         .clk            = "dss_fck",
4496         .addr           = omap44xx_dss_dma_addrs,
4497         .user           = OCP_USER_SDMA,
4498 };
4499
4500 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4501         {
4502                 .pa_start       = 0x48040000,
4503                 .pa_end         = 0x4804007f,
4504                 .flags          = ADDR_TYPE_RT
4505         },
4506         { }
4507 };
4508
4509 /* l4_per -> dss */
4510 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4511         .master         = &omap44xx_l4_per_hwmod,
4512         .slave          = &omap44xx_dss_hwmod,
4513         .clk            = "l4_div_ck",
4514         .addr           = omap44xx_dss_addrs,
4515         .user           = OCP_USER_MPU,
4516 };
4517
4518 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4519         {
4520                 .pa_start       = 0x58001000,
4521                 .pa_end         = 0x58001fff,
4522                 .flags          = ADDR_TYPE_RT
4523         },
4524         { }
4525 };
4526
4527 /* l3_main_2 -> dss_dispc */
4528 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4529         .master         = &omap44xx_l3_main_2_hwmod,
4530         .slave          = &omap44xx_dss_dispc_hwmod,
4531         .clk            = "dss_fck",
4532         .addr           = omap44xx_dss_dispc_dma_addrs,
4533         .user           = OCP_USER_SDMA,
4534 };
4535
4536 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4537         {
4538                 .pa_start       = 0x48041000,
4539                 .pa_end         = 0x48041fff,
4540                 .flags          = ADDR_TYPE_RT
4541         },
4542         { }
4543 };
4544
4545 /* l4_per -> dss_dispc */
4546 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4547         .master         = &omap44xx_l4_per_hwmod,
4548         .slave          = &omap44xx_dss_dispc_hwmod,
4549         .clk            = "l4_div_ck",
4550         .addr           = omap44xx_dss_dispc_addrs,
4551         .user           = OCP_USER_MPU,
4552 };
4553
4554 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4555         {
4556                 .pa_start       = 0x58004000,
4557                 .pa_end         = 0x580041ff,
4558                 .flags          = ADDR_TYPE_RT
4559         },
4560         { }
4561 };
4562
4563 /* l3_main_2 -> dss_dsi1 */
4564 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4565         .master         = &omap44xx_l3_main_2_hwmod,
4566         .slave          = &omap44xx_dss_dsi1_hwmod,
4567         .clk            = "dss_fck",
4568         .addr           = omap44xx_dss_dsi1_dma_addrs,
4569         .user           = OCP_USER_SDMA,
4570 };
4571
4572 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4573         {
4574                 .pa_start       = 0x48044000,
4575                 .pa_end         = 0x480441ff,
4576                 .flags          = ADDR_TYPE_RT
4577         },
4578         { }
4579 };
4580
4581 /* l4_per -> dss_dsi1 */
4582 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4583         .master         = &omap44xx_l4_per_hwmod,
4584         .slave          = &omap44xx_dss_dsi1_hwmod,
4585         .clk            = "l4_div_ck",
4586         .addr           = omap44xx_dss_dsi1_addrs,
4587         .user           = OCP_USER_MPU,
4588 };
4589
4590 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4591         {
4592                 .pa_start       = 0x58005000,
4593                 .pa_end         = 0x580051ff,
4594                 .flags          = ADDR_TYPE_RT
4595         },
4596         { }
4597 };
4598
4599 /* l3_main_2 -> dss_dsi2 */
4600 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4601         .master         = &omap44xx_l3_main_2_hwmod,
4602         .slave          = &omap44xx_dss_dsi2_hwmod,
4603         .clk            = "dss_fck",
4604         .addr           = omap44xx_dss_dsi2_dma_addrs,
4605         .user           = OCP_USER_SDMA,
4606 };
4607
4608 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4609         {
4610                 .pa_start       = 0x48045000,
4611                 .pa_end         = 0x480451ff,
4612                 .flags          = ADDR_TYPE_RT
4613         },
4614         { }
4615 };
4616
4617 /* l4_per -> dss_dsi2 */
4618 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4619         .master         = &omap44xx_l4_per_hwmod,
4620         .slave          = &omap44xx_dss_dsi2_hwmod,
4621         .clk            = "l4_div_ck",
4622         .addr           = omap44xx_dss_dsi2_addrs,
4623         .user           = OCP_USER_MPU,
4624 };
4625
4626 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4627         {
4628                 .pa_start       = 0x58006000,
4629                 .pa_end         = 0x58006fff,
4630                 .flags          = ADDR_TYPE_RT
4631         },
4632         { }
4633 };
4634
4635 /* l3_main_2 -> dss_hdmi */
4636 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4637         .master         = &omap44xx_l3_main_2_hwmod,
4638         .slave          = &omap44xx_dss_hdmi_hwmod,
4639         .clk            = "dss_fck",
4640         .addr           = omap44xx_dss_hdmi_dma_addrs,
4641         .user           = OCP_USER_SDMA,
4642 };
4643
4644 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4645         {
4646                 .pa_start       = 0x48046000,
4647                 .pa_end         = 0x48046fff,
4648                 .flags          = ADDR_TYPE_RT
4649         },
4650         { }
4651 };
4652
4653 /* l4_per -> dss_hdmi */
4654 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4655         .master         = &omap44xx_l4_per_hwmod,
4656         .slave          = &omap44xx_dss_hdmi_hwmod,
4657         .clk            = "l4_div_ck",
4658         .addr           = omap44xx_dss_hdmi_addrs,
4659         .user           = OCP_USER_MPU,
4660 };
4661
4662 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4663         {
4664                 .pa_start       = 0x58002000,
4665                 .pa_end         = 0x580020ff,
4666                 .flags          = ADDR_TYPE_RT
4667         },
4668         { }
4669 };
4670
4671 /* l3_main_2 -> dss_rfbi */
4672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4673         .master         = &omap44xx_l3_main_2_hwmod,
4674         .slave          = &omap44xx_dss_rfbi_hwmod,
4675         .clk            = "dss_fck",
4676         .addr           = omap44xx_dss_rfbi_dma_addrs,
4677         .user           = OCP_USER_SDMA,
4678 };
4679
4680 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4681         {
4682                 .pa_start       = 0x48042000,
4683                 .pa_end         = 0x480420ff,
4684                 .flags          = ADDR_TYPE_RT
4685         },
4686         { }
4687 };
4688
4689 /* l4_per -> dss_rfbi */
4690 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4691         .master         = &omap44xx_l4_per_hwmod,
4692         .slave          = &omap44xx_dss_rfbi_hwmod,
4693         .clk            = "l4_div_ck",
4694         .addr           = omap44xx_dss_rfbi_addrs,
4695         .user           = OCP_USER_MPU,
4696 };
4697
4698 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4699         {
4700                 .pa_start       = 0x58003000,
4701                 .pa_end         = 0x580030ff,
4702                 .flags          = ADDR_TYPE_RT
4703         },
4704         { }
4705 };
4706
4707 /* l3_main_2 -> dss_venc */
4708 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4709         .master         = &omap44xx_l3_main_2_hwmod,
4710         .slave          = &omap44xx_dss_venc_hwmod,
4711         .clk            = "dss_fck",
4712         .addr           = omap44xx_dss_venc_dma_addrs,
4713         .user           = OCP_USER_SDMA,
4714 };
4715
4716 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4717         {
4718                 .pa_start       = 0x48043000,
4719                 .pa_end         = 0x480430ff,
4720                 .flags          = ADDR_TYPE_RT
4721         },
4722         { }
4723 };
4724
4725 /* l4_per -> dss_venc */
4726 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4727         .master         = &omap44xx_l4_per_hwmod,
4728         .slave          = &omap44xx_dss_venc_hwmod,
4729         .clk            = "l4_div_ck",
4730         .addr           = omap44xx_dss_venc_addrs,
4731         .user           = OCP_USER_MPU,
4732 };
4733
4734 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4735         {
4736                 .pa_start       = 0x48078000,
4737                 .pa_end         = 0x48078fff,
4738                 .flags          = ADDR_TYPE_RT
4739         },
4740         { }
4741 };
4742
4743 /* l4_per -> elm */
4744 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4745         .master         = &omap44xx_l4_per_hwmod,
4746         .slave          = &omap44xx_elm_hwmod,
4747         .clk            = "l4_div_ck",
4748         .addr           = omap44xx_elm_addrs,
4749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4750 };
4751
4752 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4753         {
4754                 .pa_start       = 0x4c000000,
4755                 .pa_end         = 0x4c0000ff,
4756                 .flags          = ADDR_TYPE_RT
4757         },
4758         { }
4759 };
4760
4761 /* emif_fw -> emif1 */
4762 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4763         .master         = &omap44xx_emif_fw_hwmod,
4764         .slave          = &omap44xx_emif1_hwmod,
4765         .clk            = "l3_div_ck",
4766         .addr           = omap44xx_emif1_addrs,
4767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4768 };
4769
4770 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4771         {
4772                 .pa_start       = 0x4d000000,
4773                 .pa_end         = 0x4d0000ff,
4774                 .flags          = ADDR_TYPE_RT
4775         },
4776         { }
4777 };
4778
4779 /* emif_fw -> emif2 */
4780 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4781         .master         = &omap44xx_emif_fw_hwmod,
4782         .slave          = &omap44xx_emif2_hwmod,
4783         .clk            = "l3_div_ck",
4784         .addr           = omap44xx_emif2_addrs,
4785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4786 };
4787
4788 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4789         {
4790                 .pa_start       = 0x4a10a000,
4791                 .pa_end         = 0x4a10a1ff,
4792                 .flags          = ADDR_TYPE_RT
4793         },
4794         { }
4795 };
4796
4797 /* l4_cfg -> fdif */
4798 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4799         .master         = &omap44xx_l4_cfg_hwmod,
4800         .slave          = &omap44xx_fdif_hwmod,
4801         .clk            = "l4_div_ck",
4802         .addr           = omap44xx_fdif_addrs,
4803         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4804 };
4805
4806 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4807         {
4808                 .pa_start       = 0x4a310000,
4809                 .pa_end         = 0x4a3101ff,
4810                 .flags          = ADDR_TYPE_RT
4811         },
4812         { }
4813 };
4814
4815 /* l4_wkup -> gpio1 */
4816 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4817         .master         = &omap44xx_l4_wkup_hwmod,
4818         .slave          = &omap44xx_gpio1_hwmod,
4819         .clk            = "l4_wkup_clk_mux_ck",
4820         .addr           = omap44xx_gpio1_addrs,
4821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4822 };
4823
4824 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4825         {
4826                 .pa_start       = 0x48055000,
4827                 .pa_end         = 0x480551ff,
4828                 .flags          = ADDR_TYPE_RT
4829         },
4830         { }
4831 };
4832
4833 /* l4_per -> gpio2 */
4834 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4835         .master         = &omap44xx_l4_per_hwmod,
4836         .slave          = &omap44xx_gpio2_hwmod,
4837         .clk            = "l4_div_ck",
4838         .addr           = omap44xx_gpio2_addrs,
4839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4840 };
4841
4842 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4843         {
4844                 .pa_start       = 0x48057000,
4845                 .pa_end         = 0x480571ff,
4846                 .flags          = ADDR_TYPE_RT
4847         },
4848         { }
4849 };
4850
4851 /* l4_per -> gpio3 */
4852 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4853         .master         = &omap44xx_l4_per_hwmod,
4854         .slave          = &omap44xx_gpio3_hwmod,
4855         .clk            = "l4_div_ck",
4856         .addr           = omap44xx_gpio3_addrs,
4857         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4858 };
4859
4860 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4861         {
4862                 .pa_start       = 0x48059000,
4863                 .pa_end         = 0x480591ff,
4864                 .flags          = ADDR_TYPE_RT
4865         },
4866         { }
4867 };
4868
4869 /* l4_per -> gpio4 */
4870 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4871         .master         = &omap44xx_l4_per_hwmod,
4872         .slave          = &omap44xx_gpio4_hwmod,
4873         .clk            = "l4_div_ck",
4874         .addr           = omap44xx_gpio4_addrs,
4875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4876 };
4877
4878 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4879         {
4880                 .pa_start       = 0x4805b000,
4881                 .pa_end         = 0x4805b1ff,
4882                 .flags          = ADDR_TYPE_RT
4883         },
4884         { }
4885 };
4886
4887 /* l4_per -> gpio5 */
4888 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4889         .master         = &omap44xx_l4_per_hwmod,
4890         .slave          = &omap44xx_gpio5_hwmod,
4891         .clk            = "l4_div_ck",
4892         .addr           = omap44xx_gpio5_addrs,
4893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4894 };
4895
4896 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4897         {
4898                 .pa_start       = 0x4805d000,
4899                 .pa_end         = 0x4805d1ff,
4900                 .flags          = ADDR_TYPE_RT
4901         },
4902         { }
4903 };
4904
4905 /* l4_per -> gpio6 */
4906 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4907         .master         = &omap44xx_l4_per_hwmod,
4908         .slave          = &omap44xx_gpio6_hwmod,
4909         .clk            = "l4_div_ck",
4910         .addr           = omap44xx_gpio6_addrs,
4911         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4912 };
4913
4914 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4915         {
4916                 .pa_start       = 0x50000000,
4917                 .pa_end         = 0x500003ff,
4918                 .flags          = ADDR_TYPE_RT
4919         },
4920         { }
4921 };
4922
4923 /* l3_main_2 -> gpmc */
4924 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4925         .master         = &omap44xx_l3_main_2_hwmod,
4926         .slave          = &omap44xx_gpmc_hwmod,
4927         .clk            = "l3_div_ck",
4928         .addr           = omap44xx_gpmc_addrs,
4929         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4930 };
4931
4932 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4933         {
4934                 .pa_start       = 0x56000000,
4935                 .pa_end         = 0x5600ffff,
4936                 .flags          = ADDR_TYPE_RT
4937         },
4938         { }
4939 };
4940
4941 /* l3_main_2 -> gpu */
4942 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4943         .master         = &omap44xx_l3_main_2_hwmod,
4944         .slave          = &omap44xx_gpu_hwmod,
4945         .clk            = "l3_div_ck",
4946         .addr           = omap44xx_gpu_addrs,
4947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4948 };
4949
4950 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4951         {
4952                 .pa_start       = 0x480b2000,
4953                 .pa_end         = 0x480b201f,
4954                 .flags          = ADDR_TYPE_RT
4955         },
4956         { }
4957 };
4958
4959 /* l4_per -> hdq1w */
4960 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4961         .master         = &omap44xx_l4_per_hwmod,
4962         .slave          = &omap44xx_hdq1w_hwmod,
4963         .clk            = "l4_div_ck",
4964         .addr           = omap44xx_hdq1w_addrs,
4965         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4966 };
4967
4968 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4969         {
4970                 .pa_start       = 0x4a058000,
4971                 .pa_end         = 0x4a05bfff,
4972                 .flags          = ADDR_TYPE_RT
4973         },
4974         { }
4975 };
4976
4977 /* l4_cfg -> hsi */
4978 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4979         .master         = &omap44xx_l4_cfg_hwmod,
4980         .slave          = &omap44xx_hsi_hwmod,
4981         .clk            = "l4_div_ck",
4982         .addr           = omap44xx_hsi_addrs,
4983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4984 };
4985
4986 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4987         {
4988                 .pa_start       = 0x48070000,
4989                 .pa_end         = 0x480700ff,
4990                 .flags          = ADDR_TYPE_RT
4991         },
4992         { }
4993 };
4994
4995 /* l4_per -> i2c1 */
4996 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4997         .master         = &omap44xx_l4_per_hwmod,
4998         .slave          = &omap44xx_i2c1_hwmod,
4999         .clk            = "l4_div_ck",
5000         .addr           = omap44xx_i2c1_addrs,
5001         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5002 };
5003
5004 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
5005         {
5006                 .pa_start       = 0x48072000,
5007                 .pa_end         = 0x480720ff,
5008                 .flags          = ADDR_TYPE_RT
5009         },
5010         { }
5011 };
5012
5013 /* l4_per -> i2c2 */
5014 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5015         .master         = &omap44xx_l4_per_hwmod,
5016         .slave          = &omap44xx_i2c2_hwmod,
5017         .clk            = "l4_div_ck",
5018         .addr           = omap44xx_i2c2_addrs,
5019         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5020 };
5021
5022 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5023         {
5024                 .pa_start       = 0x48060000,
5025                 .pa_end         = 0x480600ff,
5026                 .flags          = ADDR_TYPE_RT
5027         },
5028         { }
5029 };
5030
5031 /* l4_per -> i2c3 */
5032 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5033         .master         = &omap44xx_l4_per_hwmod,
5034         .slave          = &omap44xx_i2c3_hwmod,
5035         .clk            = "l4_div_ck",
5036         .addr           = omap44xx_i2c3_addrs,
5037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5038 };
5039
5040 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5041         {
5042                 .pa_start       = 0x48350000,
5043                 .pa_end         = 0x483500ff,
5044                 .flags          = ADDR_TYPE_RT
5045         },
5046         { }
5047 };
5048
5049 /* l4_per -> i2c4 */
5050 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5051         .master         = &omap44xx_l4_per_hwmod,
5052         .slave          = &omap44xx_i2c4_hwmod,
5053         .clk            = "l4_div_ck",
5054         .addr           = omap44xx_i2c4_addrs,
5055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5056 };
5057
5058 /* l3_main_2 -> ipu */
5059 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5060         .master         = &omap44xx_l3_main_2_hwmod,
5061         .slave          = &omap44xx_ipu_hwmod,
5062         .clk            = "l3_div_ck",
5063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5064 };
5065
5066 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5067         {
5068                 .pa_start       = 0x52000000,
5069                 .pa_end         = 0x520000ff,
5070                 .flags          = ADDR_TYPE_RT
5071         },
5072         { }
5073 };
5074
5075 /* l3_main_2 -> iss */
5076 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5077         .master         = &omap44xx_l3_main_2_hwmod,
5078         .slave          = &omap44xx_iss_hwmod,
5079         .clk            = "l3_div_ck",
5080         .addr           = omap44xx_iss_addrs,
5081         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5082 };
5083
5084 /* iva -> sl2if */
5085 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5086         .master         = &omap44xx_iva_hwmod,
5087         .slave          = &omap44xx_sl2if_hwmod,
5088         .clk            = "dpll_iva_m5x2_ck",
5089         .user           = OCP_USER_IVA,
5090 };
5091
5092 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5093         {
5094                 .pa_start       = 0x5a000000,
5095                 .pa_end         = 0x5a07ffff,
5096                 .flags          = ADDR_TYPE_RT
5097         },
5098         { }
5099 };
5100
5101 /* l3_main_2 -> iva */
5102 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5103         .master         = &omap44xx_l3_main_2_hwmod,
5104         .slave          = &omap44xx_iva_hwmod,
5105         .clk            = "l3_div_ck",
5106         .addr           = omap44xx_iva_addrs,
5107         .user           = OCP_USER_MPU,
5108 };
5109
5110 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5111         {
5112                 .pa_start       = 0x4a31c000,
5113                 .pa_end         = 0x4a31c07f,
5114                 .flags          = ADDR_TYPE_RT
5115         },
5116         { }
5117 };
5118
5119 /* l4_wkup -> kbd */
5120 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5121         .master         = &omap44xx_l4_wkup_hwmod,
5122         .slave          = &omap44xx_kbd_hwmod,
5123         .clk            = "l4_wkup_clk_mux_ck",
5124         .addr           = omap44xx_kbd_addrs,
5125         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5126 };
5127
5128 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5129         {
5130                 .pa_start       = 0x4a0f4000,
5131                 .pa_end         = 0x4a0f41ff,
5132                 .flags          = ADDR_TYPE_RT
5133         },
5134         { }
5135 };
5136
5137 /* l4_cfg -> mailbox */
5138 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5139         .master         = &omap44xx_l4_cfg_hwmod,
5140         .slave          = &omap44xx_mailbox_hwmod,
5141         .clk            = "l4_div_ck",
5142         .addr           = omap44xx_mailbox_addrs,
5143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5144 };
5145
5146 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5147         {
5148                 .pa_start       = 0x40128000,
5149                 .pa_end         = 0x401283ff,
5150                 .flags          = ADDR_TYPE_RT
5151         },
5152         { }
5153 };
5154
5155 /* l4_abe -> mcasp */
5156 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5157         .master         = &omap44xx_l4_abe_hwmod,
5158         .slave          = &omap44xx_mcasp_hwmod,
5159         .clk            = "ocp_abe_iclk",
5160         .addr           = omap44xx_mcasp_addrs,
5161         .user           = OCP_USER_MPU,
5162 };
5163
5164 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5165         {
5166                 .pa_start       = 0x49028000,
5167                 .pa_end         = 0x490283ff,
5168                 .flags          = ADDR_TYPE_RT
5169         },
5170         { }
5171 };
5172
5173 /* l4_abe -> mcasp (dma) */
5174 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5175         .master         = &omap44xx_l4_abe_hwmod,
5176         .slave          = &omap44xx_mcasp_hwmod,
5177         .clk            = "ocp_abe_iclk",
5178         .addr           = omap44xx_mcasp_dma_addrs,
5179         .user           = OCP_USER_SDMA,
5180 };
5181
5182 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5183         {
5184                 .name           = "mpu",
5185                 .pa_start       = 0x40122000,
5186                 .pa_end         = 0x401220ff,
5187                 .flags          = ADDR_TYPE_RT
5188         },
5189         { }
5190 };
5191
5192 /* l4_abe -> mcbsp1 */
5193 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5194         .master         = &omap44xx_l4_abe_hwmod,
5195         .slave          = &omap44xx_mcbsp1_hwmod,
5196         .clk            = "ocp_abe_iclk",
5197         .addr           = omap44xx_mcbsp1_addrs,
5198         .user           = OCP_USER_MPU,
5199 };
5200
5201 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5202         {
5203                 .name           = "dma",
5204                 .pa_start       = 0x49022000,
5205                 .pa_end         = 0x490220ff,
5206                 .flags          = ADDR_TYPE_RT
5207         },
5208         { }
5209 };
5210
5211 /* l4_abe -> mcbsp1 (dma) */
5212 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5213         .master         = &omap44xx_l4_abe_hwmod,
5214         .slave          = &omap44xx_mcbsp1_hwmod,
5215         .clk            = "ocp_abe_iclk",
5216         .addr           = omap44xx_mcbsp1_dma_addrs,
5217         .user           = OCP_USER_SDMA,
5218 };
5219
5220 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5221         {
5222                 .name           = "mpu",
5223                 .pa_start       = 0x40124000,
5224                 .pa_end         = 0x401240ff,
5225                 .flags          = ADDR_TYPE_RT
5226         },
5227         { }
5228 };
5229
5230 /* l4_abe -> mcbsp2 */
5231 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5232         .master         = &omap44xx_l4_abe_hwmod,
5233         .slave          = &omap44xx_mcbsp2_hwmod,
5234         .clk            = "ocp_abe_iclk",
5235         .addr           = omap44xx_mcbsp2_addrs,
5236         .user           = OCP_USER_MPU,
5237 };
5238
5239 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5240         {
5241                 .name           = "dma",
5242                 .pa_start       = 0x49024000,
5243                 .pa_end         = 0x490240ff,
5244                 .flags          = ADDR_TYPE_RT
5245         },
5246         { }
5247 };
5248
5249 /* l4_abe -> mcbsp2 (dma) */
5250 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5251         .master         = &omap44xx_l4_abe_hwmod,
5252         .slave          = &omap44xx_mcbsp2_hwmod,
5253         .clk            = "ocp_abe_iclk",
5254         .addr           = omap44xx_mcbsp2_dma_addrs,
5255         .user           = OCP_USER_SDMA,
5256 };
5257
5258 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5259         {
5260                 .name           = "mpu",
5261                 .pa_start       = 0x40126000,
5262                 .pa_end         = 0x401260ff,
5263                 .flags          = ADDR_TYPE_RT
5264         },
5265         { }
5266 };
5267
5268 /* l4_abe -> mcbsp3 */
5269 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5270         .master         = &omap44xx_l4_abe_hwmod,
5271         .slave          = &omap44xx_mcbsp3_hwmod,
5272         .clk            = "ocp_abe_iclk",
5273         .addr           = omap44xx_mcbsp3_addrs,
5274         .user           = OCP_USER_MPU,
5275 };
5276
5277 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5278         {
5279                 .name           = "dma",
5280                 .pa_start       = 0x49026000,
5281                 .pa_end         = 0x490260ff,
5282                 .flags          = ADDR_TYPE_RT
5283         },
5284         { }
5285 };
5286
5287 /* l4_abe -> mcbsp3 (dma) */
5288 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5289         .master         = &omap44xx_l4_abe_hwmod,
5290         .slave          = &omap44xx_mcbsp3_hwmod,
5291         .clk            = "ocp_abe_iclk",
5292         .addr           = omap44xx_mcbsp3_dma_addrs,
5293         .user           = OCP_USER_SDMA,
5294 };
5295
5296 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5297         {
5298                 .pa_start       = 0x48096000,
5299                 .pa_end         = 0x480960ff,
5300                 .flags          = ADDR_TYPE_RT
5301         },
5302         { }
5303 };
5304
5305 /* l4_per -> mcbsp4 */
5306 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5307         .master         = &omap44xx_l4_per_hwmod,
5308         .slave          = &omap44xx_mcbsp4_hwmod,
5309         .clk            = "l4_div_ck",
5310         .addr           = omap44xx_mcbsp4_addrs,
5311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5312 };
5313
5314 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5315         {
5316                 .name           = "mpu",
5317                 .pa_start       = 0x40132000,
5318                 .pa_end         = 0x4013207f,
5319                 .flags          = ADDR_TYPE_RT
5320         },
5321         { }
5322 };
5323
5324 /* l4_abe -> mcpdm */
5325 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5326         .master         = &omap44xx_l4_abe_hwmod,
5327         .slave          = &omap44xx_mcpdm_hwmod,
5328         .clk            = "ocp_abe_iclk",
5329         .addr           = omap44xx_mcpdm_addrs,
5330         .user           = OCP_USER_MPU,
5331 };
5332
5333 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5334         {
5335                 .name           = "dma",
5336                 .pa_start       = 0x49032000,
5337                 .pa_end         = 0x4903207f,
5338                 .flags          = ADDR_TYPE_RT
5339         },
5340         { }
5341 };
5342
5343 /* l4_abe -> mcpdm (dma) */
5344 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5345         .master         = &omap44xx_l4_abe_hwmod,
5346         .slave          = &omap44xx_mcpdm_hwmod,
5347         .clk            = "ocp_abe_iclk",
5348         .addr           = omap44xx_mcpdm_dma_addrs,
5349         .user           = OCP_USER_SDMA,
5350 };
5351
5352 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5353         {
5354                 .pa_start       = 0x48098000,
5355                 .pa_end         = 0x480981ff,
5356                 .flags          = ADDR_TYPE_RT
5357         },
5358         { }
5359 };
5360
5361 /* l4_per -> mcspi1 */
5362 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5363         .master         = &omap44xx_l4_per_hwmod,
5364         .slave          = &omap44xx_mcspi1_hwmod,
5365         .clk            = "l4_div_ck",
5366         .addr           = omap44xx_mcspi1_addrs,
5367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5368 };
5369
5370 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5371         {
5372                 .pa_start       = 0x4809a000,
5373                 .pa_end         = 0x4809a1ff,
5374                 .flags          = ADDR_TYPE_RT
5375         },
5376         { }
5377 };
5378
5379 /* l4_per -> mcspi2 */
5380 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5381         .master         = &omap44xx_l4_per_hwmod,
5382         .slave          = &omap44xx_mcspi2_hwmod,
5383         .clk            = "l4_div_ck",
5384         .addr           = omap44xx_mcspi2_addrs,
5385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5386 };
5387
5388 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5389         {
5390                 .pa_start       = 0x480b8000,
5391                 .pa_end         = 0x480b81ff,
5392                 .flags          = ADDR_TYPE_RT
5393         },
5394         { }
5395 };
5396
5397 /* l4_per -> mcspi3 */
5398 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5399         .master         = &omap44xx_l4_per_hwmod,
5400         .slave          = &omap44xx_mcspi3_hwmod,
5401         .clk            = "l4_div_ck",
5402         .addr           = omap44xx_mcspi3_addrs,
5403         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5404 };
5405
5406 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5407         {
5408                 .pa_start       = 0x480ba000,
5409                 .pa_end         = 0x480ba1ff,
5410                 .flags          = ADDR_TYPE_RT
5411         },
5412         { }
5413 };
5414
5415 /* l4_per -> mcspi4 */
5416 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5417         .master         = &omap44xx_l4_per_hwmod,
5418         .slave          = &omap44xx_mcspi4_hwmod,
5419         .clk            = "l4_div_ck",
5420         .addr           = omap44xx_mcspi4_addrs,
5421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5422 };
5423
5424 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5425         {
5426                 .pa_start       = 0x4809c000,
5427                 .pa_end         = 0x4809c3ff,
5428                 .flags          = ADDR_TYPE_RT
5429         },
5430         { }
5431 };
5432
5433 /* l4_per -> mmc1 */
5434 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5435         .master         = &omap44xx_l4_per_hwmod,
5436         .slave          = &omap44xx_mmc1_hwmod,
5437         .clk            = "l4_div_ck",
5438         .addr           = omap44xx_mmc1_addrs,
5439         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5440 };
5441
5442 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5443         {
5444                 .pa_start       = 0x480b4000,
5445                 .pa_end         = 0x480b43ff,
5446                 .flags          = ADDR_TYPE_RT
5447         },
5448         { }
5449 };
5450
5451 /* l4_per -> mmc2 */
5452 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5453         .master         = &omap44xx_l4_per_hwmod,
5454         .slave          = &omap44xx_mmc2_hwmod,
5455         .clk            = "l4_div_ck",
5456         .addr           = omap44xx_mmc2_addrs,
5457         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5458 };
5459
5460 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5461         {
5462                 .pa_start       = 0x480ad000,
5463                 .pa_end         = 0x480ad3ff,
5464                 .flags          = ADDR_TYPE_RT
5465         },
5466         { }
5467 };
5468
5469 /* l4_per -> mmc3 */
5470 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5471         .master         = &omap44xx_l4_per_hwmod,
5472         .slave          = &omap44xx_mmc3_hwmod,
5473         .clk            = "l4_div_ck",
5474         .addr           = omap44xx_mmc3_addrs,
5475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5476 };
5477
5478 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5479         {
5480                 .pa_start       = 0x480d1000,
5481                 .pa_end         = 0x480d13ff,
5482                 .flags          = ADDR_TYPE_RT
5483         },
5484         { }
5485 };
5486
5487 /* l4_per -> mmc4 */
5488 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5489         .master         = &omap44xx_l4_per_hwmod,
5490         .slave          = &omap44xx_mmc4_hwmod,
5491         .clk            = "l4_div_ck",
5492         .addr           = omap44xx_mmc4_addrs,
5493         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5494 };
5495
5496 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5497         {
5498                 .pa_start       = 0x480d5000,
5499                 .pa_end         = 0x480d53ff,
5500                 .flags          = ADDR_TYPE_RT
5501         },
5502         { }
5503 };
5504
5505 /* l4_per -> mmc5 */
5506 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5507         .master         = &omap44xx_l4_per_hwmod,
5508         .slave          = &omap44xx_mmc5_hwmod,
5509         .clk            = "l4_div_ck",
5510         .addr           = omap44xx_mmc5_addrs,
5511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5512 };
5513
5514 /* l3_main_2 -> ocmc_ram */
5515 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5516         .master         = &omap44xx_l3_main_2_hwmod,
5517         .slave          = &omap44xx_ocmc_ram_hwmod,
5518         .clk            = "l3_div_ck",
5519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5520 };
5521
5522 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5523         {
5524                 .pa_start       = 0x4a0ad000,
5525                 .pa_end         = 0x4a0ad01f,
5526                 .flags          = ADDR_TYPE_RT
5527         },
5528         { }
5529 };
5530
5531 /* l4_cfg -> ocp2scp_usb_phy */
5532 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5533         .master         = &omap44xx_l4_cfg_hwmod,
5534         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5535         .clk            = "l4_div_ck",
5536         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5538 };
5539
5540 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5541         {
5542                 .pa_start       = 0x48243000,
5543                 .pa_end         = 0x48243fff,
5544                 .flags          = ADDR_TYPE_RT
5545         },
5546         { }
5547 };
5548
5549 /* mpu_private -> prcm_mpu */
5550 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5551         .master         = &omap44xx_mpu_private_hwmod,
5552         .slave          = &omap44xx_prcm_mpu_hwmod,
5553         .clk            = "l3_div_ck",
5554         .addr           = omap44xx_prcm_mpu_addrs,
5555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5556 };
5557
5558 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5559         {
5560                 .pa_start       = 0x4a004000,
5561                 .pa_end         = 0x4a004fff,
5562                 .flags          = ADDR_TYPE_RT
5563         },
5564         { }
5565 };
5566
5567 /* l4_wkup -> cm_core_aon */
5568 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5569         .master         = &omap44xx_l4_wkup_hwmod,
5570         .slave          = &omap44xx_cm_core_aon_hwmod,
5571         .clk            = "l4_wkup_clk_mux_ck",
5572         .addr           = omap44xx_cm_core_aon_addrs,
5573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5574 };
5575
5576 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5577         {
5578                 .pa_start       = 0x4a008000,
5579                 .pa_end         = 0x4a009fff,
5580                 .flags          = ADDR_TYPE_RT
5581         },
5582         { }
5583 };
5584
5585 /* l4_cfg -> cm_core */
5586 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5587         .master         = &omap44xx_l4_cfg_hwmod,
5588         .slave          = &omap44xx_cm_core_hwmod,
5589         .clk            = "l4_div_ck",
5590         .addr           = omap44xx_cm_core_addrs,
5591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5592 };
5593
5594 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5595         {
5596                 .pa_start       = 0x4a306000,
5597                 .pa_end         = 0x4a307fff,
5598                 .flags          = ADDR_TYPE_RT
5599         },
5600         { }
5601 };
5602
5603 /* l4_wkup -> prm */
5604 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5605         .master         = &omap44xx_l4_wkup_hwmod,
5606         .slave          = &omap44xx_prm_hwmod,
5607         .clk            = "l4_wkup_clk_mux_ck",
5608         .addr           = omap44xx_prm_addrs,
5609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5610 };
5611
5612 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5613         {
5614                 .pa_start       = 0x4a30a000,
5615                 .pa_end         = 0x4a30a7ff,
5616                 .flags          = ADDR_TYPE_RT
5617         },
5618         { }
5619 };
5620
5621 /* l4_wkup -> scrm */
5622 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5623         .master         = &omap44xx_l4_wkup_hwmod,
5624         .slave          = &omap44xx_scrm_hwmod,
5625         .clk            = "l4_wkup_clk_mux_ck",
5626         .addr           = omap44xx_scrm_addrs,
5627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5628 };
5629
5630 /* l3_main_2 -> sl2if */
5631 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5632         .master         = &omap44xx_l3_main_2_hwmod,
5633         .slave          = &omap44xx_sl2if_hwmod,
5634         .clk            = "l3_div_ck",
5635         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5636 };
5637
5638 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5639         {
5640                 .pa_start       = 0x4012c000,
5641                 .pa_end         = 0x4012c3ff,
5642                 .flags          = ADDR_TYPE_RT
5643         },
5644         { }
5645 };
5646
5647 /* l4_abe -> slimbus1 */
5648 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5649         .master         = &omap44xx_l4_abe_hwmod,
5650         .slave          = &omap44xx_slimbus1_hwmod,
5651         .clk            = "ocp_abe_iclk",
5652         .addr           = omap44xx_slimbus1_addrs,
5653         .user           = OCP_USER_MPU,
5654 };
5655
5656 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5657         {
5658                 .pa_start       = 0x4902c000,
5659                 .pa_end         = 0x4902c3ff,
5660                 .flags          = ADDR_TYPE_RT
5661         },
5662         { }
5663 };
5664
5665 /* l4_abe -> slimbus1 (dma) */
5666 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5667         .master         = &omap44xx_l4_abe_hwmod,
5668         .slave          = &omap44xx_slimbus1_hwmod,
5669         .clk            = "ocp_abe_iclk",
5670         .addr           = omap44xx_slimbus1_dma_addrs,
5671         .user           = OCP_USER_SDMA,
5672 };
5673
5674 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5675         {
5676                 .pa_start       = 0x48076000,
5677                 .pa_end         = 0x480763ff,
5678                 .flags          = ADDR_TYPE_RT
5679         },
5680         { }
5681 };
5682
5683 /* l4_per -> slimbus2 */
5684 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5685         .master         = &omap44xx_l4_per_hwmod,
5686         .slave          = &omap44xx_slimbus2_hwmod,
5687         .clk            = "l4_div_ck",
5688         .addr           = omap44xx_slimbus2_addrs,
5689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5690 };
5691
5692 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5693         {
5694                 .pa_start       = 0x4a0dd000,
5695                 .pa_end         = 0x4a0dd03f,
5696                 .flags          = ADDR_TYPE_RT
5697         },
5698         { }
5699 };
5700
5701 /* l4_cfg -> smartreflex_core */
5702 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5703         .master         = &omap44xx_l4_cfg_hwmod,
5704         .slave          = &omap44xx_smartreflex_core_hwmod,
5705         .clk            = "l4_div_ck",
5706         .addr           = omap44xx_smartreflex_core_addrs,
5707         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5708 };
5709
5710 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5711         {
5712                 .pa_start       = 0x4a0db000,
5713                 .pa_end         = 0x4a0db03f,
5714                 .flags          = ADDR_TYPE_RT
5715         },
5716         { }
5717 };
5718
5719 /* l4_cfg -> smartreflex_iva */
5720 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5721         .master         = &omap44xx_l4_cfg_hwmod,
5722         .slave          = &omap44xx_smartreflex_iva_hwmod,
5723         .clk            = "l4_div_ck",
5724         .addr           = omap44xx_smartreflex_iva_addrs,
5725         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5726 };
5727
5728 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5729         {
5730                 .pa_start       = 0x4a0d9000,
5731                 .pa_end         = 0x4a0d903f,
5732                 .flags          = ADDR_TYPE_RT
5733         },
5734         { }
5735 };
5736
5737 /* l4_cfg -> smartreflex_mpu */
5738 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5739         .master         = &omap44xx_l4_cfg_hwmod,
5740         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5741         .clk            = "l4_div_ck",
5742         .addr           = omap44xx_smartreflex_mpu_addrs,
5743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5744 };
5745
5746 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5747         {
5748                 .pa_start       = 0x4a0f6000,
5749                 .pa_end         = 0x4a0f6fff,
5750                 .flags          = ADDR_TYPE_RT
5751         },
5752         { }
5753 };
5754
5755 /* l4_cfg -> spinlock */
5756 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5757         .master         = &omap44xx_l4_cfg_hwmod,
5758         .slave          = &omap44xx_spinlock_hwmod,
5759         .clk            = "l4_div_ck",
5760         .addr           = omap44xx_spinlock_addrs,
5761         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5762 };
5763
5764 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5765         {
5766                 .pa_start       = 0x4a318000,
5767                 .pa_end         = 0x4a31807f,
5768                 .flags          = ADDR_TYPE_RT
5769         },
5770         { }
5771 };
5772
5773 /* l4_wkup -> timer1 */
5774 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5775         .master         = &omap44xx_l4_wkup_hwmod,
5776         .slave          = &omap44xx_timer1_hwmod,
5777         .clk            = "l4_wkup_clk_mux_ck",
5778         .addr           = omap44xx_timer1_addrs,
5779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5780 };
5781
5782 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5783         {
5784                 .pa_start       = 0x48032000,
5785                 .pa_end         = 0x4803207f,
5786                 .flags          = ADDR_TYPE_RT
5787         },
5788         { }
5789 };
5790
5791 /* l4_per -> timer2 */
5792 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5793         .master         = &omap44xx_l4_per_hwmod,
5794         .slave          = &omap44xx_timer2_hwmod,
5795         .clk            = "l4_div_ck",
5796         .addr           = omap44xx_timer2_addrs,
5797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5798 };
5799
5800 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5801         {
5802                 .pa_start       = 0x48034000,
5803                 .pa_end         = 0x4803407f,
5804                 .flags          = ADDR_TYPE_RT
5805         },
5806         { }
5807 };
5808
5809 /* l4_per -> timer3 */
5810 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5811         .master         = &omap44xx_l4_per_hwmod,
5812         .slave          = &omap44xx_timer3_hwmod,
5813         .clk            = "l4_div_ck",
5814         .addr           = omap44xx_timer3_addrs,
5815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5816 };
5817
5818 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5819         {
5820                 .pa_start       = 0x48036000,
5821                 .pa_end         = 0x4803607f,
5822                 .flags          = ADDR_TYPE_RT
5823         },
5824         { }
5825 };
5826
5827 /* l4_per -> timer4 */
5828 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5829         .master         = &omap44xx_l4_per_hwmod,
5830         .slave          = &omap44xx_timer4_hwmod,
5831         .clk            = "l4_div_ck",
5832         .addr           = omap44xx_timer4_addrs,
5833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5834 };
5835
5836 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5837         {
5838                 .pa_start       = 0x40138000,
5839                 .pa_end         = 0x4013807f,
5840                 .flags          = ADDR_TYPE_RT
5841         },
5842         { }
5843 };
5844
5845 /* l4_abe -> timer5 */
5846 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5847         .master         = &omap44xx_l4_abe_hwmod,
5848         .slave          = &omap44xx_timer5_hwmod,
5849         .clk            = "ocp_abe_iclk",
5850         .addr           = omap44xx_timer5_addrs,
5851         .user           = OCP_USER_MPU,
5852 };
5853
5854 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5855         {
5856                 .pa_start       = 0x49038000,
5857                 .pa_end         = 0x4903807f,
5858                 .flags          = ADDR_TYPE_RT
5859         },
5860         { }
5861 };
5862
5863 /* l4_abe -> timer5 (dma) */
5864 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5865         .master         = &omap44xx_l4_abe_hwmod,
5866         .slave          = &omap44xx_timer5_hwmod,
5867         .clk            = "ocp_abe_iclk",
5868         .addr           = omap44xx_timer5_dma_addrs,
5869         .user           = OCP_USER_SDMA,
5870 };
5871
5872 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5873         {
5874                 .pa_start       = 0x4013a000,
5875                 .pa_end         = 0x4013a07f,
5876                 .flags          = ADDR_TYPE_RT
5877         },
5878         { }
5879 };
5880
5881 /* l4_abe -> timer6 */
5882 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5883         .master         = &omap44xx_l4_abe_hwmod,
5884         .slave          = &omap44xx_timer6_hwmod,
5885         .clk            = "ocp_abe_iclk",
5886         .addr           = omap44xx_timer6_addrs,
5887         .user           = OCP_USER_MPU,
5888 };
5889
5890 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5891         {
5892                 .pa_start       = 0x4903a000,
5893                 .pa_end         = 0x4903a07f,
5894                 .flags          = ADDR_TYPE_RT
5895         },
5896         { }
5897 };
5898
5899 /* l4_abe -> timer6 (dma) */
5900 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5901         .master         = &omap44xx_l4_abe_hwmod,
5902         .slave          = &omap44xx_timer6_hwmod,
5903         .clk            = "ocp_abe_iclk",
5904         .addr           = omap44xx_timer6_dma_addrs,
5905         .user           = OCP_USER_SDMA,
5906 };
5907
5908 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5909         {
5910                 .pa_start       = 0x4013c000,
5911                 .pa_end         = 0x4013c07f,
5912                 .flags          = ADDR_TYPE_RT
5913         },
5914         { }
5915 };
5916
5917 /* l4_abe -> timer7 */
5918 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5919         .master         = &omap44xx_l4_abe_hwmod,
5920         .slave          = &omap44xx_timer7_hwmod,
5921         .clk            = "ocp_abe_iclk",
5922         .addr           = omap44xx_timer7_addrs,
5923         .user           = OCP_USER_MPU,
5924 };
5925
5926 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5927         {
5928                 .pa_start       = 0x4903c000,
5929                 .pa_end         = 0x4903c07f,
5930                 .flags          = ADDR_TYPE_RT
5931         },
5932         { }
5933 };
5934
5935 /* l4_abe -> timer7 (dma) */
5936 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5937         .master         = &omap44xx_l4_abe_hwmod,
5938         .slave          = &omap44xx_timer7_hwmod,
5939         .clk            = "ocp_abe_iclk",
5940         .addr           = omap44xx_timer7_dma_addrs,
5941         .user           = OCP_USER_SDMA,
5942 };
5943
5944 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5945         {
5946                 .pa_start       = 0x4013e000,
5947                 .pa_end         = 0x4013e07f,
5948                 .flags          = ADDR_TYPE_RT
5949         },
5950         { }
5951 };
5952
5953 /* l4_abe -> timer8 */
5954 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5955         .master         = &omap44xx_l4_abe_hwmod,
5956         .slave          = &omap44xx_timer8_hwmod,
5957         .clk            = "ocp_abe_iclk",
5958         .addr           = omap44xx_timer8_addrs,
5959         .user           = OCP_USER_MPU,
5960 };
5961
5962 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5963         {
5964                 .pa_start       = 0x4903e000,
5965                 .pa_end         = 0x4903e07f,
5966                 .flags          = ADDR_TYPE_RT
5967         },
5968         { }
5969 };
5970
5971 /* l4_abe -> timer8 (dma) */
5972 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5973         .master         = &omap44xx_l4_abe_hwmod,
5974         .slave          = &omap44xx_timer8_hwmod,
5975         .clk            = "ocp_abe_iclk",
5976         .addr           = omap44xx_timer8_dma_addrs,
5977         .user           = OCP_USER_SDMA,
5978 };
5979
5980 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5981         {
5982                 .pa_start       = 0x4803e000,
5983                 .pa_end         = 0x4803e07f,
5984                 .flags          = ADDR_TYPE_RT
5985         },
5986         { }
5987 };
5988
5989 /* l4_per -> timer9 */
5990 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5991         .master         = &omap44xx_l4_per_hwmod,
5992         .slave          = &omap44xx_timer9_hwmod,
5993         .clk            = "l4_div_ck",
5994         .addr           = omap44xx_timer9_addrs,
5995         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5996 };
5997
5998 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5999         {
6000                 .pa_start       = 0x48086000,
6001                 .pa_end         = 0x4808607f,
6002                 .flags          = ADDR_TYPE_RT
6003         },
6004         { }
6005 };
6006
6007 /* l4_per -> timer10 */
6008 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6009         .master         = &omap44xx_l4_per_hwmod,
6010         .slave          = &omap44xx_timer10_hwmod,
6011         .clk            = "l4_div_ck",
6012         .addr           = omap44xx_timer10_addrs,
6013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6014 };
6015
6016 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6017         {
6018                 .pa_start       = 0x48088000,
6019                 .pa_end         = 0x4808807f,
6020                 .flags          = ADDR_TYPE_RT
6021         },
6022         { }
6023 };
6024
6025 /* l4_per -> timer11 */
6026 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6027         .master         = &omap44xx_l4_per_hwmod,
6028         .slave          = &omap44xx_timer11_hwmod,
6029         .clk            = "l4_div_ck",
6030         .addr           = omap44xx_timer11_addrs,
6031         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6032 };
6033
6034 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6035         {
6036                 .pa_start       = 0x4806a000,
6037                 .pa_end         = 0x4806a0ff,
6038                 .flags          = ADDR_TYPE_RT
6039         },
6040         { }
6041 };
6042
6043 /* l4_per -> uart1 */
6044 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6045         .master         = &omap44xx_l4_per_hwmod,
6046         .slave          = &omap44xx_uart1_hwmod,
6047         .clk            = "l4_div_ck",
6048         .addr           = omap44xx_uart1_addrs,
6049         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6050 };
6051
6052 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6053         {
6054                 .pa_start       = 0x4806c000,
6055                 .pa_end         = 0x4806c0ff,
6056                 .flags          = ADDR_TYPE_RT
6057         },
6058         { }
6059 };
6060
6061 /* l4_per -> uart2 */
6062 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6063         .master         = &omap44xx_l4_per_hwmod,
6064         .slave          = &omap44xx_uart2_hwmod,
6065         .clk            = "l4_div_ck",
6066         .addr           = omap44xx_uart2_addrs,
6067         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6068 };
6069
6070 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6071         {
6072                 .pa_start       = 0x48020000,
6073                 .pa_end         = 0x480200ff,
6074                 .flags          = ADDR_TYPE_RT
6075         },
6076         { }
6077 };
6078
6079 /* l4_per -> uart3 */
6080 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6081         .master         = &omap44xx_l4_per_hwmod,
6082         .slave          = &omap44xx_uart3_hwmod,
6083         .clk            = "l4_div_ck",
6084         .addr           = omap44xx_uart3_addrs,
6085         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6086 };
6087
6088 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6089         {
6090                 .pa_start       = 0x4806e000,
6091                 .pa_end         = 0x4806e0ff,
6092                 .flags          = ADDR_TYPE_RT
6093         },
6094         { }
6095 };
6096
6097 /* l4_per -> uart4 */
6098 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6099         .master         = &omap44xx_l4_per_hwmod,
6100         .slave          = &omap44xx_uart4_hwmod,
6101         .clk            = "l4_div_ck",
6102         .addr           = omap44xx_uart4_addrs,
6103         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6104 };
6105
6106 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6107         {
6108                 .pa_start       = 0x4a0a9000,
6109                 .pa_end         = 0x4a0a93ff,
6110                 .flags          = ADDR_TYPE_RT
6111         },
6112         { }
6113 };
6114
6115 /* l4_cfg -> usb_host_fs */
6116 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6117         .master         = &omap44xx_l4_cfg_hwmod,
6118         .slave          = &omap44xx_usb_host_fs_hwmod,
6119         .clk            = "l4_div_ck",
6120         .addr           = omap44xx_usb_host_fs_addrs,
6121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6122 };
6123
6124 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6125         {
6126                 .name           = "uhh",
6127                 .pa_start       = 0x4a064000,
6128                 .pa_end         = 0x4a0647ff,
6129                 .flags          = ADDR_TYPE_RT
6130         },
6131         {
6132                 .name           = "ohci",
6133                 .pa_start       = 0x4a064800,
6134                 .pa_end         = 0x4a064bff,
6135         },
6136         {
6137                 .name           = "ehci",
6138                 .pa_start       = 0x4a064c00,
6139                 .pa_end         = 0x4a064fff,
6140         },
6141         {}
6142 };
6143
6144 /* l4_cfg -> usb_host_hs */
6145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6146         .master         = &omap44xx_l4_cfg_hwmod,
6147         .slave          = &omap44xx_usb_host_hs_hwmod,
6148         .clk            = "l4_div_ck",
6149         .addr           = omap44xx_usb_host_hs_addrs,
6150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6151 };
6152
6153 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6154         {
6155                 .pa_start       = 0x4a0ab000,
6156                 .pa_end         = 0x4a0ab7ff,
6157                 .flags          = ADDR_TYPE_RT
6158         },
6159         {
6160                 /* XXX: Remove this once control module driver is in place */
6161                 .pa_start       = 0x4a00233c,
6162                 .pa_end         = 0x4a00233f,
6163                 .flags          = ADDR_TYPE_RT
6164         },
6165         { }
6166 };
6167
6168 /* l4_cfg -> usb_otg_hs */
6169 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6170         .master         = &omap44xx_l4_cfg_hwmod,
6171         .slave          = &omap44xx_usb_otg_hs_hwmod,
6172         .clk            = "l4_div_ck",
6173         .addr           = omap44xx_usb_otg_hs_addrs,
6174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6175 };
6176
6177 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6178         {
6179                 .name           = "tll",
6180                 .pa_start       = 0x4a062000,
6181                 .pa_end         = 0x4a063fff,
6182                 .flags          = ADDR_TYPE_RT
6183         },
6184         {}
6185 };
6186
6187 /* l4_cfg -> usb_tll_hs */
6188 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6189         .master         = &omap44xx_l4_cfg_hwmod,
6190         .slave          = &omap44xx_usb_tll_hs_hwmod,
6191         .clk            = "l4_div_ck",
6192         .addr           = omap44xx_usb_tll_hs_addrs,
6193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6194 };
6195
6196 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6197         {
6198                 .pa_start       = 0x4a314000,
6199                 .pa_end         = 0x4a31407f,
6200                 .flags          = ADDR_TYPE_RT
6201         },
6202         { }
6203 };
6204
6205 /* l4_wkup -> wd_timer2 */
6206 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6207         .master         = &omap44xx_l4_wkup_hwmod,
6208         .slave          = &omap44xx_wd_timer2_hwmod,
6209         .clk            = "l4_wkup_clk_mux_ck",
6210         .addr           = omap44xx_wd_timer2_addrs,
6211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6212 };
6213
6214 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6215         {
6216                 .pa_start       = 0x40130000,
6217                 .pa_end         = 0x4013007f,
6218                 .flags          = ADDR_TYPE_RT
6219         },
6220         { }
6221 };
6222
6223 /* l4_abe -> wd_timer3 */
6224 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6225         .master         = &omap44xx_l4_abe_hwmod,
6226         .slave          = &omap44xx_wd_timer3_hwmod,
6227         .clk            = "ocp_abe_iclk",
6228         .addr           = omap44xx_wd_timer3_addrs,
6229         .user           = OCP_USER_MPU,
6230 };
6231
6232 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6233         {
6234                 .pa_start       = 0x49030000,
6235                 .pa_end         = 0x4903007f,
6236                 .flags          = ADDR_TYPE_RT
6237         },
6238         { }
6239 };
6240
6241 /* l4_abe -> wd_timer3 (dma) */
6242 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6243         .master         = &omap44xx_l4_abe_hwmod,
6244         .slave          = &omap44xx_wd_timer3_hwmod,
6245         .clk            = "ocp_abe_iclk",
6246         .addr           = omap44xx_wd_timer3_dma_addrs,
6247         .user           = OCP_USER_SDMA,
6248 };
6249
6250 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6251         &omap44xx_c2c__c2c_target_fw,
6252         &omap44xx_l4_cfg__c2c_target_fw,
6253         &omap44xx_l3_main_1__dmm,
6254         &omap44xx_mpu__dmm,
6255         &omap44xx_c2c__emif_fw,
6256         &omap44xx_dmm__emif_fw,
6257         &omap44xx_l4_cfg__emif_fw,
6258         &omap44xx_iva__l3_instr,
6259         &omap44xx_l3_main_3__l3_instr,
6260         &omap44xx_ocp_wp_noc__l3_instr,
6261         &omap44xx_dsp__l3_main_1,
6262         &omap44xx_dss__l3_main_1,
6263         &omap44xx_l3_main_2__l3_main_1,
6264         &omap44xx_l4_cfg__l3_main_1,
6265         &omap44xx_mmc1__l3_main_1,
6266         &omap44xx_mmc2__l3_main_1,
6267         &omap44xx_mpu__l3_main_1,
6268         &omap44xx_c2c_target_fw__l3_main_2,
6269         &omap44xx_debugss__l3_main_2,
6270         &omap44xx_dma_system__l3_main_2,
6271         &omap44xx_fdif__l3_main_2,
6272         &omap44xx_gpu__l3_main_2,
6273         &omap44xx_hsi__l3_main_2,
6274         &omap44xx_ipu__l3_main_2,
6275         &omap44xx_iss__l3_main_2,
6276         &omap44xx_iva__l3_main_2,
6277         &omap44xx_l3_main_1__l3_main_2,
6278         &omap44xx_l4_cfg__l3_main_2,
6279         /* &omap44xx_usb_host_fs__l3_main_2, */
6280         &omap44xx_usb_host_hs__l3_main_2,
6281         &omap44xx_usb_otg_hs__l3_main_2,
6282         &omap44xx_l3_main_1__l3_main_3,
6283         &omap44xx_l3_main_2__l3_main_3,
6284         &omap44xx_l4_cfg__l3_main_3,
6285         /* &omap44xx_aess__l4_abe, */
6286         &omap44xx_dsp__l4_abe,
6287         &omap44xx_l3_main_1__l4_abe,
6288         &omap44xx_mpu__l4_abe,
6289         &omap44xx_l3_main_1__l4_cfg,
6290         &omap44xx_l3_main_2__l4_per,
6291         &omap44xx_l4_cfg__l4_wkup,
6292         &omap44xx_mpu__mpu_private,
6293         &omap44xx_l4_cfg__ocp_wp_noc,
6294         /* &omap44xx_l4_abe__aess, */
6295         /* &omap44xx_l4_abe__aess_dma, */
6296         &omap44xx_l3_main_2__c2c,
6297         &omap44xx_l4_wkup__counter_32k,
6298         &omap44xx_l4_cfg__ctrl_module_core,
6299         &omap44xx_l4_cfg__ctrl_module_pad_core,
6300         &omap44xx_l4_wkup__ctrl_module_wkup,
6301         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6302         &omap44xx_l3_instr__debugss,
6303         &omap44xx_l4_cfg__dma_system,
6304         &omap44xx_l4_abe__dmic,
6305         &omap44xx_l4_abe__dmic_dma,
6306         &omap44xx_dsp__iva,
6307         /* &omap44xx_dsp__sl2if, */
6308         &omap44xx_l4_cfg__dsp,
6309         &omap44xx_l3_main_2__dss,
6310         &omap44xx_l4_per__dss,
6311         &omap44xx_l3_main_2__dss_dispc,
6312         &omap44xx_l4_per__dss_dispc,
6313         &omap44xx_l3_main_2__dss_dsi1,
6314         &omap44xx_l4_per__dss_dsi1,
6315         &omap44xx_l3_main_2__dss_dsi2,
6316         &omap44xx_l4_per__dss_dsi2,
6317         &omap44xx_l3_main_2__dss_hdmi,
6318         &omap44xx_l4_per__dss_hdmi,
6319         &omap44xx_l3_main_2__dss_rfbi,
6320         &omap44xx_l4_per__dss_rfbi,
6321         &omap44xx_l3_main_2__dss_venc,
6322         &omap44xx_l4_per__dss_venc,
6323         &omap44xx_l4_per__elm,
6324         &omap44xx_emif_fw__emif1,
6325         &omap44xx_emif_fw__emif2,
6326         &omap44xx_l4_cfg__fdif,
6327         &omap44xx_l4_wkup__gpio1,
6328         &omap44xx_l4_per__gpio2,
6329         &omap44xx_l4_per__gpio3,
6330         &omap44xx_l4_per__gpio4,
6331         &omap44xx_l4_per__gpio5,
6332         &omap44xx_l4_per__gpio6,
6333         &omap44xx_l3_main_2__gpmc,
6334         &omap44xx_l3_main_2__gpu,
6335         &omap44xx_l4_per__hdq1w,
6336         &omap44xx_l4_cfg__hsi,
6337         &omap44xx_l4_per__i2c1,
6338         &omap44xx_l4_per__i2c2,
6339         &omap44xx_l4_per__i2c3,
6340         &omap44xx_l4_per__i2c4,
6341         &omap44xx_l3_main_2__ipu,
6342         &omap44xx_l3_main_2__iss,
6343         /* &omap44xx_iva__sl2if, */
6344         &omap44xx_l3_main_2__iva,
6345         &omap44xx_l4_wkup__kbd,
6346         &omap44xx_l4_cfg__mailbox,
6347         &omap44xx_l4_abe__mcasp,
6348         &omap44xx_l4_abe__mcasp_dma,
6349         &omap44xx_l4_abe__mcbsp1,
6350         &omap44xx_l4_abe__mcbsp1_dma,
6351         &omap44xx_l4_abe__mcbsp2,
6352         &omap44xx_l4_abe__mcbsp2_dma,
6353         &omap44xx_l4_abe__mcbsp3,
6354         &omap44xx_l4_abe__mcbsp3_dma,
6355         &omap44xx_l4_per__mcbsp4,
6356         &omap44xx_l4_abe__mcpdm,
6357         &omap44xx_l4_abe__mcpdm_dma,
6358         &omap44xx_l4_per__mcspi1,
6359         &omap44xx_l4_per__mcspi2,
6360         &omap44xx_l4_per__mcspi3,
6361         &omap44xx_l4_per__mcspi4,
6362         &omap44xx_l4_per__mmc1,
6363         &omap44xx_l4_per__mmc2,
6364         &omap44xx_l4_per__mmc3,
6365         &omap44xx_l4_per__mmc4,
6366         &omap44xx_l4_per__mmc5,
6367         &omap44xx_l3_main_2__mmu_ipu,
6368         &omap44xx_l4_cfg__mmu_dsp,
6369         &omap44xx_l3_main_2__ocmc_ram,
6370         &omap44xx_l4_cfg__ocp2scp_usb_phy,
6371         &omap44xx_mpu_private__prcm_mpu,
6372         &omap44xx_l4_wkup__cm_core_aon,
6373         &omap44xx_l4_cfg__cm_core,
6374         &omap44xx_l4_wkup__prm,
6375         &omap44xx_l4_wkup__scrm,
6376         /* &omap44xx_l3_main_2__sl2if, */
6377         &omap44xx_l4_abe__slimbus1,
6378         &omap44xx_l4_abe__slimbus1_dma,
6379         &omap44xx_l4_per__slimbus2,
6380         &omap44xx_l4_cfg__smartreflex_core,
6381         &omap44xx_l4_cfg__smartreflex_iva,
6382         &omap44xx_l4_cfg__smartreflex_mpu,
6383         &omap44xx_l4_cfg__spinlock,
6384         &omap44xx_l4_wkup__timer1,
6385         &omap44xx_l4_per__timer2,
6386         &omap44xx_l4_per__timer3,
6387         &omap44xx_l4_per__timer4,
6388         &omap44xx_l4_abe__timer5,
6389         &omap44xx_l4_abe__timer5_dma,
6390         &omap44xx_l4_abe__timer6,
6391         &omap44xx_l4_abe__timer6_dma,
6392         &omap44xx_l4_abe__timer7,
6393         &omap44xx_l4_abe__timer7_dma,
6394         &omap44xx_l4_abe__timer8,
6395         &omap44xx_l4_abe__timer8_dma,
6396         &omap44xx_l4_per__timer9,
6397         &omap44xx_l4_per__timer10,
6398         &omap44xx_l4_per__timer11,
6399         &omap44xx_l4_per__uart1,
6400         &omap44xx_l4_per__uart2,
6401         &omap44xx_l4_per__uart3,
6402         &omap44xx_l4_per__uart4,
6403         /* &omap44xx_l4_cfg__usb_host_fs, */
6404         &omap44xx_l4_cfg__usb_host_hs,
6405         &omap44xx_l4_cfg__usb_otg_hs,
6406         &omap44xx_l4_cfg__usb_tll_hs,
6407         &omap44xx_l4_wkup__wd_timer2,
6408         &omap44xx_l4_abe__wd_timer3,
6409         &omap44xx_l4_abe__wd_timer3_dma,
6410         NULL,
6411 };
6412
6413 int __init omap44xx_hwmod_init(void)
6414 {
6415         omap_hwmod_init();
6416         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
6417 }
6418