arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/mcbsp.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "cm1_44xx.h"
  33 #include "cm2_44xx.h"
  34 #include "prm44xx.h"
  35 #include "prm-regbits-44xx.h"
  36 #include "wd_timer.h"
  37
  38 /* Base offset for all OMAP4 interrupts external to MPUSS */
  39 #define OMAP44XX_IRQ_GIC_START  32
  40
  41 /* Base offset for all OMAP4 dma requests */
  42 #define OMAP44XX_DMA_REQ_START  1
  43
  44 /* Backward references (IPs with Bus Master capability) */
  45 static struct omap_hwmod omap44xx_aess_hwmod;
  46 static struct omap_hwmod omap44xx_dma_system_hwmod;
  47 static struct omap_hwmod omap44xx_dmm_hwmod;
  48 static struct omap_hwmod omap44xx_dsp_hwmod;
  49 static struct omap_hwmod omap44xx_dss_hwmod;
  50 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  51 static struct omap_hwmod omap44xx_hsi_hwmod;
  52 static struct omap_hwmod omap44xx_ipu_hwmod;
  53 static struct omap_hwmod omap44xx_iss_hwmod;
  54 static struct omap_hwmod omap44xx_iva_hwmod;
  55 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  56 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  57 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  58 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  59 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  60 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  61 static struct omap_hwmod omap44xx_l4_per_hwmod;
  62 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  63 static struct omap_hwmod omap44xx_mmc1_hwmod;
  64 static struct omap_hwmod omap44xx_mmc2_hwmod;
  65 static struct omap_hwmod omap44xx_mpu_hwmod;
  66 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  67 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  68
  69 /*
  70  * Interconnects omap_hwmod structures
  71  * hwmods that compose the global OMAP interconnect
  72  */
  73
  74 /*
  75  * 'dmm' class
  76  * instance(s): dmm
  77  */
  78 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  79         .name   = "dmm",
  80 };
  81
  82 /* dmm interface data */
  83 /* l3_main_1 -> dmm */
  84 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  85         .master         = &omap44xx_l3_main_1_hwmod,
  86         .slave          = &omap44xx_dmm_hwmod,
  87         .clk            = "l3_div_ck",
  88         .user           = OCP_USER_SDMA,
  89 };
  90
  91 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  92         {
  93                 .pa_start       = 0x4e000000,
  94                 .pa_end         = 0x4e0007ff,
  95                 .flags          = ADDR_TYPE_RT
  96         },
  97 };
  98
  99 /* mpu -> dmm */
 100 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 101         .master         = &omap44xx_mpu_hwmod,
 102         .slave          = &omap44xx_dmm_hwmod,
 103         .clk            = "l3_div_ck",
 104         .addr           = omap44xx_dmm_addrs,
 105         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
 106         .user           = OCP_USER_MPU,
 107 };
 108
 109 /* dmm slave ports */
 110 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 111         &omap44xx_l3_main_1__dmm,
 112         &omap44xx_mpu__dmm,
 113 };
 114
 115 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 116         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 117 };
 118
 119 static struct omap_hwmod omap44xx_dmm_hwmod = {
 120         .name           = "dmm",
 121         .class          = &omap44xx_dmm_hwmod_class,
 122         .slaves         = omap44xx_dmm_slaves,
 123         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 124         .mpu_irqs       = omap44xx_dmm_irqs,
 125         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 126         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 127 };
 128
 129 /*
 130  * 'emif_fw' class
 131  * instance(s): emif_fw
 132  */
 133 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 134         .name   = "emif_fw",
 135 };
 136
 137 /* emif_fw interface data */
 138 /* dmm -> emif_fw */
 139 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 140         .master         = &omap44xx_dmm_hwmod,
 141         .slave          = &omap44xx_emif_fw_hwmod,
 142         .clk            = "l3_div_ck",
 143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 144 };
 145
 146 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 147         {
 148                 .pa_start       = 0x4a20c000,
 149                 .pa_end         = 0x4a20c0ff,
 150                 .flags          = ADDR_TYPE_RT
 151         },
 152 };
 153
 154 /* l4_cfg -> emif_fw */
 155 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 156         .master         = &omap44xx_l4_cfg_hwmod,
 157         .slave          = &omap44xx_emif_fw_hwmod,
 158         .clk            = "l4_div_ck",
 159         .addr           = omap44xx_emif_fw_addrs,
 160         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 161         .user           = OCP_USER_MPU,
 162 };
 163
 164 /* emif_fw slave ports */
 165 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 166         &omap44xx_dmm__emif_fw,
 167         &omap44xx_l4_cfg__emif_fw,
 168 };
 169
 170 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 171         .name           = "emif_fw",
 172         .class          = &omap44xx_emif_fw_hwmod_class,
 173         .slaves         = omap44xx_emif_fw_slaves,
 174         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 175         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 176 };
 177
 178 /*
 179  * 'l3' class
 180  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 181  */
 182 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 183         .name   = "l3",
 184 };
 185
 186 /* l3_instr interface data */
 187 /* iva -> l3_instr */
 188 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 189         .master         = &omap44xx_iva_hwmod,
 190         .slave          = &omap44xx_l3_instr_hwmod,
 191         .clk            = "l3_div_ck",
 192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 193 };
 194
 195 /* l3_main_3 -> l3_instr */
 196 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 197         .master         = &omap44xx_l3_main_3_hwmod,
 198         .slave          = &omap44xx_l3_instr_hwmod,
 199         .clk            = "l3_div_ck",
 200         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 201 };
 202
 203 /* l3_instr slave ports */
 204 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 205         &omap44xx_iva__l3_instr,
 206         &omap44xx_l3_main_3__l3_instr,
 207 };
 208
 209 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 210         .name           = "l3_instr",
 211         .class          = &omap44xx_l3_hwmod_class,
 212         .slaves         = omap44xx_l3_instr_slaves,
 213         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 214         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 215 };
 216
 217 /* l3_main_1 interface data */
 218 /* dsp -> l3_main_1 */
 219 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 220         .master         = &omap44xx_dsp_hwmod,
 221         .slave          = &omap44xx_l3_main_1_hwmod,
 222         .clk            = "l3_div_ck",
 223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 224 };
 225
 226 /* dss -> l3_main_1 */
 227 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 228         .master         = &omap44xx_dss_hwmod,
 229         .slave          = &omap44xx_l3_main_1_hwmod,
 230         .clk            = "l3_div_ck",
 231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 232 };
 233
 234 /* l3_main_2 -> l3_main_1 */
 235 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 236         .master         = &omap44xx_l3_main_2_hwmod,
 237         .slave          = &omap44xx_l3_main_1_hwmod,
 238         .clk            = "l3_div_ck",
 239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 240 };
 241
 242 /* l4_cfg -> l3_main_1 */
 243 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 244         .master         = &omap44xx_l4_cfg_hwmod,
 245         .slave          = &omap44xx_l3_main_1_hwmod,
 246         .clk            = "l4_div_ck",
 247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 248 };
 249
 250 /* mmc1 -> l3_main_1 */
 251 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 252         .master         = &omap44xx_mmc1_hwmod,
 253         .slave          = &omap44xx_l3_main_1_hwmod,
 254         .clk            = "l3_div_ck",
 255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 256 };
 257
 258 /* mmc2 -> l3_main_1 */
 259 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 260         .master         = &omap44xx_mmc2_hwmod,
 261         .slave          = &omap44xx_l3_main_1_hwmod,
 262         .clk            = "l3_div_ck",
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* mpu -> l3_main_1 */
 267 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 268         .master         = &omap44xx_mpu_hwmod,
 269         .slave          = &omap44xx_l3_main_1_hwmod,
 270         .clk            = "l3_div_ck",
 271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 272 };
 273
 274 /* l3_main_1 slave ports */
 275 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 276         &omap44xx_dsp__l3_main_1,
 277         &omap44xx_dss__l3_main_1,
 278         &omap44xx_l3_main_2__l3_main_1,
 279         &omap44xx_l4_cfg__l3_main_1,
 280         &omap44xx_mmc1__l3_main_1,
 281         &omap44xx_mmc2__l3_main_1,
 282         &omap44xx_mpu__l3_main_1,
 283 };
 284
 285 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 286         .name           = "l3_main_1",
 287         .class          = &omap44xx_l3_hwmod_class,
 288         .slaves         = omap44xx_l3_main_1_slaves,
 289         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 290         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 291 };
 292
 293 /* l3_main_2 interface data */
 294 /* dma_system -> l3_main_2 */
 295 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 296         .master         = &omap44xx_dma_system_hwmod,
 297         .slave          = &omap44xx_l3_main_2_hwmod,
 298         .clk            = "l3_div_ck",
 299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 300 };
 301
 302 /* hsi -> l3_main_2 */
 303 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 304         .master         = &omap44xx_hsi_hwmod,
 305         .slave          = &omap44xx_l3_main_2_hwmod,
 306         .clk            = "l3_div_ck",
 307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 308 };
 309
 310 /* ipu -> l3_main_2 */
 311 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 312         .master         = &omap44xx_ipu_hwmod,
 313         .slave          = &omap44xx_l3_main_2_hwmod,
 314         .clk            = "l3_div_ck",
 315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 316 };
 317
 318 /* iss -> l3_main_2 */
 319 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 320         .master         = &omap44xx_iss_hwmod,
 321         .slave          = &omap44xx_l3_main_2_hwmod,
 322         .clk            = "l3_div_ck",
 323         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 324 };
 325
 326 /* iva -> l3_main_2 */
 327 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 328         .master         = &omap44xx_iva_hwmod,
 329         .slave          = &omap44xx_l3_main_2_hwmod,
 330         .clk            = "l3_div_ck",
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 /* l3_main_1 -> l3_main_2 */
 335 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 336         .master         = &omap44xx_l3_main_1_hwmod,
 337         .slave          = &omap44xx_l3_main_2_hwmod,
 338         .clk            = "l3_div_ck",
 339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 340 };
 341
 342 /* l4_cfg -> l3_main_2 */
 343 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 344         .master         = &omap44xx_l4_cfg_hwmod,
 345         .slave          = &omap44xx_l3_main_2_hwmod,
 346         .clk            = "l4_div_ck",
 347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 348 };
 349
 350 /* usb_otg_hs -> l3_main_2 */
 351 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 352         .master         = &omap44xx_usb_otg_hs_hwmod,
 353         .slave          = &omap44xx_l3_main_2_hwmod,
 354         .clk            = "l3_div_ck",
 355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 356 };
 357
 358 /* l3_main_2 slave ports */
 359 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 360         &omap44xx_dma_system__l3_main_2,
 361         &omap44xx_hsi__l3_main_2,
 362         &omap44xx_ipu__l3_main_2,
 363         &omap44xx_iss__l3_main_2,
 364         &omap44xx_iva__l3_main_2,
 365         &omap44xx_l3_main_1__l3_main_2,
 366         &omap44xx_l4_cfg__l3_main_2,
 367         &omap44xx_usb_otg_hs__l3_main_2,
 368 };
 369
 370 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 371         .name           = "l3_main_2",
 372         .class          = &omap44xx_l3_hwmod_class,
 373         .slaves         = omap44xx_l3_main_2_slaves,
 374         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 375         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 376 };
 377
 378 /* l3_main_3 interface data */
 379 /* l3_main_1 -> l3_main_3 */
 380 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 381         .master         = &omap44xx_l3_main_1_hwmod,
 382         .slave          = &omap44xx_l3_main_3_hwmod,
 383         .clk            = "l3_div_ck",
 384         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 385 };
 386
 387 /* l3_main_2 -> l3_main_3 */
 388 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 389         .master         = &omap44xx_l3_main_2_hwmod,
 390         .slave          = &omap44xx_l3_main_3_hwmod,
 391         .clk            = "l3_div_ck",
 392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 393 };
 394
 395 /* l4_cfg -> l3_main_3 */
 396 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 397         .master         = &omap44xx_l4_cfg_hwmod,
 398         .slave          = &omap44xx_l3_main_3_hwmod,
 399         .clk            = "l4_div_ck",
 400         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 401 };
 402
 403 /* l3_main_3 slave ports */
 404 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 405         &omap44xx_l3_main_1__l3_main_3,
 406         &omap44xx_l3_main_2__l3_main_3,
 407         &omap44xx_l4_cfg__l3_main_3,
 408 };
 409
 410 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 411         .name           = "l3_main_3",
 412         .class          = &omap44xx_l3_hwmod_class,
 413         .slaves         = omap44xx_l3_main_3_slaves,
 414         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 415         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 416 };
 417
 418 /*
 419  * 'l4' class
 420  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 421  */
 422 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 423         .name   = "l4",
 424 };
 425
 426 /* l4_abe interface data */
 427 /* aess -> l4_abe */
 428 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 429         .master         = &omap44xx_aess_hwmod,
 430         .slave          = &omap44xx_l4_abe_hwmod,
 431         .clk            = "ocp_abe_iclk",
 432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 433 };
 434
 435 /* dsp -> l4_abe */
 436 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 437         .master         = &omap44xx_dsp_hwmod,
 438         .slave          = &omap44xx_l4_abe_hwmod,
 439         .clk            = "ocp_abe_iclk",
 440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 441 };
 442
 443 /* l3_main_1 -> l4_abe */
 444 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 445         .master         = &omap44xx_l3_main_1_hwmod,
 446         .slave          = &omap44xx_l4_abe_hwmod,
 447         .clk            = "l3_div_ck",
 448         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 449 };
 450
 451 /* mpu -> l4_abe */
 452 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 453         .master         = &omap44xx_mpu_hwmod,
 454         .slave          = &omap44xx_l4_abe_hwmod,
 455         .clk            = "ocp_abe_iclk",
 456         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 457 };
 458
 459 /* l4_abe slave ports */
 460 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 461         &omap44xx_aess__l4_abe,
 462         &omap44xx_dsp__l4_abe,
 463         &omap44xx_l3_main_1__l4_abe,
 464         &omap44xx_mpu__l4_abe,
 465 };
 466
 467 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 468         .name           = "l4_abe",
 469         .class          = &omap44xx_l4_hwmod_class,
 470         .slaves         = omap44xx_l4_abe_slaves,
 471         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 472         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 473 };
 474
 475 /* l4_cfg interface data */
 476 /* l3_main_1 -> l4_cfg */
 477 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 478         .master         = &omap44xx_l3_main_1_hwmod,
 479         .slave          = &omap44xx_l4_cfg_hwmod,
 480         .clk            = "l3_div_ck",
 481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 482 };
 483
 484 /* l4_cfg slave ports */
 485 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 486         &omap44xx_l3_main_1__l4_cfg,
 487 };
 488
 489 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 490         .name           = "l4_cfg",
 491         .class          = &omap44xx_l4_hwmod_class,
 492         .slaves         = omap44xx_l4_cfg_slaves,
 493         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 494         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 495 };
 496
 497 /* l4_per interface data */
 498 /* l3_main_2 -> l4_per */
 499 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 500         .master         = &omap44xx_l3_main_2_hwmod,
 501         .slave          = &omap44xx_l4_per_hwmod,
 502         .clk            = "l3_div_ck",
 503         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 504 };
 505
 506 /* l4_per slave ports */
 507 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 508         &omap44xx_l3_main_2__l4_per,
 509 };
 510
 511 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 512         .name           = "l4_per",
 513         .class          = &omap44xx_l4_hwmod_class,
 514         .slaves         = omap44xx_l4_per_slaves,
 515         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 516         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 517 };
 518
 519 /* l4_wkup interface data */
 520 /* l4_cfg -> l4_wkup */
 521 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 522         .master         = &omap44xx_l4_cfg_hwmod,
 523         .slave          = &omap44xx_l4_wkup_hwmod,
 524         .clk            = "l4_div_ck",
 525         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 526 };
 527
 528 /* l4_wkup slave ports */
 529 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 530         &omap44xx_l4_cfg__l4_wkup,
 531 };
 532
 533 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 534         .name           = "l4_wkup",
 535         .class          = &omap44xx_l4_hwmod_class,
 536         .slaves         = omap44xx_l4_wkup_slaves,
 537         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 538         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 539 };
 540
 541 /*
 542  * 'mpu_bus' class
 543  * instance(s): mpu_private
 544  */
 545 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 546         .name   = "mpu_bus",
 547 };
 548
 549 /* mpu_private interface data */
 550 /* mpu -> mpu_private */
 551 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 552         .master         = &omap44xx_mpu_hwmod,
 553         .slave          = &omap44xx_mpu_private_hwmod,
 554         .clk            = "l3_div_ck",
 555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 556 };
 557
 558 /* mpu_private slave ports */
 559 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 560         &omap44xx_mpu__mpu_private,
 561 };
 562
 563 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 564         .name           = "mpu_private",
 565         .class          = &omap44xx_mpu_bus_hwmod_class,
 566         .slaves         = omap44xx_mpu_private_slaves,
 567         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 568         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 569 };
 570
 571 /*
 572  * Modules omap_hwmod structures
 573  *
 574  * The following IPs are excluded for the moment because:
 575  * - They do not need an explicit SW control using omap_hwmod API.
 576  * - They still need to be validated with the driver
 577  *   properly adapted to omap_hwmod / omap_device
 578  *
 579  *  c2c
 580  *  c2c_target_fw
 581  *  cm_core
 582  *  cm_core_aon
 583  *  ctrl_module_core
 584  *  ctrl_module_pad_core
 585  *  ctrl_module_pad_wkup
 586  *  ctrl_module_wkup
 587  *  debugss
 588  *  efuse_ctrl_cust
 589  *  efuse_ctrl_std
 590  *  elm
 591  *  emif1
 592  *  emif2
 593  *  fdif
 594  *  gpmc
 595  *  gpu
 596  *  hdq1w
 597  *  hsi
 598  *  ocmc_ram
 599  *  ocp2scp_usb_phy
 600  *  ocp_wp_noc
 601  *  prcm_mpu
 602  *  prm
 603  *  scrm
 604  *  sl2if
 605  *  slimbus1
 606  *  slimbus2
 607  *  usb_host_fs
 608  *  usb_host_hs
 609  *  usb_phy_cm
 610  *  usb_tll_hs
 611  *  usim
 612  */
 613
 614 /*
 615  * 'aess' class
 616  * audio engine sub system
 617  */
 618
 619 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 620         .rev_offs       = 0x0000,
 621         .sysc_offs      = 0x0010,
 622         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 623         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 624                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 625         .sysc_fields    = &omap_hwmod_sysc_type2,
 626 };
 627
 628 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 629         .name   = "aess",
 630         .sysc   = &omap44xx_aess_sysc,
 631 };
 632
 633 /* aess */
 634 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 635         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 636 };
 637
 638 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 639         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 640         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 641         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 642         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 643         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 644         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 645         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 646         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 647 };
 648
 649 /* aess master ports */
 650 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 651         &omap44xx_aess__l4_abe,
 652 };
 653
 654 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 655         {
 656                 .pa_start       = 0x401f1000,
 657                 .pa_end         = 0x401f13ff,
 658                 .flags          = ADDR_TYPE_RT
 659         },
 660 };
 661
 662 /* l4_abe -> aess */
 663 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 664         .master         = &omap44xx_l4_abe_hwmod,
 665         .slave          = &omap44xx_aess_hwmod,
 666         .clk            = "ocp_abe_iclk",
 667         .addr           = omap44xx_aess_addrs,
 668         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_addrs),
 669         .user           = OCP_USER_MPU,
 670 };
 671
 672 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 673         {
 674                 .pa_start       = 0x490f1000,
 675                 .pa_end         = 0x490f13ff,
 676                 .flags          = ADDR_TYPE_RT
 677         },
 678 };
 679
 680 /* l4_abe -> aess (dma) */
 681 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 682         .master         = &omap44xx_l4_abe_hwmod,
 683         .slave          = &omap44xx_aess_hwmod,
 684         .clk            = "ocp_abe_iclk",
 685         .addr           = omap44xx_aess_dma_addrs,
 686         .addr_cnt       = ARRAY_SIZE(omap44xx_aess_dma_addrs),
 687         .user           = OCP_USER_SDMA,
 688 };
 689
 690 /* aess slave ports */
 691 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 692         &omap44xx_l4_abe__aess,
 693         &omap44xx_l4_abe__aess_dma,
 694 };
 695
 696 static struct omap_hwmod omap44xx_aess_hwmod = {
 697         .name           = "aess",
 698         .class          = &omap44xx_aess_hwmod_class,
 699         .mpu_irqs       = omap44xx_aess_irqs,
 700         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_aess_irqs),
 701         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 702         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
 703         .main_clk       = "aess_fck",
 704         .prcm           = {
 705                 .omap4 = {
 706                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 707                 },
 708         },
 709         .slaves         = omap44xx_aess_slaves,
 710         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 711         .masters        = omap44xx_aess_masters,
 712         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 713         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 714 };
 715
 716 /*
 717  * 'bandgap' class
 718  * bangap reference for ldo regulators
 719  */
 720
 721 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 722         .name   = "bandgap",
 723 };
 724
 725 /* bandgap */
 726 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 727         { .role = "fclk", .clk = "bandgap_fclk" },
 728 };
 729
 730 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 731         .name           = "bandgap",
 732         .class          = &omap44xx_bandgap_hwmod_class,
 733         .prcm           = {
 734                 .omap4 = {
 735                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 736                 },
 737         },
 738         .opt_clks       = bandgap_opt_clks,
 739         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 740         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 741 };
 742
 743 /*
 744  * 'counter' class
 745  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 746  */
 747
 748 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 749         .rev_offs       = 0x0000,
 750         .sysc_offs      = 0x0004,
 751         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 752         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 753                            SIDLE_SMART_WKUP),
 754         .sysc_fields    = &omap_hwmod_sysc_type1,
 755 };
 756
 757 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 758         .name   = "counter",
 759         .sysc   = &omap44xx_counter_sysc,
 760 };
 761
 762 /* counter_32k */
 763 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 764 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 765         {
 766                 .pa_start       = 0x4a304000,
 767                 .pa_end         = 0x4a30401f,
 768                 .flags          = ADDR_TYPE_RT
 769         },
 770 };
 771
 772 /* l4_wkup -> counter_32k */
 773 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 774         .master         = &omap44xx_l4_wkup_hwmod,
 775         .slave          = &omap44xx_counter_32k_hwmod,
 776         .clk            = "l4_wkup_clk_mux_ck",
 777         .addr           = omap44xx_counter_32k_addrs,
 778         .addr_cnt       = ARRAY_SIZE(omap44xx_counter_32k_addrs),
 779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 780 };
 781
 782 /* counter_32k slave ports */
 783 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 784         &omap44xx_l4_wkup__counter_32k,
 785 };
 786
 787 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 788         .name           = "counter_32k",
 789         .class          = &omap44xx_counter_hwmod_class,
 790         .flags          = HWMOD_SWSUP_SIDLE,
 791         .main_clk       = "sys_32k_ck",
 792         .prcm           = {
 793                 .omap4 = {
 794                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 795                 },
 796         },
 797         .slaves         = omap44xx_counter_32k_slaves,
 798         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 799         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 800 };
 801
 802 /*
 803  * 'dma' class
 804  * dma controller for data exchange between memory to memory (i.e. internal or
 805  * external memory) and gp peripherals to memory or memory to gp peripherals
 806  */
 807
 808 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 809         .rev_offs       = 0x0000,
 810         .sysc_offs      = 0x002c,
 811         .syss_offs      = 0x0028,
 812         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 813                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 814                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 815                            SYSS_HAS_RESET_STATUS),
 816         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 817                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 818         .sysc_fields    = &omap_hwmod_sysc_type1,
 819 };
 820
 821 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 822         .name   = "dma",
 823         .sysc   = &omap44xx_dma_sysc,
 824 };
 825
 826 /* dma dev_attr */
 827 static struct omap_dma_dev_attr dma_dev_attr = {
 828         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 829                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 830         .lch_count      = 32,
 831 };
 832
 833 /* dma_system */
 834 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 835         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 836         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 837         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 838         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 839 };
 840
 841 /* dma_system master ports */
 842 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 843         &omap44xx_dma_system__l3_main_2,
 844 };
 845
 846 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 847         {
 848                 .pa_start       = 0x4a056000,
 849                 .pa_end         = 0x4a0560ff,
 850                 .flags          = ADDR_TYPE_RT
 851         },
 852 };
 853
 854 /* l4_cfg -> dma_system */
 855 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 856         .master         = &omap44xx_l4_cfg_hwmod,
 857         .slave          = &omap44xx_dma_system_hwmod,
 858         .clk            = "l4_div_ck",
 859         .addr           = omap44xx_dma_system_addrs,
 860         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
 861         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 862 };
 863
 864 /* dma_system slave ports */
 865 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 866         &omap44xx_l4_cfg__dma_system,
 867 };
 868
 869 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 870         .name           = "dma_system",
 871         .class          = &omap44xx_dma_hwmod_class,
 872         .mpu_irqs       = omap44xx_dma_system_irqs,
 873         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
 874         .main_clk       = "l3_div_ck",
 875         .prcm = {
 876                 .omap4 = {
 877                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 878                 },
 879         },
 880         .dev_attr       = &dma_dev_attr,
 881         .slaves         = omap44xx_dma_system_slaves,
 882         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 883         .masters        = omap44xx_dma_system_masters,
 884         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 885         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 886 };
 887
 888 /*
 889  * 'dmic' class
 890  * digital microphone controller
 891  */
 892
 893 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 894         .rev_offs       = 0x0000,
 895         .sysc_offs      = 0x0010,
 896         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 897                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 898         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 899                            SIDLE_SMART_WKUP),
 900         .sysc_fields    = &omap_hwmod_sysc_type2,
 901 };
 902
 903 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 904         .name   = "dmic",
 905         .sysc   = &omap44xx_dmic_sysc,
 906 };
 907
 908 /* dmic */
 909 static struct omap_hwmod omap44xx_dmic_hwmod;
 910 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 911         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 912 };
 913
 914 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 915         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 916 };
 917
 918 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 919         {
 920                 .pa_start       = 0x4012e000,
 921                 .pa_end         = 0x4012e07f,
 922                 .flags          = ADDR_TYPE_RT
 923         },
 924 };
 925
 926 /* l4_abe -> dmic */
 927 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 928         .master         = &omap44xx_l4_abe_hwmod,
 929         .slave          = &omap44xx_dmic_hwmod,
 930         .clk            = "ocp_abe_iclk",
 931         .addr           = omap44xx_dmic_addrs,
 932         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_addrs),
 933         .user           = OCP_USER_MPU,
 934 };
 935
 936 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 937         {
 938                 .pa_start       = 0x4902e000,
 939                 .pa_end         = 0x4902e07f,
 940                 .flags          = ADDR_TYPE_RT
 941         },
 942 };
 943
 944 /* l4_abe -> dmic (dma) */
 945 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 946         .master         = &omap44xx_l4_abe_hwmod,
 947         .slave          = &omap44xx_dmic_hwmod,
 948         .clk            = "ocp_abe_iclk",
 949         .addr           = omap44xx_dmic_dma_addrs,
 950         .addr_cnt       = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
 951         .user           = OCP_USER_SDMA,
 952 };
 953
 954 /* dmic slave ports */
 955 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 956         &omap44xx_l4_abe__dmic,
 957         &omap44xx_l4_abe__dmic_dma,
 958 };
 959
 960 static struct omap_hwmod omap44xx_dmic_hwmod = {
 961         .name           = "dmic",
 962         .class          = &omap44xx_dmic_hwmod_class,
 963         .mpu_irqs       = omap44xx_dmic_irqs,
 964         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmic_irqs),
 965         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 966         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
 967         .main_clk       = "dmic_fck",
 968         .prcm           = {
 969                 .omap4 = {
 970                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
 971                 },
 972         },
 973         .slaves         = omap44xx_dmic_slaves,
 974         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
 975         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 976 };
 977
 978 /*
 979  * 'dsp' class
 980  * dsp sub-system
 981  */
 982
 983 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 984         .name   = "dsp",
 985 };
 986
 987 /* dsp */
 988 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 989         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 990 };
 991
 992 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 993         { .name = "mmu_cache", .rst_shift = 1 },
 994 };
 995
 996 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 997         { .name = "dsp", .rst_shift = 0 },
 998 };
 999
1000 /* dsp -> iva */
1001 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1002         .master         = &omap44xx_dsp_hwmod,
1003         .slave          = &omap44xx_iva_hwmod,
1004         .clk            = "dpll_iva_m5x2_ck",
1005 };
1006
1007 /* dsp master ports */
1008 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1009         &omap44xx_dsp__l3_main_1,
1010         &omap44xx_dsp__l4_abe,
1011         &omap44xx_dsp__iva,
1012 };
1013
1014 /* l4_cfg -> dsp */
1015 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1016         .master         = &omap44xx_l4_cfg_hwmod,
1017         .slave          = &omap44xx_dsp_hwmod,
1018         .clk            = "l4_div_ck",
1019         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1020 };
1021
1022 /* dsp slave ports */
1023 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1024         &omap44xx_l4_cfg__dsp,
1025 };
1026
1027 /* Pseudo hwmod for reset control purpose only */
1028 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1029         .name           = "dsp_c0",
1030         .class          = &omap44xx_dsp_hwmod_class,
1031         .flags          = HWMOD_INIT_NO_RESET,
1032         .rst_lines      = omap44xx_dsp_c0_resets,
1033         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1034         .prcm = {
1035                 .omap4 = {
1036                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1037                 },
1038         },
1039         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1040 };
1041
1042 static struct omap_hwmod omap44xx_dsp_hwmod = {
1043         .name           = "dsp",
1044         .class          = &omap44xx_dsp_hwmod_class,
1045         .mpu_irqs       = omap44xx_dsp_irqs,
1046         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
1047         .rst_lines      = omap44xx_dsp_resets,
1048         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1049         .main_clk       = "dsp_fck",
1050         .prcm = {
1051                 .omap4 = {
1052                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1053                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1054                 },
1055         },
1056         .slaves         = omap44xx_dsp_slaves,
1057         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1058         .masters        = omap44xx_dsp_masters,
1059         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1060         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1061 };
1062
1063 /*
1064  * 'dss' class
1065  * display sub-system
1066  */
1067
1068 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1069         .rev_offs       = 0x0000,
1070         .syss_offs      = 0x0014,
1071         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1072 };
1073
1074 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1075         .name   = "dss",
1076         .sysc   = &omap44xx_dss_sysc,
1077 };
1078
1079 /* dss */
1080 /* dss master ports */
1081 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1082         &omap44xx_dss__l3_main_1,
1083 };
1084
1085 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1086         {
1087                 .pa_start       = 0x58000000,
1088                 .pa_end         = 0x5800007f,
1089                 .flags          = ADDR_TYPE_RT
1090         },
1091 };
1092
1093 /* l3_main_2 -> dss */
1094 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1095         .master         = &omap44xx_l3_main_2_hwmod,
1096         .slave          = &omap44xx_dss_hwmod,
1097         .clk            = "l3_div_ck",
1098         .addr           = omap44xx_dss_dma_addrs,
1099         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dma_addrs),
1100         .user           = OCP_USER_SDMA,
1101 };
1102
1103 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1104         {
1105                 .pa_start       = 0x48040000,
1106                 .pa_end         = 0x4804007f,
1107                 .flags          = ADDR_TYPE_RT
1108         },
1109 };
1110
1111 /* l4_per -> dss */
1112 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1113         .master         = &omap44xx_l4_per_hwmod,
1114         .slave          = &omap44xx_dss_hwmod,
1115         .clk            = "l4_div_ck",
1116         .addr           = omap44xx_dss_addrs,
1117         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_addrs),
1118         .user           = OCP_USER_MPU,
1119 };
1120
1121 /* dss slave ports */
1122 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1123         &omap44xx_l3_main_2__dss,
1124         &omap44xx_l4_per__dss,
1125 };
1126
1127 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1128         { .role = "sys_clk", .clk = "dss_sys_clk" },
1129         { .role = "tv_clk", .clk = "dss_tv_clk" },
1130         { .role = "dss_clk", .clk = "dss_dss_clk" },
1131         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1132 };
1133
1134 static struct omap_hwmod omap44xx_dss_hwmod = {
1135         .name           = "dss_core",
1136         .class          = &omap44xx_dss_hwmod_class,
1137         .main_clk       = "dss_fck",
1138         .prcm = {
1139                 .omap4 = {
1140                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1141                 },
1142         },
1143         .opt_clks       = dss_opt_clks,
1144         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1145         .slaves         = omap44xx_dss_slaves,
1146         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1147         .masters        = omap44xx_dss_masters,
1148         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1149         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1150 };
1151
1152 /*
1153  * 'dispc' class
1154  * display controller
1155  */
1156
1157 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1158         .rev_offs       = 0x0000,
1159         .sysc_offs      = 0x0010,
1160         .syss_offs      = 0x0014,
1161         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1162                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1163                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1164                            SYSS_HAS_RESET_STATUS),
1165         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1166                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1167         .sysc_fields    = &omap_hwmod_sysc_type1,
1168 };
1169
1170 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1171         .name   = "dispc",
1172         .sysc   = &omap44xx_dispc_sysc,
1173 };
1174
1175 /* dss_dispc */
1176 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1177 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1178         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1179 };
1180
1181 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1182         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1183 };
1184
1185 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1186         {
1187                 .pa_start       = 0x58001000,
1188                 .pa_end         = 0x58001fff,
1189                 .flags          = ADDR_TYPE_RT
1190         },
1191 };
1192
1193 /* l3_main_2 -> dss_dispc */
1194 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1195         .master         = &omap44xx_l3_main_2_hwmod,
1196         .slave          = &omap44xx_dss_dispc_hwmod,
1197         .clk            = "l3_div_ck",
1198         .addr           = omap44xx_dss_dispc_dma_addrs,
1199         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
1200         .user           = OCP_USER_SDMA,
1201 };
1202
1203 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1204         {
1205                 .pa_start       = 0x48041000,
1206                 .pa_end         = 0x48041fff,
1207                 .flags          = ADDR_TYPE_RT
1208         },
1209 };
1210
1211 /* l4_per -> dss_dispc */
1212 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1213         .master         = &omap44xx_l4_per_hwmod,
1214         .slave          = &omap44xx_dss_dispc_hwmod,
1215         .clk            = "l4_div_ck",
1216         .addr           = omap44xx_dss_dispc_addrs,
1217         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
1218         .user           = OCP_USER_MPU,
1219 };
1220
1221 /* dss_dispc slave ports */
1222 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1223         &omap44xx_l3_main_2__dss_dispc,
1224         &omap44xx_l4_per__dss_dispc,
1225 };
1226
1227 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1228         .name           = "dss_dispc",
1229         .class          = &omap44xx_dispc_hwmod_class,
1230         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1231         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
1232         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1233         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
1234         .main_clk       = "dss_fck",
1235         .prcm = {
1236                 .omap4 = {
1237                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1238                 },
1239         },
1240         .slaves         = omap44xx_dss_dispc_slaves,
1241         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1242         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1243 };
1244
1245 /*
1246  * 'dsi' class
1247  * display serial interface controller
1248  */
1249
1250 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1251         .rev_offs       = 0x0000,
1252         .sysc_offs      = 0x0010,
1253         .syss_offs      = 0x0014,
1254         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1255                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1256                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1257         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1258         .sysc_fields    = &omap_hwmod_sysc_type1,
1259 };
1260
1261 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1262         .name   = "dsi",
1263         .sysc   = &omap44xx_dsi_sysc,
1264 };
1265
1266 /* dss_dsi1 */
1267 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1268 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1269         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1270 };
1271
1272 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1273         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1274 };
1275
1276 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1277         {
1278                 .pa_start       = 0x58004000,
1279                 .pa_end         = 0x580041ff,
1280                 .flags          = ADDR_TYPE_RT
1281         },
1282 };
1283
1284 /* l3_main_2 -> dss_dsi1 */
1285 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1286         .master         = &omap44xx_l3_main_2_hwmod,
1287         .slave          = &omap44xx_dss_dsi1_hwmod,
1288         .clk            = "l3_div_ck",
1289         .addr           = omap44xx_dss_dsi1_dma_addrs,
1290         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
1291         .user           = OCP_USER_SDMA,
1292 };
1293
1294 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1295         {
1296                 .pa_start       = 0x48044000,
1297                 .pa_end         = 0x480441ff,
1298                 .flags          = ADDR_TYPE_RT
1299         },
1300 };
1301
1302 /* l4_per -> dss_dsi1 */
1303 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1304         .master         = &omap44xx_l4_per_hwmod,
1305         .slave          = &omap44xx_dss_dsi1_hwmod,
1306         .clk            = "l4_div_ck",
1307         .addr           = omap44xx_dss_dsi1_addrs,
1308         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
1309         .user           = OCP_USER_MPU,
1310 };
1311
1312 /* dss_dsi1 slave ports */
1313 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1314         &omap44xx_l3_main_2__dss_dsi1,
1315         &omap44xx_l4_per__dss_dsi1,
1316 };
1317
1318 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1319         .name           = "dss_dsi1",
1320         .class          = &omap44xx_dsi_hwmod_class,
1321         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1322         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
1323         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1324         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
1325         .main_clk       = "dss_fck",
1326         .prcm = {
1327                 .omap4 = {
1328                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1329                 },
1330         },
1331         .slaves         = omap44xx_dss_dsi1_slaves,
1332         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1333         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1334 };
1335
1336 /* dss_dsi2 */
1337 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1338 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1339         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1340 };
1341
1342 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1343         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1344 };
1345
1346 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1347         {
1348                 .pa_start       = 0x58005000,
1349                 .pa_end         = 0x580051ff,
1350                 .flags          = ADDR_TYPE_RT
1351         },
1352 };
1353
1354 /* l3_main_2 -> dss_dsi2 */
1355 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1356         .master         = &omap44xx_l3_main_2_hwmod,
1357         .slave          = &omap44xx_dss_dsi2_hwmod,
1358         .clk            = "l3_div_ck",
1359         .addr           = omap44xx_dss_dsi2_dma_addrs,
1360         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
1361         .user           = OCP_USER_SDMA,
1362 };
1363
1364 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1365         {
1366                 .pa_start       = 0x48045000,
1367                 .pa_end         = 0x480451ff,
1368                 .flags          = ADDR_TYPE_RT
1369         },
1370 };
1371
1372 /* l4_per -> dss_dsi2 */
1373 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1374         .master         = &omap44xx_l4_per_hwmod,
1375         .slave          = &omap44xx_dss_dsi2_hwmod,
1376         .clk            = "l4_div_ck",
1377         .addr           = omap44xx_dss_dsi2_addrs,
1378         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
1379         .user           = OCP_USER_MPU,
1380 };
1381
1382 /* dss_dsi2 slave ports */
1383 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1384         &omap44xx_l3_main_2__dss_dsi2,
1385         &omap44xx_l4_per__dss_dsi2,
1386 };
1387
1388 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1389         .name           = "dss_dsi2",
1390         .class          = &omap44xx_dsi_hwmod_class,
1391         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1392         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
1393         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1394         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
1395         .main_clk       = "dss_fck",
1396         .prcm = {
1397                 .omap4 = {
1398                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1399                 },
1400         },
1401         .slaves         = omap44xx_dss_dsi2_slaves,
1402         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1403         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1404 };
1405
1406 /*
1407  * 'hdmi' class
1408  * hdmi controller
1409  */
1410
1411 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1412         .rev_offs       = 0x0000,
1413         .sysc_offs      = 0x0010,
1414         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1415                            SYSC_HAS_SOFTRESET),
1416         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1417                            SIDLE_SMART_WKUP),
1418         .sysc_fields    = &omap_hwmod_sysc_type2,
1419 };
1420
1421 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1422         .name   = "hdmi",
1423         .sysc   = &omap44xx_hdmi_sysc,
1424 };
1425
1426 /* dss_hdmi */
1427 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1428 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1429         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1430 };
1431
1432 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1433         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1434 };
1435
1436 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1437         {
1438                 .pa_start       = 0x58006000,
1439                 .pa_end         = 0x58006fff,
1440                 .flags          = ADDR_TYPE_RT
1441         },
1442 };
1443
1444 /* l3_main_2 -> dss_hdmi */
1445 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1446         .master         = &omap44xx_l3_main_2_hwmod,
1447         .slave          = &omap44xx_dss_hdmi_hwmod,
1448         .clk            = "l3_div_ck",
1449         .addr           = omap44xx_dss_hdmi_dma_addrs,
1450         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
1451         .user           = OCP_USER_SDMA,
1452 };
1453
1454 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1455         {
1456                 .pa_start       = 0x48046000,
1457                 .pa_end         = 0x48046fff,
1458                 .flags          = ADDR_TYPE_RT
1459         },
1460 };
1461
1462 /* l4_per -> dss_hdmi */
1463 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1464         .master         = &omap44xx_l4_per_hwmod,
1465         .slave          = &omap44xx_dss_hdmi_hwmod,
1466         .clk            = "l4_div_ck",
1467         .addr           = omap44xx_dss_hdmi_addrs,
1468         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
1469         .user           = OCP_USER_MPU,
1470 };
1471
1472 /* dss_hdmi slave ports */
1473 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1474         &omap44xx_l3_main_2__dss_hdmi,
1475         &omap44xx_l4_per__dss_hdmi,
1476 };
1477
1478 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1479         .name           = "dss_hdmi",
1480         .class          = &omap44xx_hdmi_hwmod_class,
1481         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1482         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
1483         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1484         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
1485         .main_clk       = "dss_fck",
1486         .prcm = {
1487                 .omap4 = {
1488                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1489                 },
1490         },
1491         .slaves         = omap44xx_dss_hdmi_slaves,
1492         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1493         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1494 };
1495
1496 /*
1497  * 'rfbi' class
1498  * remote frame buffer interface
1499  */
1500
1501 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1502         .rev_offs       = 0x0000,
1503         .sysc_offs      = 0x0010,
1504         .syss_offs      = 0x0014,
1505         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1506                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1507         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1508         .sysc_fields    = &omap_hwmod_sysc_type1,
1509 };
1510
1511 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1512         .name   = "rfbi",
1513         .sysc   = &omap44xx_rfbi_sysc,
1514 };
1515
1516 /* dss_rfbi */
1517 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1518 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1519         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1520 };
1521
1522 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1523         {
1524                 .pa_start       = 0x58002000,
1525                 .pa_end         = 0x580020ff,
1526                 .flags          = ADDR_TYPE_RT
1527         },
1528 };
1529
1530 /* l3_main_2 -> dss_rfbi */
1531 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1532         .master         = &omap44xx_l3_main_2_hwmod,
1533         .slave          = &omap44xx_dss_rfbi_hwmod,
1534         .clk            = "l3_div_ck",
1535         .addr           = omap44xx_dss_rfbi_dma_addrs,
1536         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
1537         .user           = OCP_USER_SDMA,
1538 };
1539
1540 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1541         {
1542                 .pa_start       = 0x48042000,
1543                 .pa_end         = 0x480420ff,
1544                 .flags          = ADDR_TYPE_RT
1545         },
1546 };
1547
1548 /* l4_per -> dss_rfbi */
1549 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1550         .master         = &omap44xx_l4_per_hwmod,
1551         .slave          = &omap44xx_dss_rfbi_hwmod,
1552         .clk            = "l4_div_ck",
1553         .addr           = omap44xx_dss_rfbi_addrs,
1554         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
1555         .user           = OCP_USER_MPU,
1556 };
1557
1558 /* dss_rfbi slave ports */
1559 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1560         &omap44xx_l3_main_2__dss_rfbi,
1561         &omap44xx_l4_per__dss_rfbi,
1562 };
1563
1564 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1565         .name           = "dss_rfbi",
1566         .class          = &omap44xx_rfbi_hwmod_class,
1567         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1568         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
1569         .main_clk       = "dss_fck",
1570         .prcm = {
1571                 .omap4 = {
1572                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1573                 },
1574         },
1575         .slaves         = omap44xx_dss_rfbi_slaves,
1576         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1577         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1578 };
1579
1580 /*
1581  * 'venc' class
1582  * video encoder
1583  */
1584
1585 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1586         .name   = "venc",
1587 };
1588
1589 /* dss_venc */
1590 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1591 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1592         {
1593                 .pa_start       = 0x58003000,
1594                 .pa_end         = 0x580030ff,
1595                 .flags          = ADDR_TYPE_RT
1596         },
1597 };
1598
1599 /* l3_main_2 -> dss_venc */
1600 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1601         .master         = &omap44xx_l3_main_2_hwmod,
1602         .slave          = &omap44xx_dss_venc_hwmod,
1603         .clk            = "l3_div_ck",
1604         .addr           = omap44xx_dss_venc_dma_addrs,
1605         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
1606         .user           = OCP_USER_SDMA,
1607 };
1608
1609 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1610         {
1611                 .pa_start       = 0x48043000,
1612                 .pa_end         = 0x480430ff,
1613                 .flags          = ADDR_TYPE_RT
1614         },
1615 };
1616
1617 /* l4_per -> dss_venc */
1618 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1619         .master         = &omap44xx_l4_per_hwmod,
1620         .slave          = &omap44xx_dss_venc_hwmod,
1621         .clk            = "l4_div_ck",
1622         .addr           = omap44xx_dss_venc_addrs,
1623         .addr_cnt       = ARRAY_SIZE(omap44xx_dss_venc_addrs),
1624         .user           = OCP_USER_MPU,
1625 };
1626
1627 /* dss_venc slave ports */
1628 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1629         &omap44xx_l3_main_2__dss_venc,
1630         &omap44xx_l4_per__dss_venc,
1631 };
1632
1633 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1634         .name           = "dss_venc",
1635         .class          = &omap44xx_venc_hwmod_class,
1636         .main_clk       = "dss_fck",
1637         .prcm = {
1638                 .omap4 = {
1639                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1640                 },
1641         },
1642         .slaves         = omap44xx_dss_venc_slaves,
1643         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1644         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1645 };
1646
1647 /*
1648  * 'gpio' class
1649  * general purpose io module
1650  */
1651
1652 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1653         .rev_offs       = 0x0000,
1654         .sysc_offs      = 0x0010,
1655         .syss_offs      = 0x0114,
1656         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1657                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1658                            SYSS_HAS_RESET_STATUS),
1659         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1660                            SIDLE_SMART_WKUP),
1661         .sysc_fields    = &omap_hwmod_sysc_type1,
1662 };
1663
1664 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1665         .name   = "gpio",
1666         .sysc   = &omap44xx_gpio_sysc,
1667         .rev    = 2,
1668 };
1669
1670 /* gpio dev_attr */
1671 static struct omap_gpio_dev_attr gpio_dev_attr = {
1672         .bank_width     = 32,
1673         .dbck_flag      = true,
1674 };
1675
1676 /* gpio1 */
1677 static struct omap_hwmod omap44xx_gpio1_hwmod;
1678 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1679         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1680 };
1681
1682 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1683         {
1684                 .pa_start       = 0x4a310000,
1685                 .pa_end         = 0x4a3101ff,
1686                 .flags          = ADDR_TYPE_RT
1687         },
1688 };
1689
1690 /* l4_wkup -> gpio1 */
1691 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1692         .master         = &omap44xx_l4_wkup_hwmod,
1693         .slave          = &omap44xx_gpio1_hwmod,
1694         .clk            = "l4_wkup_clk_mux_ck",
1695         .addr           = omap44xx_gpio1_addrs,
1696         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1697         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1698 };
1699
1700 /* gpio1 slave ports */
1701 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1702         &omap44xx_l4_wkup__gpio1,
1703 };
1704
1705 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1706         { .role = "dbclk", .clk = "gpio1_dbclk" },
1707 };
1708
1709 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1710         .name           = "gpio1",
1711         .class          = &omap44xx_gpio_hwmod_class,
1712         .mpu_irqs       = omap44xx_gpio1_irqs,
1713         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1714         .main_clk       = "gpio1_ick",
1715         .prcm = {
1716                 .omap4 = {
1717                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1718                 },
1719         },
1720         .opt_clks       = gpio1_opt_clks,
1721         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1722         .dev_attr       = &gpio_dev_attr,
1723         .slaves         = omap44xx_gpio1_slaves,
1724         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1725         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1726 };
1727
1728 /* gpio2 */
1729 static struct omap_hwmod omap44xx_gpio2_hwmod;
1730 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1731         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1732 };
1733
1734 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1735         {
1736                 .pa_start       = 0x48055000,
1737                 .pa_end         = 0x480551ff,
1738                 .flags          = ADDR_TYPE_RT
1739         },
1740 };
1741
1742 /* l4_per -> gpio2 */
1743 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1744         .master         = &omap44xx_l4_per_hwmod,
1745         .slave          = &omap44xx_gpio2_hwmod,
1746         .clk            = "l4_div_ck",
1747         .addr           = omap44xx_gpio2_addrs,
1748         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1750 };
1751
1752 /* gpio2 slave ports */
1753 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1754         &omap44xx_l4_per__gpio2,
1755 };
1756
1757 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1758         { .role = "dbclk", .clk = "gpio2_dbclk" },
1759 };
1760
1761 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1762         .name           = "gpio2",
1763         .class          = &omap44xx_gpio_hwmod_class,
1764         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1765         .mpu_irqs       = omap44xx_gpio2_irqs,
1766         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1767         .main_clk       = "gpio2_ick",
1768         .prcm = {
1769                 .omap4 = {
1770                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1771                 },
1772         },
1773         .opt_clks       = gpio2_opt_clks,
1774         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1775         .dev_attr       = &gpio_dev_attr,
1776         .slaves         = omap44xx_gpio2_slaves,
1777         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1778         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1779 };
1780
1781 /* gpio3 */
1782 static struct omap_hwmod omap44xx_gpio3_hwmod;
1783 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1784         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1785 };
1786
1787 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1788         {
1789                 .pa_start       = 0x48057000,
1790                 .pa_end         = 0x480571ff,
1791                 .flags          = ADDR_TYPE_RT
1792         },
1793 };
1794
1795 /* l4_per -> gpio3 */
1796 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1797         .master         = &omap44xx_l4_per_hwmod,
1798         .slave          = &omap44xx_gpio3_hwmod,
1799         .clk            = "l4_div_ck",
1800         .addr           = omap44xx_gpio3_addrs,
1801         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1802         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1803 };
1804
1805 /* gpio3 slave ports */
1806 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1807         &omap44xx_l4_per__gpio3,
1808 };
1809
1810 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1811         { .role = "dbclk", .clk = "gpio3_dbclk" },
1812 };
1813
1814 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1815         .name           = "gpio3",
1816         .class          = &omap44xx_gpio_hwmod_class,
1817         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1818         .mpu_irqs       = omap44xx_gpio3_irqs,
1819         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1820         .main_clk       = "gpio3_ick",
1821         .prcm = {
1822                 .omap4 = {
1823                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1824                 },
1825         },
1826         .opt_clks       = gpio3_opt_clks,
1827         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1828         .dev_attr       = &gpio_dev_attr,
1829         .slaves         = omap44xx_gpio3_slaves,
1830         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1831         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1832 };
1833
1834 /* gpio4 */
1835 static struct omap_hwmod omap44xx_gpio4_hwmod;
1836 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1837         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1838 };
1839
1840 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1841         {
1842                 .pa_start       = 0x48059000,
1843                 .pa_end         = 0x480591ff,
1844                 .flags          = ADDR_TYPE_RT
1845         },
1846 };
1847
1848 /* l4_per -> gpio4 */
1849 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1850         .master         = &omap44xx_l4_per_hwmod,
1851         .slave          = &omap44xx_gpio4_hwmod,
1852         .clk            = "l4_div_ck",
1853         .addr           = omap44xx_gpio4_addrs,
1854         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1855         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1856 };
1857
1858 /* gpio4 slave ports */
1859 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1860         &omap44xx_l4_per__gpio4,
1861 };
1862
1863 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1864         { .role = "dbclk", .clk = "gpio4_dbclk" },
1865 };
1866
1867 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1868         .name           = "gpio4",
1869         .class          = &omap44xx_gpio_hwmod_class,
1870         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1871         .mpu_irqs       = omap44xx_gpio4_irqs,
1872         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1873         .main_clk       = "gpio4_ick",
1874         .prcm = {
1875                 .omap4 = {
1876                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1877                 },
1878         },
1879         .opt_clks       = gpio4_opt_clks,
1880         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1881         .dev_attr       = &gpio_dev_attr,
1882         .slaves         = omap44xx_gpio4_slaves,
1883         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1884         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1885 };
1886
1887 /* gpio5 */
1888 static struct omap_hwmod omap44xx_gpio5_hwmod;
1889 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1890         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1891 };
1892
1893 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1894         {
1895                 .pa_start       = 0x4805b000,
1896                 .pa_end         = 0x4805b1ff,
1897                 .flags          = ADDR_TYPE_RT
1898         },
1899 };
1900
1901 /* l4_per -> gpio5 */
1902 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1903         .master         = &omap44xx_l4_per_hwmod,
1904         .slave          = &omap44xx_gpio5_hwmod,
1905         .clk            = "l4_div_ck",
1906         .addr           = omap44xx_gpio5_addrs,
1907         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1909 };
1910
1911 /* gpio5 slave ports */
1912 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1913         &omap44xx_l4_per__gpio5,
1914 };
1915
1916 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1917         { .role = "dbclk", .clk = "gpio5_dbclk" },
1918 };
1919
1920 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1921         .name           = "gpio5",
1922         .class          = &omap44xx_gpio_hwmod_class,
1923         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1924         .mpu_irqs       = omap44xx_gpio5_irqs,
1925         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1926         .main_clk       = "gpio5_ick",
1927         .prcm = {
1928                 .omap4 = {
1929                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1930                 },
1931         },
1932         .opt_clks       = gpio5_opt_clks,
1933         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1934         .dev_attr       = &gpio_dev_attr,
1935         .slaves         = omap44xx_gpio5_slaves,
1936         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1937         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1938 };
1939
1940 /* gpio6 */
1941 static struct omap_hwmod omap44xx_gpio6_hwmod;
1942 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1943         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1944 };
1945
1946 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1947         {
1948                 .pa_start       = 0x4805d000,
1949                 .pa_end         = 0x4805d1ff,
1950                 .flags          = ADDR_TYPE_RT
1951         },
1952 };
1953
1954 /* l4_per -> gpio6 */
1955 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1956         .master         = &omap44xx_l4_per_hwmod,
1957         .slave          = &omap44xx_gpio6_hwmod,
1958         .clk            = "l4_div_ck",
1959         .addr           = omap44xx_gpio6_addrs,
1960         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1961         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1962 };
1963
1964 /* gpio6 slave ports */
1965 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1966         &omap44xx_l4_per__gpio6,
1967 };
1968
1969 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1970         { .role = "dbclk", .clk = "gpio6_dbclk" },
1971 };
1972
1973 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1974         .name           = "gpio6",
1975         .class          = &omap44xx_gpio_hwmod_class,
1976         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1977         .mpu_irqs       = omap44xx_gpio6_irqs,
1978         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1979         .main_clk       = "gpio6_ick",
1980         .prcm = {
1981                 .omap4 = {
1982                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1983                 },
1984         },
1985         .opt_clks       = gpio6_opt_clks,
1986         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1987         .dev_attr       = &gpio_dev_attr,
1988         .slaves         = omap44xx_gpio6_slaves,
1989         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1990         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1991 };
1992
1993 /*
1994  * 'hsi' class
1995  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1996  * serial if)
1997  */
1998
1999 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2000         .rev_offs       = 0x0000,
2001         .sysc_offs      = 0x0010,
2002         .syss_offs      = 0x0014,
2003         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2004                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2005                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2006         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2007                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2008                            MSTANDBY_SMART),
2009         .sysc_fields    = &omap_hwmod_sysc_type1,
2010 };
2011
2012 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2013         .name   = "hsi",
2014         .sysc   = &omap44xx_hsi_sysc,
2015 };
2016
2017 /* hsi */
2018 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2019         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2020         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2021         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2022 };
2023
2024 /* hsi master ports */
2025 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2026         &omap44xx_hsi__l3_main_2,
2027 };
2028
2029 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2030         {
2031                 .pa_start       = 0x4a058000,
2032                 .pa_end         = 0x4a05bfff,
2033                 .flags          = ADDR_TYPE_RT
2034         },
2035 };
2036
2037 /* l4_cfg -> hsi */
2038 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2039         .master         = &omap44xx_l4_cfg_hwmod,
2040         .slave          = &omap44xx_hsi_hwmod,
2041         .clk            = "l4_div_ck",
2042         .addr           = omap44xx_hsi_addrs,
2043         .addr_cnt       = ARRAY_SIZE(omap44xx_hsi_addrs),
2044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2045 };
2046
2047 /* hsi slave ports */
2048 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2049         &omap44xx_l4_cfg__hsi,
2050 };
2051
2052 static struct omap_hwmod omap44xx_hsi_hwmod = {
2053         .name           = "hsi",
2054         .class          = &omap44xx_hsi_hwmod_class,
2055         .mpu_irqs       = omap44xx_hsi_irqs,
2056         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_hsi_irqs),
2057         .main_clk       = "hsi_fck",
2058         .prcm           = {
2059                 .omap4 = {
2060                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2061                 },
2062         },
2063         .slaves         = omap44xx_hsi_slaves,
2064         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2065         .masters        = omap44xx_hsi_masters,
2066         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2067         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2068 };
2069
2070 /*
2071  * 'i2c' class
2072  * multimaster high-speed i2c controller
2073  */
2074
2075 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2076         .sysc_offs      = 0x0010,
2077         .syss_offs      = 0x0090,
2078         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2079                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2080                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2081         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2082                            SIDLE_SMART_WKUP),
2083         .sysc_fields    = &omap_hwmod_sysc_type1,
2084 };
2085
2086 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2087         .name   = "i2c",
2088         .sysc   = &omap44xx_i2c_sysc,
2089 };
2090
2091 /* i2c1 */
2092 static struct omap_hwmod omap44xx_i2c1_hwmod;
2093 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2094         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2095 };
2096
2097 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2098         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2099         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2100 };
2101
2102 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2103         {
2104                 .pa_start       = 0x48070000,
2105                 .pa_end         = 0x480700ff,
2106                 .flags          = ADDR_TYPE_RT
2107         },
2108 };
2109
2110 /* l4_per -> i2c1 */
2111 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2112         .master         = &omap44xx_l4_per_hwmod,
2113         .slave          = &omap44xx_i2c1_hwmod,
2114         .clk            = "l4_div_ck",
2115         .addr           = omap44xx_i2c1_addrs,
2116         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
2117         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2118 };
2119
2120 /* i2c1 slave ports */
2121 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2122         &omap44xx_l4_per__i2c1,
2123 };
2124
2125 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2126         .name           = "i2c1",
2127         .class          = &omap44xx_i2c_hwmod_class,
2128         .flags          = HWMOD_INIT_NO_RESET,
2129         .mpu_irqs       = omap44xx_i2c1_irqs,
2130         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
2131         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2132         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
2133         .main_clk       = "i2c1_fck",
2134         .prcm = {
2135                 .omap4 = {
2136                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2137                 },
2138         },
2139         .slaves         = omap44xx_i2c1_slaves,
2140         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2141         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2142 };
2143
2144 /* i2c2 */
2145 static struct omap_hwmod omap44xx_i2c2_hwmod;
2146 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2147         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2148 };
2149
2150 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2151         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2152         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2153 };
2154
2155 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2156         {
2157                 .pa_start       = 0x48072000,
2158                 .pa_end         = 0x480720ff,
2159                 .flags          = ADDR_TYPE_RT
2160         },
2161 };
2162
2163 /* l4_per -> i2c2 */
2164 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2165         .master         = &omap44xx_l4_per_hwmod,
2166         .slave          = &omap44xx_i2c2_hwmod,
2167         .clk            = "l4_div_ck",
2168         .addr           = omap44xx_i2c2_addrs,
2169         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
2170         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2171 };
2172
2173 /* i2c2 slave ports */
2174 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2175         &omap44xx_l4_per__i2c2,
2176 };
2177
2178 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2179         .name           = "i2c2",
2180         .class          = &omap44xx_i2c_hwmod_class,
2181         .flags          = HWMOD_INIT_NO_RESET,
2182         .mpu_irqs       = omap44xx_i2c2_irqs,
2183         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
2184         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2185         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
2186         .main_clk       = "i2c2_fck",
2187         .prcm = {
2188                 .omap4 = {
2189                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2190                 },
2191         },
2192         .slaves         = omap44xx_i2c2_slaves,
2193         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2194         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2195 };
2196
2197 /* i2c3 */
2198 static struct omap_hwmod omap44xx_i2c3_hwmod;
2199 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2200         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2201 };
2202
2203 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2204         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2205         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2206 };
2207
2208 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2209         {
2210                 .pa_start       = 0x48060000,
2211                 .pa_end         = 0x480600ff,
2212                 .flags          = ADDR_TYPE_RT
2213         },
2214 };
2215
2216 /* l4_per -> i2c3 */
2217 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2218         .master         = &omap44xx_l4_per_hwmod,
2219         .slave          = &omap44xx_i2c3_hwmod,
2220         .clk            = "l4_div_ck",
2221         .addr           = omap44xx_i2c3_addrs,
2222         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
2223         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2224 };
2225
2226 /* i2c3 slave ports */
2227 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2228         &omap44xx_l4_per__i2c3,
2229 };
2230
2231 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2232         .name           = "i2c3",
2233         .class          = &omap44xx_i2c_hwmod_class,
2234         .flags          = HWMOD_INIT_NO_RESET,
2235         .mpu_irqs       = omap44xx_i2c3_irqs,
2236         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
2237         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2238         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
2239         .main_clk       = "i2c3_fck",
2240         .prcm = {
2241                 .omap4 = {
2242                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2243                 },
2244         },
2245         .slaves         = omap44xx_i2c3_slaves,
2246         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2247         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2248 };
2249
2250 /* i2c4 */
2251 static struct omap_hwmod omap44xx_i2c4_hwmod;
2252 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2253         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2254 };
2255
2256 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2257         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2258         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2259 };
2260
2261 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2262         {
2263                 .pa_start       = 0x48350000,
2264                 .pa_end         = 0x483500ff,
2265                 .flags          = ADDR_TYPE_RT
2266         },
2267 };
2268
2269 /* l4_per -> i2c4 */
2270 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2271         .master         = &omap44xx_l4_per_hwmod,
2272         .slave          = &omap44xx_i2c4_hwmod,
2273         .clk            = "l4_div_ck",
2274         .addr           = omap44xx_i2c4_addrs,
2275         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
2276         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2277 };
2278
2279 /* i2c4 slave ports */
2280 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2281         &omap44xx_l4_per__i2c4,
2282 };
2283
2284 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2285         .name           = "i2c4",
2286         .class          = &omap44xx_i2c_hwmod_class,
2287         .flags          = HWMOD_INIT_NO_RESET,
2288         .mpu_irqs       = omap44xx_i2c4_irqs,
2289         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
2290         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2291         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
2292         .main_clk       = "i2c4_fck",
2293         .prcm = {
2294                 .omap4 = {
2295                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2296                 },
2297         },
2298         .slaves         = omap44xx_i2c4_slaves,
2299         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2300         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2301 };
2302
2303 /*
2304  * 'ipu' class
2305  * imaging processor unit
2306  */
2307
2308 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2309         .name   = "ipu",
2310 };
2311
2312 /* ipu */
2313 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2314         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2315 };
2316
2317 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2318         { .name = "cpu0", .rst_shift = 0 },
2319 };
2320
2321 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2322         { .name = "cpu1", .rst_shift = 1 },
2323 };
2324
2325 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2326         { .name = "mmu_cache", .rst_shift = 2 },
2327 };
2328
2329 /* ipu master ports */
2330 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2331         &omap44xx_ipu__l3_main_2,
2332 };
2333
2334 /* l3_main_2 -> ipu */
2335 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2336         .master         = &omap44xx_l3_main_2_hwmod,
2337         .slave          = &omap44xx_ipu_hwmod,
2338         .clk            = "l3_div_ck",
2339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2340 };
2341
2342 /* ipu slave ports */
2343 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2344         &omap44xx_l3_main_2__ipu,
2345 };
2346
2347 /* Pseudo hwmod for reset control purpose only */
2348 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2349         .name           = "ipu_c0",
2350         .class          = &omap44xx_ipu_hwmod_class,
2351         .flags          = HWMOD_INIT_NO_RESET,
2352         .rst_lines      = omap44xx_ipu_c0_resets,
2353         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2354         .prcm           = {
2355                 .omap4 = {
2356                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2357                 },
2358         },
2359         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2360 };
2361
2362 /* Pseudo hwmod for reset control purpose only */
2363 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2364         .name           = "ipu_c1",
2365         .class          = &omap44xx_ipu_hwmod_class,
2366         .flags          = HWMOD_INIT_NO_RESET,
2367         .rst_lines      = omap44xx_ipu_c1_resets,
2368         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2369         .prcm           = {
2370                 .omap4 = {
2371                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2372                 },
2373         },
2374         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2375 };
2376
2377 static struct omap_hwmod omap44xx_ipu_hwmod = {
2378         .name           = "ipu",
2379         .class          = &omap44xx_ipu_hwmod_class,
2380         .mpu_irqs       = omap44xx_ipu_irqs,
2381         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_ipu_irqs),
2382         .rst_lines      = omap44xx_ipu_resets,
2383         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2384         .main_clk       = "ipu_fck",
2385         .prcm           = {
2386                 .omap4 = {
2387                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2388                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2389                 },
2390         },
2391         .slaves         = omap44xx_ipu_slaves,
2392         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2393         .masters        = omap44xx_ipu_masters,
2394         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2395         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2396 };
2397
2398 /*
2399  * 'iss' class
2400  * external images sensor pixel data processor
2401  */
2402
2403 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2404         .rev_offs       = 0x0000,
2405         .sysc_offs      = 0x0010,
2406         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2407                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2408         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2409                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2410                            MSTANDBY_SMART),
2411         .sysc_fields    = &omap_hwmod_sysc_type2,
2412 };
2413
2414 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2415         .name   = "iss",
2416         .sysc   = &omap44xx_iss_sysc,
2417 };
2418
2419 /* iss */
2420 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2421         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2422 };
2423
2424 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2425         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2426         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2427         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2428         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2429 };
2430
2431 /* iss master ports */
2432 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2433         &omap44xx_iss__l3_main_2,
2434 };
2435
2436 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2437         {
2438                 .pa_start       = 0x52000000,
2439                 .pa_end         = 0x520000ff,
2440                 .flags          = ADDR_TYPE_RT
2441         },
2442 };
2443
2444 /* l3_main_2 -> iss */
2445 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2446         .master         = &omap44xx_l3_main_2_hwmod,
2447         .slave          = &omap44xx_iss_hwmod,
2448         .clk            = "l3_div_ck",
2449         .addr           = omap44xx_iss_addrs,
2450         .addr_cnt       = ARRAY_SIZE(omap44xx_iss_addrs),
2451         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2452 };
2453
2454 /* iss slave ports */
2455 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2456         &omap44xx_l3_main_2__iss,
2457 };
2458
2459 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2460         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2461 };
2462
2463 static struct omap_hwmod omap44xx_iss_hwmod = {
2464         .name           = "iss",
2465         .class          = &omap44xx_iss_hwmod_class,
2466         .mpu_irqs       = omap44xx_iss_irqs,
2467         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iss_irqs),
2468         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2469         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
2470         .main_clk       = "iss_fck",
2471         .prcm           = {
2472                 .omap4 = {
2473                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2474                 },
2475         },
2476         .opt_clks       = iss_opt_clks,
2477         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2478         .slaves         = omap44xx_iss_slaves,
2479         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2480         .masters        = omap44xx_iss_masters,
2481         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2482         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2483 };
2484
2485 /*
2486  * 'iva' class
2487  * multi-standard video encoder/decoder hardware accelerator
2488  */
2489
2490 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2491         .name   = "iva",
2492 };
2493
2494 /* iva */
2495 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2496         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2497         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2498         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2499 };
2500
2501 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2502         { .name = "logic", .rst_shift = 2 },
2503 };
2504
2505 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2506         { .name = "seq0", .rst_shift = 0 },
2507 };
2508
2509 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2510         { .name = "seq1", .rst_shift = 1 },
2511 };
2512
2513 /* iva master ports */
2514 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2515         &omap44xx_iva__l3_main_2,
2516         &omap44xx_iva__l3_instr,
2517 };
2518
2519 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2520         {
2521                 .pa_start       = 0x5a000000,
2522                 .pa_end         = 0x5a07ffff,
2523                 .flags          = ADDR_TYPE_RT
2524         },
2525 };
2526
2527 /* l3_main_2 -> iva */
2528 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2529         .master         = &omap44xx_l3_main_2_hwmod,
2530         .slave          = &omap44xx_iva_hwmod,
2531         .clk            = "l3_div_ck",
2532         .addr           = omap44xx_iva_addrs,
2533         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
2534         .user           = OCP_USER_MPU,
2535 };
2536
2537 /* iva slave ports */
2538 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2539         &omap44xx_dsp__iva,
2540         &omap44xx_l3_main_2__iva,
2541 };
2542
2543 /* Pseudo hwmod for reset control purpose only */
2544 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2545         .name           = "iva_seq0",
2546         .class          = &omap44xx_iva_hwmod_class,
2547         .flags          = HWMOD_INIT_NO_RESET,
2548         .rst_lines      = omap44xx_iva_seq0_resets,
2549         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2550         .prcm = {
2551                 .omap4 = {
2552                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2553                 },
2554         },
2555         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2556 };
2557
2558 /* Pseudo hwmod for reset control purpose only */
2559 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2560         .name           = "iva_seq1",
2561         .class          = &omap44xx_iva_hwmod_class,
2562         .flags          = HWMOD_INIT_NO_RESET,
2563         .rst_lines      = omap44xx_iva_seq1_resets,
2564         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2565         .prcm = {
2566                 .omap4 = {
2567                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2568                 },
2569         },
2570         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2571 };
2572
2573 static struct omap_hwmod omap44xx_iva_hwmod = {
2574         .name           = "iva",
2575         .class          = &omap44xx_iva_hwmod_class,
2576         .mpu_irqs       = omap44xx_iva_irqs,
2577         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
2578         .rst_lines      = omap44xx_iva_resets,
2579         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2580         .main_clk       = "iva_fck",
2581         .prcm = {
2582                 .omap4 = {
2583                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2584                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2585                 },
2586         },
2587         .slaves         = omap44xx_iva_slaves,
2588         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2589         .masters        = omap44xx_iva_masters,
2590         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2591         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2592 };
2593
2594 /*
2595  * 'kbd' class
2596  * keyboard controller
2597  */
2598
2599 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2600         .rev_offs       = 0x0000,
2601         .sysc_offs      = 0x0010,
2602         .syss_offs      = 0x0014,
2603         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2604                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2605                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2606                            SYSS_HAS_RESET_STATUS),
2607         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2608         .sysc_fields    = &omap_hwmod_sysc_type1,
2609 };
2610
2611 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2612         .name   = "kbd",
2613         .sysc   = &omap44xx_kbd_sysc,
2614 };
2615
2616 /* kbd */
2617 static struct omap_hwmod omap44xx_kbd_hwmod;
2618 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2619         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2620 };
2621
2622 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2623         {
2624                 .pa_start       = 0x4a31c000,
2625                 .pa_end         = 0x4a31c07f,
2626                 .flags          = ADDR_TYPE_RT
2627         },
2628 };
2629
2630 /* l4_wkup -> kbd */
2631 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2632         .master         = &omap44xx_l4_wkup_hwmod,
2633         .slave          = &omap44xx_kbd_hwmod,
2634         .clk            = "l4_wkup_clk_mux_ck",
2635         .addr           = omap44xx_kbd_addrs,
2636         .addr_cnt       = ARRAY_SIZE(omap44xx_kbd_addrs),
2637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2638 };
2639
2640 /* kbd slave ports */
2641 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2642         &omap44xx_l4_wkup__kbd,
2643 };
2644
2645 static struct omap_hwmod omap44xx_kbd_hwmod = {
2646         .name           = "kbd",
2647         .class          = &omap44xx_kbd_hwmod_class,
2648         .mpu_irqs       = omap44xx_kbd_irqs,
2649         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_kbd_irqs),
2650         .main_clk       = "kbd_fck",
2651         .prcm           = {
2652                 .omap4 = {
2653                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2654                 },
2655         },
2656         .slaves         = omap44xx_kbd_slaves,
2657         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2658         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2659 };
2660
2661 /*
2662  * 'mailbox' class
2663  * mailbox module allowing communication between the on-chip processors using a
2664  * queued mailbox-interrupt mechanism.
2665  */
2666
2667 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2668         .rev_offs       = 0x0000,
2669         .sysc_offs      = 0x0010,
2670         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2671                            SYSC_HAS_SOFTRESET),
2672         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2673         .sysc_fields    = &omap_hwmod_sysc_type2,
2674 };
2675
2676 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2677         .name   = "mailbox",
2678         .sysc   = &omap44xx_mailbox_sysc,
2679 };
2680
2681 /* mailbox */
2682 static struct omap_hwmod omap44xx_mailbox_hwmod;
2683 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2684         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2685 };
2686
2687 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2688         {
2689                 .pa_start       = 0x4a0f4000,
2690                 .pa_end         = 0x4a0f41ff,
2691                 .flags          = ADDR_TYPE_RT
2692         },
2693 };
2694
2695 /* l4_cfg -> mailbox */
2696 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2697         .master         = &omap44xx_l4_cfg_hwmod,
2698         .slave          = &omap44xx_mailbox_hwmod,
2699         .clk            = "l4_div_ck",
2700         .addr           = omap44xx_mailbox_addrs,
2701         .addr_cnt       = ARRAY_SIZE(omap44xx_mailbox_addrs),
2702         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2703 };
2704
2705 /* mailbox slave ports */
2706 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2707         &omap44xx_l4_cfg__mailbox,
2708 };
2709
2710 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2711         .name           = "mailbox",
2712         .class          = &omap44xx_mailbox_hwmod_class,
2713         .mpu_irqs       = omap44xx_mailbox_irqs,
2714         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mailbox_irqs),
2715         .prcm           = {
2716                 .omap4 = {
2717                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2718                 },
2719         },
2720         .slaves         = omap44xx_mailbox_slaves,
2721         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2722         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2723 };
2724
2725 /*
2726  * 'mcbsp' class
2727  * multi channel buffered serial port controller
2728  */
2729
2730 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2731         .sysc_offs      = 0x008c,
2732         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2733                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2734         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2735         .sysc_fields    = &omap_hwmod_sysc_type1,
2736 };
2737
2738 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2739         .name   = "mcbsp",
2740         .sysc   = &omap44xx_mcbsp_sysc,
2741         .rev    = MCBSP_CONFIG_TYPE4,
2742 };
2743
2744 /* mcbsp1 */
2745 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2746 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2747         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2748 };
2749
2750 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2751         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2752         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2753 };
2754
2755 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2756         {
2757                 .name           = "mpu",
2758                 .pa_start       = 0x40122000,
2759                 .pa_end         = 0x401220ff,
2760                 .flags          = ADDR_TYPE_RT
2761         },
2762 };
2763
2764 /* l4_abe -> mcbsp1 */
2765 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2766         .master         = &omap44xx_l4_abe_hwmod,
2767         .slave          = &omap44xx_mcbsp1_hwmod,
2768         .clk            = "ocp_abe_iclk",
2769         .addr           = omap44xx_mcbsp1_addrs,
2770         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
2771         .user           = OCP_USER_MPU,
2772 };
2773
2774 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2775         {
2776                 .name           = "dma",
2777                 .pa_start       = 0x49022000,
2778                 .pa_end         = 0x490220ff,
2779                 .flags          = ADDR_TYPE_RT
2780         },
2781 };
2782
2783 /* l4_abe -> mcbsp1 (dma) */
2784 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2785         .master         = &omap44xx_l4_abe_hwmod,
2786         .slave          = &omap44xx_mcbsp1_hwmod,
2787         .clk            = "ocp_abe_iclk",
2788         .addr           = omap44xx_mcbsp1_dma_addrs,
2789         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
2790         .user           = OCP_USER_SDMA,
2791 };
2792
2793 /* mcbsp1 slave ports */
2794 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2795         &omap44xx_l4_abe__mcbsp1,
2796         &omap44xx_l4_abe__mcbsp1_dma,
2797 };
2798
2799 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2800         .name           = "mcbsp1",
2801         .class          = &omap44xx_mcbsp_hwmod_class,
2802         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2803         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
2804         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2805         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
2806         .main_clk       = "mcbsp1_fck",
2807         .prcm = {
2808                 .omap4 = {
2809                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2810                 },
2811         },
2812         .slaves         = omap44xx_mcbsp1_slaves,
2813         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2814         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2815 };
2816
2817 /* mcbsp2 */
2818 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2819 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2820         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2821 };
2822
2823 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2824         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2825         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2826 };
2827
2828 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2829         {
2830                 .name           = "mpu",
2831                 .pa_start       = 0x40124000,
2832                 .pa_end         = 0x401240ff,
2833                 .flags          = ADDR_TYPE_RT
2834         },
2835 };
2836
2837 /* l4_abe -> mcbsp2 */
2838 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2839         .master         = &omap44xx_l4_abe_hwmod,
2840         .slave          = &omap44xx_mcbsp2_hwmod,
2841         .clk            = "ocp_abe_iclk",
2842         .addr           = omap44xx_mcbsp2_addrs,
2843         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
2844         .user           = OCP_USER_MPU,
2845 };
2846
2847 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2848         {
2849                 .name           = "dma",
2850                 .pa_start       = 0x49024000,
2851                 .pa_end         = 0x490240ff,
2852                 .flags          = ADDR_TYPE_RT
2853         },
2854 };
2855
2856 /* l4_abe -> mcbsp2 (dma) */
2857 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2858         .master         = &omap44xx_l4_abe_hwmod,
2859         .slave          = &omap44xx_mcbsp2_hwmod,
2860         .clk            = "ocp_abe_iclk",
2861         .addr           = omap44xx_mcbsp2_dma_addrs,
2862         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
2863         .user           = OCP_USER_SDMA,
2864 };
2865
2866 /* mcbsp2 slave ports */
2867 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2868         &omap44xx_l4_abe__mcbsp2,
2869         &omap44xx_l4_abe__mcbsp2_dma,
2870 };
2871
2872 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2873         .name           = "mcbsp2",
2874         .class          = &omap44xx_mcbsp_hwmod_class,
2875         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2876         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
2877         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2878         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
2879         .main_clk       = "mcbsp2_fck",
2880         .prcm = {
2881                 .omap4 = {
2882                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2883                 },
2884         },
2885         .slaves         = omap44xx_mcbsp2_slaves,
2886         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2887         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2888 };
2889
2890 /* mcbsp3 */
2891 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2892 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2893         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2894 };
2895
2896 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2897         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2898         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2899 };
2900
2901 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2902         {
2903                 .name           = "mpu",
2904                 .pa_start       = 0x40126000,
2905                 .pa_end         = 0x401260ff,
2906                 .flags          = ADDR_TYPE_RT
2907         },
2908 };
2909
2910 /* l4_abe -> mcbsp3 */
2911 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2912         .master         = &omap44xx_l4_abe_hwmod,
2913         .slave          = &omap44xx_mcbsp3_hwmod,
2914         .clk            = "ocp_abe_iclk",
2915         .addr           = omap44xx_mcbsp3_addrs,
2916         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
2917         .user           = OCP_USER_MPU,
2918 };
2919
2920 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2921         {
2922                 .name           = "dma",
2923                 .pa_start       = 0x49026000,
2924                 .pa_end         = 0x490260ff,
2925                 .flags          = ADDR_TYPE_RT
2926         },
2927 };
2928
2929 /* l4_abe -> mcbsp3 (dma) */
2930 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2931         .master         = &omap44xx_l4_abe_hwmod,
2932         .slave          = &omap44xx_mcbsp3_hwmod,
2933         .clk            = "ocp_abe_iclk",
2934         .addr           = omap44xx_mcbsp3_dma_addrs,
2935         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
2936         .user           = OCP_USER_SDMA,
2937 };
2938
2939 /* mcbsp3 slave ports */
2940 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2941         &omap44xx_l4_abe__mcbsp3,
2942         &omap44xx_l4_abe__mcbsp3_dma,
2943 };
2944
2945 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2946         .name           = "mcbsp3",
2947         .class          = &omap44xx_mcbsp_hwmod_class,
2948         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2949         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
2950         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2951         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
2952         .main_clk       = "mcbsp3_fck",
2953         .prcm = {
2954                 .omap4 = {
2955                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2956                 },
2957         },
2958         .slaves         = omap44xx_mcbsp3_slaves,
2959         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
2960         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2961 };
2962
2963 /* mcbsp4 */
2964 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
2965 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2966         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2967 };
2968
2969 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2970         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2971         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2972 };
2973
2974 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
2975         {
2976                 .pa_start       = 0x48096000,
2977                 .pa_end         = 0x480960ff,
2978                 .flags          = ADDR_TYPE_RT
2979         },
2980 };
2981
2982 /* l4_per -> mcbsp4 */
2983 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
2984         .master         = &omap44xx_l4_per_hwmod,
2985         .slave          = &omap44xx_mcbsp4_hwmod,
2986         .clk            = "l4_div_ck",
2987         .addr           = omap44xx_mcbsp4_addrs,
2988         .addr_cnt       = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
2989         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2990 };
2991
2992 /* mcbsp4 slave ports */
2993 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
2994         &omap44xx_l4_per__mcbsp4,
2995 };
2996
2997 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2998         .name           = "mcbsp4",
2999         .class          = &omap44xx_mcbsp_hwmod_class,
3000         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3001         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
3002         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3003         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
3004         .main_clk       = "mcbsp4_fck",
3005         .prcm = {
3006                 .omap4 = {
3007                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3008                 },
3009         },
3010         .slaves         = omap44xx_mcbsp4_slaves,
3011         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3012         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3013 };
3014
3015 /*
3016  * 'mcpdm' class
3017  * multi channel pdm controller (proprietary interface with phoenix power
3018  * ic)
3019  */
3020
3021 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3022         .rev_offs       = 0x0000,
3023         .sysc_offs      = 0x0010,
3024         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3025                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3026         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3027                            SIDLE_SMART_WKUP),
3028         .sysc_fields    = &omap_hwmod_sysc_type2,
3029 };
3030
3031 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3032         .name   = "mcpdm",
3033         .sysc   = &omap44xx_mcpdm_sysc,
3034 };
3035
3036 /* mcpdm */
3037 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3038 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3039         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3040 };
3041
3042 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3043         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3044         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3045 };
3046
3047 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3048         {
3049                 .pa_start       = 0x40132000,
3050                 .pa_end         = 0x4013207f,
3051                 .flags          = ADDR_TYPE_RT
3052         },
3053 };
3054
3055 /* l4_abe -> mcpdm */
3056 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3057         .master         = &omap44xx_l4_abe_hwmod,
3058         .slave          = &omap44xx_mcpdm_hwmod,
3059         .clk            = "ocp_abe_iclk",
3060         .addr           = omap44xx_mcpdm_addrs,
3061         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_addrs),
3062         .user           = OCP_USER_MPU,
3063 };
3064
3065 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3066         {
3067                 .pa_start       = 0x49032000,
3068                 .pa_end         = 0x4903207f,
3069                 .flags          = ADDR_TYPE_RT
3070         },
3071 };
3072
3073 /* l4_abe -> mcpdm (dma) */
3074 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3075         .master         = &omap44xx_l4_abe_hwmod,
3076         .slave          = &omap44xx_mcpdm_hwmod,
3077         .clk            = "ocp_abe_iclk",
3078         .addr           = omap44xx_mcpdm_dma_addrs,
3079         .addr_cnt       = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
3080         .user           = OCP_USER_SDMA,
3081 };
3082
3083 /* mcpdm slave ports */
3084 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3085         &omap44xx_l4_abe__mcpdm,
3086         &omap44xx_l4_abe__mcpdm_dma,
3087 };
3088
3089 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3090         .name           = "mcpdm",
3091         .class          = &omap44xx_mcpdm_hwmod_class,
3092         .mpu_irqs       = omap44xx_mcpdm_irqs,
3093         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcpdm_irqs),
3094         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3095         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
3096         .main_clk       = "mcpdm_fck",
3097         .prcm           = {
3098                 .omap4 = {
3099                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3100                 },
3101         },
3102         .slaves         = omap44xx_mcpdm_slaves,
3103         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3104         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3105 };
3106
3107 /*
3108  * 'mcspi' class
3109  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3110  * bus
3111  */
3112
3113 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3114         .rev_offs       = 0x0000,
3115         .sysc_offs      = 0x0010,
3116         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3117                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3118         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3119                            SIDLE_SMART_WKUP),
3120         .sysc_fields    = &omap_hwmod_sysc_type2,
3121 };
3122
3123 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3124         .name   = "mcspi",
3125         .sysc   = &omap44xx_mcspi_sysc,
3126         .rev    = OMAP4_MCSPI_REV,
3127 };
3128
3129 /* mcspi1 */
3130 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3131 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3132         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3133 };
3134
3135 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3136         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3137         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3138         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3139         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3140         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3141         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3142         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3143         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3144 };
3145
3146 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3147         {
3148                 .pa_start       = 0x48098000,
3149                 .pa_end         = 0x480981ff,
3150                 .flags          = ADDR_TYPE_RT
3151         },
3152 };
3153
3154 /* l4_per -> mcspi1 */
3155 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3156         .master         = &omap44xx_l4_per_hwmod,
3157         .slave          = &omap44xx_mcspi1_hwmod,
3158         .clk            = "l4_div_ck",
3159         .addr           = omap44xx_mcspi1_addrs,
3160         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
3161         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3162 };
3163
3164 /* mcspi1 slave ports */
3165 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3166         &omap44xx_l4_per__mcspi1,
3167 };
3168
3169 /* mcspi1 dev_attr */
3170 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3171         .num_chipselect = 4,
3172 };
3173
3174 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3175         .name           = "mcspi1",
3176         .class          = &omap44xx_mcspi_hwmod_class,
3177         .mpu_irqs       = omap44xx_mcspi1_irqs,
3178         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
3179         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3180         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
3181         .main_clk       = "mcspi1_fck",
3182         .prcm = {
3183                 .omap4 = {
3184                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3185                 },
3186         },
3187         .dev_attr       = &mcspi1_dev_attr,
3188         .slaves         = omap44xx_mcspi1_slaves,
3189         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3190         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3191 };
3192
3193 /* mcspi2 */
3194 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3195 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3196         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3197 };
3198
3199 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3200         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3201         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3202         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3203         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3204 };
3205
3206 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3207         {
3208                 .pa_start       = 0x4809a000,
3209                 .pa_end         = 0x4809a1ff,
3210                 .flags          = ADDR_TYPE_RT
3211         },
3212 };
3213
3214 /* l4_per -> mcspi2 */
3215 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3216         .master         = &omap44xx_l4_per_hwmod,
3217         .slave          = &omap44xx_mcspi2_hwmod,
3218         .clk            = "l4_div_ck",
3219         .addr           = omap44xx_mcspi2_addrs,
3220         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
3221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3222 };
3223
3224 /* mcspi2 slave ports */
3225 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3226         &omap44xx_l4_per__mcspi2,
3227 };
3228
3229 /* mcspi2 dev_attr */
3230 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3231         .num_chipselect = 2,
3232 };
3233
3234 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3235         .name           = "mcspi2",
3236         .class          = &omap44xx_mcspi_hwmod_class,
3237         .mpu_irqs       = omap44xx_mcspi2_irqs,
3238         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
3239         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3240         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
3241         .main_clk       = "mcspi2_fck",
3242         .prcm = {
3243                 .omap4 = {
3244                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3245                 },
3246         },
3247         .dev_attr       = &mcspi2_dev_attr,
3248         .slaves         = omap44xx_mcspi2_slaves,
3249         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3250         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3251 };
3252
3253 /* mcspi3 */
3254 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3255 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3256         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3257 };
3258
3259 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3260         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3261         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3262         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3263         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3264 };
3265
3266 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3267         {
3268                 .pa_start       = 0x480b8000,
3269                 .pa_end         = 0x480b81ff,
3270                 .flags          = ADDR_TYPE_RT
3271         },
3272 };
3273
3274 /* l4_per -> mcspi3 */
3275 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3276         .master         = &omap44xx_l4_per_hwmod,
3277         .slave          = &omap44xx_mcspi3_hwmod,
3278         .clk            = "l4_div_ck",
3279         .addr           = omap44xx_mcspi3_addrs,
3280         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
3281         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3282 };
3283
3284 /* mcspi3 slave ports */
3285 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3286         &omap44xx_l4_per__mcspi3,
3287 };
3288
3289 /* mcspi3 dev_attr */
3290 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3291         .num_chipselect = 2,
3292 };
3293
3294 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3295         .name           = "mcspi3",
3296         .class          = &omap44xx_mcspi_hwmod_class,
3297         .mpu_irqs       = omap44xx_mcspi3_irqs,
3298         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
3299         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3300         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
3301         .main_clk       = "mcspi3_fck",
3302         .prcm = {
3303                 .omap4 = {
3304                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3305                 },
3306         },
3307         .dev_attr       = &mcspi3_dev_attr,
3308         .slaves         = omap44xx_mcspi3_slaves,
3309         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3310         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3311 };
3312
3313 /* mcspi4 */
3314 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3315 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3316         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3317 };
3318
3319 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3320         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3321         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3322 };
3323
3324 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3325         {
3326                 .pa_start       = 0x480ba000,
3327                 .pa_end         = 0x480ba1ff,
3328                 .flags          = ADDR_TYPE_RT
3329         },
3330 };
3331
3332 /* l4_per -> mcspi4 */
3333 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3334         .master         = &omap44xx_l4_per_hwmod,
3335         .slave          = &omap44xx_mcspi4_hwmod,
3336         .clk            = "l4_div_ck",
3337         .addr           = omap44xx_mcspi4_addrs,
3338         .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
3339         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3340 };
3341
3342 /* mcspi4 slave ports */
3343 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3344         &omap44xx_l4_per__mcspi4,
3345 };
3346
3347 /* mcspi4 dev_attr */
3348 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3349         .num_chipselect = 1,
3350 };
3351
3352 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3353         .name           = "mcspi4",
3354         .class          = &omap44xx_mcspi_hwmod_class,
3355         .mpu_irqs       = omap44xx_mcspi4_irqs,
3356         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
3357         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3358         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
3359         .main_clk       = "mcspi4_fck",
3360         .prcm = {
3361                 .omap4 = {
3362                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3363                 },
3364         },
3365         .dev_attr       = &mcspi4_dev_attr,
3366         .slaves         = omap44xx_mcspi4_slaves,
3367         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3368         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3369 };
3370
3371 /*
3372  * 'mmc' class
3373  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3374  */
3375
3376 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3377         .rev_offs       = 0x0000,
3378         .sysc_offs      = 0x0010,
3379         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3380                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3381                            SYSC_HAS_SOFTRESET),
3382         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3383                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3384                            MSTANDBY_SMART),
3385         .sysc_fields    = &omap_hwmod_sysc_type2,
3386 };
3387
3388 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3389         .name   = "mmc",
3390         .sysc   = &omap44xx_mmc_sysc,
3391 };
3392
3393 /* mmc1 */
3394 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3395         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3396 };
3397
3398 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3399         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3400         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3401 };
3402
3403 /* mmc1 master ports */
3404 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3405         &omap44xx_mmc1__l3_main_1,
3406 };
3407
3408 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3409         {
3410                 .pa_start       = 0x4809c000,
3411                 .pa_end         = 0x4809c3ff,
3412                 .flags          = ADDR_TYPE_RT
3413         },
3414 };
3415
3416 /* l4_per -> mmc1 */
3417 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3418         .master         = &omap44xx_l4_per_hwmod,
3419         .slave          = &omap44xx_mmc1_hwmod,
3420         .clk            = "l4_div_ck",
3421         .addr           = omap44xx_mmc1_addrs,
3422         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc1_addrs),
3423         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3424 };
3425
3426 /* mmc1 slave ports */
3427 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3428         &omap44xx_l4_per__mmc1,
3429 };
3430
3431 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3432         .name           = "mmc1",
3433         .class          = &omap44xx_mmc_hwmod_class,
3434         .mpu_irqs       = omap44xx_mmc1_irqs,
3435         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc1_irqs),
3436         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3437         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
3438         .main_clk       = "mmc1_fck",
3439         .prcm           = {
3440                 .omap4 = {
3441                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3442                 },
3443         },
3444         .slaves         = omap44xx_mmc1_slaves,
3445         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3446         .masters        = omap44xx_mmc1_masters,
3447         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3448         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3449 };
3450
3451 /* mmc2 */
3452 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3453         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3454 };
3455
3456 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3457         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3458         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3459 };
3460
3461 /* mmc2 master ports */
3462 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3463         &omap44xx_mmc2__l3_main_1,
3464 };
3465
3466 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3467         {
3468                 .pa_start       = 0x480b4000,
3469                 .pa_end         = 0x480b43ff,
3470                 .flags          = ADDR_TYPE_RT
3471         },
3472 };
3473
3474 /* l4_per -> mmc2 */
3475 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3476         .master         = &omap44xx_l4_per_hwmod,
3477         .slave          = &omap44xx_mmc2_hwmod,
3478         .clk            = "l4_div_ck",
3479         .addr           = omap44xx_mmc2_addrs,
3480         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc2_addrs),
3481         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3482 };
3483
3484 /* mmc2 slave ports */
3485 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3486         &omap44xx_l4_per__mmc2,
3487 };
3488
3489 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3490         .name           = "mmc2",
3491         .class          = &omap44xx_mmc_hwmod_class,
3492         .mpu_irqs       = omap44xx_mmc2_irqs,
3493         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc2_irqs),
3494         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3495         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
3496         .main_clk       = "mmc2_fck",
3497         .prcm           = {
3498                 .omap4 = {
3499                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3500                 },
3501         },
3502         .slaves         = omap44xx_mmc2_slaves,
3503         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3504         .masters        = omap44xx_mmc2_masters,
3505         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3506         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3507 };
3508
3509 /* mmc3 */
3510 static struct omap_hwmod omap44xx_mmc3_hwmod;
3511 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3512         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3513 };
3514
3515 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3516         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3517         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3518 };
3519
3520 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3521         {
3522                 .pa_start       = 0x480ad000,
3523                 .pa_end         = 0x480ad3ff,
3524                 .flags          = ADDR_TYPE_RT
3525         },
3526 };
3527
3528 /* l4_per -> mmc3 */
3529 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3530         .master         = &omap44xx_l4_per_hwmod,
3531         .slave          = &omap44xx_mmc3_hwmod,
3532         .clk            = "l4_div_ck",
3533         .addr           = omap44xx_mmc3_addrs,
3534         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc3_addrs),
3535         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3536 };
3537
3538 /* mmc3 slave ports */
3539 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3540         &omap44xx_l4_per__mmc3,
3541 };
3542
3543 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3544         .name           = "mmc3",
3545         .class          = &omap44xx_mmc_hwmod_class,
3546         .mpu_irqs       = omap44xx_mmc3_irqs,
3547         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc3_irqs),
3548         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3549         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
3550         .main_clk       = "mmc3_fck",
3551         .prcm           = {
3552                 .omap4 = {
3553                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3554                 },
3555         },
3556         .slaves         = omap44xx_mmc3_slaves,
3557         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3558         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3559 };
3560
3561 /* mmc4 */
3562 static struct omap_hwmod omap44xx_mmc4_hwmod;
3563 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3564         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3565 };
3566
3567 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3568         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3569         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3570 };
3571
3572 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3573         {
3574                 .pa_start       = 0x480d1000,
3575                 .pa_end         = 0x480d13ff,
3576                 .flags          = ADDR_TYPE_RT
3577         },
3578 };
3579
3580 /* l4_per -> mmc4 */
3581 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3582         .master         = &omap44xx_l4_per_hwmod,
3583         .slave          = &omap44xx_mmc4_hwmod,
3584         .clk            = "l4_div_ck",
3585         .addr           = omap44xx_mmc4_addrs,
3586         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc4_addrs),
3587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3588 };
3589
3590 /* mmc4 slave ports */
3591 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3592         &omap44xx_l4_per__mmc4,
3593 };
3594
3595 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3596         .name           = "mmc4",
3597         .class          = &omap44xx_mmc_hwmod_class,
3598         .mpu_irqs       = omap44xx_mmc4_irqs,
3599         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc4_irqs),
3600         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3601         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
3602         .main_clk       = "mmc4_fck",
3603         .prcm           = {
3604                 .omap4 = {
3605                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3606                 },
3607         },
3608         .slaves         = omap44xx_mmc4_slaves,
3609         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3610         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3611 };
3612
3613 /* mmc5 */
3614 static struct omap_hwmod omap44xx_mmc5_hwmod;
3615 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3616         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3617 };
3618
3619 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3620         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3621         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3622 };
3623
3624 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3625         {
3626                 .pa_start       = 0x480d5000,
3627                 .pa_end         = 0x480d53ff,
3628                 .flags          = ADDR_TYPE_RT
3629         },
3630 };
3631
3632 /* l4_per -> mmc5 */
3633 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3634         .master         = &omap44xx_l4_per_hwmod,
3635         .slave          = &omap44xx_mmc5_hwmod,
3636         .clk            = "l4_div_ck",
3637         .addr           = omap44xx_mmc5_addrs,
3638         .addr_cnt       = ARRAY_SIZE(omap44xx_mmc5_addrs),
3639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3640 };
3641
3642 /* mmc5 slave ports */
3643 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3644         &omap44xx_l4_per__mmc5,
3645 };
3646
3647 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3648         .name           = "mmc5",
3649         .class          = &omap44xx_mmc_hwmod_class,
3650         .mpu_irqs       = omap44xx_mmc5_irqs,
3651         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mmc5_irqs),
3652         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3653         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
3654         .main_clk       = "mmc5_fck",
3655         .prcm           = {
3656                 .omap4 = {
3657                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3658                 },
3659         },
3660         .slaves         = omap44xx_mmc5_slaves,
3661         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3663 };
3664
3665 /*
3666  * 'mpu' class
3667  * mpu sub-system
3668  */
3669
3670 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3671         .name   = "mpu",
3672 };
3673
3674 /* mpu */
3675 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3676         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3677         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3678         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3679 };
3680
3681 /* mpu master ports */
3682 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3683         &omap44xx_mpu__l3_main_1,
3684         &omap44xx_mpu__l4_abe,
3685         &omap44xx_mpu__dmm,
3686 };
3687
3688 static struct omap_hwmod omap44xx_mpu_hwmod = {
3689         .name           = "mpu",
3690         .class          = &omap44xx_mpu_hwmod_class,
3691         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
3692         .mpu_irqs       = omap44xx_mpu_irqs,
3693         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
3694         .main_clk       = "dpll_mpu_m2_ck",
3695         .prcm = {
3696                 .omap4 = {
3697                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3698                 },
3699         },
3700         .masters        = omap44xx_mpu_masters,
3701         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3702         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3703 };
3704
3705 /*
3706  * 'smartreflex' class
3707  * smartreflex module (monitor silicon performance and outputs a measure of
3708  * performance error)
3709  */
3710
3711 /* The IP is not compliant to type1 / type2 scheme */
3712 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3713         .sidle_shift    = 24,
3714         .enwkup_shift   = 26,
3715 };
3716
3717 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3718         .sysc_offs      = 0x0038,
3719         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3720         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3721                            SIDLE_SMART_WKUP),
3722         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3723 };
3724
3725 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3726         .name   = "smartreflex",
3727         .sysc   = &omap44xx_smartreflex_sysc,
3728         .rev    = 2,
3729 };
3730
3731 /* smartreflex_core */
3732 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3733 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3734         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3735 };
3736
3737 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3738         {
3739                 .pa_start       = 0x4a0dd000,
3740                 .pa_end         = 0x4a0dd03f,
3741                 .flags          = ADDR_TYPE_RT
3742         },
3743 };
3744
3745 /* l4_cfg -> smartreflex_core */
3746 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3747         .master         = &omap44xx_l4_cfg_hwmod,
3748         .slave          = &omap44xx_smartreflex_core_hwmod,
3749         .clk            = "l4_div_ck",
3750         .addr           = omap44xx_smartreflex_core_addrs,
3751         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
3752         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3753 };
3754
3755 /* smartreflex_core slave ports */
3756 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3757         &omap44xx_l4_cfg__smartreflex_core,
3758 };
3759
3760 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3761         .name           = "smartreflex_core",
3762         .class          = &omap44xx_smartreflex_hwmod_class,
3763         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3764         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
3765         .main_clk       = "smartreflex_core_fck",
3766         .vdd_name       = "core",
3767         .prcm = {
3768                 .omap4 = {
3769                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3770                 },
3771         },
3772         .slaves         = omap44xx_smartreflex_core_slaves,
3773         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3774         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3775 };
3776
3777 /* smartreflex_iva */
3778 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3779 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3780         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3781 };
3782
3783 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3784         {
3785                 .pa_start       = 0x4a0db000,
3786                 .pa_end         = 0x4a0db03f,
3787                 .flags          = ADDR_TYPE_RT
3788         },
3789 };
3790
3791 /* l4_cfg -> smartreflex_iva */
3792 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3793         .master         = &omap44xx_l4_cfg_hwmod,
3794         .slave          = &omap44xx_smartreflex_iva_hwmod,
3795         .clk            = "l4_div_ck",
3796         .addr           = omap44xx_smartreflex_iva_addrs,
3797         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
3798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3799 };
3800
3801 /* smartreflex_iva slave ports */
3802 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3803         &omap44xx_l4_cfg__smartreflex_iva,
3804 };
3805
3806 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3807         .name           = "smartreflex_iva",
3808         .class          = &omap44xx_smartreflex_hwmod_class,
3809         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3810         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
3811         .main_clk       = "smartreflex_iva_fck",
3812         .vdd_name       = "iva",
3813         .prcm = {
3814                 .omap4 = {
3815                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3816                 },
3817         },
3818         .slaves         = omap44xx_smartreflex_iva_slaves,
3819         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3820         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3821 };
3822
3823 /* smartreflex_mpu */
3824 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3825 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3826         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3827 };
3828
3829 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3830         {
3831                 .pa_start       = 0x4a0d9000,
3832                 .pa_end         = 0x4a0d903f,
3833                 .flags          = ADDR_TYPE_RT
3834         },
3835 };
3836
3837 /* l4_cfg -> smartreflex_mpu */
3838 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3839         .master         = &omap44xx_l4_cfg_hwmod,
3840         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3841         .clk            = "l4_div_ck",
3842         .addr           = omap44xx_smartreflex_mpu_addrs,
3843         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
3844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3845 };
3846
3847 /* smartreflex_mpu slave ports */
3848 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3849         &omap44xx_l4_cfg__smartreflex_mpu,
3850 };
3851
3852 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3853         .name           = "smartreflex_mpu",
3854         .class          = &omap44xx_smartreflex_hwmod_class,
3855         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3856         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
3857         .main_clk       = "smartreflex_mpu_fck",
3858         .vdd_name       = "mpu",
3859         .prcm = {
3860                 .omap4 = {
3861                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3862                 },
3863         },
3864         .slaves         = omap44xx_smartreflex_mpu_slaves,
3865         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3866         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3867 };
3868
3869 /*
3870  * 'spinlock' class
3871  * spinlock provides hardware assistance for synchronizing the processes
3872  * running on multiple processors
3873  */
3874
3875 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3876         .rev_offs       = 0x0000,
3877         .sysc_offs      = 0x0010,
3878         .syss_offs      = 0x0014,
3879         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3880                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3881                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3882         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3883                            SIDLE_SMART_WKUP),
3884         .sysc_fields    = &omap_hwmod_sysc_type1,
3885 };
3886
3887 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3888         .name   = "spinlock",
3889         .sysc   = &omap44xx_spinlock_sysc,
3890 };
3891
3892 /* spinlock */
3893 static struct omap_hwmod omap44xx_spinlock_hwmod;
3894 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3895         {
3896                 .pa_start       = 0x4a0f6000,
3897                 .pa_end         = 0x4a0f6fff,
3898                 .flags          = ADDR_TYPE_RT
3899         },
3900 };
3901
3902 /* l4_cfg -> spinlock */
3903 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3904         .master         = &omap44xx_l4_cfg_hwmod,
3905         .slave          = &omap44xx_spinlock_hwmod,
3906         .clk            = "l4_div_ck",
3907         .addr           = omap44xx_spinlock_addrs,
3908         .addr_cnt       = ARRAY_SIZE(omap44xx_spinlock_addrs),
3909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3910 };
3911
3912 /* spinlock slave ports */
3913 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3914         &omap44xx_l4_cfg__spinlock,
3915 };
3916
3917 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3918         .name           = "spinlock",
3919         .class          = &omap44xx_spinlock_hwmod_class,
3920         .prcm = {
3921                 .omap4 = {
3922                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3923                 },
3924         },
3925         .slaves         = omap44xx_spinlock_slaves,
3926         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
3927         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3928 };
3929
3930 /*
3931  * 'timer' class
3932  * general purpose timer module with accurate 1ms tick
3933  * This class contains several variants: ['timer_1ms', 'timer']
3934  */
3935
3936 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3937         .rev_offs       = 0x0000,
3938         .sysc_offs      = 0x0010,
3939         .syss_offs      = 0x0014,
3940         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3941                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3942                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3943                            SYSS_HAS_RESET_STATUS),
3944         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3945         .sysc_fields    = &omap_hwmod_sysc_type1,
3946 };
3947
3948 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3949         .name   = "timer",
3950         .sysc   = &omap44xx_timer_1ms_sysc,
3951 };
3952
3953 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3954         .rev_offs       = 0x0000,
3955         .sysc_offs      = 0x0010,
3956         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3957                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3958         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3959                            SIDLE_SMART_WKUP),
3960         .sysc_fields    = &omap_hwmod_sysc_type2,
3961 };
3962
3963 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3964         .name   = "timer",
3965         .sysc   = &omap44xx_timer_sysc,
3966 };
3967
3968 /* timer1 */
3969 static struct omap_hwmod omap44xx_timer1_hwmod;
3970 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3971         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3972 };
3973
3974 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
3975         {
3976                 .pa_start       = 0x4a318000,
3977                 .pa_end         = 0x4a31807f,
3978                 .flags          = ADDR_TYPE_RT
3979         },
3980 };
3981
3982 /* l4_wkup -> timer1 */
3983 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3984         .master         = &omap44xx_l4_wkup_hwmod,
3985         .slave          = &omap44xx_timer1_hwmod,
3986         .clk            = "l4_wkup_clk_mux_ck",
3987         .addr           = omap44xx_timer1_addrs,
3988         .addr_cnt       = ARRAY_SIZE(omap44xx_timer1_addrs),
3989         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3990 };
3991
3992 /* timer1 slave ports */
3993 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
3994         &omap44xx_l4_wkup__timer1,
3995 };
3996
3997 static struct omap_hwmod omap44xx_timer1_hwmod = {
3998         .name           = "timer1",
3999         .class          = &omap44xx_timer_1ms_hwmod_class,
4000         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4001         .mpu_irqs       = omap44xx_timer1_irqs,
4002         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
4003         .main_clk       = "timer1_fck",
4004         .prcm = {
4005                 .omap4 = {
4006                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4007                 },
4008         },
4009         .slaves         = omap44xx_timer1_slaves,
4010         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4011         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4012 };
4013
4014 /* timer2 */
4015 static struct omap_hwmod omap44xx_timer2_hwmod;
4016 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4017         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4018 };
4019
4020 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4021         {
4022                 .pa_start       = 0x48032000,
4023                 .pa_end         = 0x4803207f,
4024                 .flags          = ADDR_TYPE_RT
4025         },
4026 };
4027
4028 /* l4_per -> timer2 */
4029 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4030         .master         = &omap44xx_l4_per_hwmod,
4031         .slave          = &omap44xx_timer2_hwmod,
4032         .clk            = "l4_div_ck",
4033         .addr           = omap44xx_timer2_addrs,
4034         .addr_cnt       = ARRAY_SIZE(omap44xx_timer2_addrs),
4035         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4036 };
4037
4038 /* timer2 slave ports */
4039 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4040         &omap44xx_l4_per__timer2,
4041 };
4042
4043 static struct omap_hwmod omap44xx_timer2_hwmod = {
4044         .name           = "timer2",
4045         .class          = &omap44xx_timer_1ms_hwmod_class,
4046         .mpu_irqs       = omap44xx_timer2_irqs,
4047         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer2_irqs),
4048         .main_clk       = "timer2_fck",
4049         .prcm = {
4050                 .omap4 = {
4051                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4052                 },
4053         },
4054         .slaves         = omap44xx_timer2_slaves,
4055         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4056         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4057 };
4058
4059 /* timer3 */
4060 static struct omap_hwmod omap44xx_timer3_hwmod;
4061 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4062         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4063 };
4064
4065 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4066         {
4067                 .pa_start       = 0x48034000,
4068                 .pa_end         = 0x4803407f,
4069                 .flags          = ADDR_TYPE_RT
4070         },
4071 };
4072
4073 /* l4_per -> timer3 */
4074 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4075         .master         = &omap44xx_l4_per_hwmod,
4076         .slave          = &omap44xx_timer3_hwmod,
4077         .clk            = "l4_div_ck",
4078         .addr           = omap44xx_timer3_addrs,
4079         .addr_cnt       = ARRAY_SIZE(omap44xx_timer3_addrs),
4080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4081 };
4082
4083 /* timer3 slave ports */
4084 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4085         &omap44xx_l4_per__timer3,
4086 };
4087
4088 static struct omap_hwmod omap44xx_timer3_hwmod = {
4089         .name           = "timer3",
4090         .class          = &omap44xx_timer_hwmod_class,
4091         .mpu_irqs       = omap44xx_timer3_irqs,
4092         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer3_irqs),
4093         .main_clk       = "timer3_fck",
4094         .prcm = {
4095                 .omap4 = {
4096                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4097                 },
4098         },
4099         .slaves         = omap44xx_timer3_slaves,
4100         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4101         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4102 };
4103
4104 /* timer4 */
4105 static struct omap_hwmod omap44xx_timer4_hwmod;
4106 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4107         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4108 };
4109
4110 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4111         {
4112                 .pa_start       = 0x48036000,
4113                 .pa_end         = 0x4803607f,
4114                 .flags          = ADDR_TYPE_RT
4115         },
4116 };
4117
4118 /* l4_per -> timer4 */
4119 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4120         .master         = &omap44xx_l4_per_hwmod,
4121         .slave          = &omap44xx_timer4_hwmod,
4122         .clk            = "l4_div_ck",
4123         .addr           = omap44xx_timer4_addrs,
4124         .addr_cnt       = ARRAY_SIZE(omap44xx_timer4_addrs),
4125         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4126 };
4127
4128 /* timer4 slave ports */
4129 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4130         &omap44xx_l4_per__timer4,
4131 };
4132
4133 static struct omap_hwmod omap44xx_timer4_hwmod = {
4134         .name           = "timer4",
4135         .class          = &omap44xx_timer_hwmod_class,
4136         .mpu_irqs       = omap44xx_timer4_irqs,
4137         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer4_irqs),
4138         .main_clk       = "timer4_fck",
4139         .prcm = {
4140                 .omap4 = {
4141                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4142                 },
4143         },
4144         .slaves         = omap44xx_timer4_slaves,
4145         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4146         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4147 };
4148
4149 /* timer5 */
4150 static struct omap_hwmod omap44xx_timer5_hwmod;
4151 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4152         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4153 };
4154
4155 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4156         {
4157                 .pa_start       = 0x40138000,
4158                 .pa_end         = 0x4013807f,
4159                 .flags          = ADDR_TYPE_RT
4160         },
4161 };
4162
4163 /* l4_abe -> timer5 */
4164 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4165         .master         = &omap44xx_l4_abe_hwmod,
4166         .slave          = &omap44xx_timer5_hwmod,
4167         .clk            = "ocp_abe_iclk",
4168         .addr           = omap44xx_timer5_addrs,
4169         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_addrs),
4170         .user           = OCP_USER_MPU,
4171 };
4172
4173 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4174         {
4175                 .pa_start       = 0x49038000,
4176                 .pa_end         = 0x4903807f,
4177                 .flags          = ADDR_TYPE_RT
4178         },
4179 };
4180
4181 /* l4_abe -> timer5 (dma) */
4182 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4183         .master         = &omap44xx_l4_abe_hwmod,
4184         .slave          = &omap44xx_timer5_hwmod,
4185         .clk            = "ocp_abe_iclk",
4186         .addr           = omap44xx_timer5_dma_addrs,
4187         .addr_cnt       = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
4188         .user           = OCP_USER_SDMA,
4189 };
4190
4191 /* timer5 slave ports */
4192 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4193         &omap44xx_l4_abe__timer5,
4194         &omap44xx_l4_abe__timer5_dma,
4195 };
4196
4197 static struct omap_hwmod omap44xx_timer5_hwmod = {
4198         .name           = "timer5",
4199         .class          = &omap44xx_timer_hwmod_class,
4200         .mpu_irqs       = omap44xx_timer5_irqs,
4201         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer5_irqs),
4202         .main_clk       = "timer5_fck",
4203         .prcm = {
4204                 .omap4 = {
4205                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4206                 },
4207         },
4208         .slaves         = omap44xx_timer5_slaves,
4209         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4210         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4211 };
4212
4213 /* timer6 */
4214 static struct omap_hwmod omap44xx_timer6_hwmod;
4215 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4216         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4217 };
4218
4219 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4220         {
4221                 .pa_start       = 0x4013a000,
4222                 .pa_end         = 0x4013a07f,
4223                 .flags          = ADDR_TYPE_RT
4224         },
4225 };
4226
4227 /* l4_abe -> timer6 */
4228 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4229         .master         = &omap44xx_l4_abe_hwmod,
4230         .slave          = &omap44xx_timer6_hwmod,
4231         .clk            = "ocp_abe_iclk",
4232         .addr           = omap44xx_timer6_addrs,
4233         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_addrs),
4234         .user           = OCP_USER_MPU,
4235 };
4236
4237 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4238         {
4239                 .pa_start       = 0x4903a000,
4240                 .pa_end         = 0x4903a07f,
4241                 .flags          = ADDR_TYPE_RT
4242         },
4243 };
4244
4245 /* l4_abe -> timer6 (dma) */
4246 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4247         .master         = &omap44xx_l4_abe_hwmod,
4248         .slave          = &omap44xx_timer6_hwmod,
4249         .clk            = "ocp_abe_iclk",
4250         .addr           = omap44xx_timer6_dma_addrs,
4251         .addr_cnt       = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
4252         .user           = OCP_USER_SDMA,
4253 };
4254
4255 /* timer6 slave ports */
4256 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4257         &omap44xx_l4_abe__timer6,
4258         &omap44xx_l4_abe__timer6_dma,
4259 };
4260
4261 static struct omap_hwmod omap44xx_timer6_hwmod = {
4262         .name           = "timer6",
4263         .class          = &omap44xx_timer_hwmod_class,
4264         .mpu_irqs       = omap44xx_timer6_irqs,
4265         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer6_irqs),
4266         .main_clk       = "timer6_fck",
4267         .prcm = {
4268                 .omap4 = {
4269                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4270                 },
4271         },
4272         .slaves         = omap44xx_timer6_slaves,
4273         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4274         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4275 };
4276
4277 /* timer7 */
4278 static struct omap_hwmod omap44xx_timer7_hwmod;
4279 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4280         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4281 };
4282
4283 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4284         {
4285                 .pa_start       = 0x4013c000,
4286                 .pa_end         = 0x4013c07f,
4287                 .flags          = ADDR_TYPE_RT
4288         },
4289 };
4290
4291 /* l4_abe -> timer7 */
4292 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4293         .master         = &omap44xx_l4_abe_hwmod,
4294         .slave          = &omap44xx_timer7_hwmod,
4295         .clk            = "ocp_abe_iclk",
4296         .addr           = omap44xx_timer7_addrs,
4297         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_addrs),
4298         .user           = OCP_USER_MPU,
4299 };
4300
4301 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4302         {
4303                 .pa_start       = 0x4903c000,
4304                 .pa_end         = 0x4903c07f,
4305                 .flags          = ADDR_TYPE_RT
4306         },
4307 };
4308
4309 /* l4_abe -> timer7 (dma) */
4310 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4311         .master         = &omap44xx_l4_abe_hwmod,
4312         .slave          = &omap44xx_timer7_hwmod,
4313         .clk            = "ocp_abe_iclk",
4314         .addr           = omap44xx_timer7_dma_addrs,
4315         .addr_cnt       = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
4316         .user           = OCP_USER_SDMA,
4317 };
4318
4319 /* timer7 slave ports */
4320 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4321         &omap44xx_l4_abe__timer7,
4322         &omap44xx_l4_abe__timer7_dma,
4323 };
4324
4325 static struct omap_hwmod omap44xx_timer7_hwmod = {
4326         .name           = "timer7",
4327         .class          = &omap44xx_timer_hwmod_class,
4328         .mpu_irqs       = omap44xx_timer7_irqs,
4329         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer7_irqs),
4330         .main_clk       = "timer7_fck",
4331         .prcm = {
4332                 .omap4 = {
4333                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4334                 },
4335         },
4336         .slaves         = omap44xx_timer7_slaves,
4337         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4338         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4339 };
4340
4341 /* timer8 */
4342 static struct omap_hwmod omap44xx_timer8_hwmod;
4343 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4344         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4345 };
4346
4347 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4348         {
4349                 .pa_start       = 0x4013e000,
4350                 .pa_end         = 0x4013e07f,
4351                 .flags          = ADDR_TYPE_RT
4352         },
4353 };
4354
4355 /* l4_abe -> timer8 */
4356 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4357         .master         = &omap44xx_l4_abe_hwmod,
4358         .slave          = &omap44xx_timer8_hwmod,
4359         .clk            = "ocp_abe_iclk",
4360         .addr           = omap44xx_timer8_addrs,
4361         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_addrs),
4362         .user           = OCP_USER_MPU,
4363 };
4364
4365 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4366         {
4367                 .pa_start       = 0x4903e000,
4368                 .pa_end         = 0x4903e07f,
4369                 .flags          = ADDR_TYPE_RT
4370         },
4371 };
4372
4373 /* l4_abe -> timer8 (dma) */
4374 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4375         .master         = &omap44xx_l4_abe_hwmod,
4376         .slave          = &omap44xx_timer8_hwmod,
4377         .clk            = "ocp_abe_iclk",
4378         .addr           = omap44xx_timer8_dma_addrs,
4379         .addr_cnt       = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
4380         .user           = OCP_USER_SDMA,
4381 };
4382
4383 /* timer8 slave ports */
4384 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4385         &omap44xx_l4_abe__timer8,
4386         &omap44xx_l4_abe__timer8_dma,
4387 };
4388
4389 static struct omap_hwmod omap44xx_timer8_hwmod = {
4390         .name           = "timer8",
4391         .class          = &omap44xx_timer_hwmod_class,
4392         .mpu_irqs       = omap44xx_timer8_irqs,
4393         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer8_irqs),
4394         .main_clk       = "timer8_fck",
4395         .prcm = {
4396                 .omap4 = {
4397                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4398                 },
4399         },
4400         .slaves         = omap44xx_timer8_slaves,
4401         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4402         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4403 };
4404
4405 /* timer9 */
4406 static struct omap_hwmod omap44xx_timer9_hwmod;
4407 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4408         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4409 };
4410
4411 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4412         {
4413                 .pa_start       = 0x4803e000,
4414                 .pa_end         = 0x4803e07f,
4415                 .flags          = ADDR_TYPE_RT
4416         },
4417 };
4418
4419 /* l4_per -> timer9 */
4420 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4421         .master         = &omap44xx_l4_per_hwmod,
4422         .slave          = &omap44xx_timer9_hwmod,
4423         .clk            = "l4_div_ck",
4424         .addr           = omap44xx_timer9_addrs,
4425         .addr_cnt       = ARRAY_SIZE(omap44xx_timer9_addrs),
4426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4427 };
4428
4429 /* timer9 slave ports */
4430 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4431         &omap44xx_l4_per__timer9,
4432 };
4433
4434 static struct omap_hwmod omap44xx_timer9_hwmod = {
4435         .name           = "timer9",
4436         .class          = &omap44xx_timer_hwmod_class,
4437         .mpu_irqs       = omap44xx_timer9_irqs,
4438         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer9_irqs),
4439         .main_clk       = "timer9_fck",
4440         .prcm = {
4441                 .omap4 = {
4442                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4443                 },
4444         },
4445         .slaves         = omap44xx_timer9_slaves,
4446         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4447         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4448 };
4449
4450 /* timer10 */
4451 static struct omap_hwmod omap44xx_timer10_hwmod;
4452 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4453         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4454 };
4455
4456 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4457         {
4458                 .pa_start       = 0x48086000,
4459                 .pa_end         = 0x4808607f,
4460                 .flags          = ADDR_TYPE_RT
4461         },
4462 };
4463
4464 /* l4_per -> timer10 */
4465 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4466         .master         = &omap44xx_l4_per_hwmod,
4467         .slave          = &omap44xx_timer10_hwmod,
4468         .clk            = "l4_div_ck",
4469         .addr           = omap44xx_timer10_addrs,
4470         .addr_cnt       = ARRAY_SIZE(omap44xx_timer10_addrs),
4471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4472 };
4473
4474 /* timer10 slave ports */
4475 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4476         &omap44xx_l4_per__timer10,
4477 };
4478
4479 static struct omap_hwmod omap44xx_timer10_hwmod = {
4480         .name           = "timer10",
4481         .class          = &omap44xx_timer_1ms_hwmod_class,
4482         .mpu_irqs       = omap44xx_timer10_irqs,
4483         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer10_irqs),
4484         .main_clk       = "timer10_fck",
4485         .prcm = {
4486                 .omap4 = {
4487                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4488                 },
4489         },
4490         .slaves         = omap44xx_timer10_slaves,
4491         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4493 };
4494
4495 /* timer11 */
4496 static struct omap_hwmod omap44xx_timer11_hwmod;
4497 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4498         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4499 };
4500
4501 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4502         {
4503                 .pa_start       = 0x48088000,
4504                 .pa_end         = 0x4808807f,
4505                 .flags          = ADDR_TYPE_RT
4506         },
4507 };
4508
4509 /* l4_per -> timer11 */
4510 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4511         .master         = &omap44xx_l4_per_hwmod,
4512         .slave          = &omap44xx_timer11_hwmod,
4513         .clk            = "l4_div_ck",
4514         .addr           = omap44xx_timer11_addrs,
4515         .addr_cnt       = ARRAY_SIZE(omap44xx_timer11_addrs),
4516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4517 };
4518
4519 /* timer11 slave ports */
4520 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4521         &omap44xx_l4_per__timer11,
4522 };
4523
4524 static struct omap_hwmod omap44xx_timer11_hwmod = {
4525         .name           = "timer11",
4526         .class          = &omap44xx_timer_hwmod_class,
4527         .mpu_irqs       = omap44xx_timer11_irqs,
4528         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer11_irqs),
4529         .main_clk       = "timer11_fck",
4530         .prcm = {
4531                 .omap4 = {
4532                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4533                 },
4534         },
4535         .slaves         = omap44xx_timer11_slaves,
4536         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4537         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4538 };
4539
4540 /*
4541  * 'uart' class
4542  * universal asynchronous receiver/transmitter (uart)
4543  */
4544
4545 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4546         .rev_offs       = 0x0050,
4547         .sysc_offs      = 0x0054,
4548         .syss_offs      = 0x0058,
4549         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4550                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4551                            SYSS_HAS_RESET_STATUS),
4552         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4553                            SIDLE_SMART_WKUP),
4554         .sysc_fields    = &omap_hwmod_sysc_type1,
4555 };
4556
4557 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4558         .name   = "uart",
4559         .sysc   = &omap44xx_uart_sysc,
4560 };
4561
4562 /* uart1 */
4563 static struct omap_hwmod omap44xx_uart1_hwmod;
4564 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4565         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4566 };
4567
4568 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4569         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4570         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4571 };
4572
4573 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4574         {
4575                 .pa_start       = 0x4806a000,
4576                 .pa_end         = 0x4806a0ff,
4577                 .flags          = ADDR_TYPE_RT
4578         },
4579 };
4580
4581 /* l4_per -> uart1 */
4582 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4583         .master         = &omap44xx_l4_per_hwmod,
4584         .slave          = &omap44xx_uart1_hwmod,
4585         .clk            = "l4_div_ck",
4586         .addr           = omap44xx_uart1_addrs,
4587         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
4588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4589 };
4590
4591 /* uart1 slave ports */
4592 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4593         &omap44xx_l4_per__uart1,
4594 };
4595
4596 static struct omap_hwmod omap44xx_uart1_hwmod = {
4597         .name           = "uart1",
4598         .class          = &omap44xx_uart_hwmod_class,
4599         .mpu_irqs       = omap44xx_uart1_irqs,
4600         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
4601         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4602         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
4603         .main_clk       = "uart1_fck",
4604         .prcm = {
4605                 .omap4 = {
4606                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4607                 },
4608         },
4609         .slaves         = omap44xx_uart1_slaves,
4610         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4611         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4612 };
4613
4614 /* uart2 */
4615 static struct omap_hwmod omap44xx_uart2_hwmod;
4616 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4617         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4618 };
4619
4620 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4621         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4622         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4623 };
4624
4625 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4626         {
4627                 .pa_start       = 0x4806c000,
4628                 .pa_end         = 0x4806c0ff,
4629                 .flags          = ADDR_TYPE_RT
4630         },
4631 };
4632
4633 /* l4_per -> uart2 */
4634 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4635         .master         = &omap44xx_l4_per_hwmod,
4636         .slave          = &omap44xx_uart2_hwmod,
4637         .clk            = "l4_div_ck",
4638         .addr           = omap44xx_uart2_addrs,
4639         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
4640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4641 };
4642
4643 /* uart2 slave ports */
4644 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4645         &omap44xx_l4_per__uart2,
4646 };
4647
4648 static struct omap_hwmod omap44xx_uart2_hwmod = {
4649         .name           = "uart2",
4650         .class          = &omap44xx_uart_hwmod_class,
4651         .mpu_irqs       = omap44xx_uart2_irqs,
4652         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
4653         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4654         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
4655         .main_clk       = "uart2_fck",
4656         .prcm = {
4657                 .omap4 = {
4658                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4659                 },
4660         },
4661         .slaves         = omap44xx_uart2_slaves,
4662         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4663         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4664 };
4665
4666 /* uart3 */
4667 static struct omap_hwmod omap44xx_uart3_hwmod;
4668 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4669         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4670 };
4671
4672 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4673         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4674         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4675 };
4676
4677 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4678         {
4679                 .pa_start       = 0x48020000,
4680                 .pa_end         = 0x480200ff,
4681                 .flags          = ADDR_TYPE_RT
4682         },
4683 };
4684
4685 /* l4_per -> uart3 */
4686 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4687         .master         = &omap44xx_l4_per_hwmod,
4688         .slave          = &omap44xx_uart3_hwmod,
4689         .clk            = "l4_div_ck",
4690         .addr           = omap44xx_uart3_addrs,
4691         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
4692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4693 };
4694
4695 /* uart3 slave ports */
4696 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4697         &omap44xx_l4_per__uart3,
4698 };
4699
4700 static struct omap_hwmod omap44xx_uart3_hwmod = {
4701         .name           = "uart3",
4702         .class          = &omap44xx_uart_hwmod_class,
4703         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
4704         .mpu_irqs       = omap44xx_uart3_irqs,
4705         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
4706         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4707         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
4708         .main_clk       = "uart3_fck",
4709         .prcm = {
4710                 .omap4 = {
4711                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4712                 },
4713         },
4714         .slaves         = omap44xx_uart3_slaves,
4715         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4716         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4717 };
4718
4719 /* uart4 */
4720 static struct omap_hwmod omap44xx_uart4_hwmod;
4721 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4722         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4723 };
4724
4725 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4726         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4727         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4728 };
4729
4730 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4731         {
4732                 .pa_start       = 0x4806e000,
4733                 .pa_end         = 0x4806e0ff,
4734                 .flags          = ADDR_TYPE_RT
4735         },
4736 };
4737
4738 /* l4_per -> uart4 */
4739 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4740         .master         = &omap44xx_l4_per_hwmod,
4741         .slave          = &omap44xx_uart4_hwmod,
4742         .clk            = "l4_div_ck",
4743         .addr           = omap44xx_uart4_addrs,
4744         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
4745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4746 };
4747
4748 /* uart4 slave ports */
4749 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4750         &omap44xx_l4_per__uart4,
4751 };
4752
4753 static struct omap_hwmod omap44xx_uart4_hwmod = {
4754         .name           = "uart4",
4755         .class          = &omap44xx_uart_hwmod_class,
4756         .mpu_irqs       = omap44xx_uart4_irqs,
4757         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
4758         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4759         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
4760         .main_clk       = "uart4_fck",
4761         .prcm = {
4762                 .omap4 = {
4763                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4764                 },
4765         },
4766         .slaves         = omap44xx_uart4_slaves,
4767         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4768         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4769 };
4770
4771 /*
4772  * 'usb_otg_hs' class
4773  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4774  */
4775
4776 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4777         .rev_offs       = 0x0400,
4778         .sysc_offs      = 0x0404,
4779         .syss_offs      = 0x0408,
4780         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4781                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4782                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4783         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4784                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4785                            MSTANDBY_SMART),
4786         .sysc_fields    = &omap_hwmod_sysc_type1,
4787 };
4788
4789 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4790         .name = "usb_otg_hs",
4791         .sysc = &omap44xx_usb_otg_hs_sysc,
4792 };
4793
4794 /* usb_otg_hs */
4795 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4796         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4797         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4798 };
4799
4800 /* usb_otg_hs master ports */
4801 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4802         &omap44xx_usb_otg_hs__l3_main_2,
4803 };
4804
4805 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4806         {
4807                 .pa_start       = 0x4a0ab000,
4808                 .pa_end         = 0x4a0ab003,
4809                 .flags          = ADDR_TYPE_RT
4810         },
4811 };
4812
4813 /* l4_cfg -> usb_otg_hs */
4814 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4815         .master         = &omap44xx_l4_cfg_hwmod,
4816         .slave          = &omap44xx_usb_otg_hs_hwmod,
4817         .clk            = "l4_div_ck",
4818         .addr           = omap44xx_usb_otg_hs_addrs,
4819         .addr_cnt       = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
4820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4821 };
4822
4823 /* usb_otg_hs slave ports */
4824 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4825         &omap44xx_l4_cfg__usb_otg_hs,
4826 };
4827
4828 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4829         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4830 };
4831
4832 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4833         .name           = "usb_otg_hs",
4834         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4835         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4836         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4837         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
4838         .main_clk       = "usb_otg_hs_ick",
4839         .prcm = {
4840                 .omap4 = {
4841                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4842                 },
4843         },
4844         .opt_clks       = usb_otg_hs_opt_clks,
4845         .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
4846         .slaves         = omap44xx_usb_otg_hs_slaves,
4847         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4848         .masters        = omap44xx_usb_otg_hs_masters,
4849         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4850         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4851 };
4852
4853 /*
4854  * 'wd_timer' class
4855  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4856  * overflow condition
4857  */
4858
4859 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4860         .rev_offs       = 0x0000,
4861         .sysc_offs      = 0x0010,
4862         .syss_offs      = 0x0014,
4863         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4864                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4865         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4866                            SIDLE_SMART_WKUP),
4867         .sysc_fields    = &omap_hwmod_sysc_type1,
4868 };
4869
4870 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4871         .name           = "wd_timer",
4872         .sysc           = &omap44xx_wd_timer_sysc,
4873         .pre_shutdown   = &omap2_wd_timer_disable,
4874 };
4875
4876 /* wd_timer2 */
4877 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4878 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4879         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4880 };
4881
4882 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4883         {
4884                 .pa_start       = 0x4a314000,
4885                 .pa_end         = 0x4a31407f,
4886                 .flags          = ADDR_TYPE_RT
4887         },
4888 };
4889
4890 /* l4_wkup -> wd_timer2 */
4891 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4892         .master         = &omap44xx_l4_wkup_hwmod,
4893         .slave          = &omap44xx_wd_timer2_hwmod,
4894         .clk            = "l4_wkup_clk_mux_ck",
4895         .addr           = omap44xx_wd_timer2_addrs,
4896         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
4897         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4898 };
4899
4900 /* wd_timer2 slave ports */
4901 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4902         &omap44xx_l4_wkup__wd_timer2,
4903 };
4904
4905 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4906         .name           = "wd_timer2",
4907         .class          = &omap44xx_wd_timer_hwmod_class,
4908         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4909         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
4910         .main_clk       = "wd_timer2_fck",
4911         .prcm = {
4912                 .omap4 = {
4913                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4914                 },
4915         },
4916         .slaves         = omap44xx_wd_timer2_slaves,
4917         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4918         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4919 };
4920
4921 /* wd_timer3 */
4922 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4923 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4924         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4925 };
4926
4927 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4928         {
4929                 .pa_start       = 0x40130000,
4930                 .pa_end         = 0x4013007f,
4931                 .flags          = ADDR_TYPE_RT
4932         },
4933 };
4934
4935 /* l4_abe -> wd_timer3 */
4936 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4937         .master         = &omap44xx_l4_abe_hwmod,
4938         .slave          = &omap44xx_wd_timer3_hwmod,
4939         .clk            = "ocp_abe_iclk",
4940         .addr           = omap44xx_wd_timer3_addrs,
4941         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
4942         .user           = OCP_USER_MPU,
4943 };
4944
4945 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4946         {
4947                 .pa_start       = 0x49030000,
4948                 .pa_end         = 0x4903007f,
4949                 .flags          = ADDR_TYPE_RT
4950         },
4951 };
4952
4953 /* l4_abe -> wd_timer3 (dma) */
4954 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4955         .master         = &omap44xx_l4_abe_hwmod,
4956         .slave          = &omap44xx_wd_timer3_hwmod,
4957         .clk            = "ocp_abe_iclk",
4958         .addr           = omap44xx_wd_timer3_dma_addrs,
4959         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
4960         .user           = OCP_USER_SDMA,
4961 };
4962
4963 /* wd_timer3 slave ports */
4964 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
4965         &omap44xx_l4_abe__wd_timer3,
4966         &omap44xx_l4_abe__wd_timer3_dma,
4967 };
4968
4969 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
4970         .name           = "wd_timer3",
4971         .class          = &omap44xx_wd_timer_hwmod_class,
4972         .mpu_irqs       = omap44xx_wd_timer3_irqs,
4973         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
4974         .main_clk       = "wd_timer3_fck",
4975         .prcm = {
4976                 .omap4 = {
4977                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
4978                 },
4979         },
4980         .slaves         = omap44xx_wd_timer3_slaves,
4981         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
4982         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4983 };
4984
4985 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
4986
4987         /* dmm class */
4988         &omap44xx_dmm_hwmod,
4989
4990         /* emif_fw class */
4991         &omap44xx_emif_fw_hwmod,
4992
4993         /* l3 class */
4994         &omap44xx_l3_instr_hwmod,
4995         &omap44xx_l3_main_1_hwmod,
4996         &omap44xx_l3_main_2_hwmod,
4997         &omap44xx_l3_main_3_hwmod,
4998
4999         /* l4 class */
5000         &omap44xx_l4_abe_hwmod,
5001         &omap44xx_l4_cfg_hwmod,
5002         &omap44xx_l4_per_hwmod,
5003         &omap44xx_l4_wkup_hwmod,
5004
5005         /* mpu_bus class */
5006         &omap44xx_mpu_private_hwmod,
5007
5008         /* aess class */
5009 /*      &omap44xx_aess_hwmod, */
5010
5011         /* bandgap class */
5012         &omap44xx_bandgap_hwmod,
5013
5014         /* counter class */
5015 /*      &omap44xx_counter_32k_hwmod, */
5016
5017         /* dma class */
5018         &omap44xx_dma_system_hwmod,
5019
5020         /* dmic class */
5021         &omap44xx_dmic_hwmod,
5022
5023         /* dsp class */
5024         &omap44xx_dsp_hwmod,
5025         &omap44xx_dsp_c0_hwmod,
5026
5027         /* dss class */
5028         &omap44xx_dss_hwmod,
5029         &omap44xx_dss_dispc_hwmod,
5030         &omap44xx_dss_dsi1_hwmod,
5031         &omap44xx_dss_dsi2_hwmod,
5032         &omap44xx_dss_hdmi_hwmod,
5033         &omap44xx_dss_rfbi_hwmod,
5034         &omap44xx_dss_venc_hwmod,
5035
5036         /* gpio class */
5037         &omap44xx_gpio1_hwmod,
5038         &omap44xx_gpio2_hwmod,
5039         &omap44xx_gpio3_hwmod,
5040         &omap44xx_gpio4_hwmod,
5041         &omap44xx_gpio5_hwmod,
5042         &omap44xx_gpio6_hwmod,
5043
5044         /* hsi class */
5045 /*      &omap44xx_hsi_hwmod, */
5046
5047         /* i2c class */
5048         &omap44xx_i2c1_hwmod,
5049         &omap44xx_i2c2_hwmod,
5050         &omap44xx_i2c3_hwmod,
5051         &omap44xx_i2c4_hwmod,
5052
5053         /* ipu class */
5054         &omap44xx_ipu_hwmod,
5055         &omap44xx_ipu_c0_hwmod,
5056         &omap44xx_ipu_c1_hwmod,
5057
5058         /* iss class */
5059 /*      &omap44xx_iss_hwmod, */
5060
5061         /* iva class */
5062         &omap44xx_iva_hwmod,
5063         &omap44xx_iva_seq0_hwmod,
5064         &omap44xx_iva_seq1_hwmod,
5065
5066         /* kbd class */
5067 /*      &omap44xx_kbd_hwmod, */
5068
5069         /* mailbox class */
5070         &omap44xx_mailbox_hwmod,
5071
5072         /* mcbsp class */
5073         &omap44xx_mcbsp1_hwmod,
5074         &omap44xx_mcbsp2_hwmod,
5075         &omap44xx_mcbsp3_hwmod,
5076         &omap44xx_mcbsp4_hwmod,
5077
5078         /* mcpdm class */
5079 /*      &omap44xx_mcpdm_hwmod, */
5080
5081         /* mcspi class */
5082         &omap44xx_mcspi1_hwmod,
5083         &omap44xx_mcspi2_hwmod,
5084         &omap44xx_mcspi3_hwmod,
5085         &omap44xx_mcspi4_hwmod,
5086
5087         /* mmc class */
5088 /*      &omap44xx_mmc1_hwmod, */
5089 /*      &omap44xx_mmc2_hwmod, */
5090 /*      &omap44xx_mmc3_hwmod, */
5091 /*      &omap44xx_mmc4_hwmod, */
5092 /*      &omap44xx_mmc5_hwmod, */
5093
5094         /* mpu class */
5095         &omap44xx_mpu_hwmod,
5096
5097         /* smartreflex class */
5098         &omap44xx_smartreflex_core_hwmod,
5099         &omap44xx_smartreflex_iva_hwmod,
5100         &omap44xx_smartreflex_mpu_hwmod,
5101
5102         /* spinlock class */
5103         &omap44xx_spinlock_hwmod,
5104
5105         /* timer class */
5106         &omap44xx_timer1_hwmod,
5107         &omap44xx_timer2_hwmod,
5108         &omap44xx_timer3_hwmod,
5109         &omap44xx_timer4_hwmod,
5110         &omap44xx_timer5_hwmod,
5111         &omap44xx_timer6_hwmod,
5112         &omap44xx_timer7_hwmod,
5113         &omap44xx_timer8_hwmod,
5114         &omap44xx_timer9_hwmod,
5115         &omap44xx_timer10_hwmod,
5116         &omap44xx_timer11_hwmod,
5117
5118         /* uart class */
5119         &omap44xx_uart1_hwmod,
5120         &omap44xx_uart2_hwmod,
5121         &omap44xx_uart3_hwmod,
5122         &omap44xx_uart4_hwmod,
5123
5124         /* usb_otg_hs class */
5125         &omap44xx_usb_otg_hs_hwmod,
5126
5127         /* wd_timer class */
5128         &omap44xx_wd_timer2_hwmod,
5129         &omap44xx_wd_timer3_hwmod,
5130
5131         NULL,
5132 };
5133
5134 int __init omap44xx_hwmod_init(void)
5135 {
5136         return omap_hwmod_init(omap44xx_hwmods);
5137 }
5138