2 * Copyright (C) 2013 Texas Instruments Incorporated
4 * Hwmod present only in AM43x and those that differ other than register
5 * offsets as compared to AM335x.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/platform_data/gpio-omap.h>
18 #include <linux/platform_data/spi-omap2-mcspi.h>
19 #include "omap_hwmod.h"
20 #include "omap_hwmod_33xx_43xx_common_data.h"
22 #include "omap_hwmod_common_data.h"
26 static struct omap_hwmod am43xx_l4_hs_hwmod = {
28 .class = &am33xx_l4_hwmod_class,
29 .clkdm_name = "l3_clkdm",
30 .flags = HWMOD_INIT_NO_IDLE,
31 .main_clk = "l4hs_gclk",
34 .clkctrl_offs = AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET,
35 .modulemode = MODULEMODE_SWCTRL,
40 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
41 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
44 static struct omap_hwmod am43xx_wkup_m3_hwmod = {
46 .class = &am33xx_wkup_m3_hwmod_class,
47 .clkdm_name = "l4_wkup_aon_clkdm",
48 /* Keep hardreset asserted */
49 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
50 .main_clk = "sys_clkin_ck",
53 .clkctrl_offs = AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
54 .rstctrl_offs = AM43XX_RM_WKUP_RSTCTRL_OFFSET,
55 .rstst_offs = AM43XX_RM_WKUP_RSTST_OFFSET,
56 .modulemode = MODULEMODE_SWCTRL,
59 .rst_lines = am33xx_wkup_m3_resets,
60 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
63 static struct omap_hwmod am43xx_control_hwmod = {
65 .class = &am33xx_control_hwmod_class,
66 .clkdm_name = "l4_wkup_clkdm",
67 .flags = HWMOD_INIT_NO_IDLE,
68 .main_clk = "sys_clkin_ck",
71 .clkctrl_offs = AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
72 .modulemode = MODULEMODE_SWCTRL,
77 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
78 { .role = "dbclk", .clk = "gpio0_dbclk" },
81 static struct omap_hwmod am43xx_gpio0_hwmod = {
83 .class = &am33xx_gpio_hwmod_class,
84 .clkdm_name = "l4_wkup_clkdm",
85 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
86 .main_clk = "sys_clkin_ck",
89 .clkctrl_offs = AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
90 .modulemode = MODULEMODE_SWCTRL,
93 .opt_clks = gpio0_opt_clks,
94 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
95 .dev_attr = &gpio_dev_attr,
98 static struct omap_hwmod_class_sysconfig am43xx_synctimer_sysc = {
101 .sysc_flags = SYSC_HAS_SIDLEMODE,
102 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
103 .sysc_fields = &omap_hwmod_sysc_type1,
106 static struct omap_hwmod_class am43xx_synctimer_hwmod_class = {
108 .sysc = &am43xx_synctimer_sysc,
111 static struct omap_hwmod am43xx_synctimer_hwmod = {
112 .name = "counter_32k",
113 .class = &am43xx_synctimer_hwmod_class,
114 .clkdm_name = "l4_wkup_aon_clkdm",
115 .flags = HWMOD_SWSUP_SIDLE,
116 .main_clk = "synctimer_32kclk",
119 .clkctrl_offs = AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
120 .modulemode = MODULEMODE_SWCTRL,
125 static struct omap_hwmod am43xx_timer8_hwmod = {
127 .class = &am33xx_timer_hwmod_class,
128 .clkdm_name = "l4ls_clkdm",
129 .main_clk = "timer8_fck",
132 .clkctrl_offs = AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET,
133 .modulemode = MODULEMODE_SWCTRL,
138 static struct omap_hwmod am43xx_timer9_hwmod = {
140 .class = &am33xx_timer_hwmod_class,
141 .clkdm_name = "l4ls_clkdm",
142 .main_clk = "timer9_fck",
145 .clkctrl_offs = AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET,
146 .modulemode = MODULEMODE_SWCTRL,
151 static struct omap_hwmod am43xx_timer10_hwmod = {
153 .class = &am33xx_timer_hwmod_class,
154 .clkdm_name = "l4ls_clkdm",
155 .main_clk = "timer10_fck",
158 .clkctrl_offs = AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET,
159 .modulemode = MODULEMODE_SWCTRL,
164 static struct omap_hwmod am43xx_timer11_hwmod = {
166 .class = &am33xx_timer_hwmod_class,
167 .clkdm_name = "l4ls_clkdm",
168 .main_clk = "timer11_fck",
171 .clkctrl_offs = AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET,
172 .modulemode = MODULEMODE_SWCTRL,
177 static struct omap_hwmod am43xx_epwmss3_hwmod = {
179 .class = &am33xx_epwmss_hwmod_class,
180 .clkdm_name = "l4ls_clkdm",
181 .main_clk = "l4ls_gclk",
184 .clkctrl_offs = AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET,
185 .modulemode = MODULEMODE_SWCTRL,
190 static struct omap_hwmod am43xx_ehrpwm3_hwmod = {
192 .class = &am33xx_ehrpwm_hwmod_class,
193 .clkdm_name = "l4ls_clkdm",
194 .main_clk = "l4ls_gclk",
197 static struct omap_hwmod am43xx_epwmss4_hwmod = {
199 .class = &am33xx_epwmss_hwmod_class,
200 .clkdm_name = "l4ls_clkdm",
201 .main_clk = "l4ls_gclk",
204 .clkctrl_offs = AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET,
205 .modulemode = MODULEMODE_SWCTRL,
210 static struct omap_hwmod am43xx_ehrpwm4_hwmod = {
212 .class = &am33xx_ehrpwm_hwmod_class,
213 .clkdm_name = "l4ls_clkdm",
214 .main_clk = "l4ls_gclk",
217 static struct omap_hwmod am43xx_epwmss5_hwmod = {
219 .class = &am33xx_epwmss_hwmod_class,
220 .clkdm_name = "l4ls_clkdm",
221 .main_clk = "l4ls_gclk",
224 .clkctrl_offs = AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET,
225 .modulemode = MODULEMODE_SWCTRL,
230 static struct omap_hwmod am43xx_ehrpwm5_hwmod = {
232 .class = &am33xx_ehrpwm_hwmod_class,
233 .clkdm_name = "l4ls_clkdm",
234 .main_clk = "l4ls_gclk",
237 static struct omap_hwmod am43xx_spi2_hwmod = {
239 .class = &am33xx_spi_hwmod_class,
240 .clkdm_name = "l4ls_clkdm",
241 .main_clk = "dpll_per_m2_div4_ck",
244 .clkctrl_offs = AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET,
245 .modulemode = MODULEMODE_SWCTRL,
248 .dev_attr = &mcspi_attrib,
251 static struct omap_hwmod am43xx_spi3_hwmod = {
253 .class = &am33xx_spi_hwmod_class,
254 .clkdm_name = "l4ls_clkdm",
255 .main_clk = "dpll_per_m2_div4_ck",
258 .clkctrl_offs = AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET,
259 .modulemode = MODULEMODE_SWCTRL,
262 .dev_attr = &mcspi_attrib,
265 static struct omap_hwmod am43xx_spi4_hwmod = {
267 .class = &am33xx_spi_hwmod_class,
268 .clkdm_name = "l4ls_clkdm",
269 .main_clk = "dpll_per_m2_div4_ck",
272 .clkctrl_offs = AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET,
273 .modulemode = MODULEMODE_SWCTRL,
276 .dev_attr = &mcspi_attrib,
279 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
280 { .role = "dbclk", .clk = "gpio4_dbclk" },
283 static struct omap_hwmod am43xx_gpio4_hwmod = {
285 .class = &am33xx_gpio_hwmod_class,
286 .clkdm_name = "l4ls_clkdm",
287 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
288 .main_clk = "l4ls_gclk",
291 .clkctrl_offs = AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET,
292 .modulemode = MODULEMODE_SWCTRL,
295 .opt_clks = gpio4_opt_clks,
296 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
297 .dev_attr = &gpio_dev_attr,
300 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
301 { .role = "dbclk", .clk = "gpio5_dbclk" },
304 static struct omap_hwmod am43xx_gpio5_hwmod = {
306 .class = &am33xx_gpio_hwmod_class,
307 .clkdm_name = "l4ls_clkdm",
308 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
309 .main_clk = "l4ls_gclk",
312 .clkctrl_offs = AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET,
313 .modulemode = MODULEMODE_SWCTRL,
316 .opt_clks = gpio5_opt_clks,
317 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
318 .dev_attr = &gpio_dev_attr,
321 static struct omap_hwmod_class am43xx_ocp2scp_hwmod_class = {
325 static struct omap_hwmod am43xx_ocp2scp0_hwmod = {
327 .class = &am43xx_ocp2scp_hwmod_class,
328 .clkdm_name = "l4ls_clkdm",
329 .main_clk = "l4ls_gclk",
332 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET,
333 .modulemode = MODULEMODE_SWCTRL,
338 static struct omap_hwmod am43xx_ocp2scp1_hwmod = {
340 .class = &am43xx_ocp2scp_hwmod_class,
341 .clkdm_name = "l4ls_clkdm",
342 .main_clk = "l4ls_gclk",
345 .clkctrl_offs = AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET,
346 .modulemode = MODULEMODE_SWCTRL,
351 static struct omap_hwmod_class_sysconfig am43xx_usb_otg_ss_sysc = {
354 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
356 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
357 SIDLE_SMART_WKUP | MSTANDBY_FORCE |
358 MSTANDBY_NO | MSTANDBY_SMART |
359 MSTANDBY_SMART_WKUP),
360 .sysc_fields = &omap_hwmod_sysc_type2,
363 static struct omap_hwmod_class am43xx_usb_otg_ss_hwmod_class = {
364 .name = "usb_otg_ss",
365 .sysc = &am43xx_usb_otg_ss_sysc,
368 static struct omap_hwmod am43xx_usb_otg_ss0_hwmod = {
369 .name = "usb_otg_ss0",
370 .class = &am43xx_usb_otg_ss_hwmod_class,
371 .clkdm_name = "l3s_clkdm",
372 .main_clk = "l3s_gclk",
375 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET,
376 .modulemode = MODULEMODE_SWCTRL,
381 static struct omap_hwmod am43xx_usb_otg_ss1_hwmod = {
382 .name = "usb_otg_ss1",
383 .class = &am43xx_usb_otg_ss_hwmod_class,
384 .clkdm_name = "l3s_clkdm",
385 .main_clk = "l3s_gclk",
388 .clkctrl_offs = AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET,
389 .modulemode = MODULEMODE_SWCTRL,
394 static struct omap_hwmod_class_sysconfig am43xx_qspi_sysc = {
396 .sysc_flags = SYSC_HAS_SIDLEMODE,
397 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
399 .sysc_fields = &omap_hwmod_sysc_type2,
402 static struct omap_hwmod_class am43xx_qspi_hwmod_class = {
404 .sysc = &am43xx_qspi_sysc,
407 static struct omap_hwmod am43xx_qspi_hwmod = {
409 .class = &am43xx_qspi_hwmod_class,
410 .clkdm_name = "l3s_clkdm",
411 .main_clk = "l3s_gclk",
414 .clkctrl_offs = AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET,
415 .modulemode = MODULEMODE_SWCTRL,
422 static struct omap_hwmod am43xx_dss_core_hwmod = {
424 .class = &omap2_dss_hwmod_class,
425 .clkdm_name = "dss_clkdm",
426 .main_clk = "disp_clk",
429 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
430 .modulemode = MODULEMODE_SWCTRL,
437 struct omap_dss_dispc_dev_attr am43xx_dss_dispc_dev_attr = {
439 .has_framedonetv_irq = 0
442 static struct omap_hwmod_class_sysconfig am43xx_dispc_sysc = {
446 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
447 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
448 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_MIDLEMODE),
449 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
450 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
451 .sysc_fields = &omap_hwmod_sysc_type1,
454 static struct omap_hwmod_class am43xx_dispc_hwmod_class = {
456 .sysc = &am43xx_dispc_sysc,
459 static struct omap_hwmod am43xx_dss_dispc_hwmod = {
461 .class = &am43xx_dispc_hwmod_class,
462 .clkdm_name = "dss_clkdm",
463 .main_clk = "disp_clk",
466 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
469 .dev_attr = &am43xx_dss_dispc_dev_attr,
474 static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
476 .class = &omap2_rfbi_hwmod_class,
477 .clkdm_name = "dss_clkdm",
478 .main_clk = "disp_clk",
481 .clkctrl_offs = AM43XX_CM_PER_DSS_CLKCTRL_OFFSET,
487 static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
488 .master = &am33xx_l3_main_hwmod,
489 .slave = &am43xx_l4_hs_hwmod,
491 .user = OCP_USER_MPU | OCP_USER_SDMA,
494 static struct omap_hwmod_ocp_if am43xx_wkup_m3__l4_wkup = {
495 .master = &am43xx_wkup_m3_hwmod,
496 .slave = &am33xx_l4_wkup_hwmod,
497 .clk = "sys_clkin_ck",
498 .user = OCP_USER_MPU | OCP_USER_SDMA,
501 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wkup_m3 = {
502 .master = &am33xx_l4_wkup_hwmod,
503 .slave = &am43xx_wkup_m3_hwmod,
504 .clk = "sys_clkin_ck",
505 .user = OCP_USER_MPU | OCP_USER_SDMA,
508 static struct omap_hwmod_ocp_if am43xx_l3_main__pruss = {
509 .master = &am33xx_l3_main_hwmod,
510 .slave = &am33xx_pruss_hwmod,
511 .clk = "dpll_core_m4_ck",
512 .user = OCP_USER_MPU,
515 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex0 = {
516 .master = &am33xx_l4_wkup_hwmod,
517 .slave = &am33xx_smartreflex0_hwmod,
518 .clk = "sys_clkin_ck",
519 .user = OCP_USER_MPU,
522 static struct omap_hwmod_ocp_if am43xx_l4_wkup__smartreflex1 = {
523 .master = &am33xx_l4_wkup_hwmod,
524 .slave = &am33xx_smartreflex1_hwmod,
525 .clk = "sys_clkin_ck",
526 .user = OCP_USER_MPU,
529 static struct omap_hwmod_ocp_if am43xx_l4_wkup__control = {
530 .master = &am33xx_l4_wkup_hwmod,
531 .slave = &am43xx_control_hwmod,
532 .clk = "sys_clkin_ck",
533 .user = OCP_USER_MPU,
536 static struct omap_hwmod_ocp_if am43xx_l4_wkup__i2c1 = {
537 .master = &am33xx_l4_wkup_hwmod,
538 .slave = &am33xx_i2c1_hwmod,
539 .clk = "sys_clkin_ck",
540 .user = OCP_USER_MPU,
543 static struct omap_hwmod_ocp_if am43xx_l4_wkup__gpio0 = {
544 .master = &am33xx_l4_wkup_hwmod,
545 .slave = &am43xx_gpio0_hwmod,
546 .clk = "sys_clkin_ck",
547 .user = OCP_USER_MPU | OCP_USER_SDMA,
550 static struct omap_hwmod_ocp_if am43xx_l4_hs__cpgmac0 = {
551 .master = &am43xx_l4_hs_hwmod,
552 .slave = &am33xx_cpgmac0_hwmod,
553 .clk = "cpsw_125mhz_gclk",
554 .user = OCP_USER_MPU,
557 static struct omap_hwmod_ocp_if am43xx_l4_wkup__timer1 = {
558 .master = &am33xx_l4_wkup_hwmod,
559 .slave = &am33xx_timer1_hwmod,
560 .clk = "sys_clkin_ck",
561 .user = OCP_USER_MPU,
564 static struct omap_hwmod_ocp_if am43xx_l4_wkup__uart1 = {
565 .master = &am33xx_l4_wkup_hwmod,
566 .slave = &am33xx_uart1_hwmod,
567 .clk = "sys_clkin_ck",
568 .user = OCP_USER_MPU,
571 static struct omap_hwmod_ocp_if am43xx_l4_wkup__wd_timer1 = {
572 .master = &am33xx_l4_wkup_hwmod,
573 .slave = &am33xx_wd_timer1_hwmod,
574 .clk = "sys_clkin_ck",
575 .user = OCP_USER_MPU,
578 static struct omap_hwmod_ocp_if am33xx_l4_wkup__synctimer = {
579 .master = &am33xx_l4_wkup_hwmod,
580 .slave = &am43xx_synctimer_hwmod,
581 .clk = "sys_clkin_ck",
582 .user = OCP_USER_MPU,
585 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer8 = {
586 .master = &am33xx_l4_ls_hwmod,
587 .slave = &am43xx_timer8_hwmod,
589 .user = OCP_USER_MPU,
592 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer9 = {
593 .master = &am33xx_l4_ls_hwmod,
594 .slave = &am43xx_timer9_hwmod,
596 .user = OCP_USER_MPU,
599 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer10 = {
600 .master = &am33xx_l4_ls_hwmod,
601 .slave = &am43xx_timer10_hwmod,
603 .user = OCP_USER_MPU,
606 static struct omap_hwmod_ocp_if am43xx_l4_ls__timer11 = {
607 .master = &am33xx_l4_ls_hwmod,
608 .slave = &am43xx_timer11_hwmod,
610 .user = OCP_USER_MPU,
613 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss3 = {
614 .master = &am33xx_l4_ls_hwmod,
615 .slave = &am43xx_epwmss3_hwmod,
617 .user = OCP_USER_MPU,
620 static struct omap_hwmod_ocp_if am43xx_epwmss3__ehrpwm3 = {
621 .master = &am43xx_epwmss3_hwmod,
622 .slave = &am43xx_ehrpwm3_hwmod,
624 .user = OCP_USER_MPU,
627 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss4 = {
628 .master = &am33xx_l4_ls_hwmod,
629 .slave = &am43xx_epwmss4_hwmod,
631 .user = OCP_USER_MPU,
634 static struct omap_hwmod_ocp_if am43xx_epwmss4__ehrpwm4 = {
635 .master = &am43xx_epwmss4_hwmod,
636 .slave = &am43xx_ehrpwm4_hwmod,
638 .user = OCP_USER_MPU,
641 static struct omap_hwmod_ocp_if am43xx_l4_ls__epwmss5 = {
642 .master = &am33xx_l4_ls_hwmod,
643 .slave = &am43xx_epwmss5_hwmod,
645 .user = OCP_USER_MPU,
648 static struct omap_hwmod_ocp_if am43xx_epwmss5__ehrpwm5 = {
649 .master = &am43xx_epwmss5_hwmod,
650 .slave = &am43xx_ehrpwm5_hwmod,
652 .user = OCP_USER_MPU,
655 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi2 = {
656 .master = &am33xx_l4_ls_hwmod,
657 .slave = &am43xx_spi2_hwmod,
659 .user = OCP_USER_MPU,
662 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi3 = {
663 .master = &am33xx_l4_ls_hwmod,
664 .slave = &am43xx_spi3_hwmod,
666 .user = OCP_USER_MPU,
669 static struct omap_hwmod_ocp_if am43xx_l4_ls__mcspi4 = {
670 .master = &am33xx_l4_ls_hwmod,
671 .slave = &am43xx_spi4_hwmod,
673 .user = OCP_USER_MPU,
676 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio4 = {
677 .master = &am33xx_l4_ls_hwmod,
678 .slave = &am43xx_gpio4_hwmod,
680 .user = OCP_USER_MPU | OCP_USER_SDMA,
683 static struct omap_hwmod_ocp_if am43xx_l4_ls__gpio5 = {
684 .master = &am33xx_l4_ls_hwmod,
685 .slave = &am43xx_gpio5_hwmod,
687 .user = OCP_USER_MPU | OCP_USER_SDMA,
690 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp0 = {
691 .master = &am33xx_l4_ls_hwmod,
692 .slave = &am43xx_ocp2scp0_hwmod,
694 .user = OCP_USER_MPU,
697 static struct omap_hwmod_ocp_if am43xx_l4_ls__ocp2scp1 = {
698 .master = &am33xx_l4_ls_hwmod,
699 .slave = &am43xx_ocp2scp1_hwmod,
701 .user = OCP_USER_MPU,
704 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss0 = {
705 .master = &am33xx_l3_s_hwmod,
706 .slave = &am43xx_usb_otg_ss0_hwmod,
708 .user = OCP_USER_MPU | OCP_USER_SDMA,
711 static struct omap_hwmod_ocp_if am43xx_l3_s__usbotgss1 = {
712 .master = &am33xx_l3_s_hwmod,
713 .slave = &am43xx_usb_otg_ss1_hwmod,
715 .user = OCP_USER_MPU | OCP_USER_SDMA,
718 static struct omap_hwmod_ocp_if am43xx_l3_s__qspi = {
719 .master = &am33xx_l3_s_hwmod,
720 .slave = &am43xx_qspi_hwmod,
722 .user = OCP_USER_MPU | OCP_USER_SDMA,
725 static struct omap_hwmod_ocp_if am43xx_dss__l3_main = {
726 .master = &am43xx_dss_core_hwmod,
727 .slave = &am33xx_l3_main_hwmod,
729 .user = OCP_USER_MPU | OCP_USER_SDMA,
732 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss = {
733 .master = &am33xx_l4_ls_hwmod,
734 .slave = &am43xx_dss_core_hwmod,
736 .user = OCP_USER_MPU | OCP_USER_SDMA,
739 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_dispc = {
740 .master = &am33xx_l4_ls_hwmod,
741 .slave = &am43xx_dss_dispc_hwmod,
743 .user = OCP_USER_MPU | OCP_USER_SDMA,
746 static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
747 .master = &am33xx_l4_ls_hwmod,
748 .slave = &am43xx_dss_rfbi_hwmod,
750 .user = OCP_USER_MPU | OCP_USER_SDMA,
753 static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
754 &am33xx_l4_wkup__synctimer,
755 &am43xx_l4_ls__timer8,
756 &am43xx_l4_ls__timer9,
757 &am43xx_l4_ls__timer10,
758 &am43xx_l4_ls__timer11,
759 &am43xx_l4_ls__epwmss3,
760 &am43xx_epwmss3__ehrpwm3,
761 &am43xx_l4_ls__epwmss4,
762 &am43xx_epwmss4__ehrpwm4,
763 &am43xx_l4_ls__epwmss5,
764 &am43xx_epwmss5__ehrpwm5,
765 &am43xx_l4_ls__mcspi2,
766 &am43xx_l4_ls__mcspi3,
767 &am43xx_l4_ls__mcspi4,
768 &am43xx_l4_ls__gpio4,
769 &am43xx_l4_ls__gpio5,
770 &am43xx_l3_main__pruss,
771 &am33xx_mpu__l3_main,
774 &am33xx_l3_s__l4_wkup,
775 &am43xx_l3_main__l4_hs,
776 &am33xx_l3_main__l3_s,
777 &am33xx_l3_main__l3_instr,
778 &am33xx_l3_main__gfx,
779 &am33xx_l3_s__l3_main,
780 &am33xx_pruss__l3_main,
781 &am43xx_wkup_m3__l4_wkup,
782 &am33xx_gfx__l3_main,
783 &am43xx_l4_wkup__wkup_m3,
784 &am43xx_l4_wkup__control,
785 &am43xx_l4_wkup__smartreflex0,
786 &am43xx_l4_wkup__smartreflex1,
787 &am43xx_l4_wkup__uart1,
788 &am43xx_l4_wkup__timer1,
789 &am43xx_l4_wkup__i2c1,
790 &am43xx_l4_wkup__gpio0,
791 &am43xx_l4_wkup__wd_timer1,
793 &am33xx_l4_per__dcan0,
794 &am33xx_l4_per__dcan1,
795 &am33xx_l4_per__gpio1,
796 &am33xx_l4_per__gpio2,
797 &am33xx_l4_per__gpio3,
798 &am33xx_l4_per__i2c2,
799 &am33xx_l4_per__i2c3,
800 &am33xx_l4_per__mailbox,
801 &am33xx_l4_ls__mcasp0,
802 &am33xx_l4_ls__mcasp1,
806 &am33xx_l4_ls__timer2,
807 &am33xx_l4_ls__timer3,
808 &am33xx_l4_ls__timer4,
809 &am33xx_l4_ls__timer5,
810 &am33xx_l4_ls__timer6,
811 &am33xx_l4_ls__timer7,
812 &am33xx_l3_main__tpcc,
813 &am33xx_l4_ls__uart2,
814 &am33xx_l4_ls__uart3,
815 &am33xx_l4_ls__uart4,
816 &am33xx_l4_ls__uart5,
817 &am33xx_l4_ls__uart6,
818 &am33xx_l4_ls__spinlock,
820 &am33xx_l4_ls__epwmss0,
821 &am33xx_epwmss0__ecap0,
822 &am33xx_epwmss0__eqep0,
823 &am33xx_epwmss0__ehrpwm0,
824 &am33xx_l4_ls__epwmss1,
825 &am33xx_epwmss1__ecap1,
826 &am33xx_epwmss1__eqep1,
827 &am33xx_epwmss1__ehrpwm1,
828 &am33xx_l4_ls__epwmss2,
829 &am33xx_epwmss2__ecap2,
830 &am33xx_epwmss2__eqep2,
831 &am33xx_epwmss2__ehrpwm2,
833 &am33xx_l4_ls__mcspi0,
834 &am33xx_l4_ls__mcspi1,
835 &am33xx_l3_main__tptc0,
836 &am33xx_l3_main__tptc1,
837 &am33xx_l3_main__tptc2,
838 &am33xx_l3_main__ocmc,
839 &am43xx_l4_hs__cpgmac0,
840 &am33xx_cpgmac0__mdio,
841 &am33xx_l3_main__sha0,
842 &am33xx_l3_main__aes0,
843 &am43xx_l4_ls__ocp2scp0,
844 &am43xx_l4_ls__ocp2scp1,
845 &am43xx_l3_s__usbotgss0,
846 &am43xx_l3_s__usbotgss1,
847 &am43xx_dss__l3_main,
849 &am43xx_l4_ls__dss_dispc,
850 &am43xx_l4_ls__dss_rfbi,
854 int __init am43xx_hwmod_init(void)
856 omap_hwmod_am43xx_reg();
858 return omap_hwmod_register_links(am43xx_hwmod_ocp_ifs);