arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106         { .irq = -1 }
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115         { }
 116 };
 117
 118 /* MPU -> L3 interface */
 119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 120         .master   = &omap3xxx_mpu_hwmod,
 121         .slave    = &omap3xxx_l3_main_hwmod,
 122         .addr     = omap3xxx_l3_main_addrs,
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 194         .master         = &omap3xxx_l4_core_hwmod,
 195         .slave          = &omap3xxx_mmc1_hwmod,
 196         .clk            = "mmchs1_ick",
 197         .addr           = omap2430_mmc1_addr_space,
 198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 199         .flags          = OMAP_FIREWALL_L4
 200 };
 201
 202 /* L4 CORE -> MMC2 interface */
 203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 204         .master         = &omap3xxx_l4_core_hwmod,
 205         .slave          = &omap3xxx_mmc2_hwmod,
 206         .clk            = "mmchs2_ick",
 207         .addr           = omap2430_mmc2_addr_space,
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209         .flags          = OMAP_FIREWALL_L4
 210 };
 211
 212 /* L4 CORE -> MMC3 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 214         {
 215                 .pa_start       = 0x480ad000,
 216                 .pa_end         = 0x480ad1ff,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219         { }
 220 };
 221
 222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 223         .master         = &omap3xxx_l4_core_hwmod,
 224         .slave          = &omap3xxx_mmc3_hwmod,
 225         .clk            = "mmchs3_ick",
 226         .addr           = omap3xxx_mmc3_addr_space,
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228         .flags          = OMAP_FIREWALL_L4
 229 };
 230
 231 /* L4 CORE -> UART1 interface */
 232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 233         {
 234                 .pa_start       = OMAP3_UART1_BASE,
 235                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 236                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 237         },
 238         { }
 239 };
 240
 241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 242         .master         = &omap3xxx_l4_core_hwmod,
 243         .slave          = &omap3xxx_uart1_hwmod,
 244         .clk            = "uart1_ick",
 245         .addr           = omap3xxx_uart1_addr_space,
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* L4 CORE -> UART2 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART2_BASE,
 253                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256         { }
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart2_hwmod,
 262         .clk            = "uart2_ick",
 263         .addr           = omap3xxx_uart2_addr_space,
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 PER -> UART3 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART3_BASE,
 271                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274         { }
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 278         .master         = &omap3xxx_l4_per_hwmod,
 279         .slave          = &omap3xxx_uart3_hwmod,
 280         .clk            = "uart3_ick",
 281         .addr           = omap3xxx_uart3_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART4 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART4_BASE,
 289                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292         { }
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart4_hwmod,
 298         .clk            = "uart4_ick",
 299         .addr           = omap3xxx_uart4_addr_space,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 CORE -> I2C1 interface */
 304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 305         .master         = &omap3xxx_l4_core_hwmod,
 306         .slave          = &omap3xxx_i2c1_hwmod,
 307         .clk            = "i2c1_ick",
 308         .addr           = omap2_i2c1_addr_space,
 309         .fw = {
 310                 .omap2 = {
 311                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 312                         .l4_prot_group = 7,
 313                         .flags  = OMAP_FIREWALL_L4,
 314                 }
 315         },
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* L4 CORE -> I2C2 interface */
 320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 321         .master         = &omap3xxx_l4_core_hwmod,
 322         .slave          = &omap3xxx_i2c2_hwmod,
 323         .clk            = "i2c2_ick",
 324         .addr           = omap2_i2c2_addr_space,
 325         .fw = {
 326                 .omap2 = {
 327                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 328                         .l4_prot_group = 7,
 329                         .flags = OMAP_FIREWALL_L4,
 330                 }
 331         },
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* L4 CORE -> I2C3 interface */
 336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 337         {
 338                 .pa_start       = 0x48060000,
 339                 .pa_end         = 0x48060000 + SZ_128 - 1,
 340                 .flags          = ADDR_TYPE_RT,
 341         },
 342         { }
 343 };
 344
 345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 346         .master         = &omap3xxx_l4_core_hwmod,
 347         .slave          = &omap3xxx_i2c3_hwmod,
 348         .clk            = "i2c3_ick",
 349         .addr           = omap3xxx_i2c3_addr_space,
 350         .fw = {
 351                 .omap2 = {
 352                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 353                         .l4_prot_group = 7,
 354                         .flags = OMAP_FIREWALL_L4,
 355                 }
 356         },
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* L4 CORE -> SR1 interface */
 361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 362         {
 363                 .pa_start       = OMAP34XX_SR1_BASE,
 364                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 365                 .flags          = ADDR_TYPE_RT,
 366         },
 367         { }
 368 };
 369
 370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 371         .master         = &omap3xxx_l4_core_hwmod,
 372         .slave          = &omap34xx_sr1_hwmod,
 373         .clk            = "sr_l4_ick",
 374         .addr           = omap3_sr1_addr_space,
 375         .user           = OCP_USER_MPU,
 376 };
 377
 378 /* L4 CORE -> SR1 interface */
 379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 380         {
 381                 .pa_start       = OMAP34XX_SR2_BASE,
 382                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 383                 .flags          = ADDR_TYPE_RT,
 384         },
 385         { }
 386 };
 387
 388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 389         .master         = &omap3xxx_l4_core_hwmod,
 390         .slave          = &omap34xx_sr2_hwmod,
 391         .clk            = "sr_l4_ick",
 392         .addr           = omap3_sr2_addr_space,
 393         .user           = OCP_USER_MPU,
 394 };
 395
 396 /*
 397 * usbhsotg interface data
 398 */
 399
 400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 401         {
 402                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 403                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 404                 .flags          = ADDR_TYPE_RT
 405         },
 406         { }
 407 };
 408
 409 /* l4_core -> usbhsotg  */
 410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 411         .master         = &omap3xxx_l4_core_hwmod,
 412         .slave          = &omap3xxx_usbhsotg_hwmod,
 413         .clk            = "l4_ick",
 414         .addr           = omap3xxx_usbhsotg_addrs,
 415         .user           = OCP_USER_MPU,
 416 };
 417
 418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 419         &omap3xxx_usbhsotg__l3,
 420 };
 421
 422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 423         &omap3xxx_l4_core__usbhsotg,
 424 };
 425
 426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 427         {
 428                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 429                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 430                 .flags          = ADDR_TYPE_RT
 431         },
 432         { }
 433 };
 434
 435 /* l4_core -> usbhsotg  */
 436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 437         .master         = &omap3xxx_l4_core_hwmod,
 438         .slave          = &am35xx_usbhsotg_hwmod,
 439         .clk            = "l4_ick",
 440         .addr           = am35xx_usbhsotg_addrs,
 441         .user           = OCP_USER_MPU,
 442 };
 443
 444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 445         &am35xx_usbhsotg__l3,
 446 };
 447
 448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 449         &am35xx_l4_core__usbhsotg,
 450 };
 451 /* Slave interfaces on the L4_CORE interconnect */
 452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 453         &omap3xxx_l3_main__l4_core,
 454 };
 455
 456 /* L4 CORE */
 457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 458         .name           = "l4_core",
 459         .class          = &l4_hwmod_class,
 460         .slaves         = omap3xxx_l4_core_slaves,
 461         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 463         .flags          = HWMOD_NO_IDLEST,
 464 };
 465
 466 /* Slave interfaces on the L4_PER interconnect */
 467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 468         &omap3xxx_l3_main__l4_per,
 469 };
 470
 471 /* L4 PER */
 472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 473         .name           = "l4_per",
 474         .class          = &l4_hwmod_class,
 475         .slaves         = omap3xxx_l4_per_slaves,
 476         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 477         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 478         .flags          = HWMOD_NO_IDLEST,
 479 };
 480
 481 /* Slave interfaces on the L4_WKUP interconnect */
 482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 483         &omap3xxx_l4_core__l4_wkup,
 484 };
 485
 486 /* L4 WKUP */
 487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 488         .name           = "l4_wkup",
 489         .class          = &l4_hwmod_class,
 490         .slaves         = omap3xxx_l4_wkup_slaves,
 491         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 493         .flags          = HWMOD_NO_IDLEST,
 494 };
 495
 496 /* Master interfaces on the MPU device */
 497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 498         &omap3xxx_mpu__l3_main,
 499 };
 500
 501 /* MPU */
 502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 503         .name           = "mpu",
 504         .class          = &mpu_hwmod_class,
 505         .main_clk       = "arm_fck",
 506         .masters        = omap3xxx_mpu_masters,
 507         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 509 };
 510
 511 /*
 512  * IVA2_2 interface data
 513  */
 514
 515 /* IVA2 <- L3 interface */
 516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 517         .master         = &omap3xxx_l3_main_hwmod,
 518         .slave          = &omap3xxx_iva_hwmod,
 519         .clk            = "iva2_ck",
 520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 521 };
 522
 523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 524         &omap3xxx_l3__iva,
 525 };
 526
 527 /*
 528  * IVA2 (IVA2)
 529  */
 530
 531 static struct omap_hwmod omap3xxx_iva_hwmod = {
 532         .name           = "iva",
 533         .class          = &iva_hwmod_class,
 534         .masters        = omap3xxx_iva_masters,
 535         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 536         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 537 };
 538
 539 /* timer class */
 540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 541         .rev_offs       = 0x0000,
 542         .sysc_offs      = 0x0010,
 543         .syss_offs      = 0x0014,
 544         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 545                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 546                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 548         .sysc_fields    = &omap_hwmod_sysc_type1,
 549 };
 550
 551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 552         .name = "timer",
 553         .sysc = &omap3xxx_timer_1ms_sysc,
 554         .rev = OMAP_TIMER_IP_VERSION_1,
 555 };
 556
 557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 558         .rev_offs       = 0x0000,
 559         .sysc_offs      = 0x0010,
 560         .syss_offs      = 0x0014,
 561         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 562                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 564         .sysc_fields    = &omap_hwmod_sysc_type1,
 565 };
 566
 567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 568         .name = "timer",
 569         .sysc = &omap3xxx_timer_sysc,
 570         .rev =  OMAP_TIMER_IP_VERSION_1,
 571 };
 572
 573 /* timer1 */
 574 static struct omap_hwmod omap3xxx_timer1_hwmod;
 575
 576 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 577         {
 578                 .pa_start       = 0x48318000,
 579                 .pa_end         = 0x48318000 + SZ_1K - 1,
 580                 .flags          = ADDR_TYPE_RT
 581         },
 582         { }
 583 };
 584
 585 /* l4_wkup -> timer1 */
 586 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 587         .master         = &omap3xxx_l4_wkup_hwmod,
 588         .slave          = &omap3xxx_timer1_hwmod,
 589         .clk            = "gpt1_ick",
 590         .addr           = omap3xxx_timer1_addrs,
 591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 592 };
 593
 594 /* timer1 slave port */
 595 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 596         &omap3xxx_l4_wkup__timer1,
 597 };
 598
 599 /* timer1 hwmod */
 600 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 601         .name           = "timer1",
 602         .mpu_irqs       = omap2_timer1_mpu_irqs,
 603         .main_clk       = "gpt1_fck",
 604         .prcm           = {
 605                 .omap2 = {
 606                         .prcm_reg_id = 1,
 607                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 608                         .module_offs = WKUP_MOD,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 611                 },
 612         },
 613         .slaves         = omap3xxx_timer1_slaves,
 614         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 615         .class          = &omap3xxx_timer_1ms_hwmod_class,
 616         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 617 };
 618
 619 /* timer2 */
 620 static struct omap_hwmod omap3xxx_timer2_hwmod;
 621
 622 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 623         {
 624                 .pa_start       = 0x49032000,
 625                 .pa_end         = 0x49032000 + SZ_1K - 1,
 626                 .flags          = ADDR_TYPE_RT
 627         },
 628         { }
 629 };
 630
 631 /* l4_per -> timer2 */
 632 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 633         .master         = &omap3xxx_l4_per_hwmod,
 634         .slave          = &omap3xxx_timer2_hwmod,
 635         .clk            = "gpt2_ick",
 636         .addr           = omap3xxx_timer2_addrs,
 637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 638 };
 639
 640 /* timer2 slave port */
 641 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 642         &omap3xxx_l4_per__timer2,
 643 };
 644
 645 /* timer2 hwmod */
 646 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 647         .name           = "timer2",
 648         .mpu_irqs       = omap2_timer2_mpu_irqs,
 649         .main_clk       = "gpt2_fck",
 650         .prcm           = {
 651                 .omap2 = {
 652                         .prcm_reg_id = 1,
 653                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 654                         .module_offs = OMAP3430_PER_MOD,
 655                         .idlest_reg_id = 1,
 656                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 657                 },
 658         },
 659         .slaves         = omap3xxx_timer2_slaves,
 660         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 661         .class          = &omap3xxx_timer_1ms_hwmod_class,
 662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 663 };
 664
 665 /* timer3 */
 666 static struct omap_hwmod omap3xxx_timer3_hwmod;
 667
 668 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 669         {
 670                 .pa_start       = 0x49034000,
 671                 .pa_end         = 0x49034000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674         { }
 675 };
 676
 677 /* l4_per -> timer3 */
 678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 679         .master         = &omap3xxx_l4_per_hwmod,
 680         .slave          = &omap3xxx_timer3_hwmod,
 681         .clk            = "gpt3_ick",
 682         .addr           = omap3xxx_timer3_addrs,
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer3 slave port */
 687 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 688         &omap3xxx_l4_per__timer3,
 689 };
 690
 691 /* timer3 hwmod */
 692 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 693         .name           = "timer3",
 694         .mpu_irqs       = omap2_timer3_mpu_irqs,
 695         .main_clk       = "gpt3_fck",
 696         .prcm           = {
 697                 .omap2 = {
 698                         .prcm_reg_id = 1,
 699                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 700                         .module_offs = OMAP3430_PER_MOD,
 701                         .idlest_reg_id = 1,
 702                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 703                 },
 704         },
 705         .slaves         = omap3xxx_timer3_slaves,
 706         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 707         .class          = &omap3xxx_timer_hwmod_class,
 708         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 709 };
 710
 711 /* timer4 */
 712 static struct omap_hwmod omap3xxx_timer4_hwmod;
 713
 714 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 715         {
 716                 .pa_start       = 0x49036000,
 717                 .pa_end         = 0x49036000 + SZ_1K - 1,
 718                 .flags          = ADDR_TYPE_RT
 719         },
 720         { }
 721 };
 722
 723 /* l4_per -> timer4 */
 724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 725         .master         = &omap3xxx_l4_per_hwmod,
 726         .slave          = &omap3xxx_timer4_hwmod,
 727         .clk            = "gpt4_ick",
 728         .addr           = omap3xxx_timer4_addrs,
 729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 730 };
 731
 732 /* timer4 slave port */
 733 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 734         &omap3xxx_l4_per__timer4,
 735 };
 736
 737 /* timer4 hwmod */
 738 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 739         .name           = "timer4",
 740         .mpu_irqs       = omap2_timer4_mpu_irqs,
 741         .main_clk       = "gpt4_fck",
 742         .prcm           = {
 743                 .omap2 = {
 744                         .prcm_reg_id = 1,
 745                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 746                         .module_offs = OMAP3430_PER_MOD,
 747                         .idlest_reg_id = 1,
 748                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 749                 },
 750         },
 751         .slaves         = omap3xxx_timer4_slaves,
 752         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 753         .class          = &omap3xxx_timer_hwmod_class,
 754         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 755 };
 756
 757 /* timer5 */
 758 static struct omap_hwmod omap3xxx_timer5_hwmod;
 759
 760 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 761         {
 762                 .pa_start       = 0x49038000,
 763                 .pa_end         = 0x49038000 + SZ_1K - 1,
 764                 .flags          = ADDR_TYPE_RT
 765         },
 766         { }
 767 };
 768
 769 /* l4_per -> timer5 */
 770 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 771         .master         = &omap3xxx_l4_per_hwmod,
 772         .slave          = &omap3xxx_timer5_hwmod,
 773         .clk            = "gpt5_ick",
 774         .addr           = omap3xxx_timer5_addrs,
 775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 776 };
 777
 778 /* timer5 slave port */
 779 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 780         &omap3xxx_l4_per__timer5,
 781 };
 782
 783 /* timer5 hwmod */
 784 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 785         .name           = "timer5",
 786         .mpu_irqs       = omap2_timer5_mpu_irqs,
 787         .main_clk       = "gpt5_fck",
 788         .prcm           = {
 789                 .omap2 = {
 790                         .prcm_reg_id = 1,
 791                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 792                         .module_offs = OMAP3430_PER_MOD,
 793                         .idlest_reg_id = 1,
 794                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 795                 },
 796         },
 797         .slaves         = omap3xxx_timer5_slaves,
 798         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 799         .class          = &omap3xxx_timer_hwmod_class,
 800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 801 };
 802
 803 /* timer6 */
 804 static struct omap_hwmod omap3xxx_timer6_hwmod;
 805
 806 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 807         {
 808                 .pa_start       = 0x4903A000,
 809                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 810                 .flags          = ADDR_TYPE_RT
 811         },
 812         { }
 813 };
 814
 815 /* l4_per -> timer6 */
 816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 817         .master         = &omap3xxx_l4_per_hwmod,
 818         .slave          = &omap3xxx_timer6_hwmod,
 819         .clk            = "gpt6_ick",
 820         .addr           = omap3xxx_timer6_addrs,
 821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 822 };
 823
 824 /* timer6 slave port */
 825 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 826         &omap3xxx_l4_per__timer6,
 827 };
 828
 829 /* timer6 hwmod */
 830 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 831         .name           = "timer6",
 832         .mpu_irqs       = omap2_timer6_mpu_irqs,
 833         .main_clk       = "gpt6_fck",
 834         .prcm           = {
 835                 .omap2 = {
 836                         .prcm_reg_id = 1,
 837                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 838                         .module_offs = OMAP3430_PER_MOD,
 839                         .idlest_reg_id = 1,
 840                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 841                 },
 842         },
 843         .slaves         = omap3xxx_timer6_slaves,
 844         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 845         .class          = &omap3xxx_timer_hwmod_class,
 846         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 847 };
 848
 849 /* timer7 */
 850 static struct omap_hwmod omap3xxx_timer7_hwmod;
 851
 852 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 853         {
 854                 .pa_start       = 0x4903C000,
 855                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 856                 .flags          = ADDR_TYPE_RT
 857         },
 858         { }
 859 };
 860
 861 /* l4_per -> timer7 */
 862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 863         .master         = &omap3xxx_l4_per_hwmod,
 864         .slave          = &omap3xxx_timer7_hwmod,
 865         .clk            = "gpt7_ick",
 866         .addr           = omap3xxx_timer7_addrs,
 867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 868 };
 869
 870 /* timer7 slave port */
 871 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 872         &omap3xxx_l4_per__timer7,
 873 };
 874
 875 /* timer7 hwmod */
 876 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 877         .name           = "timer7",
 878         .mpu_irqs       = omap2_timer7_mpu_irqs,
 879         .main_clk       = "gpt7_fck",
 880         .prcm           = {
 881                 .omap2 = {
 882                         .prcm_reg_id = 1,
 883                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 884                         .module_offs = OMAP3430_PER_MOD,
 885                         .idlest_reg_id = 1,
 886                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 887                 },
 888         },
 889         .slaves         = omap3xxx_timer7_slaves,
 890         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 891         .class          = &omap3xxx_timer_hwmod_class,
 892         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 893 };
 894
 895 /* timer8 */
 896 static struct omap_hwmod omap3xxx_timer8_hwmod;
 897
 898 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 899         {
 900                 .pa_start       = 0x4903E000,
 901                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 902                 .flags          = ADDR_TYPE_RT
 903         },
 904         { }
 905 };
 906
 907 /* l4_per -> timer8 */
 908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 909         .master         = &omap3xxx_l4_per_hwmod,
 910         .slave          = &omap3xxx_timer8_hwmod,
 911         .clk            = "gpt8_ick",
 912         .addr           = omap3xxx_timer8_addrs,
 913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 914 };
 915
 916 /* timer8 slave port */
 917 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 918         &omap3xxx_l4_per__timer8,
 919 };
 920
 921 /* timer8 hwmod */
 922 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 923         .name           = "timer8",
 924         .mpu_irqs       = omap2_timer8_mpu_irqs,
 925         .main_clk       = "gpt8_fck",
 926         .prcm           = {
 927                 .omap2 = {
 928                         .prcm_reg_id = 1,
 929                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 930                         .module_offs = OMAP3430_PER_MOD,
 931                         .idlest_reg_id = 1,
 932                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 933                 },
 934         },
 935         .slaves         = omap3xxx_timer8_slaves,
 936         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 937         .class          = &omap3xxx_timer_hwmod_class,
 938         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 939 };
 940
 941 /* timer9 */
 942 static struct omap_hwmod omap3xxx_timer9_hwmod;
 943
 944 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 945         {
 946                 .pa_start       = 0x49040000,
 947                 .pa_end         = 0x49040000 + SZ_1K - 1,
 948                 .flags          = ADDR_TYPE_RT
 949         },
 950         { }
 951 };
 952
 953 /* l4_per -> timer9 */
 954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 955         .master         = &omap3xxx_l4_per_hwmod,
 956         .slave          = &omap3xxx_timer9_hwmod,
 957         .clk            = "gpt9_ick",
 958         .addr           = omap3xxx_timer9_addrs,
 959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 960 };
 961
 962 /* timer9 slave port */
 963 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 964         &omap3xxx_l4_per__timer9,
 965 };
 966
 967 /* timer9 hwmod */
 968 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 969         .name           = "timer9",
 970         .mpu_irqs       = omap2_timer9_mpu_irqs,
 971         .main_clk       = "gpt9_fck",
 972         .prcm           = {
 973                 .omap2 = {
 974                         .prcm_reg_id = 1,
 975                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 976                         .module_offs = OMAP3430_PER_MOD,
 977                         .idlest_reg_id = 1,
 978                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 979                 },
 980         },
 981         .slaves         = omap3xxx_timer9_slaves,
 982         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 983         .class          = &omap3xxx_timer_hwmod_class,
 984         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 985 };
 986
 987 /* timer10 */
 988 static struct omap_hwmod omap3xxx_timer10_hwmod;
 989
 990 /* l4_core -> timer10 */
 991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
 992         .master         = &omap3xxx_l4_core_hwmod,
 993         .slave          = &omap3xxx_timer10_hwmod,
 994         .clk            = "gpt10_ick",
 995         .addr           = omap2_timer10_addrs,
 996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 997 };
 998
 999 /* timer10 slave port */
1000 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1001         &omap3xxx_l4_core__timer10,
1002 };
1003
1004 /* timer10 hwmod */
1005 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1006         .name           = "timer10",
1007         .mpu_irqs       = omap2_timer10_mpu_irqs,
1008         .main_clk       = "gpt10_fck",
1009         .prcm           = {
1010                 .omap2 = {
1011                         .prcm_reg_id = 1,
1012                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1013                         .module_offs = CORE_MOD,
1014                         .idlest_reg_id = 1,
1015                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1016                 },
1017         },
1018         .slaves         = omap3xxx_timer10_slaves,
1019         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1020         .class          = &omap3xxx_timer_1ms_hwmod_class,
1021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1022 };
1023
1024 /* timer11 */
1025 static struct omap_hwmod omap3xxx_timer11_hwmod;
1026
1027 /* l4_core -> timer11 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1029         .master         = &omap3xxx_l4_core_hwmod,
1030         .slave          = &omap3xxx_timer11_hwmod,
1031         .clk            = "gpt11_ick",
1032         .addr           = omap2_timer11_addrs,
1033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer11 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1038         &omap3xxx_l4_core__timer11,
1039 };
1040
1041 /* timer11 hwmod */
1042 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1043         .name           = "timer11",
1044         .mpu_irqs       = omap2_timer11_mpu_irqs,
1045         .main_clk       = "gpt11_fck",
1046         .prcm           = {
1047                 .omap2 = {
1048                         .prcm_reg_id = 1,
1049                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1050                         .module_offs = CORE_MOD,
1051                         .idlest_reg_id = 1,
1052                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1053                 },
1054         },
1055         .slaves         = omap3xxx_timer11_slaves,
1056         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1057         .class          = &omap3xxx_timer_hwmod_class,
1058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1059 };
1060
1061 /* timer12*/
1062 static struct omap_hwmod omap3xxx_timer12_hwmod;
1063 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1064         { .irq = 95, },
1065         { .irq = -1 }
1066 };
1067
1068 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1069         {
1070                 .pa_start       = 0x48304000,
1071                 .pa_end         = 0x48304000 + SZ_1K - 1,
1072                 .flags          = ADDR_TYPE_RT
1073         },
1074         { }
1075 };
1076
1077 /* l4_core -> timer12 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1079         .master         = &omap3xxx_l4_core_hwmod,
1080         .slave          = &omap3xxx_timer12_hwmod,
1081         .clk            = "gpt12_ick",
1082         .addr           = omap3xxx_timer12_addrs,
1083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1084 };
1085
1086 /* timer12 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1088         &omap3xxx_l4_core__timer12,
1089 };
1090
1091 /* timer12 hwmod */
1092 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1093         .name           = "timer12",
1094         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1095         .main_clk       = "gpt12_fck",
1096         .prcm           = {
1097                 .omap2 = {
1098                         .prcm_reg_id = 1,
1099                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1100                         .module_offs = WKUP_MOD,
1101                         .idlest_reg_id = 1,
1102                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1103                 },
1104         },
1105         .slaves         = omap3xxx_timer12_slaves,
1106         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1107         .class          = &omap3xxx_timer_hwmod_class,
1108         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1109 };
1110
1111 /* l4_wkup -> wd_timer2 */
1112 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1113         {
1114                 .pa_start       = 0x48314000,
1115                 .pa_end         = 0x4831407f,
1116                 .flags          = ADDR_TYPE_RT
1117         },
1118         { }
1119 };
1120
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1122         .master         = &omap3xxx_l4_wkup_hwmod,
1123         .slave          = &omap3xxx_wd_timer2_hwmod,
1124         .clk            = "wdt2_ick",
1125         .addr           = omap3xxx_wd_timer2_addrs,
1126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1127 };
1128
1129 /*
1130  * 'wd_timer' class
1131  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1132  * overflow condition
1133  */
1134
1135 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1136         .rev_offs       = 0x0000,
1137         .sysc_offs      = 0x0010,
1138         .syss_offs      = 0x0014,
1139         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1140                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1141                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142                            SYSS_HAS_RESET_STATUS),
1143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144         .sysc_fields    = &omap_hwmod_sysc_type1,
1145 };
1146
1147 /* I2C common */
1148 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1149         .rev_offs       = 0x00,
1150         .sysc_offs      = 0x20,
1151         .syss_offs      = 0x10,
1152         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1153                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1154                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1155         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1156         .sysc_fields    = &omap_hwmod_sysc_type1,
1157 };
1158
1159 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1160         .name           = "wd_timer",
1161         .sysc           = &omap3xxx_wd_timer_sysc,
1162         .pre_shutdown   = &omap2_wd_timer_disable
1163 };
1164
1165 /* wd_timer2 */
1166 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1167         &omap3xxx_l4_wkup__wd_timer2,
1168 };
1169
1170 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1171         .name           = "wd_timer2",
1172         .class          = &omap3xxx_wd_timer_hwmod_class,
1173         .main_clk       = "wdt2_fck",
1174         .prcm           = {
1175                 .omap2 = {
1176                         .prcm_reg_id = 1,
1177                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1178                         .module_offs = WKUP_MOD,
1179                         .idlest_reg_id = 1,
1180                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1181                 },
1182         },
1183         .slaves         = omap3xxx_wd_timer2_slaves,
1184         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1185         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1186         /*
1187          * XXX: Use software supervised mode, HW supervised smartidle seems to
1188          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1189          */
1190         .flags          = HWMOD_SWSUP_SIDLE,
1191 };
1192
1193 /* UART common */
1194
1195 static struct omap_hwmod_class_sysconfig uart_sysc = {
1196         .rev_offs       = 0x50,
1197         .sysc_offs      = 0x54,
1198         .syss_offs      = 0x58,
1199         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1200                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1201                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1202         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1203         .sysc_fields    = &omap_hwmod_sysc_type1,
1204 };
1205
1206 static struct omap_hwmod_class uart_class = {
1207         .name = "uart",
1208         .sysc = &uart_sysc,
1209 };
1210
1211 /* UART1 */
1212
1213 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1214         &omap3_l4_core__uart1,
1215 };
1216
1217 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1218         .name           = "uart1",
1219         .mpu_irqs       = omap2_uart1_mpu_irqs,
1220         .sdma_reqs      = omap2_uart1_sdma_reqs,
1221         .main_clk       = "uart1_fck",
1222         .prcm           = {
1223                 .omap2 = {
1224                         .module_offs = CORE_MOD,
1225                         .prcm_reg_id = 1,
1226                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1227                         .idlest_reg_id = 1,
1228                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1229                 },
1230         },
1231         .slaves         = omap3xxx_uart1_slaves,
1232         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1233         .class          = &uart_class,
1234         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1235 };
1236
1237 /* UART2 */
1238
1239 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1240         &omap3_l4_core__uart2,
1241 };
1242
1243 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1244         .name           = "uart2",
1245         .mpu_irqs       = omap2_uart2_mpu_irqs,
1246         .sdma_reqs      = omap2_uart2_sdma_reqs,
1247         .main_clk       = "uart2_fck",
1248         .prcm           = {
1249                 .omap2 = {
1250                         .module_offs = CORE_MOD,
1251                         .prcm_reg_id = 1,
1252                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1253                         .idlest_reg_id = 1,
1254                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1255                 },
1256         },
1257         .slaves         = omap3xxx_uart2_slaves,
1258         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1259         .class          = &uart_class,
1260         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1261 };
1262
1263 /* UART3 */
1264
1265 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1266         &omap3_l4_per__uart3,
1267 };
1268
1269 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1270         .name           = "uart3",
1271         .mpu_irqs       = omap2_uart3_mpu_irqs,
1272         .sdma_reqs      = omap2_uart3_sdma_reqs,
1273         .main_clk       = "uart3_fck",
1274         .prcm           = {
1275                 .omap2 = {
1276                         .module_offs = OMAP3430_PER_MOD,
1277                         .prcm_reg_id = 1,
1278                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1279                         .idlest_reg_id = 1,
1280                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1281                 },
1282         },
1283         .slaves         = omap3xxx_uart3_slaves,
1284         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1285         .class          = &uart_class,
1286         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1287 };
1288
1289 /* UART4 */
1290
1291 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1292         { .irq = INT_36XX_UART4_IRQ, },
1293         { .irq = -1 }
1294 };
1295
1296 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1297         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1298         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1299         { .dma_req = -1 }
1300 };
1301
1302 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1303         &omap3_l4_per__uart4,
1304 };
1305
1306 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1307         .name           = "uart4",
1308         .mpu_irqs       = uart4_mpu_irqs,
1309         .sdma_reqs      = uart4_sdma_reqs,
1310         .main_clk       = "uart4_fck",
1311         .prcm           = {
1312                 .omap2 = {
1313                         .module_offs = OMAP3430_PER_MOD,
1314                         .prcm_reg_id = 1,
1315                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1316                         .idlest_reg_id = 1,
1317                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1318                 },
1319         },
1320         .slaves         = omap3xxx_uart4_slaves,
1321         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1322         .class          = &uart_class,
1323         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1324 };
1325
1326 static struct omap_hwmod_class i2c_class = {
1327         .name = "i2c",
1328         .sysc = &i2c_sysc,
1329 };
1330
1331 /*
1332  * 'dss' class
1333  * display sub-system
1334  */
1335
1336 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1337         .rev_offs       = 0x0000,
1338         .sysc_offs      = 0x0010,
1339         .syss_offs      = 0x0014,
1340         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1341         .sysc_fields    = &omap_hwmod_sysc_type1,
1342 };
1343
1344 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1345         .name = "dss",
1346         .sysc = &omap3xxx_dss_sysc,
1347 };
1348
1349 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1350         { .name = "dispc", .dma_req = 5 },
1351         { .name = "dsi1", .dma_req = 74 },
1352         { .dma_req = -1 }
1353 };
1354
1355 /* dss */
1356 /* dss master ports */
1357 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1358         &omap3xxx_dss__l3,
1359 };
1360
1361 /* l4_core -> dss */
1362 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1363         .master         = &omap3xxx_l4_core_hwmod,
1364         .slave          = &omap3430es1_dss_core_hwmod,
1365         .clk            = "dss_ick",
1366         .addr           = omap2_dss_addrs,
1367         .fw = {
1368                 .omap2 = {
1369                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1370                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1371                         .flags  = OMAP_FIREWALL_L4,
1372                 }
1373         },
1374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1375 };
1376
1377 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1378         .master         = &omap3xxx_l4_core_hwmod,
1379         .slave          = &omap3xxx_dss_core_hwmod,
1380         .clk            = "dss_ick",
1381         .addr           = omap2_dss_addrs,
1382         .fw = {
1383                 .omap2 = {
1384                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1385                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1386                         .flags  = OMAP_FIREWALL_L4,
1387                 }
1388         },
1389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1390 };
1391
1392 /* dss slave ports */
1393 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1394         &omap3430es1_l4_core__dss,
1395 };
1396
1397 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1398         &omap3xxx_l4_core__dss,
1399 };
1400
1401 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1402         { .role = "tv_clk", .clk = "dss_tv_fck" },
1403         { .role = "video_clk", .clk = "dss_96m_fck" },
1404         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1405 };
1406
1407 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1408         .name           = "dss_core",
1409         .class          = &omap3xxx_dss_hwmod_class,
1410         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1411         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1412         .prcm           = {
1413                 .omap2 = {
1414                         .prcm_reg_id = 1,
1415                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1416                         .module_offs = OMAP3430_DSS_MOD,
1417                         .idlest_reg_id = 1,
1418                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1419                 },
1420         },
1421         .opt_clks       = dss_opt_clks,
1422         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1423         .slaves         = omap3430es1_dss_slaves,
1424         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1425         .masters        = omap3xxx_dss_masters,
1426         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1427         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1428         .flags          = HWMOD_NO_IDLEST,
1429 };
1430
1431 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1432         .name           = "dss_core",
1433         .class          = &omap3xxx_dss_hwmod_class,
1434         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1435         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1436         .prcm           = {
1437                 .omap2 = {
1438                         .prcm_reg_id = 1,
1439                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1440                         .module_offs = OMAP3430_DSS_MOD,
1441                         .idlest_reg_id = 1,
1442                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1443                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1444                 },
1445         },
1446         .opt_clks       = dss_opt_clks,
1447         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1448         .slaves         = omap3xxx_dss_slaves,
1449         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1450         .masters        = omap3xxx_dss_masters,
1451         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1452         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1453                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1454 };
1455
1456 /*
1457  * 'dispc' class
1458  * display controller
1459  */
1460
1461 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1462         .rev_offs       = 0x0000,
1463         .sysc_offs      = 0x0010,
1464         .syss_offs      = 0x0014,
1465         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1466                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1467                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1468         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1469                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1470         .sysc_fields    = &omap_hwmod_sysc_type1,
1471 };
1472
1473 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1474         .name = "dispc",
1475         .sysc = &omap3xxx_dispc_sysc,
1476 };
1477
1478 /* l4_core -> dss_dispc */
1479 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1480         .master         = &omap3xxx_l4_core_hwmod,
1481         .slave          = &omap3xxx_dss_dispc_hwmod,
1482         .clk            = "dss_ick",
1483         .addr           = omap2_dss_dispc_addrs,
1484         .fw = {
1485                 .omap2 = {
1486                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1487                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1488                         .flags  = OMAP_FIREWALL_L4,
1489                 }
1490         },
1491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1492 };
1493
1494 /* dss_dispc slave ports */
1495 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1496         &omap3xxx_l4_core__dss_dispc,
1497 };
1498
1499 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1500         .name           = "dss_dispc",
1501         .class          = &omap3xxx_dispc_hwmod_class,
1502         .mpu_irqs       = omap2_dispc_irqs,
1503         .main_clk       = "dss1_alwon_fck",
1504         .prcm           = {
1505                 .omap2 = {
1506                         .prcm_reg_id = 1,
1507                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1508                         .module_offs = OMAP3430_DSS_MOD,
1509                 },
1510         },
1511         .slaves         = omap3xxx_dss_dispc_slaves,
1512         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1513         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1514                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1515                                 CHIP_GE_OMAP3630ES1_1),
1516         .flags          = HWMOD_NO_IDLEST,
1517 };
1518
1519 /*
1520  * 'dsi' class
1521  * display serial interface controller
1522  */
1523
1524 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1525         .name = "dsi",
1526 };
1527
1528 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1529         { .irq = 25 },
1530         { .irq = -1 }
1531 };
1532
1533 /* dss_dsi1 */
1534 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1535         {
1536                 .pa_start       = 0x4804FC00,
1537                 .pa_end         = 0x4804FFFF,
1538                 .flags          = ADDR_TYPE_RT
1539         },
1540         { }
1541 };
1542
1543 /* l4_core -> dss_dsi1 */
1544 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1545         .master         = &omap3xxx_l4_core_hwmod,
1546         .slave          = &omap3xxx_dss_dsi1_hwmod,
1547         .addr           = omap3xxx_dss_dsi1_addrs,
1548         .fw = {
1549                 .omap2 = {
1550                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1551                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1552                         .flags  = OMAP_FIREWALL_L4,
1553                 }
1554         },
1555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1556 };
1557
1558 /* dss_dsi1 slave ports */
1559 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1560         &omap3xxx_l4_core__dss_dsi1,
1561 };
1562
1563 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1564         .name           = "dss_dsi1",
1565         .class          = &omap3xxx_dsi_hwmod_class,
1566         .mpu_irqs       = omap3xxx_dsi1_irqs,
1567         .main_clk       = "dss1_alwon_fck",
1568         .prcm           = {
1569                 .omap2 = {
1570                         .prcm_reg_id = 1,
1571                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1572                         .module_offs = OMAP3430_DSS_MOD,
1573                 },
1574         },
1575         .slaves         = omap3xxx_dss_dsi1_slaves,
1576         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1577         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1578                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1579                                 CHIP_GE_OMAP3630ES1_1),
1580         .flags          = HWMOD_NO_IDLEST,
1581 };
1582
1583 /*
1584  * 'rfbi' class
1585  * remote frame buffer interface
1586  */
1587
1588 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1589         .rev_offs       = 0x0000,
1590         .sysc_offs      = 0x0010,
1591         .syss_offs      = 0x0014,
1592         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1593                            SYSC_HAS_AUTOIDLE),
1594         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1595         .sysc_fields    = &omap_hwmod_sysc_type1,
1596 };
1597
1598 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1599         .name = "rfbi",
1600         .sysc = &omap3xxx_rfbi_sysc,
1601 };
1602
1603 /* l4_core -> dss_rfbi */
1604 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1605         .master         = &omap3xxx_l4_core_hwmod,
1606         .slave          = &omap3xxx_dss_rfbi_hwmod,
1607         .clk            = "dss_ick",
1608         .addr           = omap2_dss_rfbi_addrs,
1609         .fw = {
1610                 .omap2 = {
1611                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1612                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1613                         .flags  = OMAP_FIREWALL_L4,
1614                 }
1615         },
1616         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1617 };
1618
1619 /* dss_rfbi slave ports */
1620 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1621         &omap3xxx_l4_core__dss_rfbi,
1622 };
1623
1624 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1625         .name           = "dss_rfbi",
1626         .class          = &omap3xxx_rfbi_hwmod_class,
1627         .main_clk       = "dss1_alwon_fck",
1628         .prcm           = {
1629                 .omap2 = {
1630                         .prcm_reg_id = 1,
1631                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1632                         .module_offs = OMAP3430_DSS_MOD,
1633                 },
1634         },
1635         .slaves         = omap3xxx_dss_rfbi_slaves,
1636         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1637         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1638                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1639                                 CHIP_GE_OMAP3630ES1_1),
1640         .flags          = HWMOD_NO_IDLEST,
1641 };
1642
1643 /*
1644  * 'venc' class
1645  * video encoder
1646  */
1647
1648 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1649         .name = "venc",
1650 };
1651
1652 /* l4_core -> dss_venc */
1653 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1654         .master         = &omap3xxx_l4_core_hwmod,
1655         .slave          = &omap3xxx_dss_venc_hwmod,
1656         .clk            = "dss_tv_fck",
1657         .addr           = omap2_dss_venc_addrs,
1658         .fw = {
1659                 .omap2 = {
1660                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1661                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1662                         .flags  = OMAP_FIREWALL_L4,
1663                 }
1664         },
1665         .flags          = OCPIF_SWSUP_IDLE,
1666         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1667 };
1668
1669 /* dss_venc slave ports */
1670 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1671         &omap3xxx_l4_core__dss_venc,
1672 };
1673
1674 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1675         .name           = "dss_venc",
1676         .class          = &omap3xxx_venc_hwmod_class,
1677         .main_clk       = "dss1_alwon_fck",
1678         .prcm           = {
1679                 .omap2 = {
1680                         .prcm_reg_id = 1,
1681                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1682                         .module_offs = OMAP3430_DSS_MOD,
1683                 },
1684         },
1685         .slaves         = omap3xxx_dss_venc_slaves,
1686         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1687         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1688                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1689                                 CHIP_GE_OMAP3630ES1_1),
1690         .flags          = HWMOD_NO_IDLEST,
1691 };
1692
1693 /* I2C1 */
1694
1695 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1696         .fifo_depth     = 8, /* bytes */
1697 };
1698
1699 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1700         &omap3_l4_core__i2c1,
1701 };
1702
1703 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1704         .name           = "i2c1",
1705         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1706         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1707         .main_clk       = "i2c1_fck",
1708         .prcm           = {
1709                 .omap2 = {
1710                         .module_offs = CORE_MOD,
1711                         .prcm_reg_id = 1,
1712                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1713                         .idlest_reg_id = 1,
1714                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1715                 },
1716         },
1717         .slaves         = omap3xxx_i2c1_slaves,
1718         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1719         .class          = &i2c_class,
1720         .dev_attr       = &i2c1_dev_attr,
1721         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1722 };
1723
1724 /* I2C2 */
1725
1726 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1727         .fifo_depth     = 8, /* bytes */
1728 };
1729
1730 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1731         &omap3_l4_core__i2c2,
1732 };
1733
1734 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1735         .name           = "i2c2",
1736         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1737         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1738         .main_clk       = "i2c2_fck",
1739         .prcm           = {
1740                 .omap2 = {
1741                         .module_offs = CORE_MOD,
1742                         .prcm_reg_id = 1,
1743                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1744                         .idlest_reg_id = 1,
1745                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1746                 },
1747         },
1748         .slaves         = omap3xxx_i2c2_slaves,
1749         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1750         .class          = &i2c_class,
1751         .dev_attr       = &i2c2_dev_attr,
1752         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1753 };
1754
1755 /* I2C3 */
1756
1757 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1758         .fifo_depth     = 64, /* bytes */
1759 };
1760
1761 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1762         { .irq = INT_34XX_I2C3_IRQ, },
1763         { .irq = -1 }
1764 };
1765
1766 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1767         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1768         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1769         { .dma_req = -1 }
1770 };
1771
1772 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1773         &omap3_l4_core__i2c3,
1774 };
1775
1776 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1777         .name           = "i2c3",
1778         .mpu_irqs       = i2c3_mpu_irqs,
1779         .sdma_reqs      = i2c3_sdma_reqs,
1780         .main_clk       = "i2c3_fck",
1781         .prcm           = {
1782                 .omap2 = {
1783                         .module_offs = CORE_MOD,
1784                         .prcm_reg_id = 1,
1785                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1786                         .idlest_reg_id = 1,
1787                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1788                 },
1789         },
1790         .slaves         = omap3xxx_i2c3_slaves,
1791         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1792         .class          = &i2c_class,
1793         .dev_attr       = &i2c3_dev_attr,
1794         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1795 };
1796
1797 /* l4_wkup -> gpio1 */
1798 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1799         {
1800                 .pa_start       = 0x48310000,
1801                 .pa_end         = 0x483101ff,
1802                 .flags          = ADDR_TYPE_RT
1803         },
1804         { }
1805 };
1806
1807 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1808         .master         = &omap3xxx_l4_wkup_hwmod,
1809         .slave          = &omap3xxx_gpio1_hwmod,
1810         .addr           = omap3xxx_gpio1_addrs,
1811         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1812 };
1813
1814 /* l4_per -> gpio2 */
1815 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1816         {
1817                 .pa_start       = 0x49050000,
1818                 .pa_end         = 0x490501ff,
1819                 .flags          = ADDR_TYPE_RT
1820         },
1821         { }
1822 };
1823
1824 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1825         .master         = &omap3xxx_l4_per_hwmod,
1826         .slave          = &omap3xxx_gpio2_hwmod,
1827         .addr           = omap3xxx_gpio2_addrs,
1828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1829 };
1830
1831 /* l4_per -> gpio3 */
1832 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1833         {
1834                 .pa_start       = 0x49052000,
1835                 .pa_end         = 0x490521ff,
1836                 .flags          = ADDR_TYPE_RT
1837         },
1838         { }
1839 };
1840
1841 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1842         .master         = &omap3xxx_l4_per_hwmod,
1843         .slave          = &omap3xxx_gpio3_hwmod,
1844         .addr           = omap3xxx_gpio3_addrs,
1845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1846 };
1847
1848 /* l4_per -> gpio4 */
1849 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1850         {
1851                 .pa_start       = 0x49054000,
1852                 .pa_end         = 0x490541ff,
1853                 .flags          = ADDR_TYPE_RT
1854         },
1855         { }
1856 };
1857
1858 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1859         .master         = &omap3xxx_l4_per_hwmod,
1860         .slave          = &omap3xxx_gpio4_hwmod,
1861         .addr           = omap3xxx_gpio4_addrs,
1862         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1863 };
1864
1865 /* l4_per -> gpio5 */
1866 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1867         {
1868                 .pa_start       = 0x49056000,
1869                 .pa_end         = 0x490561ff,
1870                 .flags          = ADDR_TYPE_RT
1871         },
1872         { }
1873 };
1874
1875 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1876         .master         = &omap3xxx_l4_per_hwmod,
1877         .slave          = &omap3xxx_gpio5_hwmod,
1878         .addr           = omap3xxx_gpio5_addrs,
1879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1880 };
1881
1882 /* l4_per -> gpio6 */
1883 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1884         {
1885                 .pa_start       = 0x49058000,
1886                 .pa_end         = 0x490581ff,
1887                 .flags          = ADDR_TYPE_RT
1888         },
1889         { }
1890 };
1891
1892 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1893         .master         = &omap3xxx_l4_per_hwmod,
1894         .slave          = &omap3xxx_gpio6_hwmod,
1895         .addr           = omap3xxx_gpio6_addrs,
1896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1897 };
1898
1899 /*
1900  * 'gpio' class
1901  * general purpose io module
1902  */
1903
1904 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1905         .rev_offs       = 0x0000,
1906         .sysc_offs      = 0x0010,
1907         .syss_offs      = 0x0014,
1908         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1909                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1910                            SYSS_HAS_RESET_STATUS),
1911         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1912         .sysc_fields    = &omap_hwmod_sysc_type1,
1913 };
1914
1915 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1916         .name = "gpio",
1917         .sysc = &omap3xxx_gpio_sysc,
1918         .rev = 1,
1919 };
1920
1921 /* gpio_dev_attr*/
1922 static struct omap_gpio_dev_attr gpio_dev_attr = {
1923         .bank_width = 32,
1924         .dbck_flag = true,
1925 };
1926
1927 /* gpio1 */
1928 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1929         { .role = "dbclk", .clk = "gpio1_dbck", },
1930 };
1931
1932 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1933         &omap3xxx_l4_wkup__gpio1,
1934 };
1935
1936 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1937         .name           = "gpio1",
1938         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1939         .mpu_irqs       = omap2_gpio1_irqs,
1940         .main_clk       = "gpio1_ick",
1941         .opt_clks       = gpio1_opt_clks,
1942         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1943         .prcm           = {
1944                 .omap2 = {
1945                         .prcm_reg_id = 1,
1946                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1947                         .module_offs = WKUP_MOD,
1948                         .idlest_reg_id = 1,
1949                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1950                 },
1951         },
1952         .slaves         = omap3xxx_gpio1_slaves,
1953         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1954         .class          = &omap3xxx_gpio_hwmod_class,
1955         .dev_attr       = &gpio_dev_attr,
1956         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1957 };
1958
1959 /* gpio2 */
1960 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1961         { .role = "dbclk", .clk = "gpio2_dbck", },
1962 };
1963
1964 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1965         &omap3xxx_l4_per__gpio2,
1966 };
1967
1968 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1969         .name           = "gpio2",
1970         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1971         .mpu_irqs       = omap2_gpio2_irqs,
1972         .main_clk       = "gpio2_ick",
1973         .opt_clks       = gpio2_opt_clks,
1974         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1975         .prcm           = {
1976                 .omap2 = {
1977                         .prcm_reg_id = 1,
1978                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1979                         .module_offs = OMAP3430_PER_MOD,
1980                         .idlest_reg_id = 1,
1981                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1982                 },
1983         },
1984         .slaves         = omap3xxx_gpio2_slaves,
1985         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1986         .class          = &omap3xxx_gpio_hwmod_class,
1987         .dev_attr       = &gpio_dev_attr,
1988         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1989 };
1990
1991 /* gpio3 */
1992 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1993         { .role = "dbclk", .clk = "gpio3_dbck", },
1994 };
1995
1996 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1997         &omap3xxx_l4_per__gpio3,
1998 };
1999
2000 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2001         .name           = "gpio3",
2002         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2003         .mpu_irqs       = omap2_gpio3_irqs,
2004         .main_clk       = "gpio3_ick",
2005         .opt_clks       = gpio3_opt_clks,
2006         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2007         .prcm           = {
2008                 .omap2 = {
2009                         .prcm_reg_id = 1,
2010                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2011                         .module_offs = OMAP3430_PER_MOD,
2012                         .idlest_reg_id = 1,
2013                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2014                 },
2015         },
2016         .slaves         = omap3xxx_gpio3_slaves,
2017         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2018         .class          = &omap3xxx_gpio_hwmod_class,
2019         .dev_attr       = &gpio_dev_attr,
2020         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2021 };
2022
2023 /* gpio4 */
2024 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2025         { .role = "dbclk", .clk = "gpio4_dbck", },
2026 };
2027
2028 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2029         &omap3xxx_l4_per__gpio4,
2030 };
2031
2032 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2033         .name           = "gpio4",
2034         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2035         .mpu_irqs       = omap2_gpio4_irqs,
2036         .main_clk       = "gpio4_ick",
2037         .opt_clks       = gpio4_opt_clks,
2038         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2039         .prcm           = {
2040                 .omap2 = {
2041                         .prcm_reg_id = 1,
2042                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2043                         .module_offs = OMAP3430_PER_MOD,
2044                         .idlest_reg_id = 1,
2045                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2046                 },
2047         },
2048         .slaves         = omap3xxx_gpio4_slaves,
2049         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2050         .class          = &omap3xxx_gpio_hwmod_class,
2051         .dev_attr       = &gpio_dev_attr,
2052         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2053 };
2054
2055 /* gpio5 */
2056 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2057         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2058         { .irq = -1 }
2059 };
2060
2061 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2062         { .role = "dbclk", .clk = "gpio5_dbck", },
2063 };
2064
2065 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2066         &omap3xxx_l4_per__gpio5,
2067 };
2068
2069 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2070         .name           = "gpio5",
2071         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2072         .mpu_irqs       = omap3xxx_gpio5_irqs,
2073         .main_clk       = "gpio5_ick",
2074         .opt_clks       = gpio5_opt_clks,
2075         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2076         .prcm           = {
2077                 .omap2 = {
2078                         .prcm_reg_id = 1,
2079                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2080                         .module_offs = OMAP3430_PER_MOD,
2081                         .idlest_reg_id = 1,
2082                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2083                 },
2084         },
2085         .slaves         = omap3xxx_gpio5_slaves,
2086         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2087         .class          = &omap3xxx_gpio_hwmod_class,
2088         .dev_attr       = &gpio_dev_attr,
2089         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2090 };
2091
2092 /* gpio6 */
2093 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2094         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2095         { .irq = -1 }
2096 };
2097
2098 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2099         { .role = "dbclk", .clk = "gpio6_dbck", },
2100 };
2101
2102 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2103         &omap3xxx_l4_per__gpio6,
2104 };
2105
2106 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2107         .name           = "gpio6",
2108         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2109         .mpu_irqs       = omap3xxx_gpio6_irqs,
2110         .main_clk       = "gpio6_ick",
2111         .opt_clks       = gpio6_opt_clks,
2112         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2113         .prcm           = {
2114                 .omap2 = {
2115                         .prcm_reg_id = 1,
2116                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2117                         .module_offs = OMAP3430_PER_MOD,
2118                         .idlest_reg_id = 1,
2119                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2120                 },
2121         },
2122         .slaves         = omap3xxx_gpio6_slaves,
2123         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2124         .class          = &omap3xxx_gpio_hwmod_class,
2125         .dev_attr       = &gpio_dev_attr,
2126         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2127 };
2128
2129 /* dma_system -> L3 */
2130 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2131         .master         = &omap3xxx_dma_system_hwmod,
2132         .slave          = &omap3xxx_l3_main_hwmod,
2133         .clk            = "core_l3_ick",
2134         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2135 };
2136
2137 /* dma attributes */
2138 static struct omap_dma_dev_attr dma_dev_attr = {
2139         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2140                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2141         .lch_count = 32,
2142 };
2143
2144 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2145         .rev_offs       = 0x0000,
2146         .sysc_offs      = 0x002c,
2147         .syss_offs      = 0x0028,
2148         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2149                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2150                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2151                            SYSS_HAS_RESET_STATUS),
2152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2153                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2154         .sysc_fields    = &omap_hwmod_sysc_type1,
2155 };
2156
2157 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2158         .name = "dma",
2159         .sysc = &omap3xxx_dma_sysc,
2160 };
2161
2162 /* dma_system */
2163 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2164         {
2165                 .pa_start       = 0x48056000,
2166                 .pa_end         = 0x48056fff,
2167                 .flags          = ADDR_TYPE_RT
2168         },
2169         { }
2170 };
2171
2172 /* dma_system master ports */
2173 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2174         &omap3xxx_dma_system__l3,
2175 };
2176
2177 /* l4_cfg -> dma_system */
2178 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2179         .master         = &omap3xxx_l4_core_hwmod,
2180         .slave          = &omap3xxx_dma_system_hwmod,
2181         .clk            = "core_l4_ick",
2182         .addr           = omap3xxx_dma_system_addrs,
2183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2184 };
2185
2186 /* dma_system slave ports */
2187 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2188         &omap3xxx_l4_core__dma_system,
2189 };
2190
2191 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2192         .name           = "dma",
2193         .class          = &omap3xxx_dma_hwmod_class,
2194         .mpu_irqs       = omap2_dma_system_irqs,
2195         .main_clk       = "core_l3_ick",
2196         .prcm = {
2197                 .omap2 = {
2198                         .module_offs            = CORE_MOD,
2199                         .prcm_reg_id            = 1,
2200                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2201                         .idlest_reg_id          = 1,
2202                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2203                 },
2204         },
2205         .slaves         = omap3xxx_dma_system_slaves,
2206         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2207         .masters        = omap3xxx_dma_system_masters,
2208         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2209         .dev_attr       = &dma_dev_attr,
2210         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2211         .flags          = HWMOD_NO_IDLEST,
2212 };
2213
2214 /*
2215  * 'mcbsp' class
2216  * multi channel buffered serial port controller
2217  */
2218
2219 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2220         .sysc_offs      = 0x008c,
2221         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2222                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2223         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2224         .sysc_fields    = &omap_hwmod_sysc_type1,
2225         .clockact       = 0x2,
2226 };
2227
2228 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2229         .name = "mcbsp",
2230         .sysc = &omap3xxx_mcbsp_sysc,
2231         .rev  = MCBSP_CONFIG_TYPE3,
2232 };
2233
2234 /* mcbsp1 */
2235 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2236         { .name = "irq", .irq = 16 },
2237         { .name = "tx", .irq = 59 },
2238         { .name = "rx", .irq = 60 },
2239         { .irq = -1 }
2240 };
2241
2242 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2243         {
2244                 .name           = "mpu",
2245                 .pa_start       = 0x48074000,
2246                 .pa_end         = 0x480740ff,
2247                 .flags          = ADDR_TYPE_RT
2248         },
2249         { }
2250 };
2251
2252 /* l4_core -> mcbsp1 */
2253 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2254         .master         = &omap3xxx_l4_core_hwmod,
2255         .slave          = &omap3xxx_mcbsp1_hwmod,
2256         .clk            = "mcbsp1_ick",
2257         .addr           = omap3xxx_mcbsp1_addrs,
2258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260
2261 /* mcbsp1 slave ports */
2262 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2263         &omap3xxx_l4_core__mcbsp1,
2264 };
2265
2266 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2267         .name           = "mcbsp1",
2268         .class          = &omap3xxx_mcbsp_hwmod_class,
2269         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2270         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2271         .main_clk       = "mcbsp1_fck",
2272         .prcm           = {
2273                 .omap2 = {
2274                         .prcm_reg_id = 1,
2275                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2276                         .module_offs = CORE_MOD,
2277                         .idlest_reg_id = 1,
2278                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2279                 },
2280         },
2281         .slaves         = omap3xxx_mcbsp1_slaves,
2282         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2283         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2284 };
2285
2286 /* mcbsp2 */
2287 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2288         { .name = "irq", .irq = 17 },
2289         { .name = "tx", .irq = 62 },
2290         { .name = "rx", .irq = 63 },
2291         { .irq = -1 }
2292 };
2293
2294 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2295         {
2296                 .name           = "mpu",
2297                 .pa_start       = 0x49022000,
2298                 .pa_end         = 0x490220ff,
2299                 .flags          = ADDR_TYPE_RT
2300         },
2301         { }
2302 };
2303
2304 /* l4_per -> mcbsp2 */
2305 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2306         .master         = &omap3xxx_l4_per_hwmod,
2307         .slave          = &omap3xxx_mcbsp2_hwmod,
2308         .clk            = "mcbsp2_ick",
2309         .addr           = omap3xxx_mcbsp2_addrs,
2310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2311 };
2312
2313 /* mcbsp2 slave ports */
2314 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2315         &omap3xxx_l4_per__mcbsp2,
2316 };
2317
2318 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2319         .sidetone       = "mcbsp2_sidetone",
2320 };
2321
2322 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2323         .name           = "mcbsp2",
2324         .class          = &omap3xxx_mcbsp_hwmod_class,
2325         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2326         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2327         .main_clk       = "mcbsp2_fck",
2328         .prcm           = {
2329                 .omap2 = {
2330                         .prcm_reg_id = 1,
2331                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2332                         .module_offs = OMAP3430_PER_MOD,
2333                         .idlest_reg_id = 1,
2334                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2335                 },
2336         },
2337         .slaves         = omap3xxx_mcbsp2_slaves,
2338         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2339         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2340         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2341 };
2342
2343 /* mcbsp3 */
2344 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2345         { .name = "irq", .irq = 22 },
2346         { .name = "tx", .irq = 89 },
2347         { .name = "rx", .irq = 90 },
2348         { .irq = -1 }
2349 };
2350
2351 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2352         {
2353                 .name           = "mpu",
2354                 .pa_start       = 0x49024000,
2355                 .pa_end         = 0x490240ff,
2356                 .flags          = ADDR_TYPE_RT
2357         },
2358         { }
2359 };
2360
2361 /* l4_per -> mcbsp3 */
2362 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2363         .master         = &omap3xxx_l4_per_hwmod,
2364         .slave          = &omap3xxx_mcbsp3_hwmod,
2365         .clk            = "mcbsp3_ick",
2366         .addr           = omap3xxx_mcbsp3_addrs,
2367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2368 };
2369
2370 /* mcbsp3 slave ports */
2371 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2372         &omap3xxx_l4_per__mcbsp3,
2373 };
2374
2375 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2376         .sidetone       = "mcbsp3_sidetone",
2377 };
2378
2379 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2380         .name           = "mcbsp3",
2381         .class          = &omap3xxx_mcbsp_hwmod_class,
2382         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2383         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2384         .main_clk       = "mcbsp3_fck",
2385         .prcm           = {
2386                 .omap2 = {
2387                         .prcm_reg_id = 1,
2388                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2389                         .module_offs = OMAP3430_PER_MOD,
2390                         .idlest_reg_id = 1,
2391                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2392                 },
2393         },
2394         .slaves         = omap3xxx_mcbsp3_slaves,
2395         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2396         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2397         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2398 };
2399
2400 /* mcbsp4 */
2401 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2402         { .name = "irq", .irq = 23 },
2403         { .name = "tx", .irq = 54 },
2404         { .name = "rx", .irq = 55 },
2405         { .irq = -1 }
2406 };
2407
2408 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2409         { .name = "rx", .dma_req = 20 },
2410         { .name = "tx", .dma_req = 19 },
2411         { .dma_req = -1 }
2412 };
2413
2414 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2415         {
2416                 .name           = "mpu",
2417                 .pa_start       = 0x49026000,
2418                 .pa_end         = 0x490260ff,
2419                 .flags          = ADDR_TYPE_RT
2420         },
2421         { }
2422 };
2423
2424 /* l4_per -> mcbsp4 */
2425 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2426         .master         = &omap3xxx_l4_per_hwmod,
2427         .slave          = &omap3xxx_mcbsp4_hwmod,
2428         .clk            = "mcbsp4_ick",
2429         .addr           = omap3xxx_mcbsp4_addrs,
2430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2431 };
2432
2433 /* mcbsp4 slave ports */
2434 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2435         &omap3xxx_l4_per__mcbsp4,
2436 };
2437
2438 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2439         .name           = "mcbsp4",
2440         .class          = &omap3xxx_mcbsp_hwmod_class,
2441         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2442         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2443         .main_clk       = "mcbsp4_fck",
2444         .prcm           = {
2445                 .omap2 = {
2446                         .prcm_reg_id = 1,
2447                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2448                         .module_offs = OMAP3430_PER_MOD,
2449                         .idlest_reg_id = 1,
2450                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2451                 },
2452         },
2453         .slaves         = omap3xxx_mcbsp4_slaves,
2454         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2455         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2456 };
2457
2458 /* mcbsp5 */
2459 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2460         { .name = "irq", .irq = 27 },
2461         { .name = "tx", .irq = 81 },
2462         { .name = "rx", .irq = 82 },
2463         { .irq = -1 }
2464 };
2465
2466 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2467         { .name = "rx", .dma_req = 22 },
2468         { .name = "tx", .dma_req = 21 },
2469         { .dma_req = -1 }
2470 };
2471
2472 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2473         {
2474                 .name           = "mpu",
2475                 .pa_start       = 0x48096000,
2476                 .pa_end         = 0x480960ff,
2477                 .flags          = ADDR_TYPE_RT
2478         },
2479         { }
2480 };
2481
2482 /* l4_core -> mcbsp5 */
2483 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2484         .master         = &omap3xxx_l4_core_hwmod,
2485         .slave          = &omap3xxx_mcbsp5_hwmod,
2486         .clk            = "mcbsp5_ick",
2487         .addr           = omap3xxx_mcbsp5_addrs,
2488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2489 };
2490
2491 /* mcbsp5 slave ports */
2492 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2493         &omap3xxx_l4_core__mcbsp5,
2494 };
2495
2496 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2497         .name           = "mcbsp5",
2498         .class          = &omap3xxx_mcbsp_hwmod_class,
2499         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2500         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2501         .main_clk       = "mcbsp5_fck",
2502         .prcm           = {
2503                 .omap2 = {
2504                         .prcm_reg_id = 1,
2505                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2506                         .module_offs = CORE_MOD,
2507                         .idlest_reg_id = 1,
2508                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2509                 },
2510         },
2511         .slaves         = omap3xxx_mcbsp5_slaves,
2512         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2513         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2514 };
2515 /* 'mcbsp sidetone' class */
2516
2517 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2518         .sysc_offs      = 0x0010,
2519         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2520         .sysc_fields    = &omap_hwmod_sysc_type1,
2521 };
2522
2523 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2524         .name = "mcbsp_sidetone",
2525         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2526 };
2527
2528 /* mcbsp2_sidetone */
2529 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2530         { .name = "irq", .irq = 4 },
2531         { .irq = -1 }
2532 };
2533
2534 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2535         {
2536                 .name           = "sidetone",
2537                 .pa_start       = 0x49028000,
2538                 .pa_end         = 0x490280ff,
2539                 .flags          = ADDR_TYPE_RT
2540         },
2541         { }
2542 };
2543
2544 /* l4_per -> mcbsp2_sidetone */
2545 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2546         .master         = &omap3xxx_l4_per_hwmod,
2547         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2548         .clk            = "mcbsp2_ick",
2549         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2550         .user           = OCP_USER_MPU,
2551 };
2552
2553 /* mcbsp2_sidetone slave ports */
2554 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2555         &omap3xxx_l4_per__mcbsp2_sidetone,
2556 };
2557
2558 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2559         .name           = "mcbsp2_sidetone",
2560         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2561         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2562         .main_clk       = "mcbsp2_fck",
2563         .prcm           = {
2564                 .omap2 = {
2565                         .prcm_reg_id = 1,
2566                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2567                         .module_offs = OMAP3430_PER_MOD,
2568                         .idlest_reg_id = 1,
2569                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2570                 },
2571         },
2572         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2573         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2574         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2575 };
2576
2577 /* mcbsp3_sidetone */
2578 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2579         { .name = "irq", .irq = 5 },
2580         { .irq = -1 }
2581 };
2582
2583 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2584         {
2585                 .name           = "sidetone",
2586                 .pa_start       = 0x4902A000,
2587                 .pa_end         = 0x4902A0ff,
2588                 .flags          = ADDR_TYPE_RT
2589         },
2590         { }
2591 };
2592
2593 /* l4_per -> mcbsp3_sidetone */
2594 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2595         .master         = &omap3xxx_l4_per_hwmod,
2596         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2597         .clk            = "mcbsp3_ick",
2598         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2599         .user           = OCP_USER_MPU,
2600 };
2601
2602 /* mcbsp3_sidetone slave ports */
2603 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2604         &omap3xxx_l4_per__mcbsp3_sidetone,
2605 };
2606
2607 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2608         .name           = "mcbsp3_sidetone",
2609         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2610         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2611         .main_clk       = "mcbsp3_fck",
2612         .prcm           = {
2613                 .omap2 = {
2614                         .prcm_reg_id = 1,
2615                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2616                         .module_offs = OMAP3430_PER_MOD,
2617                         .idlest_reg_id = 1,
2618                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2619                 },
2620         },
2621         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2622         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2623         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2624 };
2625
2626
2627 /* SR common */
2628 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2629         .clkact_shift   = 20,
2630 };
2631
2632 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2633         .sysc_offs      = 0x24,
2634         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2635         .clockact       = CLOCKACT_TEST_ICLK,
2636         .sysc_fields    = &omap34xx_sr_sysc_fields,
2637 };
2638
2639 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2640         .name = "smartreflex",
2641         .sysc = &omap34xx_sr_sysc,
2642         .rev  = 1,
2643 };
2644
2645 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2646         .sidle_shift    = 24,
2647         .enwkup_shift   = 26
2648 };
2649
2650 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2651         .sysc_offs      = 0x38,
2652         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2653         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2654                         SYSC_NO_CACHE),
2655         .sysc_fields    = &omap36xx_sr_sysc_fields,
2656 };
2657
2658 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2659         .name = "smartreflex",
2660         .sysc = &omap36xx_sr_sysc,
2661         .rev  = 2,
2662 };
2663
2664 /* SR1 */
2665 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2666         &omap3_l4_core__sr1,
2667 };
2668
2669 static struct omap_hwmod omap34xx_sr1_hwmod = {
2670         .name           = "sr1_hwmod",
2671         .class          = &omap34xx_smartreflex_hwmod_class,
2672         .main_clk       = "sr1_fck",
2673         .vdd_name       = "mpu",
2674         .prcm           = {
2675                 .omap2 = {
2676                         .prcm_reg_id = 1,
2677                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2678                         .module_offs = WKUP_MOD,
2679                         .idlest_reg_id = 1,
2680                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2681                 },
2682         },
2683         .slaves         = omap3_sr1_slaves,
2684         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2685         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2686                                         CHIP_IS_OMAP3430ES3_0 |
2687                                         CHIP_IS_OMAP3430ES3_1),
2688         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2689 };
2690
2691 static struct omap_hwmod omap36xx_sr1_hwmod = {
2692         .name           = "sr1_hwmod",
2693         .class          = &omap36xx_smartreflex_hwmod_class,
2694         .main_clk       = "sr1_fck",
2695         .vdd_name       = "mpu",
2696         .prcm           = {
2697                 .omap2 = {
2698                         .prcm_reg_id = 1,
2699                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2700                         .module_offs = WKUP_MOD,
2701                         .idlest_reg_id = 1,
2702                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2703                 },
2704         },
2705         .slaves         = omap3_sr1_slaves,
2706         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2707         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2708 };
2709
2710 /* SR2 */
2711 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2712         &omap3_l4_core__sr2,
2713 };
2714
2715 static struct omap_hwmod omap34xx_sr2_hwmod = {
2716         .name           = "sr2_hwmod",
2717         .class          = &omap34xx_smartreflex_hwmod_class,
2718         .main_clk       = "sr2_fck",
2719         .vdd_name       = "core",
2720         .prcm           = {
2721                 .omap2 = {
2722                         .prcm_reg_id = 1,
2723                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2724                         .module_offs = WKUP_MOD,
2725                         .idlest_reg_id = 1,
2726                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2727                 },
2728         },
2729         .slaves         = omap3_sr2_slaves,
2730         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2731         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2732                                         CHIP_IS_OMAP3430ES3_0 |
2733                                         CHIP_IS_OMAP3430ES3_1),
2734         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2735 };
2736
2737 static struct omap_hwmod omap36xx_sr2_hwmod = {
2738         .name           = "sr2_hwmod",
2739         .class          = &omap36xx_smartreflex_hwmod_class,
2740         .main_clk       = "sr2_fck",
2741         .vdd_name       = "core",
2742         .prcm           = {
2743                 .omap2 = {
2744                         .prcm_reg_id = 1,
2745                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2746                         .module_offs = WKUP_MOD,
2747                         .idlest_reg_id = 1,
2748                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2749                 },
2750         },
2751         .slaves         = omap3_sr2_slaves,
2752         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2753         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2754 };
2755
2756 /*
2757  * 'mailbox' class
2758  * mailbox module allowing communication between the on-chip processors
2759  * using a queued mailbox-interrupt mechanism.
2760  */
2761
2762 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2763         .rev_offs       = 0x000,
2764         .sysc_offs      = 0x010,
2765         .syss_offs      = 0x014,
2766         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2767                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2768         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2769         .sysc_fields    = &omap_hwmod_sysc_type1,
2770 };
2771
2772 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2773         .name = "mailbox",
2774         .sysc = &omap3xxx_mailbox_sysc,
2775 };
2776
2777 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2778 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2779         { .irq = 26 },
2780         { .irq = -1 }
2781 };
2782
2783 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2784         {
2785                 .pa_start       = 0x48094000,
2786                 .pa_end         = 0x480941ff,
2787                 .flags          = ADDR_TYPE_RT,
2788         },
2789         { }
2790 };
2791
2792 /* l4_core -> mailbox */
2793 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2794         .master         = &omap3xxx_l4_core_hwmod,
2795         .slave          = &omap3xxx_mailbox_hwmod,
2796         .addr           = omap3xxx_mailbox_addrs,
2797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2798 };
2799
2800 /* mailbox slave ports */
2801 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2802         &omap3xxx_l4_core__mailbox,
2803 };
2804
2805 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2806         .name           = "mailbox",
2807         .class          = &omap3xxx_mailbox_hwmod_class,
2808         .mpu_irqs       = omap3xxx_mailbox_irqs,
2809         .main_clk       = "mailboxes_ick",
2810         .prcm           = {
2811                 .omap2 = {
2812                         .prcm_reg_id = 1,
2813                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2814                         .module_offs = CORE_MOD,
2815                         .idlest_reg_id = 1,
2816                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2817                 },
2818         },
2819         .slaves         = omap3xxx_mailbox_slaves,
2820         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2821         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2822 };
2823
2824 /* l4 core -> mcspi1 interface */
2825 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2826         .master         = &omap3xxx_l4_core_hwmod,
2827         .slave          = &omap34xx_mcspi1,
2828         .clk            = "mcspi1_ick",
2829         .addr           = omap2_mcspi1_addr_space,
2830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2831 };
2832
2833 /* l4 core -> mcspi2 interface */
2834 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2835         .master         = &omap3xxx_l4_core_hwmod,
2836         .slave          = &omap34xx_mcspi2,
2837         .clk            = "mcspi2_ick",
2838         .addr           = omap2_mcspi2_addr_space,
2839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2840 };
2841
2842 /* l4 core -> mcspi3 interface */
2843 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2844         .master         = &omap3xxx_l4_core_hwmod,
2845         .slave          = &omap34xx_mcspi3,
2846         .clk            = "mcspi3_ick",
2847         .addr           = omap2430_mcspi3_addr_space,
2848         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2849 };
2850
2851 /* l4 core -> mcspi4 interface */
2852 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2853         {
2854                 .pa_start       = 0x480ba000,
2855                 .pa_end         = 0x480ba0ff,
2856                 .flags          = ADDR_TYPE_RT,
2857         },
2858         { }
2859 };
2860
2861 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2862         .master         = &omap3xxx_l4_core_hwmod,
2863         .slave          = &omap34xx_mcspi4,
2864         .clk            = "mcspi4_ick",
2865         .addr           = omap34xx_mcspi4_addr_space,
2866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2867 };
2868
2869 /*
2870  * 'mcspi' class
2871  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2872  * bus
2873  */
2874
2875 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2876         .rev_offs       = 0x0000,
2877         .sysc_offs      = 0x0010,
2878         .syss_offs      = 0x0014,
2879         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2880                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2881                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2882         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2883         .sysc_fields    = &omap_hwmod_sysc_type1,
2884 };
2885
2886 static struct omap_hwmod_class omap34xx_mcspi_class = {
2887         .name = "mcspi",
2888         .sysc = &omap34xx_mcspi_sysc,
2889         .rev = OMAP3_MCSPI_REV,
2890 };
2891
2892 /* mcspi1 */
2893 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2894         &omap34xx_l4_core__mcspi1,
2895 };
2896
2897 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2898         .num_chipselect = 4,
2899 };
2900
2901 static struct omap_hwmod omap34xx_mcspi1 = {
2902         .name           = "mcspi1",
2903         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2904         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2905         .main_clk       = "mcspi1_fck",
2906         .prcm           = {
2907                 .omap2 = {
2908                         .module_offs = CORE_MOD,
2909                         .prcm_reg_id = 1,
2910                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2911                         .idlest_reg_id = 1,
2912                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2913                 },
2914         },
2915         .slaves         = omap34xx_mcspi1_slaves,
2916         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2917         .class          = &omap34xx_mcspi_class,
2918         .dev_attr       = &omap_mcspi1_dev_attr,
2919         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2920 };
2921
2922 /* mcspi2 */
2923 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2924         &omap34xx_l4_core__mcspi2,
2925 };
2926
2927 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2928         .num_chipselect = 2,
2929 };
2930
2931 static struct omap_hwmod omap34xx_mcspi2 = {
2932         .name           = "mcspi2",
2933         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2934         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2935         .main_clk       = "mcspi2_fck",
2936         .prcm           = {
2937                 .omap2 = {
2938                         .module_offs = CORE_MOD,
2939                         .prcm_reg_id = 1,
2940                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2941                         .idlest_reg_id = 1,
2942                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2943                 },
2944         },
2945         .slaves         = omap34xx_mcspi2_slaves,
2946         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2947         .class          = &omap34xx_mcspi_class,
2948         .dev_attr       = &omap_mcspi2_dev_attr,
2949         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2950 };
2951
2952 /* mcspi3 */
2953 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2954         { .name = "irq", .irq = 91 }, /* 91 */
2955         { .irq = -1 }
2956 };
2957
2958 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2959         { .name = "tx0", .dma_req = 15 },
2960         { .name = "rx0", .dma_req = 16 },
2961         { .name = "tx1", .dma_req = 23 },
2962         { .name = "rx1", .dma_req = 24 },
2963         { .dma_req = -1 }
2964 };
2965
2966 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2967         &omap34xx_l4_core__mcspi3,
2968 };
2969
2970 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2971         .num_chipselect = 2,
2972 };
2973
2974 static struct omap_hwmod omap34xx_mcspi3 = {
2975         .name           = "mcspi3",
2976         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2977         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2978         .main_clk       = "mcspi3_fck",
2979         .prcm           = {
2980                 .omap2 = {
2981                         .module_offs = CORE_MOD,
2982                         .prcm_reg_id = 1,
2983                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2984                         .idlest_reg_id = 1,
2985                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2986                 },
2987         },
2988         .slaves         = omap34xx_mcspi3_slaves,
2989         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2990         .class          = &omap34xx_mcspi_class,
2991         .dev_attr       = &omap_mcspi3_dev_attr,
2992         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2993 };
2994
2995 /* SPI4 */
2996 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2997         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2998         { .irq = -1 }
2999 };
3000
3001 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3002         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3003         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3004         { .dma_req = -1 }
3005 };
3006
3007 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3008         &omap34xx_l4_core__mcspi4,
3009 };
3010
3011 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3012         .num_chipselect = 1,
3013 };
3014
3015 static struct omap_hwmod omap34xx_mcspi4 = {
3016         .name           = "mcspi4",
3017         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3018         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3019         .main_clk       = "mcspi4_fck",
3020         .prcm           = {
3021                 .omap2 = {
3022                         .module_offs = CORE_MOD,
3023                         .prcm_reg_id = 1,
3024                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3025                         .idlest_reg_id = 1,
3026                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3027                 },
3028         },
3029         .slaves         = omap34xx_mcspi4_slaves,
3030         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3031         .class          = &omap34xx_mcspi_class,
3032         .dev_attr       = &omap_mcspi4_dev_attr,
3033         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3034 };
3035
3036 /*
3037  * usbhsotg
3038  */
3039 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3040         .rev_offs       = 0x0400,
3041         .sysc_offs      = 0x0404,
3042         .syss_offs      = 0x0408,
3043         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3044                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3045                           SYSC_HAS_AUTOIDLE),
3046         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3047                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3048         .sysc_fields    = &omap_hwmod_sysc_type1,
3049 };
3050
3051 static struct omap_hwmod_class usbotg_class = {
3052         .name = "usbotg",
3053         .sysc = &omap3xxx_usbhsotg_sysc,
3054 };
3055 /* usb_otg_hs */
3056 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3057
3058         { .name = "mc", .irq = 92 },
3059         { .name = "dma", .irq = 93 },
3060         { .irq = -1 }
3061 };
3062
3063 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3064         .name           = "usb_otg_hs",
3065         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3066         .main_clk       = "hsotgusb_ick",
3067         .prcm           = {
3068                 .omap2 = {
3069                         .prcm_reg_id = 1,
3070                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3071                         .module_offs = CORE_MOD,
3072                         .idlest_reg_id = 1,
3073                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3074                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3075                 },
3076         },
3077         .masters        = omap3xxx_usbhsotg_masters,
3078         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3079         .slaves         = omap3xxx_usbhsotg_slaves,
3080         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3081         .class          = &usbotg_class,
3082
3083         /*
3084          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3085          * broken when autoidle is enabled
3086          * workaround is to disable the autoidle bit at module level.
3087          */
3088         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3089                                 | HWMOD_SWSUP_MSTANDBY,
3090         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3091 };
3092
3093 /* usb_otg_hs */
3094 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3095
3096         { .name = "mc", .irq = 71 },
3097         { .irq = -1 }
3098 };
3099
3100 static struct omap_hwmod_class am35xx_usbotg_class = {
3101         .name = "am35xx_usbotg",
3102         .sysc = NULL,
3103 };
3104
3105 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3106         .name           = "am35x_otg_hs",
3107         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3108         .main_clk       = NULL,
3109         .prcm = {
3110                 .omap2 = {
3111                 },
3112         },
3113         .masters        = am35xx_usbhsotg_masters,
3114         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3115         .slaves         = am35xx_usbhsotg_slaves,
3116         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3117         .class          = &am35xx_usbotg_class,
3118         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3119 };
3120
3121 /* MMC/SD/SDIO common */
3122
3123 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3124         .rev_offs       = 0x1fc,
3125         .sysc_offs      = 0x10,
3126         .syss_offs      = 0x14,
3127         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3128                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3129                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3130         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3131         .sysc_fields    = &omap_hwmod_sysc_type1,
3132 };
3133
3134 static struct omap_hwmod_class omap34xx_mmc_class = {
3135         .name = "mmc",
3136         .sysc = &omap34xx_mmc_sysc,
3137 };
3138
3139 /* MMC/SD/SDIO1 */
3140
3141 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3142         { .irq = 83, },
3143         { .irq = -1 }
3144 };
3145
3146 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3147         { .name = "tx", .dma_req = 61, },
3148         { .name = "rx", .dma_req = 62, },
3149         { .dma_req = -1 }
3150 };
3151
3152 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3153         { .role = "dbck", .clk = "omap_32k_fck", },
3154 };
3155
3156 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3157         &omap3xxx_l4_core__mmc1,
3158 };
3159
3160 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3161         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3162 };
3163
3164 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3165         .name           = "mmc1",
3166         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3167         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3168         .opt_clks       = omap34xx_mmc1_opt_clks,
3169         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3170         .main_clk       = "mmchs1_fck",
3171         .prcm           = {
3172                 .omap2 = {
3173                         .module_offs = CORE_MOD,
3174                         .prcm_reg_id = 1,
3175                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3176                         .idlest_reg_id = 1,
3177                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3178                 },
3179         },
3180         .dev_attr       = &mmc1_dev_attr,
3181         .slaves         = omap3xxx_mmc1_slaves,
3182         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3183         .class          = &omap34xx_mmc_class,
3184         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3185 };
3186
3187 /* MMC/SD/SDIO2 */
3188
3189 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3190         { .irq = INT_24XX_MMC2_IRQ, },
3191         { .irq = -1 }
3192 };
3193
3194 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3195         { .name = "tx", .dma_req = 47, },
3196         { .name = "rx", .dma_req = 48, },
3197         { .dma_req = -1 }
3198 };
3199
3200 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3201         { .role = "dbck", .clk = "omap_32k_fck", },
3202 };
3203
3204 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3205         &omap3xxx_l4_core__mmc2,
3206 };
3207
3208 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3209         .name           = "mmc2",
3210         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3211         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3212         .opt_clks       = omap34xx_mmc2_opt_clks,
3213         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3214         .main_clk       = "mmchs2_fck",
3215         .prcm           = {
3216                 .omap2 = {
3217                         .module_offs = CORE_MOD,
3218                         .prcm_reg_id = 1,
3219                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3220                         .idlest_reg_id = 1,
3221                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3222                 },
3223         },
3224         .slaves         = omap3xxx_mmc2_slaves,
3225         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3226         .class          = &omap34xx_mmc_class,
3227         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3228 };
3229
3230 /* MMC/SD/SDIO3 */
3231
3232 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3233         { .irq = 94, },
3234         { .irq = -1 }
3235 };
3236
3237 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3238         { .name = "tx", .dma_req = 77, },
3239         { .name = "rx", .dma_req = 78, },
3240         { .dma_req = -1 }
3241 };
3242
3243 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3244         { .role = "dbck", .clk = "omap_32k_fck", },
3245 };
3246
3247 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3248         &omap3xxx_l4_core__mmc3,
3249 };
3250
3251 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3252         .name           = "mmc3",
3253         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3254         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3255         .opt_clks       = omap34xx_mmc3_opt_clks,
3256         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3257         .main_clk       = "mmchs3_fck",
3258         .prcm           = {
3259                 .omap2 = {
3260                         .prcm_reg_id = 1,
3261                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3262                         .idlest_reg_id = 1,
3263                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3264                 },
3265         },
3266         .slaves         = omap3xxx_mmc3_slaves,
3267         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3268         .class          = &omap34xx_mmc_class,
3269         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3270 };
3271
3272 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3273         &omap3xxx_l3_main_hwmod,
3274         &omap3xxx_l4_core_hwmod,
3275         &omap3xxx_l4_per_hwmod,
3276         &omap3xxx_l4_wkup_hwmod,
3277         &omap3xxx_mmc1_hwmod,
3278         &omap3xxx_mmc2_hwmod,
3279         &omap3xxx_mmc3_hwmod,
3280         &omap3xxx_mpu_hwmod,
3281         &omap3xxx_iva_hwmod,
3282
3283         &omap3xxx_timer1_hwmod,
3284         &omap3xxx_timer2_hwmod,
3285         &omap3xxx_timer3_hwmod,
3286         &omap3xxx_timer4_hwmod,
3287         &omap3xxx_timer5_hwmod,
3288         &omap3xxx_timer6_hwmod,
3289         &omap3xxx_timer7_hwmod,
3290         &omap3xxx_timer8_hwmod,
3291         &omap3xxx_timer9_hwmod,
3292         &omap3xxx_timer10_hwmod,
3293         &omap3xxx_timer11_hwmod,
3294         &omap3xxx_timer12_hwmod,
3295
3296         &omap3xxx_wd_timer2_hwmod,
3297         &omap3xxx_uart1_hwmod,
3298         &omap3xxx_uart2_hwmod,
3299         &omap3xxx_uart3_hwmod,
3300         &omap3xxx_uart4_hwmod,
3301         /* dss class */
3302         &omap3430es1_dss_core_hwmod,
3303         &omap3xxx_dss_core_hwmod,
3304         &omap3xxx_dss_dispc_hwmod,
3305         &omap3xxx_dss_dsi1_hwmod,
3306         &omap3xxx_dss_rfbi_hwmod,
3307         &omap3xxx_dss_venc_hwmod,
3308
3309         /* i2c class */
3310         &omap3xxx_i2c1_hwmod,
3311         &omap3xxx_i2c2_hwmod,
3312         &omap3xxx_i2c3_hwmod,
3313         &omap34xx_sr1_hwmod,
3314         &omap34xx_sr2_hwmod,
3315         &omap36xx_sr1_hwmod,
3316         &omap36xx_sr2_hwmod,
3317
3318
3319         /* gpio class */
3320         &omap3xxx_gpio1_hwmod,
3321         &omap3xxx_gpio2_hwmod,
3322         &omap3xxx_gpio3_hwmod,
3323         &omap3xxx_gpio4_hwmod,
3324         &omap3xxx_gpio5_hwmod,
3325         &omap3xxx_gpio6_hwmod,
3326
3327         /* dma_system class*/
3328         &omap3xxx_dma_system_hwmod,
3329
3330         /* mcbsp class */
3331         &omap3xxx_mcbsp1_hwmod,
3332         &omap3xxx_mcbsp2_hwmod,
3333         &omap3xxx_mcbsp3_hwmod,
3334         &omap3xxx_mcbsp4_hwmod,
3335         &omap3xxx_mcbsp5_hwmod,
3336         &omap3xxx_mcbsp2_sidetone_hwmod,
3337         &omap3xxx_mcbsp3_sidetone_hwmod,
3338
3339         /* mailbox class */
3340         &omap3xxx_mailbox_hwmod,
3341
3342         /* mcspi class */
3343         &omap34xx_mcspi1,
3344         &omap34xx_mcspi2,
3345         &omap34xx_mcspi3,
3346         &omap34xx_mcspi4,
3347
3348         /* usbotg class */
3349         &omap3xxx_usbhsotg_hwmod,
3350
3351         /* usbotg for am35x */
3352         &am35xx_usbhsotg_hwmod,
3353
3354         NULL,
3355 };
3356
3357 int __init omap3xxx_hwmod_init(void)
3358 {
3359         return omap_hwmod_register(omap3xxx_hwmods);
3360 }