arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106         { .irq = -1 }
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115         { }
 116 };
 117
 118 /* MPU -> L3 interface */
 119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 120         .master   = &omap3xxx_mpu_hwmod,
 121         .slave    = &omap3xxx_l3_main_hwmod,
 122         .addr     = omap3xxx_l3_main_addrs,
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 194         .master         = &omap3xxx_l4_core_hwmod,
 195         .slave          = &omap3xxx_mmc1_hwmod,
 196         .clk            = "mmchs1_ick",
 197         .addr           = omap2430_mmc1_addr_space,
 198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 199         .flags          = OMAP_FIREWALL_L4
 200 };
 201
 202 /* L4 CORE -> MMC2 interface */
 203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 204         .master         = &omap3xxx_l4_core_hwmod,
 205         .slave          = &omap3xxx_mmc2_hwmod,
 206         .clk            = "mmchs2_ick",
 207         .addr           = omap2430_mmc2_addr_space,
 208         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 209         .flags          = OMAP_FIREWALL_L4
 210 };
 211
 212 /* L4 CORE -> MMC3 interface */
 213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 214         {
 215                 .pa_start       = 0x480ad000,
 216                 .pa_end         = 0x480ad1ff,
 217                 .flags          = ADDR_TYPE_RT,
 218         },
 219         { }
 220 };
 221
 222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 223         .master         = &omap3xxx_l4_core_hwmod,
 224         .slave          = &omap3xxx_mmc3_hwmod,
 225         .clk            = "mmchs3_ick",
 226         .addr           = omap3xxx_mmc3_addr_space,
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228         .flags          = OMAP_FIREWALL_L4
 229 };
 230
 231 /* L4 CORE -> UART1 interface */
 232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 233         {
 234                 .pa_start       = OMAP3_UART1_BASE,
 235                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 236                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 237         },
 238         { }
 239 };
 240
 241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 242         .master         = &omap3xxx_l4_core_hwmod,
 243         .slave          = &omap3xxx_uart1_hwmod,
 244         .clk            = "uart1_ick",
 245         .addr           = omap3xxx_uart1_addr_space,
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* L4 CORE -> UART2 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART2_BASE,
 253                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256         { }
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart2_hwmod,
 262         .clk            = "uart2_ick",
 263         .addr           = omap3xxx_uart2_addr_space,
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 PER -> UART3 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART3_BASE,
 271                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274         { }
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 278         .master         = &omap3xxx_l4_per_hwmod,
 279         .slave          = &omap3xxx_uart3_hwmod,
 280         .clk            = "uart3_ick",
 281         .addr           = omap3xxx_uart3_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART4 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART4_BASE,
 289                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292         { }
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart4_hwmod,
 298         .clk            = "uart4_ick",
 299         .addr           = omap3xxx_uart4_addr_space,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 CORE -> I2C1 interface */
 304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 305         .master         = &omap3xxx_l4_core_hwmod,
 306         .slave          = &omap3xxx_i2c1_hwmod,
 307         .clk            = "i2c1_ick",
 308         .addr           = omap2_i2c1_addr_space,
 309         .fw = {
 310                 .omap2 = {
 311                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 312                         .l4_prot_group = 7,
 313                         .flags  = OMAP_FIREWALL_L4,
 314                 }
 315         },
 316         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 317 };
 318
 319 /* L4 CORE -> I2C2 interface */
 320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 321         .master         = &omap3xxx_l4_core_hwmod,
 322         .slave          = &omap3xxx_i2c2_hwmod,
 323         .clk            = "i2c2_ick",
 324         .addr           = omap2_i2c2_addr_space,
 325         .fw = {
 326                 .omap2 = {
 327                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 328                         .l4_prot_group = 7,
 329                         .flags = OMAP_FIREWALL_L4,
 330                 }
 331         },
 332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 333 };
 334
 335 /* L4 CORE -> I2C3 interface */
 336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 337         {
 338                 .pa_start       = 0x48060000,
 339                 .pa_end         = 0x48060000 + SZ_128 - 1,
 340                 .flags          = ADDR_TYPE_RT,
 341         },
 342         { }
 343 };
 344
 345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 346         .master         = &omap3xxx_l4_core_hwmod,
 347         .slave          = &omap3xxx_i2c3_hwmod,
 348         .clk            = "i2c3_ick",
 349         .addr           = omap3xxx_i2c3_addr_space,
 350         .fw = {
 351                 .omap2 = {
 352                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 353                         .l4_prot_group = 7,
 354                         .flags = OMAP_FIREWALL_L4,
 355                 }
 356         },
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* L4 CORE -> SR1 interface */
 361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 362         {
 363                 .pa_start       = OMAP34XX_SR1_BASE,
 364                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 365                 .flags          = ADDR_TYPE_RT,
 366         },
 367         { }
 368 };
 369
 370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 371         .master         = &omap3xxx_l4_core_hwmod,
 372         .slave          = &omap34xx_sr1_hwmod,
 373         .clk            = "sr_l4_ick",
 374         .addr           = omap3_sr1_addr_space,
 375         .user           = OCP_USER_MPU,
 376 };
 377
 378 /* L4 CORE -> SR1 interface */
 379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 380         {
 381                 .pa_start       = OMAP34XX_SR2_BASE,
 382                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 383                 .flags          = ADDR_TYPE_RT,
 384         },
 385         { }
 386 };
 387
 388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 389         .master         = &omap3xxx_l4_core_hwmod,
 390         .slave          = &omap34xx_sr2_hwmod,
 391         .clk            = "sr_l4_ick",
 392         .addr           = omap3_sr2_addr_space,
 393         .user           = OCP_USER_MPU,
 394 };
 395
 396 /*
 397 * usbhsotg interface data
 398 */
 399
 400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 401         {
 402                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 403                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 404                 .flags          = ADDR_TYPE_RT
 405         },
 406         { }
 407 };
 408
 409 /* l4_core -> usbhsotg  */
 410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 411         .master         = &omap3xxx_l4_core_hwmod,
 412         .slave          = &omap3xxx_usbhsotg_hwmod,
 413         .clk            = "l4_ick",
 414         .addr           = omap3xxx_usbhsotg_addrs,
 415         .user           = OCP_USER_MPU,
 416 };
 417
 418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 419         &omap3xxx_usbhsotg__l3,
 420 };
 421
 422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 423         &omap3xxx_l4_core__usbhsotg,
 424 };
 425
 426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 427         {
 428                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 429                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 430                 .flags          = ADDR_TYPE_RT
 431         },
 432         { }
 433 };
 434
 435 /* l4_core -> usbhsotg  */
 436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 437         .master         = &omap3xxx_l4_core_hwmod,
 438         .slave          = &am35xx_usbhsotg_hwmod,
 439         .clk            = "l4_ick",
 440         .addr           = am35xx_usbhsotg_addrs,
 441         .user           = OCP_USER_MPU,
 442 };
 443
 444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 445         &am35xx_usbhsotg__l3,
 446 };
 447
 448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 449         &am35xx_l4_core__usbhsotg,
 450 };
 451 /* Slave interfaces on the L4_CORE interconnect */
 452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 453         &omap3xxx_l3_main__l4_core,
 454 };
 455
 456 /* L4 CORE */
 457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 458         .name           = "l4_core",
 459         .class          = &l4_hwmod_class,
 460         .slaves         = omap3xxx_l4_core_slaves,
 461         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 462         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 463         .flags          = HWMOD_NO_IDLEST,
 464 };
 465
 466 /* Slave interfaces on the L4_PER interconnect */
 467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 468         &omap3xxx_l3_main__l4_per,
 469 };
 470
 471 /* L4 PER */
 472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 473         .name           = "l4_per",
 474         .class          = &l4_hwmod_class,
 475         .slaves         = omap3xxx_l4_per_slaves,
 476         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 477         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 478         .flags          = HWMOD_NO_IDLEST,
 479 };
 480
 481 /* Slave interfaces on the L4_WKUP interconnect */
 482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 483         &omap3xxx_l4_core__l4_wkup,
 484 };
 485
 486 /* L4 WKUP */
 487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 488         .name           = "l4_wkup",
 489         .class          = &l4_hwmod_class,
 490         .slaves         = omap3xxx_l4_wkup_slaves,
 491         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 492         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 493         .flags          = HWMOD_NO_IDLEST,
 494 };
 495
 496 /* Master interfaces on the MPU device */
 497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 498         &omap3xxx_mpu__l3_main,
 499 };
 500
 501 /* MPU */
 502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 503         .name           = "mpu",
 504         .class          = &mpu_hwmod_class,
 505         .main_clk       = "arm_fck",
 506         .masters        = omap3xxx_mpu_masters,
 507         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 508         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 509 };
 510
 511 /*
 512  * IVA2_2 interface data
 513  */
 514
 515 /* IVA2 <- L3 interface */
 516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 517         .master         = &omap3xxx_l3_main_hwmod,
 518         .slave          = &omap3xxx_iva_hwmod,
 519         .clk            = "iva2_ck",
 520         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 521 };
 522
 523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 524         &omap3xxx_l3__iva,
 525 };
 526
 527 /*
 528  * IVA2 (IVA2)
 529  */
 530
 531 static struct omap_hwmod omap3xxx_iva_hwmod = {
 532         .name           = "iva",
 533         .class          = &iva_hwmod_class,
 534         .masters        = omap3xxx_iva_masters,
 535         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 536         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 537 };
 538
 539 /* timer class */
 540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 541         .rev_offs       = 0x0000,
 542         .sysc_offs      = 0x0010,
 543         .syss_offs      = 0x0014,
 544         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 545                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 546                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 547         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 548         .sysc_fields    = &omap_hwmod_sysc_type1,
 549 };
 550
 551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 552         .name = "timer",
 553         .sysc = &omap3xxx_timer_1ms_sysc,
 554         .rev = OMAP_TIMER_IP_VERSION_1,
 555 };
 556
 557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 558         .rev_offs       = 0x0000,
 559         .sysc_offs      = 0x0010,
 560         .syss_offs      = 0x0014,
 561         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 562                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 563         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 564         .sysc_fields    = &omap_hwmod_sysc_type1,
 565 };
 566
 567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 568         .name = "timer",
 569         .sysc = &omap3xxx_timer_sysc,
 570         .rev =  OMAP_TIMER_IP_VERSION_1,
 571 };
 572
 573 /* timer1 */
 574 static struct omap_hwmod omap3xxx_timer1_hwmod;
 575
 576 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 577         {
 578                 .pa_start       = 0x48318000,
 579                 .pa_end         = 0x48318000 + SZ_1K - 1,
 580                 .flags          = ADDR_TYPE_RT
 581         },
 582         { }
 583 };
 584
 585 /* l4_wkup -> timer1 */
 586 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 587         .master         = &omap3xxx_l4_wkup_hwmod,
 588         .slave          = &omap3xxx_timer1_hwmod,
 589         .clk            = "gpt1_ick",
 590         .addr           = omap3xxx_timer1_addrs,
 591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 592 };
 593
 594 /* timer1 slave port */
 595 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 596         &omap3xxx_l4_wkup__timer1,
 597 };
 598
 599 /* timer1 hwmod */
 600 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 601         .name           = "timer1",
 602         .mpu_irqs       = omap2_timer1_mpu_irqs,
 603         .main_clk       = "gpt1_fck",
 604         .prcm           = {
 605                 .omap2 = {
 606                         .prcm_reg_id = 1,
 607                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 608                         .module_offs = WKUP_MOD,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 611                 },
 612         },
 613         .slaves         = omap3xxx_timer1_slaves,
 614         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 615         .class          = &omap3xxx_timer_1ms_hwmod_class,
 616         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 617 };
 618
 619 /* timer2 */
 620 static struct omap_hwmod omap3xxx_timer2_hwmod;
 621
 622 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 623         {
 624                 .pa_start       = 0x49032000,
 625                 .pa_end         = 0x49032000 + SZ_1K - 1,
 626                 .flags          = ADDR_TYPE_RT
 627         },
 628         { }
 629 };
 630
 631 /* l4_per -> timer2 */
 632 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 633         .master         = &omap3xxx_l4_per_hwmod,
 634         .slave          = &omap3xxx_timer2_hwmod,
 635         .clk            = "gpt2_ick",
 636         .addr           = omap3xxx_timer2_addrs,
 637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 638 };
 639
 640 /* timer2 slave port */
 641 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 642         &omap3xxx_l4_per__timer2,
 643 };
 644
 645 /* timer2 hwmod */
 646 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 647         .name           = "timer2",
 648         .mpu_irqs       = omap2_timer2_mpu_irqs,
 649         .main_clk       = "gpt2_fck",
 650         .prcm           = {
 651                 .omap2 = {
 652                         .prcm_reg_id = 1,
 653                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 654                         .module_offs = OMAP3430_PER_MOD,
 655                         .idlest_reg_id = 1,
 656                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 657                 },
 658         },
 659         .slaves         = omap3xxx_timer2_slaves,
 660         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 661         .class          = &omap3xxx_timer_1ms_hwmod_class,
 662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 663 };
 664
 665 /* timer3 */
 666 static struct omap_hwmod omap3xxx_timer3_hwmod;
 667
 668 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 669         {
 670                 .pa_start       = 0x49034000,
 671                 .pa_end         = 0x49034000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674         { }
 675 };
 676
 677 /* l4_per -> timer3 */
 678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 679         .master         = &omap3xxx_l4_per_hwmod,
 680         .slave          = &omap3xxx_timer3_hwmod,
 681         .clk            = "gpt3_ick",
 682         .addr           = omap3xxx_timer3_addrs,
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer3 slave port */
 687 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 688         &omap3xxx_l4_per__timer3,
 689 };
 690
 691 /* timer3 hwmod */
 692 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 693         .name           = "timer3",
 694         .mpu_irqs       = omap2_timer3_mpu_irqs,
 695         .main_clk       = "gpt3_fck",
 696         .prcm           = {
 697                 .omap2 = {
 698                         .prcm_reg_id = 1,
 699                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 700                         .module_offs = OMAP3430_PER_MOD,
 701                         .idlest_reg_id = 1,
 702                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 703                 },
 704         },
 705         .slaves         = omap3xxx_timer3_slaves,
 706         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 707         .class          = &omap3xxx_timer_hwmod_class,
 708         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 709 };
 710
 711 /* timer4 */
 712 static struct omap_hwmod omap3xxx_timer4_hwmod;
 713
 714 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 715         {
 716                 .pa_start       = 0x49036000,
 717                 .pa_end         = 0x49036000 + SZ_1K - 1,
 718                 .flags          = ADDR_TYPE_RT
 719         },
 720         { }
 721 };
 722
 723 /* l4_per -> timer4 */
 724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 725         .master         = &omap3xxx_l4_per_hwmod,
 726         .slave          = &omap3xxx_timer4_hwmod,
 727         .clk            = "gpt4_ick",
 728         .addr           = omap3xxx_timer4_addrs,
 729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 730 };
 731
 732 /* timer4 slave port */
 733 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 734         &omap3xxx_l4_per__timer4,
 735 };
 736
 737 /* timer4 hwmod */
 738 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 739         .name           = "timer4",
 740         .mpu_irqs       = omap2_timer4_mpu_irqs,
 741         .main_clk       = "gpt4_fck",
 742         .prcm           = {
 743                 .omap2 = {
 744                         .prcm_reg_id = 1,
 745                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 746                         .module_offs = OMAP3430_PER_MOD,
 747                         .idlest_reg_id = 1,
 748                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 749                 },
 750         },
 751         .slaves         = omap3xxx_timer4_slaves,
 752         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 753         .class          = &omap3xxx_timer_hwmod_class,
 754         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 755 };
 756
 757 /* timer5 */
 758 static struct omap_hwmod omap3xxx_timer5_hwmod;
 759
 760 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 761         {
 762                 .pa_start       = 0x49038000,
 763                 .pa_end         = 0x49038000 + SZ_1K - 1,
 764                 .flags          = ADDR_TYPE_RT
 765         },
 766         { }
 767 };
 768
 769 /* l4_per -> timer5 */
 770 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 771         .master         = &omap3xxx_l4_per_hwmod,
 772         .slave          = &omap3xxx_timer5_hwmod,
 773         .clk            = "gpt5_ick",
 774         .addr           = omap3xxx_timer5_addrs,
 775         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 776 };
 777
 778 /* timer5 slave port */
 779 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 780         &omap3xxx_l4_per__timer5,
 781 };
 782
 783 /* timer5 hwmod */
 784 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 785         .name           = "timer5",
 786         .mpu_irqs       = omap2_timer5_mpu_irqs,
 787         .main_clk       = "gpt5_fck",
 788         .prcm           = {
 789                 .omap2 = {
 790                         .prcm_reg_id = 1,
 791                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 792                         .module_offs = OMAP3430_PER_MOD,
 793                         .idlest_reg_id = 1,
 794                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 795                 },
 796         },
 797         .slaves         = omap3xxx_timer5_slaves,
 798         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 799         .class          = &omap3xxx_timer_hwmod_class,
 800         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 801 };
 802
 803 /* timer6 */
 804 static struct omap_hwmod omap3xxx_timer6_hwmod;
 805
 806 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 807         {
 808                 .pa_start       = 0x4903A000,
 809                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 810                 .flags          = ADDR_TYPE_RT
 811         },
 812         { }
 813 };
 814
 815 /* l4_per -> timer6 */
 816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 817         .master         = &omap3xxx_l4_per_hwmod,
 818         .slave          = &omap3xxx_timer6_hwmod,
 819         .clk            = "gpt6_ick",
 820         .addr           = omap3xxx_timer6_addrs,
 821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 822 };
 823
 824 /* timer6 slave port */
 825 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 826         &omap3xxx_l4_per__timer6,
 827 };
 828
 829 /* timer6 hwmod */
 830 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 831         .name           = "timer6",
 832         .mpu_irqs       = omap2_timer6_mpu_irqs,
 833         .main_clk       = "gpt6_fck",
 834         .prcm           = {
 835                 .omap2 = {
 836                         .prcm_reg_id = 1,
 837                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 838                         .module_offs = OMAP3430_PER_MOD,
 839                         .idlest_reg_id = 1,
 840                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 841                 },
 842         },
 843         .slaves         = omap3xxx_timer6_slaves,
 844         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 845         .class          = &omap3xxx_timer_hwmod_class,
 846         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 847 };
 848
 849 /* timer7 */
 850 static struct omap_hwmod omap3xxx_timer7_hwmod;
 851
 852 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 853         {
 854                 .pa_start       = 0x4903C000,
 855                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 856                 .flags          = ADDR_TYPE_RT
 857         },
 858         { }
 859 };
 860
 861 /* l4_per -> timer7 */
 862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 863         .master         = &omap3xxx_l4_per_hwmod,
 864         .slave          = &omap3xxx_timer7_hwmod,
 865         .clk            = "gpt7_ick",
 866         .addr           = omap3xxx_timer7_addrs,
 867         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 868 };
 869
 870 /* timer7 slave port */
 871 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 872         &omap3xxx_l4_per__timer7,
 873 };
 874
 875 /* timer7 hwmod */
 876 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 877         .name           = "timer7",
 878         .mpu_irqs       = omap2_timer7_mpu_irqs,
 879         .main_clk       = "gpt7_fck",
 880         .prcm           = {
 881                 .omap2 = {
 882                         .prcm_reg_id = 1,
 883                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 884                         .module_offs = OMAP3430_PER_MOD,
 885                         .idlest_reg_id = 1,
 886                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 887                 },
 888         },
 889         .slaves         = omap3xxx_timer7_slaves,
 890         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 891         .class          = &omap3xxx_timer_hwmod_class,
 892         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 893 };
 894
 895 /* timer8 */
 896 static struct omap_hwmod omap3xxx_timer8_hwmod;
 897
 898 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 899         {
 900                 .pa_start       = 0x4903E000,
 901                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 902                 .flags          = ADDR_TYPE_RT
 903         },
 904         { }
 905 };
 906
 907 /* l4_per -> timer8 */
 908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 909         .master         = &omap3xxx_l4_per_hwmod,
 910         .slave          = &omap3xxx_timer8_hwmod,
 911         .clk            = "gpt8_ick",
 912         .addr           = omap3xxx_timer8_addrs,
 913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 914 };
 915
 916 /* timer8 slave port */
 917 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 918         &omap3xxx_l4_per__timer8,
 919 };
 920
 921 /* timer8 hwmod */
 922 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 923         .name           = "timer8",
 924         .mpu_irqs       = omap2_timer8_mpu_irqs,
 925         .main_clk       = "gpt8_fck",
 926         .prcm           = {
 927                 .omap2 = {
 928                         .prcm_reg_id = 1,
 929                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 930                         .module_offs = OMAP3430_PER_MOD,
 931                         .idlest_reg_id = 1,
 932                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 933                 },
 934         },
 935         .slaves         = omap3xxx_timer8_slaves,
 936         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 937         .class          = &omap3xxx_timer_hwmod_class,
 938         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 939 };
 940
 941 /* timer9 */
 942 static struct omap_hwmod omap3xxx_timer9_hwmod;
 943
 944 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 945         {
 946                 .pa_start       = 0x49040000,
 947                 .pa_end         = 0x49040000 + SZ_1K - 1,
 948                 .flags          = ADDR_TYPE_RT
 949         },
 950         { }
 951 };
 952
 953 /* l4_per -> timer9 */
 954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 955         .master         = &omap3xxx_l4_per_hwmod,
 956         .slave          = &omap3xxx_timer9_hwmod,
 957         .clk            = "gpt9_ick",
 958         .addr           = omap3xxx_timer9_addrs,
 959         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 960 };
 961
 962 /* timer9 slave port */
 963 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 964         &omap3xxx_l4_per__timer9,
 965 };
 966
 967 /* timer9 hwmod */
 968 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 969         .name           = "timer9",
 970         .mpu_irqs       = omap2_timer9_mpu_irqs,
 971         .main_clk       = "gpt9_fck",
 972         .prcm           = {
 973                 .omap2 = {
 974                         .prcm_reg_id = 1,
 975                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 976                         .module_offs = OMAP3430_PER_MOD,
 977                         .idlest_reg_id = 1,
 978                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 979                 },
 980         },
 981         .slaves         = omap3xxx_timer9_slaves,
 982         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 983         .class          = &omap3xxx_timer_hwmod_class,
 984         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 985 };
 986
 987 /* timer10 */
 988 static struct omap_hwmod omap3xxx_timer10_hwmod;
 989
 990 /* l4_core -> timer10 */
 991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
 992         .master         = &omap3xxx_l4_core_hwmod,
 993         .slave          = &omap3xxx_timer10_hwmod,
 994         .clk            = "gpt10_ick",
 995         .addr           = omap2_timer10_addrs,
 996         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 997 };
 998
 999 /* timer10 slave port */
1000 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1001         &omap3xxx_l4_core__timer10,
1002 };
1003
1004 /* timer10 hwmod */
1005 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1006         .name           = "timer10",
1007         .mpu_irqs       = omap2_timer10_mpu_irqs,
1008         .main_clk       = "gpt10_fck",
1009         .prcm           = {
1010                 .omap2 = {
1011                         .prcm_reg_id = 1,
1012                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1013                         .module_offs = CORE_MOD,
1014                         .idlest_reg_id = 1,
1015                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1016                 },
1017         },
1018         .slaves         = omap3xxx_timer10_slaves,
1019         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1020         .class          = &omap3xxx_timer_1ms_hwmod_class,
1021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1022 };
1023
1024 /* timer11 */
1025 static struct omap_hwmod omap3xxx_timer11_hwmod;
1026
1027 /* l4_core -> timer11 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1029         .master         = &omap3xxx_l4_core_hwmod,
1030         .slave          = &omap3xxx_timer11_hwmod,
1031         .clk            = "gpt11_ick",
1032         .addr           = omap2_timer11_addrs,
1033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer11 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1038         &omap3xxx_l4_core__timer11,
1039 };
1040
1041 /* timer11 hwmod */
1042 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1043         .name           = "timer11",
1044         .mpu_irqs       = omap2_timer11_mpu_irqs,
1045         .main_clk       = "gpt11_fck",
1046         .prcm           = {
1047                 .omap2 = {
1048                         .prcm_reg_id = 1,
1049                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1050                         .module_offs = CORE_MOD,
1051                         .idlest_reg_id = 1,
1052                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1053                 },
1054         },
1055         .slaves         = omap3xxx_timer11_slaves,
1056         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1057         .class          = &omap3xxx_timer_hwmod_class,
1058         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1059 };
1060
1061 /* timer12*/
1062 static struct omap_hwmod omap3xxx_timer12_hwmod;
1063 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1064         { .irq = 95, },
1065         { .irq = -1 }
1066 };
1067
1068 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1069         {
1070                 .pa_start       = 0x48304000,
1071                 .pa_end         = 0x48304000 + SZ_1K - 1,
1072                 .flags          = ADDR_TYPE_RT
1073         },
1074         { }
1075 };
1076
1077 /* l4_core -> timer12 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1079         .master         = &omap3xxx_l4_core_hwmod,
1080         .slave          = &omap3xxx_timer12_hwmod,
1081         .clk            = "gpt12_ick",
1082         .addr           = omap3xxx_timer12_addrs,
1083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1084 };
1085
1086 /* timer12 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1088         &omap3xxx_l4_core__timer12,
1089 };
1090
1091 /* timer12 hwmod */
1092 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1093         .name           = "timer12",
1094         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1095         .main_clk       = "gpt12_fck",
1096         .prcm           = {
1097                 .omap2 = {
1098                         .prcm_reg_id = 1,
1099                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1100                         .module_offs = WKUP_MOD,
1101                         .idlest_reg_id = 1,
1102                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1103                 },
1104         },
1105         .slaves         = omap3xxx_timer12_slaves,
1106         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1107         .class          = &omap3xxx_timer_hwmod_class,
1108         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1109 };
1110
1111 /* l4_wkup -> wd_timer2 */
1112 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1113         {
1114                 .pa_start       = 0x48314000,
1115                 .pa_end         = 0x4831407f,
1116                 .flags          = ADDR_TYPE_RT
1117         },
1118         { }
1119 };
1120
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1122         .master         = &omap3xxx_l4_wkup_hwmod,
1123         .slave          = &omap3xxx_wd_timer2_hwmod,
1124         .clk            = "wdt2_ick",
1125         .addr           = omap3xxx_wd_timer2_addrs,
1126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1127 };
1128
1129 /*
1130  * 'wd_timer' class
1131  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1132  * overflow condition
1133  */
1134
1135 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1136         .rev_offs       = 0x0000,
1137         .sysc_offs      = 0x0010,
1138         .syss_offs      = 0x0014,
1139         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1140                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1141                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142                            SYSS_HAS_RESET_STATUS),
1143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144         .sysc_fields    = &omap_hwmod_sysc_type1,
1145 };
1146
1147 /* I2C common */
1148 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1149         .rev_offs       = 0x00,
1150         .sysc_offs      = 0x20,
1151         .syss_offs      = 0x10,
1152         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1153                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1154                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1155         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1156         .sysc_fields    = &omap_hwmod_sysc_type1,
1157 };
1158
1159 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1160         .name           = "wd_timer",
1161         .sysc           = &omap3xxx_wd_timer_sysc,
1162         .pre_shutdown   = &omap2_wd_timer_disable
1163 };
1164
1165 /* wd_timer2 */
1166 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1167         &omap3xxx_l4_wkup__wd_timer2,
1168 };
1169
1170 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1171         .name           = "wd_timer2",
1172         .class          = &omap3xxx_wd_timer_hwmod_class,
1173         .main_clk       = "wdt2_fck",
1174         .prcm           = {
1175                 .omap2 = {
1176                         .prcm_reg_id = 1,
1177                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1178                         .module_offs = WKUP_MOD,
1179                         .idlest_reg_id = 1,
1180                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1181                 },
1182         },
1183         .slaves         = omap3xxx_wd_timer2_slaves,
1184         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1185         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1186         /*
1187          * XXX: Use software supervised mode, HW supervised smartidle seems to
1188          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1189          */
1190         .flags          = HWMOD_SWSUP_SIDLE,
1191 };
1192
1193 /* UART common */
1194
1195 static struct omap_hwmod_class_sysconfig uart_sysc = {
1196         .rev_offs       = 0x50,
1197         .sysc_offs      = 0x54,
1198         .syss_offs      = 0x58,
1199         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1200                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1201                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1202         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1203         .sysc_fields    = &omap_hwmod_sysc_type1,
1204 };
1205
1206 static struct omap_hwmod_class uart_class = {
1207         .name = "uart",
1208         .sysc = &uart_sysc,
1209 };
1210
1211 /* UART1 */
1212
1213 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1214         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1215         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1216         { .dma_req = -1 }
1217 };
1218
1219 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1220         &omap3_l4_core__uart1,
1221 };
1222
1223 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1224         .name           = "uart1",
1225         .mpu_irqs       = omap2_uart1_mpu_irqs,
1226         .sdma_reqs      = uart1_sdma_reqs,
1227         .main_clk       = "uart1_fck",
1228         .prcm           = {
1229                 .omap2 = {
1230                         .module_offs = CORE_MOD,
1231                         .prcm_reg_id = 1,
1232                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1233                         .idlest_reg_id = 1,
1234                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1235                 },
1236         },
1237         .slaves         = omap3xxx_uart1_slaves,
1238         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1239         .class          = &uart_class,
1240         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1241 };
1242
1243 /* UART2 */
1244
1245 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1246         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1247         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1248         { .dma_req = -1 }
1249 };
1250
1251 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1252         &omap3_l4_core__uart2,
1253 };
1254
1255 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1256         .name           = "uart2",
1257         .mpu_irqs       = omap2_uart2_mpu_irqs,
1258         .sdma_reqs      = uart2_sdma_reqs,
1259         .main_clk       = "uart2_fck",
1260         .prcm           = {
1261                 .omap2 = {
1262                         .module_offs = CORE_MOD,
1263                         .prcm_reg_id = 1,
1264                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1265                         .idlest_reg_id = 1,
1266                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1267                 },
1268         },
1269         .slaves         = omap3xxx_uart2_slaves,
1270         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1271         .class          = &uart_class,
1272         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1273 };
1274
1275 /* UART3 */
1276
1277 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1278         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1279         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1280         { .dma_req = -1 }
1281 };
1282
1283 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1284         &omap3_l4_per__uart3,
1285 };
1286
1287 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1288         .name           = "uart3",
1289         .mpu_irqs       = omap2_uart3_mpu_irqs,
1290         .sdma_reqs      = uart3_sdma_reqs,
1291         .main_clk       = "uart3_fck",
1292         .prcm           = {
1293                 .omap2 = {
1294                         .module_offs = OMAP3430_PER_MOD,
1295                         .prcm_reg_id = 1,
1296                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1297                         .idlest_reg_id = 1,
1298                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1299                 },
1300         },
1301         .slaves         = omap3xxx_uart3_slaves,
1302         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1303         .class          = &uart_class,
1304         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1305 };
1306
1307 /* UART4 */
1308
1309 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1310         { .irq = INT_36XX_UART4_IRQ, },
1311         { .irq = -1 }
1312 };
1313
1314 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1315         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1316         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1317         { .dma_req = -1 }
1318 };
1319
1320 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1321         &omap3_l4_per__uart4,
1322 };
1323
1324 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1325         .name           = "uart4",
1326         .mpu_irqs       = uart4_mpu_irqs,
1327         .sdma_reqs      = uart4_sdma_reqs,
1328         .main_clk       = "uart4_fck",
1329         .prcm           = {
1330                 .omap2 = {
1331                         .module_offs = OMAP3430_PER_MOD,
1332                         .prcm_reg_id = 1,
1333                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1334                         .idlest_reg_id = 1,
1335                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1336                 },
1337         },
1338         .slaves         = omap3xxx_uart4_slaves,
1339         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1340         .class          = &uart_class,
1341         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1342 };
1343
1344 static struct omap_hwmod_class i2c_class = {
1345         .name = "i2c",
1346         .sysc = &i2c_sysc,
1347 };
1348
1349 /*
1350  * 'dss' class
1351  * display sub-system
1352  */
1353
1354 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1355         .rev_offs       = 0x0000,
1356         .sysc_offs      = 0x0010,
1357         .syss_offs      = 0x0014,
1358         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1359         .sysc_fields    = &omap_hwmod_sysc_type1,
1360 };
1361
1362 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1363         .name = "dss",
1364         .sysc = &omap3xxx_dss_sysc,
1365 };
1366
1367 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1368         { .name = "dispc", .dma_req = 5 },
1369         { .name = "dsi1", .dma_req = 74 },
1370         { .dma_req = -1 }
1371 };
1372
1373 /* dss */
1374 /* dss master ports */
1375 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1376         &omap3xxx_dss__l3,
1377 };
1378
1379 /* l4_core -> dss */
1380 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1381         .master         = &omap3xxx_l4_core_hwmod,
1382         .slave          = &omap3430es1_dss_core_hwmod,
1383         .clk            = "dss_ick",
1384         .addr           = omap2_dss_addrs,
1385         .fw = {
1386                 .omap2 = {
1387                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1388                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1389                         .flags  = OMAP_FIREWALL_L4,
1390                 }
1391         },
1392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1393 };
1394
1395 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1396         .master         = &omap3xxx_l4_core_hwmod,
1397         .slave          = &omap3xxx_dss_core_hwmod,
1398         .clk            = "dss_ick",
1399         .addr           = omap2_dss_addrs,
1400         .fw = {
1401                 .omap2 = {
1402                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1403                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1404                         .flags  = OMAP_FIREWALL_L4,
1405                 }
1406         },
1407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1408 };
1409
1410 /* dss slave ports */
1411 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1412         &omap3430es1_l4_core__dss,
1413 };
1414
1415 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1416         &omap3xxx_l4_core__dss,
1417 };
1418
1419 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1420         { .role = "tv_clk", .clk = "dss_tv_fck" },
1421         { .role = "video_clk", .clk = "dss_96m_fck" },
1422         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1423 };
1424
1425 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1426         .name           = "dss_core",
1427         .class          = &omap3xxx_dss_hwmod_class,
1428         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1429         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1430         .prcm           = {
1431                 .omap2 = {
1432                         .prcm_reg_id = 1,
1433                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1434                         .module_offs = OMAP3430_DSS_MOD,
1435                         .idlest_reg_id = 1,
1436                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1437                 },
1438         },
1439         .opt_clks       = dss_opt_clks,
1440         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1441         .slaves         = omap3430es1_dss_slaves,
1442         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1443         .masters        = omap3xxx_dss_masters,
1444         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1445         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1446         .flags          = HWMOD_NO_IDLEST,
1447 };
1448
1449 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1450         .name           = "dss_core",
1451         .class          = &omap3xxx_dss_hwmod_class,
1452         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1453         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1454         .prcm           = {
1455                 .omap2 = {
1456                         .prcm_reg_id = 1,
1457                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1458                         .module_offs = OMAP3430_DSS_MOD,
1459                         .idlest_reg_id = 1,
1460                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1461                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1462                 },
1463         },
1464         .opt_clks       = dss_opt_clks,
1465         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1466         .slaves         = omap3xxx_dss_slaves,
1467         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1468         .masters        = omap3xxx_dss_masters,
1469         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1470         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1471                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1472 };
1473
1474 /*
1475  * 'dispc' class
1476  * display controller
1477  */
1478
1479 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1480         .rev_offs       = 0x0000,
1481         .sysc_offs      = 0x0010,
1482         .syss_offs      = 0x0014,
1483         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1484                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1485                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1486         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1487                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1488         .sysc_fields    = &omap_hwmod_sysc_type1,
1489 };
1490
1491 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1492         .name = "dispc",
1493         .sysc = &omap3xxx_dispc_sysc,
1494 };
1495
1496 /* l4_core -> dss_dispc */
1497 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1498         .master         = &omap3xxx_l4_core_hwmod,
1499         .slave          = &omap3xxx_dss_dispc_hwmod,
1500         .clk            = "dss_ick",
1501         .addr           = omap2_dss_dispc_addrs,
1502         .fw = {
1503                 .omap2 = {
1504                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1505                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1506                         .flags  = OMAP_FIREWALL_L4,
1507                 }
1508         },
1509         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1510 };
1511
1512 /* dss_dispc slave ports */
1513 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1514         &omap3xxx_l4_core__dss_dispc,
1515 };
1516
1517 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1518         .name           = "dss_dispc",
1519         .class          = &omap3xxx_dispc_hwmod_class,
1520         .mpu_irqs       = omap2_dispc_irqs,
1521         .main_clk       = "dss1_alwon_fck",
1522         .prcm           = {
1523                 .omap2 = {
1524                         .prcm_reg_id = 1,
1525                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1526                         .module_offs = OMAP3430_DSS_MOD,
1527                 },
1528         },
1529         .slaves         = omap3xxx_dss_dispc_slaves,
1530         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1531         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1532                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1533                                 CHIP_GE_OMAP3630ES1_1),
1534         .flags          = HWMOD_NO_IDLEST,
1535 };
1536
1537 /*
1538  * 'dsi' class
1539  * display serial interface controller
1540  */
1541
1542 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1543         .name = "dsi",
1544 };
1545
1546 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1547         { .irq = 25 },
1548         { .irq = -1 }
1549 };
1550
1551 /* dss_dsi1 */
1552 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1553         {
1554                 .pa_start       = 0x4804FC00,
1555                 .pa_end         = 0x4804FFFF,
1556                 .flags          = ADDR_TYPE_RT
1557         },
1558         { }
1559 };
1560
1561 /* l4_core -> dss_dsi1 */
1562 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1563         .master         = &omap3xxx_l4_core_hwmod,
1564         .slave          = &omap3xxx_dss_dsi1_hwmod,
1565         .addr           = omap3xxx_dss_dsi1_addrs,
1566         .fw = {
1567                 .omap2 = {
1568                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1569                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1570                         .flags  = OMAP_FIREWALL_L4,
1571                 }
1572         },
1573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1574 };
1575
1576 /* dss_dsi1 slave ports */
1577 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1578         &omap3xxx_l4_core__dss_dsi1,
1579 };
1580
1581 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1582         .name           = "dss_dsi1",
1583         .class          = &omap3xxx_dsi_hwmod_class,
1584         .mpu_irqs       = omap3xxx_dsi1_irqs,
1585         .main_clk       = "dss1_alwon_fck",
1586         .prcm           = {
1587                 .omap2 = {
1588                         .prcm_reg_id = 1,
1589                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1590                         .module_offs = OMAP3430_DSS_MOD,
1591                 },
1592         },
1593         .slaves         = omap3xxx_dss_dsi1_slaves,
1594         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1595         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1596                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1597                                 CHIP_GE_OMAP3630ES1_1),
1598         .flags          = HWMOD_NO_IDLEST,
1599 };
1600
1601 /*
1602  * 'rfbi' class
1603  * remote frame buffer interface
1604  */
1605
1606 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1607         .rev_offs       = 0x0000,
1608         .sysc_offs      = 0x0010,
1609         .syss_offs      = 0x0014,
1610         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1611                            SYSC_HAS_AUTOIDLE),
1612         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1613         .sysc_fields    = &omap_hwmod_sysc_type1,
1614 };
1615
1616 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1617         .name = "rfbi",
1618         .sysc = &omap3xxx_rfbi_sysc,
1619 };
1620
1621 /* l4_core -> dss_rfbi */
1622 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1623         .master         = &omap3xxx_l4_core_hwmod,
1624         .slave          = &omap3xxx_dss_rfbi_hwmod,
1625         .clk            = "dss_ick",
1626         .addr           = omap2_dss_rfbi_addrs,
1627         .fw = {
1628                 .omap2 = {
1629                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1630                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1631                         .flags  = OMAP_FIREWALL_L4,
1632                 }
1633         },
1634         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1635 };
1636
1637 /* dss_rfbi slave ports */
1638 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1639         &omap3xxx_l4_core__dss_rfbi,
1640 };
1641
1642 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1643         .name           = "dss_rfbi",
1644         .class          = &omap3xxx_rfbi_hwmod_class,
1645         .main_clk       = "dss1_alwon_fck",
1646         .prcm           = {
1647                 .omap2 = {
1648                         .prcm_reg_id = 1,
1649                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1650                         .module_offs = OMAP3430_DSS_MOD,
1651                 },
1652         },
1653         .slaves         = omap3xxx_dss_rfbi_slaves,
1654         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1655         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1656                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1657                                 CHIP_GE_OMAP3630ES1_1),
1658         .flags          = HWMOD_NO_IDLEST,
1659 };
1660
1661 /*
1662  * 'venc' class
1663  * video encoder
1664  */
1665
1666 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1667         .name = "venc",
1668 };
1669
1670 /* l4_core -> dss_venc */
1671 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1672         .master         = &omap3xxx_l4_core_hwmod,
1673         .slave          = &omap3xxx_dss_venc_hwmod,
1674         .clk            = "dss_tv_fck",
1675         .addr           = omap2_dss_venc_addrs,
1676         .fw = {
1677                 .omap2 = {
1678                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1679                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1680                         .flags  = OMAP_FIREWALL_L4,
1681                 }
1682         },
1683         .flags          = OCPIF_SWSUP_IDLE,
1684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1685 };
1686
1687 /* dss_venc slave ports */
1688 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1689         &omap3xxx_l4_core__dss_venc,
1690 };
1691
1692 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1693         .name           = "dss_venc",
1694         .class          = &omap3xxx_venc_hwmod_class,
1695         .main_clk       = "dss1_alwon_fck",
1696         .prcm           = {
1697                 .omap2 = {
1698                         .prcm_reg_id = 1,
1699                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1700                         .module_offs = OMAP3430_DSS_MOD,
1701                 },
1702         },
1703         .slaves         = omap3xxx_dss_venc_slaves,
1704         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1705         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1706                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1707                                 CHIP_GE_OMAP3630ES1_1),
1708         .flags          = HWMOD_NO_IDLEST,
1709 };
1710
1711 /* I2C1 */
1712
1713 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1714         .fifo_depth     = 8, /* bytes */
1715 };
1716
1717 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1718         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1719         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1720         { .dma_req = -1 }
1721 };
1722
1723 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1724         &omap3_l4_core__i2c1,
1725 };
1726
1727 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1728         .name           = "i2c1",
1729         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1730         .sdma_reqs      = i2c1_sdma_reqs,
1731         .main_clk       = "i2c1_fck",
1732         .prcm           = {
1733                 .omap2 = {
1734                         .module_offs = CORE_MOD,
1735                         .prcm_reg_id = 1,
1736                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1737                         .idlest_reg_id = 1,
1738                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1739                 },
1740         },
1741         .slaves         = omap3xxx_i2c1_slaves,
1742         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1743         .class          = &i2c_class,
1744         .dev_attr       = &i2c1_dev_attr,
1745         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1746 };
1747
1748 /* I2C2 */
1749
1750 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1751         .fifo_depth     = 8, /* bytes */
1752 };
1753
1754 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1755         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1756         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1757         { .dma_req = -1 }
1758 };
1759
1760 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1761         &omap3_l4_core__i2c2,
1762 };
1763
1764 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1765         .name           = "i2c2",
1766         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1767         .sdma_reqs      = i2c2_sdma_reqs,
1768         .main_clk       = "i2c2_fck",
1769         .prcm           = {
1770                 .omap2 = {
1771                         .module_offs = CORE_MOD,
1772                         .prcm_reg_id = 1,
1773                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1774                         .idlest_reg_id = 1,
1775                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1776                 },
1777         },
1778         .slaves         = omap3xxx_i2c2_slaves,
1779         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1780         .class          = &i2c_class,
1781         .dev_attr       = &i2c2_dev_attr,
1782         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1783 };
1784
1785 /* I2C3 */
1786
1787 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1788         .fifo_depth     = 64, /* bytes */
1789 };
1790
1791 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1792         { .irq = INT_34XX_I2C3_IRQ, },
1793         { .irq = -1 }
1794 };
1795
1796 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1797         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1798         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1799         { .dma_req = -1 }
1800 };
1801
1802 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1803         &omap3_l4_core__i2c3,
1804 };
1805
1806 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1807         .name           = "i2c3",
1808         .mpu_irqs       = i2c3_mpu_irqs,
1809         .sdma_reqs      = i2c3_sdma_reqs,
1810         .main_clk       = "i2c3_fck",
1811         .prcm           = {
1812                 .omap2 = {
1813                         .module_offs = CORE_MOD,
1814                         .prcm_reg_id = 1,
1815                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1816                         .idlest_reg_id = 1,
1817                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1818                 },
1819         },
1820         .slaves         = omap3xxx_i2c3_slaves,
1821         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1822         .class          = &i2c_class,
1823         .dev_attr       = &i2c3_dev_attr,
1824         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1825 };
1826
1827 /* l4_wkup -> gpio1 */
1828 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1829         {
1830                 .pa_start       = 0x48310000,
1831                 .pa_end         = 0x483101ff,
1832                 .flags          = ADDR_TYPE_RT
1833         },
1834         { }
1835 };
1836
1837 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1838         .master         = &omap3xxx_l4_wkup_hwmod,
1839         .slave          = &omap3xxx_gpio1_hwmod,
1840         .addr           = omap3xxx_gpio1_addrs,
1841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1842 };
1843
1844 /* l4_per -> gpio2 */
1845 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1846         {
1847                 .pa_start       = 0x49050000,
1848                 .pa_end         = 0x490501ff,
1849                 .flags          = ADDR_TYPE_RT
1850         },
1851         { }
1852 };
1853
1854 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1855         .master         = &omap3xxx_l4_per_hwmod,
1856         .slave          = &omap3xxx_gpio2_hwmod,
1857         .addr           = omap3xxx_gpio2_addrs,
1858         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1859 };
1860
1861 /* l4_per -> gpio3 */
1862 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1863         {
1864                 .pa_start       = 0x49052000,
1865                 .pa_end         = 0x490521ff,
1866                 .flags          = ADDR_TYPE_RT
1867         },
1868         { }
1869 };
1870
1871 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1872         .master         = &omap3xxx_l4_per_hwmod,
1873         .slave          = &omap3xxx_gpio3_hwmod,
1874         .addr           = omap3xxx_gpio3_addrs,
1875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1876 };
1877
1878 /* l4_per -> gpio4 */
1879 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1880         {
1881                 .pa_start       = 0x49054000,
1882                 .pa_end         = 0x490541ff,
1883                 .flags          = ADDR_TYPE_RT
1884         },
1885         { }
1886 };
1887
1888 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1889         .master         = &omap3xxx_l4_per_hwmod,
1890         .slave          = &omap3xxx_gpio4_hwmod,
1891         .addr           = omap3xxx_gpio4_addrs,
1892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1893 };
1894
1895 /* l4_per -> gpio5 */
1896 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1897         {
1898                 .pa_start       = 0x49056000,
1899                 .pa_end         = 0x490561ff,
1900                 .flags          = ADDR_TYPE_RT
1901         },
1902         { }
1903 };
1904
1905 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1906         .master         = &omap3xxx_l4_per_hwmod,
1907         .slave          = &omap3xxx_gpio5_hwmod,
1908         .addr           = omap3xxx_gpio5_addrs,
1909         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1910 };
1911
1912 /* l4_per -> gpio6 */
1913 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1914         {
1915                 .pa_start       = 0x49058000,
1916                 .pa_end         = 0x490581ff,
1917                 .flags          = ADDR_TYPE_RT
1918         },
1919         { }
1920 };
1921
1922 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1923         .master         = &omap3xxx_l4_per_hwmod,
1924         .slave          = &omap3xxx_gpio6_hwmod,
1925         .addr           = omap3xxx_gpio6_addrs,
1926         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1927 };
1928
1929 /*
1930  * 'gpio' class
1931  * general purpose io module
1932  */
1933
1934 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1935         .rev_offs       = 0x0000,
1936         .sysc_offs      = 0x0010,
1937         .syss_offs      = 0x0014,
1938         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1939                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1940                            SYSS_HAS_RESET_STATUS),
1941         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1942         .sysc_fields    = &omap_hwmod_sysc_type1,
1943 };
1944
1945 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1946         .name = "gpio",
1947         .sysc = &omap3xxx_gpio_sysc,
1948         .rev = 1,
1949 };
1950
1951 /* gpio_dev_attr*/
1952 static struct omap_gpio_dev_attr gpio_dev_attr = {
1953         .bank_width = 32,
1954         .dbck_flag = true,
1955 };
1956
1957 /* gpio1 */
1958 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1959         { .role = "dbclk", .clk = "gpio1_dbck", },
1960 };
1961
1962 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1963         &omap3xxx_l4_wkup__gpio1,
1964 };
1965
1966 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1967         .name           = "gpio1",
1968         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1969         .mpu_irqs       = omap2_gpio1_irqs,
1970         .main_clk       = "gpio1_ick",
1971         .opt_clks       = gpio1_opt_clks,
1972         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1973         .prcm           = {
1974                 .omap2 = {
1975                         .prcm_reg_id = 1,
1976                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1977                         .module_offs = WKUP_MOD,
1978                         .idlest_reg_id = 1,
1979                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1980                 },
1981         },
1982         .slaves         = omap3xxx_gpio1_slaves,
1983         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1984         .class          = &omap3xxx_gpio_hwmod_class,
1985         .dev_attr       = &gpio_dev_attr,
1986         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1987 };
1988
1989 /* gpio2 */
1990 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1991         { .role = "dbclk", .clk = "gpio2_dbck", },
1992 };
1993
1994 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1995         &omap3xxx_l4_per__gpio2,
1996 };
1997
1998 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1999         .name           = "gpio2",
2000         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2001         .mpu_irqs       = omap2_gpio2_irqs,
2002         .main_clk       = "gpio2_ick",
2003         .opt_clks       = gpio2_opt_clks,
2004         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
2005         .prcm           = {
2006                 .omap2 = {
2007                         .prcm_reg_id = 1,
2008                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2009                         .module_offs = OMAP3430_PER_MOD,
2010                         .idlest_reg_id = 1,
2011                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2012                 },
2013         },
2014         .slaves         = omap3xxx_gpio2_slaves,
2015         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2016         .class          = &omap3xxx_gpio_hwmod_class,
2017         .dev_attr       = &gpio_dev_attr,
2018         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2019 };
2020
2021 /* gpio3 */
2022 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2023         { .role = "dbclk", .clk = "gpio3_dbck", },
2024 };
2025
2026 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2027         &omap3xxx_l4_per__gpio3,
2028 };
2029
2030 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2031         .name           = "gpio3",
2032         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2033         .mpu_irqs       = omap2_gpio3_irqs,
2034         .main_clk       = "gpio3_ick",
2035         .opt_clks       = gpio3_opt_clks,
2036         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2037         .prcm           = {
2038                 .omap2 = {
2039                         .prcm_reg_id = 1,
2040                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2041                         .module_offs = OMAP3430_PER_MOD,
2042                         .idlest_reg_id = 1,
2043                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2044                 },
2045         },
2046         .slaves         = omap3xxx_gpio3_slaves,
2047         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2048         .class          = &omap3xxx_gpio_hwmod_class,
2049         .dev_attr       = &gpio_dev_attr,
2050         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2051 };
2052
2053 /* gpio4 */
2054 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2055         { .role = "dbclk", .clk = "gpio4_dbck", },
2056 };
2057
2058 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2059         &omap3xxx_l4_per__gpio4,
2060 };
2061
2062 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2063         .name           = "gpio4",
2064         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2065         .mpu_irqs       = omap2_gpio4_irqs,
2066         .main_clk       = "gpio4_ick",
2067         .opt_clks       = gpio4_opt_clks,
2068         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2069         .prcm           = {
2070                 .omap2 = {
2071                         .prcm_reg_id = 1,
2072                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2073                         .module_offs = OMAP3430_PER_MOD,
2074                         .idlest_reg_id = 1,
2075                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2076                 },
2077         },
2078         .slaves         = omap3xxx_gpio4_slaves,
2079         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2080         .class          = &omap3xxx_gpio_hwmod_class,
2081         .dev_attr       = &gpio_dev_attr,
2082         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2083 };
2084
2085 /* gpio5 */
2086 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2087         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2088         { .irq = -1 }
2089 };
2090
2091 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2092         { .role = "dbclk", .clk = "gpio5_dbck", },
2093 };
2094
2095 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2096         &omap3xxx_l4_per__gpio5,
2097 };
2098
2099 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2100         .name           = "gpio5",
2101         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2102         .mpu_irqs       = omap3xxx_gpio5_irqs,
2103         .main_clk       = "gpio5_ick",
2104         .opt_clks       = gpio5_opt_clks,
2105         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2106         .prcm           = {
2107                 .omap2 = {
2108                         .prcm_reg_id = 1,
2109                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2110                         .module_offs = OMAP3430_PER_MOD,
2111                         .idlest_reg_id = 1,
2112                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2113                 },
2114         },
2115         .slaves         = omap3xxx_gpio5_slaves,
2116         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2117         .class          = &omap3xxx_gpio_hwmod_class,
2118         .dev_attr       = &gpio_dev_attr,
2119         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2120 };
2121
2122 /* gpio6 */
2123 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2124         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2125         { .irq = -1 }
2126 };
2127
2128 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2129         { .role = "dbclk", .clk = "gpio6_dbck", },
2130 };
2131
2132 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2133         &omap3xxx_l4_per__gpio6,
2134 };
2135
2136 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2137         .name           = "gpio6",
2138         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2139         .mpu_irqs       = omap3xxx_gpio6_irqs,
2140         .main_clk       = "gpio6_ick",
2141         .opt_clks       = gpio6_opt_clks,
2142         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2143         .prcm           = {
2144                 .omap2 = {
2145                         .prcm_reg_id = 1,
2146                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2147                         .module_offs = OMAP3430_PER_MOD,
2148                         .idlest_reg_id = 1,
2149                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2150                 },
2151         },
2152         .slaves         = omap3xxx_gpio6_slaves,
2153         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2154         .class          = &omap3xxx_gpio_hwmod_class,
2155         .dev_attr       = &gpio_dev_attr,
2156         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2157 };
2158
2159 /* dma_system -> L3 */
2160 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2161         .master         = &omap3xxx_dma_system_hwmod,
2162         .slave          = &omap3xxx_l3_main_hwmod,
2163         .clk            = "core_l3_ick",
2164         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2165 };
2166
2167 /* dma attributes */
2168 static struct omap_dma_dev_attr dma_dev_attr = {
2169         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2170                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2171         .lch_count = 32,
2172 };
2173
2174 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2175         .rev_offs       = 0x0000,
2176         .sysc_offs      = 0x002c,
2177         .syss_offs      = 0x0028,
2178         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2179                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2180                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2181                            SYSS_HAS_RESET_STATUS),
2182         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2183                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2184         .sysc_fields    = &omap_hwmod_sysc_type1,
2185 };
2186
2187 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2188         .name = "dma",
2189         .sysc = &omap3xxx_dma_sysc,
2190 };
2191
2192 /* dma_system */
2193 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2194         {
2195                 .pa_start       = 0x48056000,
2196                 .pa_end         = 0x48056fff,
2197                 .flags          = ADDR_TYPE_RT
2198         },
2199         { }
2200 };
2201
2202 /* dma_system master ports */
2203 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2204         &omap3xxx_dma_system__l3,
2205 };
2206
2207 /* l4_cfg -> dma_system */
2208 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2209         .master         = &omap3xxx_l4_core_hwmod,
2210         .slave          = &omap3xxx_dma_system_hwmod,
2211         .clk            = "core_l4_ick",
2212         .addr           = omap3xxx_dma_system_addrs,
2213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* dma_system slave ports */
2217 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2218         &omap3xxx_l4_core__dma_system,
2219 };
2220
2221 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2222         .name           = "dma",
2223         .class          = &omap3xxx_dma_hwmod_class,
2224         .mpu_irqs       = omap2_dma_system_irqs,
2225         .main_clk       = "core_l3_ick",
2226         .prcm = {
2227                 .omap2 = {
2228                         .module_offs            = CORE_MOD,
2229                         .prcm_reg_id            = 1,
2230                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2231                         .idlest_reg_id          = 1,
2232                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2233                 },
2234         },
2235         .slaves         = omap3xxx_dma_system_slaves,
2236         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2237         .masters        = omap3xxx_dma_system_masters,
2238         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2239         .dev_attr       = &dma_dev_attr,
2240         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2241         .flags          = HWMOD_NO_IDLEST,
2242 };
2243
2244 /*
2245  * 'mcbsp' class
2246  * multi channel buffered serial port controller
2247  */
2248
2249 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2250         .sysc_offs      = 0x008c,
2251         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2252                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2253         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2254         .sysc_fields    = &omap_hwmod_sysc_type1,
2255         .clockact       = 0x2,
2256 };
2257
2258 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2259         .name = "mcbsp",
2260         .sysc = &omap3xxx_mcbsp_sysc,
2261         .rev  = MCBSP_CONFIG_TYPE3,
2262 };
2263
2264 /* mcbsp1 */
2265 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2266         { .name = "irq", .irq = 16 },
2267         { .name = "tx", .irq = 59 },
2268         { .name = "rx", .irq = 60 },
2269         { .irq = -1 }
2270 };
2271
2272 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2273         { .name = "rx", .dma_req = 32 },
2274         { .name = "tx", .dma_req = 31 },
2275         { .dma_req = -1 }
2276 };
2277
2278 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2279         {
2280                 .name           = "mpu",
2281                 .pa_start       = 0x48074000,
2282                 .pa_end         = 0x480740ff,
2283                 .flags          = ADDR_TYPE_RT
2284         },
2285         { }
2286 };
2287
2288 /* l4_core -> mcbsp1 */
2289 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2290         .master         = &omap3xxx_l4_core_hwmod,
2291         .slave          = &omap3xxx_mcbsp1_hwmod,
2292         .clk            = "mcbsp1_ick",
2293         .addr           = omap3xxx_mcbsp1_addrs,
2294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2295 };
2296
2297 /* mcbsp1 slave ports */
2298 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2299         &omap3xxx_l4_core__mcbsp1,
2300 };
2301
2302 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2303         .name           = "mcbsp1",
2304         .class          = &omap3xxx_mcbsp_hwmod_class,
2305         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2306         .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
2307         .main_clk       = "mcbsp1_fck",
2308         .prcm           = {
2309                 .omap2 = {
2310                         .prcm_reg_id = 1,
2311                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2312                         .module_offs = CORE_MOD,
2313                         .idlest_reg_id = 1,
2314                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2315                 },
2316         },
2317         .slaves         = omap3xxx_mcbsp1_slaves,
2318         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2319         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2320 };
2321
2322 /* mcbsp2 */
2323 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2324         { .name = "irq", .irq = 17 },
2325         { .name = "tx", .irq = 62 },
2326         { .name = "rx", .irq = 63 },
2327         { .irq = -1 }
2328 };
2329
2330 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2331         { .name = "rx", .dma_req = 34 },
2332         { .name = "tx", .dma_req = 33 },
2333         { .dma_req = -1 }
2334 };
2335
2336 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2337         {
2338                 .name           = "mpu",
2339                 .pa_start       = 0x49022000,
2340                 .pa_end         = 0x490220ff,
2341                 .flags          = ADDR_TYPE_RT
2342         },
2343         { }
2344 };
2345
2346 /* l4_per -> mcbsp2 */
2347 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2348         .master         = &omap3xxx_l4_per_hwmod,
2349         .slave          = &omap3xxx_mcbsp2_hwmod,
2350         .clk            = "mcbsp2_ick",
2351         .addr           = omap3xxx_mcbsp2_addrs,
2352
2353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2354 };
2355
2356 /* mcbsp2 slave ports */
2357 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2358         &omap3xxx_l4_per__mcbsp2,
2359 };
2360
2361 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2362         .sidetone       = "mcbsp2_sidetone",
2363 };
2364
2365 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2366         .name           = "mcbsp2",
2367         .class          = &omap3xxx_mcbsp_hwmod_class,
2368         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2369         .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
2370         .main_clk       = "mcbsp2_fck",
2371         .prcm           = {
2372                 .omap2 = {
2373                         .prcm_reg_id = 1,
2374                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2375                         .module_offs = OMAP3430_PER_MOD,
2376                         .idlest_reg_id = 1,
2377                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2378                 },
2379         },
2380         .slaves         = omap3xxx_mcbsp2_slaves,
2381         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2382         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2383         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2384 };
2385
2386 /* mcbsp3 */
2387 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2388         { .name = "irq", .irq = 22 },
2389         { .name = "tx", .irq = 89 },
2390         { .name = "rx", .irq = 90 },
2391         { .irq = -1 }
2392 };
2393
2394 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2395         { .name = "rx", .dma_req = 18 },
2396         { .name = "tx", .dma_req = 17 },
2397         { .dma_req = -1 }
2398 };
2399
2400 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2401         {
2402                 .name           = "mpu",
2403                 .pa_start       = 0x49024000,
2404                 .pa_end         = 0x490240ff,
2405                 .flags          = ADDR_TYPE_RT
2406         },
2407         { }
2408 };
2409
2410 /* l4_per -> mcbsp3 */
2411 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2412         .master         = &omap3xxx_l4_per_hwmod,
2413         .slave          = &omap3xxx_mcbsp3_hwmod,
2414         .clk            = "mcbsp3_ick",
2415         .addr           = omap3xxx_mcbsp3_addrs,
2416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2417 };
2418
2419 /* mcbsp3 slave ports */
2420 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2421         &omap3xxx_l4_per__mcbsp3,
2422 };
2423
2424 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2425         .sidetone       = "mcbsp3_sidetone",
2426 };
2427
2428 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2429         .name           = "mcbsp3",
2430         .class          = &omap3xxx_mcbsp_hwmod_class,
2431         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2432         .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
2433         .main_clk       = "mcbsp3_fck",
2434         .prcm           = {
2435                 .omap2 = {
2436                         .prcm_reg_id = 1,
2437                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2438                         .module_offs = OMAP3430_PER_MOD,
2439                         .idlest_reg_id = 1,
2440                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2441                 },
2442         },
2443         .slaves         = omap3xxx_mcbsp3_slaves,
2444         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2445         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2446         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2447 };
2448
2449 /* mcbsp4 */
2450 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2451         { .name = "irq", .irq = 23 },
2452         { .name = "tx", .irq = 54 },
2453         { .name = "rx", .irq = 55 },
2454         { .irq = -1 }
2455 };
2456
2457 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2458         { .name = "rx", .dma_req = 20 },
2459         { .name = "tx", .dma_req = 19 },
2460         { .dma_req = -1 }
2461 };
2462
2463 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2464         {
2465                 .name           = "mpu",
2466                 .pa_start       = 0x49026000,
2467                 .pa_end         = 0x490260ff,
2468                 .flags          = ADDR_TYPE_RT
2469         },
2470         { }
2471 };
2472
2473 /* l4_per -> mcbsp4 */
2474 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2475         .master         = &omap3xxx_l4_per_hwmod,
2476         .slave          = &omap3xxx_mcbsp4_hwmod,
2477         .clk            = "mcbsp4_ick",
2478         .addr           = omap3xxx_mcbsp4_addrs,
2479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2480 };
2481
2482 /* mcbsp4 slave ports */
2483 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2484         &omap3xxx_l4_per__mcbsp4,
2485 };
2486
2487 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2488         .name           = "mcbsp4",
2489         .class          = &omap3xxx_mcbsp_hwmod_class,
2490         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2491         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2492         .main_clk       = "mcbsp4_fck",
2493         .prcm           = {
2494                 .omap2 = {
2495                         .prcm_reg_id = 1,
2496                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2497                         .module_offs = OMAP3430_PER_MOD,
2498                         .idlest_reg_id = 1,
2499                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2500                 },
2501         },
2502         .slaves         = omap3xxx_mcbsp4_slaves,
2503         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2504         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2505 };
2506
2507 /* mcbsp5 */
2508 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2509         { .name = "irq", .irq = 27 },
2510         { .name = "tx", .irq = 81 },
2511         { .name = "rx", .irq = 82 },
2512         { .irq = -1 }
2513 };
2514
2515 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2516         { .name = "rx", .dma_req = 22 },
2517         { .name = "tx", .dma_req = 21 },
2518         { .dma_req = -1 }
2519 };
2520
2521 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2522         {
2523                 .name           = "mpu",
2524                 .pa_start       = 0x48096000,
2525                 .pa_end         = 0x480960ff,
2526                 .flags          = ADDR_TYPE_RT
2527         },
2528         { }
2529 };
2530
2531 /* l4_core -> mcbsp5 */
2532 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2533         .master         = &omap3xxx_l4_core_hwmod,
2534         .slave          = &omap3xxx_mcbsp5_hwmod,
2535         .clk            = "mcbsp5_ick",
2536         .addr           = omap3xxx_mcbsp5_addrs,
2537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2538 };
2539
2540 /* mcbsp5 slave ports */
2541 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2542         &omap3xxx_l4_core__mcbsp5,
2543 };
2544
2545 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2546         .name           = "mcbsp5",
2547         .class          = &omap3xxx_mcbsp_hwmod_class,
2548         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2549         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2550         .main_clk       = "mcbsp5_fck",
2551         .prcm           = {
2552                 .omap2 = {
2553                         .prcm_reg_id = 1,
2554                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2555                         .module_offs = CORE_MOD,
2556                         .idlest_reg_id = 1,
2557                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2558                 },
2559         },
2560         .slaves         = omap3xxx_mcbsp5_slaves,
2561         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2562         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2563 };
2564 /* 'mcbsp sidetone' class */
2565
2566 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2567         .sysc_offs      = 0x0010,
2568         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2569         .sysc_fields    = &omap_hwmod_sysc_type1,
2570 };
2571
2572 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2573         .name = "mcbsp_sidetone",
2574         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2575 };
2576
2577 /* mcbsp2_sidetone */
2578 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2579         { .name = "irq", .irq = 4 },
2580         { .irq = -1 }
2581 };
2582
2583 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2584         {
2585                 .name           = "sidetone",
2586                 .pa_start       = 0x49028000,
2587                 .pa_end         = 0x490280ff,
2588                 .flags          = ADDR_TYPE_RT
2589         },
2590         { }
2591 };
2592
2593 /* l4_per -> mcbsp2_sidetone */
2594 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2595         .master         = &omap3xxx_l4_per_hwmod,
2596         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2597         .clk            = "mcbsp2_ick",
2598         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2599         .user           = OCP_USER_MPU,
2600 };
2601
2602 /* mcbsp2_sidetone slave ports */
2603 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2604         &omap3xxx_l4_per__mcbsp2_sidetone,
2605 };
2606
2607 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2608         .name           = "mcbsp2_sidetone",
2609         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2610         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2611         .main_clk       = "mcbsp2_fck",
2612         .prcm           = {
2613                 .omap2 = {
2614                         .prcm_reg_id = 1,
2615                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2616                         .module_offs = OMAP3430_PER_MOD,
2617                         .idlest_reg_id = 1,
2618                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2619                 },
2620         },
2621         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2622         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2623         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2624 };
2625
2626 /* mcbsp3_sidetone */
2627 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2628         { .name = "irq", .irq = 5 },
2629         { .irq = -1 }
2630 };
2631
2632 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2633         {
2634                 .name           = "sidetone",
2635                 .pa_start       = 0x4902A000,
2636                 .pa_end         = 0x4902A0ff,
2637                 .flags          = ADDR_TYPE_RT
2638         },
2639         { }
2640 };
2641
2642 /* l4_per -> mcbsp3_sidetone */
2643 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2644         .master         = &omap3xxx_l4_per_hwmod,
2645         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2646         .clk            = "mcbsp3_ick",
2647         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2648         .user           = OCP_USER_MPU,
2649 };
2650
2651 /* mcbsp3_sidetone slave ports */
2652 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2653         &omap3xxx_l4_per__mcbsp3_sidetone,
2654 };
2655
2656 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2657         .name           = "mcbsp3_sidetone",
2658         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2659         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2660         .main_clk       = "mcbsp3_fck",
2661         .prcm           = {
2662                 .omap2 = {
2663                         .prcm_reg_id = 1,
2664                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2665                         .module_offs = OMAP3430_PER_MOD,
2666                         .idlest_reg_id = 1,
2667                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2668                 },
2669         },
2670         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2671         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2672         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2673 };
2674
2675
2676 /* SR common */
2677 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2678         .clkact_shift   = 20,
2679 };
2680
2681 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2682         .sysc_offs      = 0x24,
2683         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2684         .clockact       = CLOCKACT_TEST_ICLK,
2685         .sysc_fields    = &omap34xx_sr_sysc_fields,
2686 };
2687
2688 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2689         .name = "smartreflex",
2690         .sysc = &omap34xx_sr_sysc,
2691         .rev  = 1,
2692 };
2693
2694 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2695         .sidle_shift    = 24,
2696         .enwkup_shift   = 26
2697 };
2698
2699 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2700         .sysc_offs      = 0x38,
2701         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2702         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2703                         SYSC_NO_CACHE),
2704         .sysc_fields    = &omap36xx_sr_sysc_fields,
2705 };
2706
2707 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2708         .name = "smartreflex",
2709         .sysc = &omap36xx_sr_sysc,
2710         .rev  = 2,
2711 };
2712
2713 /* SR1 */
2714 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2715         &omap3_l4_core__sr1,
2716 };
2717
2718 static struct omap_hwmod omap34xx_sr1_hwmod = {
2719         .name           = "sr1_hwmod",
2720         .class          = &omap34xx_smartreflex_hwmod_class,
2721         .main_clk       = "sr1_fck",
2722         .vdd_name       = "mpu",
2723         .prcm           = {
2724                 .omap2 = {
2725                         .prcm_reg_id = 1,
2726                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2727                         .module_offs = WKUP_MOD,
2728                         .idlest_reg_id = 1,
2729                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2730                 },
2731         },
2732         .slaves         = omap3_sr1_slaves,
2733         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2734         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2735                                         CHIP_IS_OMAP3430ES3_0 |
2736                                         CHIP_IS_OMAP3430ES3_1),
2737         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2738 };
2739
2740 static struct omap_hwmod omap36xx_sr1_hwmod = {
2741         .name           = "sr1_hwmod",
2742         .class          = &omap36xx_smartreflex_hwmod_class,
2743         .main_clk       = "sr1_fck",
2744         .vdd_name       = "mpu",
2745         .prcm           = {
2746                 .omap2 = {
2747                         .prcm_reg_id = 1,
2748                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2749                         .module_offs = WKUP_MOD,
2750                         .idlest_reg_id = 1,
2751                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2752                 },
2753         },
2754         .slaves         = omap3_sr1_slaves,
2755         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2756         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2757 };
2758
2759 /* SR2 */
2760 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2761         &omap3_l4_core__sr2,
2762 };
2763
2764 static struct omap_hwmod omap34xx_sr2_hwmod = {
2765         .name           = "sr2_hwmod",
2766         .class          = &omap34xx_smartreflex_hwmod_class,
2767         .main_clk       = "sr2_fck",
2768         .vdd_name       = "core",
2769         .prcm           = {
2770                 .omap2 = {
2771                         .prcm_reg_id = 1,
2772                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2773                         .module_offs = WKUP_MOD,
2774                         .idlest_reg_id = 1,
2775                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2776                 },
2777         },
2778         .slaves         = omap3_sr2_slaves,
2779         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2780         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2781                                         CHIP_IS_OMAP3430ES3_0 |
2782                                         CHIP_IS_OMAP3430ES3_1),
2783         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2784 };
2785
2786 static struct omap_hwmod omap36xx_sr2_hwmod = {
2787         .name           = "sr2_hwmod",
2788         .class          = &omap36xx_smartreflex_hwmod_class,
2789         .main_clk       = "sr2_fck",
2790         .vdd_name       = "core",
2791         .prcm           = {
2792                 .omap2 = {
2793                         .prcm_reg_id = 1,
2794                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2795                         .module_offs = WKUP_MOD,
2796                         .idlest_reg_id = 1,
2797                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2798                 },
2799         },
2800         .slaves         = omap3_sr2_slaves,
2801         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2802         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2803 };
2804
2805 /*
2806  * 'mailbox' class
2807  * mailbox module allowing communication between the on-chip processors
2808  * using a queued mailbox-interrupt mechanism.
2809  */
2810
2811 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2812         .rev_offs       = 0x000,
2813         .sysc_offs      = 0x010,
2814         .syss_offs      = 0x014,
2815         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2816                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2817         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2818         .sysc_fields    = &omap_hwmod_sysc_type1,
2819 };
2820
2821 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2822         .name = "mailbox",
2823         .sysc = &omap3xxx_mailbox_sysc,
2824 };
2825
2826 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2827 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2828         { .irq = 26 },
2829         { .irq = -1 }
2830 };
2831
2832 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2833         {
2834                 .pa_start       = 0x48094000,
2835                 .pa_end         = 0x480941ff,
2836                 .flags          = ADDR_TYPE_RT,
2837         },
2838         { }
2839 };
2840
2841 /* l4_core -> mailbox */
2842 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2843         .master         = &omap3xxx_l4_core_hwmod,
2844         .slave          = &omap3xxx_mailbox_hwmod,
2845         .addr           = omap3xxx_mailbox_addrs,
2846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2847 };
2848
2849 /* mailbox slave ports */
2850 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2851         &omap3xxx_l4_core__mailbox,
2852 };
2853
2854 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2855         .name           = "mailbox",
2856         .class          = &omap3xxx_mailbox_hwmod_class,
2857         .mpu_irqs       = omap3xxx_mailbox_irqs,
2858         .main_clk       = "mailboxes_ick",
2859         .prcm           = {
2860                 .omap2 = {
2861                         .prcm_reg_id = 1,
2862                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2863                         .module_offs = CORE_MOD,
2864                         .idlest_reg_id = 1,
2865                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2866                 },
2867         },
2868         .slaves         = omap3xxx_mailbox_slaves,
2869         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2870         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2871 };
2872
2873 /* l4 core -> mcspi1 interface */
2874 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2875         .master         = &omap3xxx_l4_core_hwmod,
2876         .slave          = &omap34xx_mcspi1,
2877         .clk            = "mcspi1_ick",
2878         .addr           = omap2_mcspi1_addr_space,
2879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2880 };
2881
2882 /* l4 core -> mcspi2 interface */
2883 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2884         .master         = &omap3xxx_l4_core_hwmod,
2885         .slave          = &omap34xx_mcspi2,
2886         .clk            = "mcspi2_ick",
2887         .addr           = omap2_mcspi2_addr_space,
2888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2889 };
2890
2891 /* l4 core -> mcspi3 interface */
2892 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2893         .master         = &omap3xxx_l4_core_hwmod,
2894         .slave          = &omap34xx_mcspi3,
2895         .clk            = "mcspi3_ick",
2896         .addr           = omap2430_mcspi3_addr_space,
2897         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2898 };
2899
2900 /* l4 core -> mcspi4 interface */
2901 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2902         {
2903                 .pa_start       = 0x480ba000,
2904                 .pa_end         = 0x480ba0ff,
2905                 .flags          = ADDR_TYPE_RT,
2906         },
2907         { }
2908 };
2909
2910 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2911         .master         = &omap3xxx_l4_core_hwmod,
2912         .slave          = &omap34xx_mcspi4,
2913         .clk            = "mcspi4_ick",
2914         .addr           = omap34xx_mcspi4_addr_space,
2915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2916 };
2917
2918 /*
2919  * 'mcspi' class
2920  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2921  * bus
2922  */
2923
2924 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2925         .rev_offs       = 0x0000,
2926         .sysc_offs      = 0x0010,
2927         .syss_offs      = 0x0014,
2928         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2929                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2930                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2931         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2932         .sysc_fields    = &omap_hwmod_sysc_type1,
2933 };
2934
2935 static struct omap_hwmod_class omap34xx_mcspi_class = {
2936         .name = "mcspi",
2937         .sysc = &omap34xx_mcspi_sysc,
2938         .rev = OMAP3_MCSPI_REV,
2939 };
2940
2941 /* mcspi1 */
2942 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
2943         { .name = "tx0", .dma_req = 35 },
2944         { .name = "rx0", .dma_req = 36 },
2945         { .name = "tx1", .dma_req = 37 },
2946         { .name = "rx1", .dma_req = 38 },
2947         { .name = "tx2", .dma_req = 39 },
2948         { .name = "rx2", .dma_req = 40 },
2949         { .name = "tx3", .dma_req = 41 },
2950         { .name = "rx3", .dma_req = 42 },
2951         { .dma_req = -1 }
2952 };
2953
2954 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2955         &omap34xx_l4_core__mcspi1,
2956 };
2957
2958 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2959         .num_chipselect = 4,
2960 };
2961
2962 static struct omap_hwmod omap34xx_mcspi1 = {
2963         .name           = "mcspi1",
2964         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2965         .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
2966         .main_clk       = "mcspi1_fck",
2967         .prcm           = {
2968                 .omap2 = {
2969                         .module_offs = CORE_MOD,
2970                         .prcm_reg_id = 1,
2971                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2972                         .idlest_reg_id = 1,
2973                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2974                 },
2975         },
2976         .slaves         = omap34xx_mcspi1_slaves,
2977         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2978         .class          = &omap34xx_mcspi_class,
2979         .dev_attr       = &omap_mcspi1_dev_attr,
2980         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2981 };
2982
2983 /* mcspi2 */
2984 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
2985         { .name = "tx0", .dma_req = 43 },
2986         { .name = "rx0", .dma_req = 44 },
2987         { .name = "tx1", .dma_req = 45 },
2988         { .name = "rx1", .dma_req = 46 },
2989         { .dma_req = -1 }
2990 };
2991
2992 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2993         &omap34xx_l4_core__mcspi2,
2994 };
2995
2996 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2997         .num_chipselect = 2,
2998 };
2999
3000 static struct omap_hwmod omap34xx_mcspi2 = {
3001         .name           = "mcspi2",
3002         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
3003         .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
3004         .main_clk       = "mcspi2_fck",
3005         .prcm           = {
3006                 .omap2 = {
3007                         .module_offs = CORE_MOD,
3008                         .prcm_reg_id = 1,
3009                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3010                         .idlest_reg_id = 1,
3011                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3012                 },
3013         },
3014         .slaves         = omap34xx_mcspi2_slaves,
3015         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3016         .class          = &omap34xx_mcspi_class,
3017         .dev_attr       = &omap_mcspi2_dev_attr,
3018         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3019 };
3020
3021 /* mcspi3 */
3022 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3023         { .name = "irq", .irq = 91 }, /* 91 */
3024         { .irq = -1 }
3025 };
3026
3027 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3028         { .name = "tx0", .dma_req = 15 },
3029         { .name = "rx0", .dma_req = 16 },
3030         { .name = "tx1", .dma_req = 23 },
3031         { .name = "rx1", .dma_req = 24 },
3032         { .dma_req = -1 }
3033 };
3034
3035 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3036         &omap34xx_l4_core__mcspi3,
3037 };
3038
3039 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3040         .num_chipselect = 2,
3041 };
3042
3043 static struct omap_hwmod omap34xx_mcspi3 = {
3044         .name           = "mcspi3",
3045         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
3046         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
3047         .main_clk       = "mcspi3_fck",
3048         .prcm           = {
3049                 .omap2 = {
3050                         .module_offs = CORE_MOD,
3051                         .prcm_reg_id = 1,
3052                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3053                         .idlest_reg_id = 1,
3054                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3055                 },
3056         },
3057         .slaves         = omap34xx_mcspi3_slaves,
3058         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3059         .class          = &omap34xx_mcspi_class,
3060         .dev_attr       = &omap_mcspi3_dev_attr,
3061         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3062 };
3063
3064 /* SPI4 */
3065 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3066         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3067         { .irq = -1 }
3068 };
3069
3070 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3071         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3072         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3073         { .dma_req = -1 }
3074 };
3075
3076 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3077         &omap34xx_l4_core__mcspi4,
3078 };
3079
3080 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3081         .num_chipselect = 1,
3082 };
3083
3084 static struct omap_hwmod omap34xx_mcspi4 = {
3085         .name           = "mcspi4",
3086         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3087         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3088         .main_clk       = "mcspi4_fck",
3089         .prcm           = {
3090                 .omap2 = {
3091                         .module_offs = CORE_MOD,
3092                         .prcm_reg_id = 1,
3093                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3094                         .idlest_reg_id = 1,
3095                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3096                 },
3097         },
3098         .slaves         = omap34xx_mcspi4_slaves,
3099         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3100         .class          = &omap34xx_mcspi_class,
3101         .dev_attr       = &omap_mcspi4_dev_attr,
3102         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3103 };
3104
3105 /*
3106  * usbhsotg
3107  */
3108 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3109         .rev_offs       = 0x0400,
3110         .sysc_offs      = 0x0404,
3111         .syss_offs      = 0x0408,
3112         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3113                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3114                           SYSC_HAS_AUTOIDLE),
3115         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3116                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3117         .sysc_fields    = &omap_hwmod_sysc_type1,
3118 };
3119
3120 static struct omap_hwmod_class usbotg_class = {
3121         .name = "usbotg",
3122         .sysc = &omap3xxx_usbhsotg_sysc,
3123 };
3124 /* usb_otg_hs */
3125 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3126
3127         { .name = "mc", .irq = 92 },
3128         { .name = "dma", .irq = 93 },
3129         { .irq = -1 }
3130 };
3131
3132 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3133         .name           = "usb_otg_hs",
3134         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3135         .main_clk       = "hsotgusb_ick",
3136         .prcm           = {
3137                 .omap2 = {
3138                         .prcm_reg_id = 1,
3139                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3140                         .module_offs = CORE_MOD,
3141                         .idlest_reg_id = 1,
3142                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3143                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3144                 },
3145         },
3146         .masters        = omap3xxx_usbhsotg_masters,
3147         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3148         .slaves         = omap3xxx_usbhsotg_slaves,
3149         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3150         .class          = &usbotg_class,
3151
3152         /*
3153          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3154          * broken when autoidle is enabled
3155          * workaround is to disable the autoidle bit at module level.
3156          */
3157         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3158                                 | HWMOD_SWSUP_MSTANDBY,
3159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3160 };
3161
3162 /* usb_otg_hs */
3163 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3164
3165         { .name = "mc", .irq = 71 },
3166         { .irq = -1 }
3167 };
3168
3169 static struct omap_hwmod_class am35xx_usbotg_class = {
3170         .name = "am35xx_usbotg",
3171         .sysc = NULL,
3172 };
3173
3174 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3175         .name           = "am35x_otg_hs",
3176         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3177         .main_clk       = NULL,
3178         .prcm = {
3179                 .omap2 = {
3180                 },
3181         },
3182         .masters        = am35xx_usbhsotg_masters,
3183         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3184         .slaves         = am35xx_usbhsotg_slaves,
3185         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3186         .class          = &am35xx_usbotg_class,
3187         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3188 };
3189
3190 /* MMC/SD/SDIO common */
3191
3192 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3193         .rev_offs       = 0x1fc,
3194         .sysc_offs      = 0x10,
3195         .syss_offs      = 0x14,
3196         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3197                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3198                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3199         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3200         .sysc_fields    = &omap_hwmod_sysc_type1,
3201 };
3202
3203 static struct omap_hwmod_class omap34xx_mmc_class = {
3204         .name = "mmc",
3205         .sysc = &omap34xx_mmc_sysc,
3206 };
3207
3208 /* MMC/SD/SDIO1 */
3209
3210 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3211         { .irq = 83, },
3212         { .irq = -1 }
3213 };
3214
3215 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3216         { .name = "tx", .dma_req = 61, },
3217         { .name = "rx", .dma_req = 62, },
3218         { .dma_req = -1 }
3219 };
3220
3221 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3222         { .role = "dbck", .clk = "omap_32k_fck", },
3223 };
3224
3225 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3226         &omap3xxx_l4_core__mmc1,
3227 };
3228
3229 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3230         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3231 };
3232
3233 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3234         .name           = "mmc1",
3235         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3236         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3237         .opt_clks       = omap34xx_mmc1_opt_clks,
3238         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3239         .main_clk       = "mmchs1_fck",
3240         .prcm           = {
3241                 .omap2 = {
3242                         .module_offs = CORE_MOD,
3243                         .prcm_reg_id = 1,
3244                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3245                         .idlest_reg_id = 1,
3246                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3247                 },
3248         },
3249         .dev_attr       = &mmc1_dev_attr,
3250         .slaves         = omap3xxx_mmc1_slaves,
3251         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3252         .class          = &omap34xx_mmc_class,
3253         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3254 };
3255
3256 /* MMC/SD/SDIO2 */
3257
3258 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3259         { .irq = INT_24XX_MMC2_IRQ, },
3260         { .irq = -1 }
3261 };
3262
3263 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3264         { .name = "tx", .dma_req = 47, },
3265         { .name = "rx", .dma_req = 48, },
3266         { .dma_req = -1 }
3267 };
3268
3269 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3270         { .role = "dbck", .clk = "omap_32k_fck", },
3271 };
3272
3273 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3274         &omap3xxx_l4_core__mmc2,
3275 };
3276
3277 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3278         .name           = "mmc2",
3279         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3280         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3281         .opt_clks       = omap34xx_mmc2_opt_clks,
3282         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3283         .main_clk       = "mmchs2_fck",
3284         .prcm           = {
3285                 .omap2 = {
3286                         .module_offs = CORE_MOD,
3287                         .prcm_reg_id = 1,
3288                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3289                         .idlest_reg_id = 1,
3290                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3291                 },
3292         },
3293         .slaves         = omap3xxx_mmc2_slaves,
3294         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3295         .class          = &omap34xx_mmc_class,
3296         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3297 };
3298
3299 /* MMC/SD/SDIO3 */
3300
3301 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3302         { .irq = 94, },
3303         { .irq = -1 }
3304 };
3305
3306 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3307         { .name = "tx", .dma_req = 77, },
3308         { .name = "rx", .dma_req = 78, },
3309         { .dma_req = -1 }
3310 };
3311
3312 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3313         { .role = "dbck", .clk = "omap_32k_fck", },
3314 };
3315
3316 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3317         &omap3xxx_l4_core__mmc3,
3318 };
3319
3320 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3321         .name           = "mmc3",
3322         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3323         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3324         .opt_clks       = omap34xx_mmc3_opt_clks,
3325         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3326         .main_clk       = "mmchs3_fck",
3327         .prcm           = {
3328                 .omap2 = {
3329                         .prcm_reg_id = 1,
3330                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3331                         .idlest_reg_id = 1,
3332                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3333                 },
3334         },
3335         .slaves         = omap3xxx_mmc3_slaves,
3336         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3337         .class          = &omap34xx_mmc_class,
3338         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3339 };
3340
3341 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3342         &omap3xxx_l3_main_hwmod,
3343         &omap3xxx_l4_core_hwmod,
3344         &omap3xxx_l4_per_hwmod,
3345         &omap3xxx_l4_wkup_hwmod,
3346         &omap3xxx_mmc1_hwmod,
3347         &omap3xxx_mmc2_hwmod,
3348         &omap3xxx_mmc3_hwmod,
3349         &omap3xxx_mpu_hwmod,
3350         &omap3xxx_iva_hwmod,
3351
3352         &omap3xxx_timer1_hwmod,
3353         &omap3xxx_timer2_hwmod,
3354         &omap3xxx_timer3_hwmod,
3355         &omap3xxx_timer4_hwmod,
3356         &omap3xxx_timer5_hwmod,
3357         &omap3xxx_timer6_hwmod,
3358         &omap3xxx_timer7_hwmod,
3359         &omap3xxx_timer8_hwmod,
3360         &omap3xxx_timer9_hwmod,
3361         &omap3xxx_timer10_hwmod,
3362         &omap3xxx_timer11_hwmod,
3363         &omap3xxx_timer12_hwmod,
3364
3365         &omap3xxx_wd_timer2_hwmod,
3366         &omap3xxx_uart1_hwmod,
3367         &omap3xxx_uart2_hwmod,
3368         &omap3xxx_uart3_hwmod,
3369         &omap3xxx_uart4_hwmod,
3370         /* dss class */
3371         &omap3430es1_dss_core_hwmod,
3372         &omap3xxx_dss_core_hwmod,
3373         &omap3xxx_dss_dispc_hwmod,
3374         &omap3xxx_dss_dsi1_hwmod,
3375         &omap3xxx_dss_rfbi_hwmod,
3376         &omap3xxx_dss_venc_hwmod,
3377
3378         /* i2c class */
3379         &omap3xxx_i2c1_hwmod,
3380         &omap3xxx_i2c2_hwmod,
3381         &omap3xxx_i2c3_hwmod,
3382         &omap34xx_sr1_hwmod,
3383         &omap34xx_sr2_hwmod,
3384         &omap36xx_sr1_hwmod,
3385         &omap36xx_sr2_hwmod,
3386
3387
3388         /* gpio class */
3389         &omap3xxx_gpio1_hwmod,
3390         &omap3xxx_gpio2_hwmod,
3391         &omap3xxx_gpio3_hwmod,
3392         &omap3xxx_gpio4_hwmod,
3393         &omap3xxx_gpio5_hwmod,
3394         &omap3xxx_gpio6_hwmod,
3395
3396         /* dma_system class*/
3397         &omap3xxx_dma_system_hwmod,
3398
3399         /* mcbsp class */
3400         &omap3xxx_mcbsp1_hwmod,
3401         &omap3xxx_mcbsp2_hwmod,
3402         &omap3xxx_mcbsp3_hwmod,
3403         &omap3xxx_mcbsp4_hwmod,
3404         &omap3xxx_mcbsp5_hwmod,
3405         &omap3xxx_mcbsp2_sidetone_hwmod,
3406         &omap3xxx_mcbsp3_sidetone_hwmod,
3407
3408         /* mailbox class */
3409         &omap3xxx_mailbox_hwmod,
3410
3411         /* mcspi class */
3412         &omap34xx_mcspi1,
3413         &omap34xx_mcspi2,
3414         &omap34xx_mcspi3,
3415         &omap34xx_mcspi4,
3416
3417         /* usbotg class */
3418         &omap3xxx_usbhsotg_hwmod,
3419
3420         /* usbotg for am35x */
3421         &am35xx_usbhsotg_hwmod,
3422
3423         NULL,
3424 };
3425
3426 int __init omap3xxx_hwmod_init(void)
3427 {
3428         return omap_hwmod_register(omap3xxx_hwmods);
3429 }