arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106 };
 107
 108 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 109         {
 110                 .pa_start       = 0x68000000,
 111                 .pa_end         = 0x6800ffff,
 112                 .flags          = ADDR_TYPE_RT,
 113         },
 114         { }
 115 };
 116
 117 /* MPU -> L3 interface */
 118 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 119         .master   = &omap3xxx_mpu_hwmod,
 120         .slave    = &omap3xxx_l3_main_hwmod,
 121         .addr     = omap3xxx_l3_main_addrs,
 122         .user   = OCP_USER_MPU,
 123 };
 124
 125 /* Slave interfaces on the L3 interconnect */
 126 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 127         &omap3xxx_mpu__l3_main,
 128 };
 129
 130 /* DSS -> l3 */
 131 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 132         .master         = &omap3xxx_dss_core_hwmod,
 133         .slave          = &omap3xxx_l3_main_hwmod,
 134         .fw = {
 135                 .omap2 = {
 136                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 137                         .flags  = OMAP_FIREWALL_L3,
 138                 }
 139         },
 140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 141 };
 142
 143 /* Master interfaces on the L3 interconnect */
 144 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 145         &omap3xxx_l3_main__l4_core,
 146         &omap3xxx_l3_main__l4_per,
 147 };
 148
 149 /* L3 */
 150 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 151         .name           = "l3_main",
 152         .class          = &l3_hwmod_class,
 153         .mpu_irqs       = omap3xxx_l3_main_irqs,
 154         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_l3_main_irqs),
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 160         .flags          = HWMOD_NO_IDLEST,
 161 };
 162
 163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 164 static struct omap_hwmod omap3xxx_uart1_hwmod;
 165 static struct omap_hwmod omap3xxx_uart2_hwmod;
 166 static struct omap_hwmod omap3xxx_uart3_hwmod;
 167 static struct omap_hwmod omap3xxx_uart4_hwmod;
 168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 169
 170 /* l3_core -> usbhsotg interface */
 171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 172         .master         = &omap3xxx_usbhsotg_hwmod,
 173         .slave          = &omap3xxx_l3_main_hwmod,
 174         .clk            = "core_l3_ick",
 175         .user           = OCP_USER_MPU,
 176 };
 177
 178 /* l3_core -> am35xx_usbhsotg interface */
 179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 180         .master         = &am35xx_usbhsotg_hwmod,
 181         .slave          = &omap3xxx_l3_main_hwmod,
 182         .clk            = "core_l3_ick",
 183         .user           = OCP_USER_MPU,
 184 };
 185 /* L4_CORE -> L4_WKUP interface */
 186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 187         .master = &omap3xxx_l4_core_hwmod,
 188         .slave  = &omap3xxx_l4_wkup_hwmod,
 189         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 190 };
 191
 192 /* L4 CORE -> MMC1 interface */
 193 static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
 194         {
 195                 .pa_start       = 0x4809c000,
 196                 .pa_end         = 0x4809c1ff,
 197                 .flags          = ADDR_TYPE_RT,
 198         },
 199         { }
 200 };
 201
 202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 203         .master         = &omap3xxx_l4_core_hwmod,
 204         .slave          = &omap3xxx_mmc1_hwmod,
 205         .clk            = "mmchs1_ick",
 206         .addr           = omap3xxx_mmc1_addr_space,
 207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 208         .flags          = OMAP_FIREWALL_L4
 209 };
 210
 211 /* L4 CORE -> MMC2 interface */
 212 static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
 213         {
 214                 .pa_start       = 0x480b4000,
 215                 .pa_end         = 0x480b41ff,
 216                 .flags          = ADDR_TYPE_RT,
 217         },
 218         { }
 219 };
 220
 221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 222         .master         = &omap3xxx_l4_core_hwmod,
 223         .slave          = &omap3xxx_mmc2_hwmod,
 224         .clk            = "mmchs2_ick",
 225         .addr           = omap3xxx_mmc2_addr_space,
 226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 227         .flags          = OMAP_FIREWALL_L4
 228 };
 229
 230 /* L4 CORE -> MMC3 interface */
 231 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 232         {
 233                 .pa_start       = 0x480ad000,
 234                 .pa_end         = 0x480ad1ff,
 235                 .flags          = ADDR_TYPE_RT,
 236         },
 237         { }
 238 };
 239
 240 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 241         .master         = &omap3xxx_l4_core_hwmod,
 242         .slave          = &omap3xxx_mmc3_hwmod,
 243         .clk            = "mmchs3_ick",
 244         .addr           = omap3xxx_mmc3_addr_space,
 245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 246         .flags          = OMAP_FIREWALL_L4
 247 };
 248
 249 /* L4 CORE -> UART1 interface */
 250 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 251         {
 252                 .pa_start       = OMAP3_UART1_BASE,
 253                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 254                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 255         },
 256         { }
 257 };
 258
 259 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 260         .master         = &omap3xxx_l4_core_hwmod,
 261         .slave          = &omap3xxx_uart1_hwmod,
 262         .clk            = "uart1_ick",
 263         .addr           = omap3xxx_uart1_addr_space,
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* L4 CORE -> UART2 interface */
 268 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 269         {
 270                 .pa_start       = OMAP3_UART2_BASE,
 271                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 272                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 273         },
 274         { }
 275 };
 276
 277 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 278         .master         = &omap3xxx_l4_core_hwmod,
 279         .slave          = &omap3xxx_uart2_hwmod,
 280         .clk            = "uart2_ick",
 281         .addr           = omap3xxx_uart2_addr_space,
 282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 283 };
 284
 285 /* L4 PER -> UART3 interface */
 286 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 287         {
 288                 .pa_start       = OMAP3_UART3_BASE,
 289                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 290                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 291         },
 292         { }
 293 };
 294
 295 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 296         .master         = &omap3xxx_l4_per_hwmod,
 297         .slave          = &omap3xxx_uart3_hwmod,
 298         .clk            = "uart3_ick",
 299         .addr           = omap3xxx_uart3_addr_space,
 300         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 301 };
 302
 303 /* L4 PER -> UART4 interface */
 304 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 305         {
 306                 .pa_start       = OMAP3_UART4_BASE,
 307                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 308                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 309         },
 310         { }
 311 };
 312
 313 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 314         .master         = &omap3xxx_l4_per_hwmod,
 315         .slave          = &omap3xxx_uart4_hwmod,
 316         .clk            = "uart4_ick",
 317         .addr           = omap3xxx_uart4_addr_space,
 318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 319 };
 320
 321 /* I2C IP block address space length (in bytes) */
 322 #define OMAP2_I2C_AS_LEN                128
 323
 324 /* L4 CORE -> I2C1 interface */
 325 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
 326         {
 327                 .pa_start       = 0x48070000,
 328                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 329                 .flags          = ADDR_TYPE_RT,
 330         },
 331         { }
 332 };
 333
 334 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 335         .master         = &omap3xxx_l4_core_hwmod,
 336         .slave          = &omap3xxx_i2c1_hwmod,
 337         .clk            = "i2c1_ick",
 338         .addr           = omap3xxx_i2c1_addr_space,
 339         .fw = {
 340                 .omap2 = {
 341                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 342                         .l4_prot_group = 7,
 343                         .flags  = OMAP_FIREWALL_L4,
 344                 }
 345         },
 346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 347 };
 348
 349 /* L4 CORE -> I2C2 interface */
 350 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
 351         {
 352                 .pa_start       = 0x48072000,
 353                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 354                 .flags          = ADDR_TYPE_RT,
 355         },
 356         { }
 357 };
 358
 359 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 360         .master         = &omap3xxx_l4_core_hwmod,
 361         .slave          = &omap3xxx_i2c2_hwmod,
 362         .clk            = "i2c2_ick",
 363         .addr           = omap3xxx_i2c2_addr_space,
 364         .fw = {
 365                 .omap2 = {
 366                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 367                         .l4_prot_group = 7,
 368                         .flags = OMAP_FIREWALL_L4,
 369                 }
 370         },
 371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 372 };
 373
 374 /* L4 CORE -> I2C3 interface */
 375 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 376         {
 377                 .pa_start       = 0x48060000,
 378                 .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
 379                 .flags          = ADDR_TYPE_RT,
 380         },
 381         { }
 382 };
 383
 384 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 385         .master         = &omap3xxx_l4_core_hwmod,
 386         .slave          = &omap3xxx_i2c3_hwmod,
 387         .clk            = "i2c3_ick",
 388         .addr           = omap3xxx_i2c3_addr_space,
 389         .fw = {
 390                 .omap2 = {
 391                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 392                         .l4_prot_group = 7,
 393                         .flags = OMAP_FIREWALL_L4,
 394                 }
 395         },
 396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 397 };
 398
 399 /* L4 CORE -> SR1 interface */
 400 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 401         {
 402                 .pa_start       = OMAP34XX_SR1_BASE,
 403                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 404                 .flags          = ADDR_TYPE_RT,
 405         },
 406         { }
 407 };
 408
 409 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 410         .master         = &omap3xxx_l4_core_hwmod,
 411         .slave          = &omap34xx_sr1_hwmod,
 412         .clk            = "sr_l4_ick",
 413         .addr           = omap3_sr1_addr_space,
 414         .user           = OCP_USER_MPU,
 415 };
 416
 417 /* L4 CORE -> SR1 interface */
 418 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 419         {
 420                 .pa_start       = OMAP34XX_SR2_BASE,
 421                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 422                 .flags          = ADDR_TYPE_RT,
 423         },
 424         { }
 425 };
 426
 427 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 428         .master         = &omap3xxx_l4_core_hwmod,
 429         .slave          = &omap34xx_sr2_hwmod,
 430         .clk            = "sr_l4_ick",
 431         .addr           = omap3_sr2_addr_space,
 432         .user           = OCP_USER_MPU,
 433 };
 434
 435 /*
 436 * usbhsotg interface data
 437 */
 438
 439 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 440         {
 441                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 442                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 443                 .flags          = ADDR_TYPE_RT
 444         },
 445         { }
 446 };
 447
 448 /* l4_core -> usbhsotg  */
 449 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 450         .master         = &omap3xxx_l4_core_hwmod,
 451         .slave          = &omap3xxx_usbhsotg_hwmod,
 452         .clk            = "l4_ick",
 453         .addr           = omap3xxx_usbhsotg_addrs,
 454         .user           = OCP_USER_MPU,
 455 };
 456
 457 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 458         &omap3xxx_usbhsotg__l3,
 459 };
 460
 461 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 462         &omap3xxx_l4_core__usbhsotg,
 463 };
 464
 465 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 466         {
 467                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 468                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 469                 .flags          = ADDR_TYPE_RT
 470         },
 471         { }
 472 };
 473
 474 /* l4_core -> usbhsotg  */
 475 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 476         .master         = &omap3xxx_l4_core_hwmod,
 477         .slave          = &am35xx_usbhsotg_hwmod,
 478         .clk            = "l4_ick",
 479         .addr           = am35xx_usbhsotg_addrs,
 480         .user           = OCP_USER_MPU,
 481 };
 482
 483 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 484         &am35xx_usbhsotg__l3,
 485 };
 486
 487 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 488         &am35xx_l4_core__usbhsotg,
 489 };
 490 /* Slave interfaces on the L4_CORE interconnect */
 491 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 492         &omap3xxx_l3_main__l4_core,
 493 };
 494
 495 /* L4 CORE */
 496 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 497         .name           = "l4_core",
 498         .class          = &l4_hwmod_class,
 499         .slaves         = omap3xxx_l4_core_slaves,
 500         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 501         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 502         .flags          = HWMOD_NO_IDLEST,
 503 };
 504
 505 /* Slave interfaces on the L4_PER interconnect */
 506 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 507         &omap3xxx_l3_main__l4_per,
 508 };
 509
 510 /* L4 PER */
 511 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 512         .name           = "l4_per",
 513         .class          = &l4_hwmod_class,
 514         .slaves         = omap3xxx_l4_per_slaves,
 515         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 516         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 517         .flags          = HWMOD_NO_IDLEST,
 518 };
 519
 520 /* Slave interfaces on the L4_WKUP interconnect */
 521 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 522         &omap3xxx_l4_core__l4_wkup,
 523 };
 524
 525 /* L4 WKUP */
 526 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 527         .name           = "l4_wkup",
 528         .class          = &l4_hwmod_class,
 529         .slaves         = omap3xxx_l4_wkup_slaves,
 530         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 531         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 532         .flags          = HWMOD_NO_IDLEST,
 533 };
 534
 535 /* Master interfaces on the MPU device */
 536 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 537         &omap3xxx_mpu__l3_main,
 538 };
 539
 540 /* MPU */
 541 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 542         .name           = "mpu",
 543         .class          = &mpu_hwmod_class,
 544         .main_clk       = "arm_fck",
 545         .masters        = omap3xxx_mpu_masters,
 546         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 547         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 548 };
 549
 550 /*
 551  * IVA2_2 interface data
 552  */
 553
 554 /* IVA2 <- L3 interface */
 555 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 556         .master         = &omap3xxx_l3_main_hwmod,
 557         .slave          = &omap3xxx_iva_hwmod,
 558         .clk            = "iva2_ck",
 559         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 560 };
 561
 562 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 563         &omap3xxx_l3__iva,
 564 };
 565
 566 /*
 567  * IVA2 (IVA2)
 568  */
 569
 570 static struct omap_hwmod omap3xxx_iva_hwmod = {
 571         .name           = "iva",
 572         .class          = &iva_hwmod_class,
 573         .masters        = omap3xxx_iva_masters,
 574         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 575         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 576 };
 577
 578 /* timer class */
 579 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 580         .rev_offs       = 0x0000,
 581         .sysc_offs      = 0x0010,
 582         .syss_offs      = 0x0014,
 583         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 584                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 585                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 586         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 587         .sysc_fields    = &omap_hwmod_sysc_type1,
 588 };
 589
 590 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 591         .name = "timer",
 592         .sysc = &omap3xxx_timer_1ms_sysc,
 593         .rev = OMAP_TIMER_IP_VERSION_1,
 594 };
 595
 596 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 597         .rev_offs       = 0x0000,
 598         .sysc_offs      = 0x0010,
 599         .syss_offs      = 0x0014,
 600         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 601                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 602         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 603         .sysc_fields    = &omap_hwmod_sysc_type1,
 604 };
 605
 606 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 607         .name = "timer",
 608         .sysc = &omap3xxx_timer_sysc,
 609         .rev =  OMAP_TIMER_IP_VERSION_1,
 610 };
 611
 612 /* timer1 */
 613 static struct omap_hwmod omap3xxx_timer1_hwmod;
 614 static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
 615         { .irq = 37, },
 616 };
 617
 618 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 619         {
 620                 .pa_start       = 0x48318000,
 621                 .pa_end         = 0x48318000 + SZ_1K - 1,
 622                 .flags          = ADDR_TYPE_RT
 623         },
 624         { }
 625 };
 626
 627 /* l4_wkup -> timer1 */
 628 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 629         .master         = &omap3xxx_l4_wkup_hwmod,
 630         .slave          = &omap3xxx_timer1_hwmod,
 631         .clk            = "gpt1_ick",
 632         .addr           = omap3xxx_timer1_addrs,
 633         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 634 };
 635
 636 /* timer1 slave port */
 637 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 638         &omap3xxx_l4_wkup__timer1,
 639 };
 640
 641 /* timer1 hwmod */
 642 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 643         .name           = "timer1",
 644         .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
 645         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
 646         .main_clk       = "gpt1_fck",
 647         .prcm           = {
 648                 .omap2 = {
 649                         .prcm_reg_id = 1,
 650                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 651                         .module_offs = WKUP_MOD,
 652                         .idlest_reg_id = 1,
 653                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 654                 },
 655         },
 656         .slaves         = omap3xxx_timer1_slaves,
 657         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 658         .class          = &omap3xxx_timer_1ms_hwmod_class,
 659         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 660 };
 661
 662 /* timer2 */
 663 static struct omap_hwmod omap3xxx_timer2_hwmod;
 664 static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
 665         { .irq = 38, },
 666 };
 667
 668 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 669         {
 670                 .pa_start       = 0x49032000,
 671                 .pa_end         = 0x49032000 + SZ_1K - 1,
 672                 .flags          = ADDR_TYPE_RT
 673         },
 674         { }
 675 };
 676
 677 /* l4_per -> timer2 */
 678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 679         .master         = &omap3xxx_l4_per_hwmod,
 680         .slave          = &omap3xxx_timer2_hwmod,
 681         .clk            = "gpt2_ick",
 682         .addr           = omap3xxx_timer2_addrs,
 683         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 684 };
 685
 686 /* timer2 slave port */
 687 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 688         &omap3xxx_l4_per__timer2,
 689 };
 690
 691 /* timer2 hwmod */
 692 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 693         .name           = "timer2",
 694         .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
 695         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
 696         .main_clk       = "gpt2_fck",
 697         .prcm           = {
 698                 .omap2 = {
 699                         .prcm_reg_id = 1,
 700                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 701                         .module_offs = OMAP3430_PER_MOD,
 702                         .idlest_reg_id = 1,
 703                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 704                 },
 705         },
 706         .slaves         = omap3xxx_timer2_slaves,
 707         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 708         .class          = &omap3xxx_timer_1ms_hwmod_class,
 709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 710 };
 711
 712 /* timer3 */
 713 static struct omap_hwmod omap3xxx_timer3_hwmod;
 714 static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
 715         { .irq = 39, },
 716 };
 717
 718 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 719         {
 720                 .pa_start       = 0x49034000,
 721                 .pa_end         = 0x49034000 + SZ_1K - 1,
 722                 .flags          = ADDR_TYPE_RT
 723         },
 724         { }
 725 };
 726
 727 /* l4_per -> timer3 */
 728 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 729         .master         = &omap3xxx_l4_per_hwmod,
 730         .slave          = &omap3xxx_timer3_hwmod,
 731         .clk            = "gpt3_ick",
 732         .addr           = omap3xxx_timer3_addrs,
 733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 734 };
 735
 736 /* timer3 slave port */
 737 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 738         &omap3xxx_l4_per__timer3,
 739 };
 740
 741 /* timer3 hwmod */
 742 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 743         .name           = "timer3",
 744         .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
 745         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
 746         .main_clk       = "gpt3_fck",
 747         .prcm           = {
 748                 .omap2 = {
 749                         .prcm_reg_id = 1,
 750                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 751                         .module_offs = OMAP3430_PER_MOD,
 752                         .idlest_reg_id = 1,
 753                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 754                 },
 755         },
 756         .slaves         = omap3xxx_timer3_slaves,
 757         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 758         .class          = &omap3xxx_timer_hwmod_class,
 759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 760 };
 761
 762 /* timer4 */
 763 static struct omap_hwmod omap3xxx_timer4_hwmod;
 764 static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
 765         { .irq = 40, },
 766 };
 767
 768 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 769         {
 770                 .pa_start       = 0x49036000,
 771                 .pa_end         = 0x49036000 + SZ_1K - 1,
 772                 .flags          = ADDR_TYPE_RT
 773         },
 774         { }
 775 };
 776
 777 /* l4_per -> timer4 */
 778 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 779         .master         = &omap3xxx_l4_per_hwmod,
 780         .slave          = &omap3xxx_timer4_hwmod,
 781         .clk            = "gpt4_ick",
 782         .addr           = omap3xxx_timer4_addrs,
 783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 784 };
 785
 786 /* timer4 slave port */
 787 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 788         &omap3xxx_l4_per__timer4,
 789 };
 790
 791 /* timer4 hwmod */
 792 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 793         .name           = "timer4",
 794         .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
 795         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
 796         .main_clk       = "gpt4_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 801                         .module_offs = OMAP3430_PER_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 804                 },
 805         },
 806         .slaves         = omap3xxx_timer4_slaves,
 807         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 808         .class          = &omap3xxx_timer_hwmod_class,
 809         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 810 };
 811
 812 /* timer5 */
 813 static struct omap_hwmod omap3xxx_timer5_hwmod;
 814 static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
 815         { .irq = 41, },
 816 };
 817
 818 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 819         {
 820                 .pa_start       = 0x49038000,
 821                 .pa_end         = 0x49038000 + SZ_1K - 1,
 822                 .flags          = ADDR_TYPE_RT
 823         },
 824         { }
 825 };
 826
 827 /* l4_per -> timer5 */
 828 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 829         .master         = &omap3xxx_l4_per_hwmod,
 830         .slave          = &omap3xxx_timer5_hwmod,
 831         .clk            = "gpt5_ick",
 832         .addr           = omap3xxx_timer5_addrs,
 833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 834 };
 835
 836 /* timer5 slave port */
 837 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 838         &omap3xxx_l4_per__timer5,
 839 };
 840
 841 /* timer5 hwmod */
 842 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 843         .name           = "timer5",
 844         .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
 845         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
 846         .main_clk       = "gpt5_fck",
 847         .prcm           = {
 848                 .omap2 = {
 849                         .prcm_reg_id = 1,
 850                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 851                         .module_offs = OMAP3430_PER_MOD,
 852                         .idlest_reg_id = 1,
 853                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 854                 },
 855         },
 856         .slaves         = omap3xxx_timer5_slaves,
 857         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 858         .class          = &omap3xxx_timer_hwmod_class,
 859         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 860 };
 861
 862 /* timer6 */
 863 static struct omap_hwmod omap3xxx_timer6_hwmod;
 864 static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
 865         { .irq = 42, },
 866 };
 867
 868 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 869         {
 870                 .pa_start       = 0x4903A000,
 871                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 872                 .flags          = ADDR_TYPE_RT
 873         },
 874         { }
 875 };
 876
 877 /* l4_per -> timer6 */
 878 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 879         .master         = &omap3xxx_l4_per_hwmod,
 880         .slave          = &omap3xxx_timer6_hwmod,
 881         .clk            = "gpt6_ick",
 882         .addr           = omap3xxx_timer6_addrs,
 883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 884 };
 885
 886 /* timer6 slave port */
 887 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 888         &omap3xxx_l4_per__timer6,
 889 };
 890
 891 /* timer6 hwmod */
 892 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 893         .name           = "timer6",
 894         .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
 895         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
 896         .main_clk       = "gpt6_fck",
 897         .prcm           = {
 898                 .omap2 = {
 899                         .prcm_reg_id = 1,
 900                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 901                         .module_offs = OMAP3430_PER_MOD,
 902                         .idlest_reg_id = 1,
 903                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 904                 },
 905         },
 906         .slaves         = omap3xxx_timer6_slaves,
 907         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 908         .class          = &omap3xxx_timer_hwmod_class,
 909         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 910 };
 911
 912 /* timer7 */
 913 static struct omap_hwmod omap3xxx_timer7_hwmod;
 914 static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
 915         { .irq = 43, },
 916 };
 917
 918 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 919         {
 920                 .pa_start       = 0x4903C000,
 921                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 922                 .flags          = ADDR_TYPE_RT
 923         },
 924         { }
 925 };
 926
 927 /* l4_per -> timer7 */
 928 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 929         .master         = &omap3xxx_l4_per_hwmod,
 930         .slave          = &omap3xxx_timer7_hwmod,
 931         .clk            = "gpt7_ick",
 932         .addr           = omap3xxx_timer7_addrs,
 933         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 934 };
 935
 936 /* timer7 slave port */
 937 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 938         &omap3xxx_l4_per__timer7,
 939 };
 940
 941 /* timer7 hwmod */
 942 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 943         .name           = "timer7",
 944         .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
 945         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
 946         .main_clk       = "gpt7_fck",
 947         .prcm           = {
 948                 .omap2 = {
 949                         .prcm_reg_id = 1,
 950                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 951                         .module_offs = OMAP3430_PER_MOD,
 952                         .idlest_reg_id = 1,
 953                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 954                 },
 955         },
 956         .slaves         = omap3xxx_timer7_slaves,
 957         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 958         .class          = &omap3xxx_timer_hwmod_class,
 959         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 960 };
 961
 962 /* timer8 */
 963 static struct omap_hwmod omap3xxx_timer8_hwmod;
 964 static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
 965         { .irq = 44, },
 966 };
 967
 968 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 969         {
 970                 .pa_start       = 0x4903E000,
 971                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 972                 .flags          = ADDR_TYPE_RT
 973         },
 974         { }
 975 };
 976
 977 /* l4_per -> timer8 */
 978 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 979         .master         = &omap3xxx_l4_per_hwmod,
 980         .slave          = &omap3xxx_timer8_hwmod,
 981         .clk            = "gpt8_ick",
 982         .addr           = omap3xxx_timer8_addrs,
 983         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 984 };
 985
 986 /* timer8 slave port */
 987 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 988         &omap3xxx_l4_per__timer8,
 989 };
 990
 991 /* timer8 hwmod */
 992 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 993         .name           = "timer8",
 994         .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
 995         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
 996         .main_clk       = "gpt8_fck",
 997         .prcm           = {
 998                 .omap2 = {
 999                         .prcm_reg_id = 1,
1000                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
1001                         .module_offs = OMAP3430_PER_MOD,
1002                         .idlest_reg_id = 1,
1003                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
1004                 },
1005         },
1006         .slaves         = omap3xxx_timer8_slaves,
1007         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
1008         .class          = &omap3xxx_timer_hwmod_class,
1009         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1010 };
1011
1012 /* timer9 */
1013 static struct omap_hwmod omap3xxx_timer9_hwmod;
1014 static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
1015         { .irq = 45, },
1016 };
1017
1018 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
1019         {
1020                 .pa_start       = 0x49040000,
1021                 .pa_end         = 0x49040000 + SZ_1K - 1,
1022                 .flags          = ADDR_TYPE_RT
1023         },
1024         { }
1025 };
1026
1027 /* l4_per -> timer9 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
1029         .master         = &omap3xxx_l4_per_hwmod,
1030         .slave          = &omap3xxx_timer9_hwmod,
1031         .clk            = "gpt9_ick",
1032         .addr           = omap3xxx_timer9_addrs,
1033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1034 };
1035
1036 /* timer9 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
1038         &omap3xxx_l4_per__timer9,
1039 };
1040
1041 /* timer9 hwmod */
1042 static struct omap_hwmod omap3xxx_timer9_hwmod = {
1043         .name           = "timer9",
1044         .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
1045         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
1046         .main_clk       = "gpt9_fck",
1047         .prcm           = {
1048                 .omap2 = {
1049                         .prcm_reg_id = 1,
1050                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
1051                         .module_offs = OMAP3430_PER_MOD,
1052                         .idlest_reg_id = 1,
1053                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
1054                 },
1055         },
1056         .slaves         = omap3xxx_timer9_slaves,
1057         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
1058         .class          = &omap3xxx_timer_hwmod_class,
1059         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1060 };
1061
1062 /* timer10 */
1063 static struct omap_hwmod omap3xxx_timer10_hwmod;
1064 static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
1065         { .irq = 46, },
1066 };
1067
1068 static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
1069         {
1070                 .pa_start       = 0x48086000,
1071                 .pa_end         = 0x48086000 + SZ_1K - 1,
1072                 .flags          = ADDR_TYPE_RT
1073         },
1074         { }
1075 };
1076
1077 /* l4_core -> timer10 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1079         .master         = &omap3xxx_l4_core_hwmod,
1080         .slave          = &omap3xxx_timer10_hwmod,
1081         .clk            = "gpt10_ick",
1082         .addr           = omap3xxx_timer10_addrs,
1083         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1084 };
1085
1086 /* timer10 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1088         &omap3xxx_l4_core__timer10,
1089 };
1090
1091 /* timer10 hwmod */
1092 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1093         .name           = "timer10",
1094         .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
1095         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
1096         .main_clk       = "gpt10_fck",
1097         .prcm           = {
1098                 .omap2 = {
1099                         .prcm_reg_id = 1,
1100                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1101                         .module_offs = CORE_MOD,
1102                         .idlest_reg_id = 1,
1103                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1104                 },
1105         },
1106         .slaves         = omap3xxx_timer10_slaves,
1107         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1108         .class          = &omap3xxx_timer_1ms_hwmod_class,
1109         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1110 };
1111
1112 /* timer11 */
1113 static struct omap_hwmod omap3xxx_timer11_hwmod;
1114 static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
1115         { .irq = 47, },
1116 };
1117
1118 static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
1119         {
1120                 .pa_start       = 0x48088000,
1121                 .pa_end         = 0x48088000 + SZ_1K - 1,
1122                 .flags          = ADDR_TYPE_RT
1123         },
1124         { }
1125 };
1126
1127 /* l4_core -> timer11 */
1128 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1129         .master         = &omap3xxx_l4_core_hwmod,
1130         .slave          = &omap3xxx_timer11_hwmod,
1131         .clk            = "gpt11_ick",
1132         .addr           = omap3xxx_timer11_addrs,
1133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1134 };
1135
1136 /* timer11 slave port */
1137 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1138         &omap3xxx_l4_core__timer11,
1139 };
1140
1141 /* timer11 hwmod */
1142 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1143         .name           = "timer11",
1144         .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
1145         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
1146         .main_clk       = "gpt11_fck",
1147         .prcm           = {
1148                 .omap2 = {
1149                         .prcm_reg_id = 1,
1150                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1151                         .module_offs = CORE_MOD,
1152                         .idlest_reg_id = 1,
1153                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1154                 },
1155         },
1156         .slaves         = omap3xxx_timer11_slaves,
1157         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1158         .class          = &omap3xxx_timer_hwmod_class,
1159         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1160 };
1161
1162 /* timer12*/
1163 static struct omap_hwmod omap3xxx_timer12_hwmod;
1164 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1165         { .irq = 95, },
1166 };
1167
1168 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1169         {
1170                 .pa_start       = 0x48304000,
1171                 .pa_end         = 0x48304000 + SZ_1K - 1,
1172                 .flags          = ADDR_TYPE_RT
1173         },
1174         { }
1175 };
1176
1177 /* l4_core -> timer12 */
1178 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1179         .master         = &omap3xxx_l4_core_hwmod,
1180         .slave          = &omap3xxx_timer12_hwmod,
1181         .clk            = "gpt12_ick",
1182         .addr           = omap3xxx_timer12_addrs,
1183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1184 };
1185
1186 /* timer12 slave port */
1187 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1188         &omap3xxx_l4_core__timer12,
1189 };
1190
1191 /* timer12 hwmod */
1192 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1193         .name           = "timer12",
1194         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1195         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
1196         .main_clk       = "gpt12_fck",
1197         .prcm           = {
1198                 .omap2 = {
1199                         .prcm_reg_id = 1,
1200                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1201                         .module_offs = WKUP_MOD,
1202                         .idlest_reg_id = 1,
1203                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1204                 },
1205         },
1206         .slaves         = omap3xxx_timer12_slaves,
1207         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1208         .class          = &omap3xxx_timer_hwmod_class,
1209         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1210 };
1211
1212 /* l4_wkup -> wd_timer2 */
1213 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1214         {
1215                 .pa_start       = 0x48314000,
1216                 .pa_end         = 0x4831407f,
1217                 .flags          = ADDR_TYPE_RT
1218         },
1219         { }
1220 };
1221
1222 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1223         .master         = &omap3xxx_l4_wkup_hwmod,
1224         .slave          = &omap3xxx_wd_timer2_hwmod,
1225         .clk            = "wdt2_ick",
1226         .addr           = omap3xxx_wd_timer2_addrs,
1227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1228 };
1229
1230 /*
1231  * 'wd_timer' class
1232  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1233  * overflow condition
1234  */
1235
1236 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1237         .rev_offs       = 0x0000,
1238         .sysc_offs      = 0x0010,
1239         .syss_offs      = 0x0014,
1240         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1241                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1242                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1243                            SYSS_HAS_RESET_STATUS),
1244         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1245         .sysc_fields    = &omap_hwmod_sysc_type1,
1246 };
1247
1248 /* I2C common */
1249 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1250         .rev_offs       = 0x00,
1251         .sysc_offs      = 0x20,
1252         .syss_offs      = 0x10,
1253         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1254                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1255                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1256         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1257         .sysc_fields    = &omap_hwmod_sysc_type1,
1258 };
1259
1260 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1261         .name           = "wd_timer",
1262         .sysc           = &omap3xxx_wd_timer_sysc,
1263         .pre_shutdown   = &omap2_wd_timer_disable
1264 };
1265
1266 /* wd_timer2 */
1267 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1268         &omap3xxx_l4_wkup__wd_timer2,
1269 };
1270
1271 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1272         .name           = "wd_timer2",
1273         .class          = &omap3xxx_wd_timer_hwmod_class,
1274         .main_clk       = "wdt2_fck",
1275         .prcm           = {
1276                 .omap2 = {
1277                         .prcm_reg_id = 1,
1278                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1279                         .module_offs = WKUP_MOD,
1280                         .idlest_reg_id = 1,
1281                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1282                 },
1283         },
1284         .slaves         = omap3xxx_wd_timer2_slaves,
1285         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1286         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1287         /*
1288          * XXX: Use software supervised mode, HW supervised smartidle seems to
1289          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1290          */
1291         .flags          = HWMOD_SWSUP_SIDLE,
1292 };
1293
1294 /* UART common */
1295
1296 static struct omap_hwmod_class_sysconfig uart_sysc = {
1297         .rev_offs       = 0x50,
1298         .sysc_offs      = 0x54,
1299         .syss_offs      = 0x58,
1300         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
1301                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1302                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1303         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304         .sysc_fields    = &omap_hwmod_sysc_type1,
1305 };
1306
1307 static struct omap_hwmod_class uart_class = {
1308         .name = "uart",
1309         .sysc = &uart_sysc,
1310 };
1311
1312 /* UART1 */
1313
1314 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
1315         { .irq = INT_24XX_UART1_IRQ, },
1316 };
1317
1318 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1319         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1320         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1321 };
1322
1323 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1324         &omap3_l4_core__uart1,
1325 };
1326
1327 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1328         .name           = "uart1",
1329         .mpu_irqs       = uart1_mpu_irqs,
1330         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
1331         .sdma_reqs      = uart1_sdma_reqs,
1332         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
1333         .main_clk       = "uart1_fck",
1334         .prcm           = {
1335                 .omap2 = {
1336                         .module_offs = CORE_MOD,
1337                         .prcm_reg_id = 1,
1338                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1339                         .idlest_reg_id = 1,
1340                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1341                 },
1342         },
1343         .slaves         = omap3xxx_uart1_slaves,
1344         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1345         .class          = &uart_class,
1346         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1347 };
1348
1349 /* UART2 */
1350
1351 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
1352         { .irq = INT_24XX_UART2_IRQ, },
1353 };
1354
1355 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1356         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1357         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1358 };
1359
1360 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1361         &omap3_l4_core__uart2,
1362 };
1363
1364 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1365         .name           = "uart2",
1366         .mpu_irqs       = uart2_mpu_irqs,
1367         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
1368         .sdma_reqs      = uart2_sdma_reqs,
1369         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
1370         .main_clk       = "uart2_fck",
1371         .prcm           = {
1372                 .omap2 = {
1373                         .module_offs = CORE_MOD,
1374                         .prcm_reg_id = 1,
1375                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1376                         .idlest_reg_id = 1,
1377                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1378                 },
1379         },
1380         .slaves         = omap3xxx_uart2_slaves,
1381         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1382         .class          = &uart_class,
1383         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1384 };
1385
1386 /* UART3 */
1387
1388 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
1389         { .irq = INT_24XX_UART3_IRQ, },
1390 };
1391
1392 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1393         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1394         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1395 };
1396
1397 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1398         &omap3_l4_per__uart3,
1399 };
1400
1401 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1402         .name           = "uart3",
1403         .mpu_irqs       = uart3_mpu_irqs,
1404         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
1405         .sdma_reqs      = uart3_sdma_reqs,
1406         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
1407         .main_clk       = "uart3_fck",
1408         .prcm           = {
1409                 .omap2 = {
1410                         .module_offs = OMAP3430_PER_MOD,
1411                         .prcm_reg_id = 1,
1412                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1413                         .idlest_reg_id = 1,
1414                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1415                 },
1416         },
1417         .slaves         = omap3xxx_uart3_slaves,
1418         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1419         .class          = &uart_class,
1420         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1421 };
1422
1423 /* UART4 */
1424
1425 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1426         { .irq = INT_36XX_UART4_IRQ, },
1427 };
1428
1429 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1430         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1431         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1432 };
1433
1434 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1435         &omap3_l4_per__uart4,
1436 };
1437
1438 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1439         .name           = "uart4",
1440         .mpu_irqs       = uart4_mpu_irqs,
1441         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
1442         .sdma_reqs      = uart4_sdma_reqs,
1443         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
1444         .main_clk       = "uart4_fck",
1445         .prcm           = {
1446                 .omap2 = {
1447                         .module_offs = OMAP3430_PER_MOD,
1448                         .prcm_reg_id = 1,
1449                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1450                         .idlest_reg_id = 1,
1451                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1452                 },
1453         },
1454         .slaves         = omap3xxx_uart4_slaves,
1455         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1456         .class          = &uart_class,
1457         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1458 };
1459
1460 static struct omap_hwmod_class i2c_class = {
1461         .name = "i2c",
1462         .sysc = &i2c_sysc,
1463 };
1464
1465 /*
1466  * 'dss' class
1467  * display sub-system
1468  */
1469
1470 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1471         .rev_offs       = 0x0000,
1472         .sysc_offs      = 0x0010,
1473         .syss_offs      = 0x0014,
1474         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1475         .sysc_fields    = &omap_hwmod_sysc_type1,
1476 };
1477
1478 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1479         .name = "dss",
1480         .sysc = &omap3xxx_dss_sysc,
1481 };
1482
1483 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1484         { .name = "dispc", .dma_req = 5 },
1485         { .name = "dsi1", .dma_req = 74 },
1486 };
1487
1488 /* dss */
1489 /* dss master ports */
1490 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1491         &omap3xxx_dss__l3,
1492 };
1493
1494 static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
1495         {
1496                 .pa_start       = 0x48050000,
1497                 .pa_end         = 0x480503FF,
1498                 .flags          = ADDR_TYPE_RT
1499         },
1500         { }
1501 };
1502
1503 /* l4_core -> dss */
1504 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1505         .master         = &omap3xxx_l4_core_hwmod,
1506         .slave          = &omap3430es1_dss_core_hwmod,
1507         .clk            = "dss_ick",
1508         .addr           = omap3xxx_dss_addrs,
1509         .fw = {
1510                 .omap2 = {
1511                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1512                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1513                         .flags  = OMAP_FIREWALL_L4,
1514                 }
1515         },
1516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1517 };
1518
1519 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1520         .master         = &omap3xxx_l4_core_hwmod,
1521         .slave          = &omap3xxx_dss_core_hwmod,
1522         .clk            = "dss_ick",
1523         .addr           = omap3xxx_dss_addrs,
1524         .fw = {
1525                 .omap2 = {
1526                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1527                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1528                         .flags  = OMAP_FIREWALL_L4,
1529                 }
1530         },
1531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1532 };
1533
1534 /* dss slave ports */
1535 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1536         &omap3430es1_l4_core__dss,
1537 };
1538
1539 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1540         &omap3xxx_l4_core__dss,
1541 };
1542
1543 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1544         { .role = "tv_clk", .clk = "dss_tv_fck" },
1545         { .role = "video_clk", .clk = "dss_96m_fck" },
1546         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1547 };
1548
1549 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1550         .name           = "dss_core",
1551         .class          = &omap3xxx_dss_hwmod_class,
1552         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1553         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1554         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1555
1556         .prcm           = {
1557                 .omap2 = {
1558                         .prcm_reg_id = 1,
1559                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1560                         .module_offs = OMAP3430_DSS_MOD,
1561                         .idlest_reg_id = 1,
1562                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1563                 },
1564         },
1565         .opt_clks       = dss_opt_clks,
1566         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1567         .slaves         = omap3430es1_dss_slaves,
1568         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1569         .masters        = omap3xxx_dss_masters,
1570         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1571         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1572         .flags          = HWMOD_NO_IDLEST,
1573 };
1574
1575 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1576         .name           = "dss_core",
1577         .class          = &omap3xxx_dss_hwmod_class,
1578         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1579         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1580         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1581
1582         .prcm           = {
1583                 .omap2 = {
1584                         .prcm_reg_id = 1,
1585                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1586                         .module_offs = OMAP3430_DSS_MOD,
1587                         .idlest_reg_id = 1,
1588                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1589                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1590                 },
1591         },
1592         .opt_clks       = dss_opt_clks,
1593         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1594         .slaves         = omap3xxx_dss_slaves,
1595         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1596         .masters        = omap3xxx_dss_masters,
1597         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1598         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1599                                 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1600 };
1601
1602 /*
1603  * 'dispc' class
1604  * display controller
1605  */
1606
1607 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1608         .rev_offs       = 0x0000,
1609         .sysc_offs      = 0x0010,
1610         .syss_offs      = 0x0014,
1611         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1612                            SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1613                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1614         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1615                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1616         .sysc_fields    = &omap_hwmod_sysc_type1,
1617 };
1618
1619 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1620         .name = "dispc",
1621         .sysc = &omap3xxx_dispc_sysc,
1622 };
1623
1624 static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
1625         { .irq = 25 },
1626 };
1627
1628 static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
1629         {
1630                 .pa_start       = 0x48050400,
1631                 .pa_end         = 0x480507FF,
1632                 .flags          = ADDR_TYPE_RT
1633         },
1634         { }
1635 };
1636
1637 /* l4_core -> dss_dispc */
1638 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1639         .master         = &omap3xxx_l4_core_hwmod,
1640         .slave          = &omap3xxx_dss_dispc_hwmod,
1641         .clk            = "dss_ick",
1642         .addr           = omap3xxx_dss_dispc_addrs,
1643         .fw = {
1644                 .omap2 = {
1645                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1646                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1647                         .flags  = OMAP_FIREWALL_L4,
1648                 }
1649         },
1650         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1651 };
1652
1653 /* dss_dispc slave ports */
1654 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1655         &omap3xxx_l4_core__dss_dispc,
1656 };
1657
1658 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1659         .name           = "dss_dispc",
1660         .class          = &omap3xxx_dispc_hwmod_class,
1661         .mpu_irqs       = omap3xxx_dispc_irqs,
1662         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dispc_irqs),
1663         .main_clk       = "dss1_alwon_fck",
1664         .prcm           = {
1665                 .omap2 = {
1666                         .prcm_reg_id = 1,
1667                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1668                         .module_offs = OMAP3430_DSS_MOD,
1669                 },
1670         },
1671         .slaves         = omap3xxx_dss_dispc_slaves,
1672         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1673         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1674                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1675                                 CHIP_GE_OMAP3630ES1_1),
1676         .flags          = HWMOD_NO_IDLEST,
1677 };
1678
1679 /*
1680  * 'dsi' class
1681  * display serial interface controller
1682  */
1683
1684 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1685         .name = "dsi",
1686 };
1687
1688 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1689         { .irq = 25 },
1690 };
1691
1692 /* dss_dsi1 */
1693 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1694         {
1695                 .pa_start       = 0x4804FC00,
1696                 .pa_end         = 0x4804FFFF,
1697                 .flags          = ADDR_TYPE_RT
1698         },
1699         { }
1700 };
1701
1702 /* l4_core -> dss_dsi1 */
1703 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1704         .master         = &omap3xxx_l4_core_hwmod,
1705         .slave          = &omap3xxx_dss_dsi1_hwmod,
1706         .addr           = omap3xxx_dss_dsi1_addrs,
1707         .fw = {
1708                 .omap2 = {
1709                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1710                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1711                         .flags  = OMAP_FIREWALL_L4,
1712                 }
1713         },
1714         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1715 };
1716
1717 /* dss_dsi1 slave ports */
1718 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1719         &omap3xxx_l4_core__dss_dsi1,
1720 };
1721
1722 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1723         .name           = "dss_dsi1",
1724         .class          = &omap3xxx_dsi_hwmod_class,
1725         .mpu_irqs       = omap3xxx_dsi1_irqs,
1726         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dsi1_irqs),
1727         .main_clk       = "dss1_alwon_fck",
1728         .prcm           = {
1729                 .omap2 = {
1730                         .prcm_reg_id = 1,
1731                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1732                         .module_offs = OMAP3430_DSS_MOD,
1733                 },
1734         },
1735         .slaves         = omap3xxx_dss_dsi1_slaves,
1736         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1737         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1738                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1739                                 CHIP_GE_OMAP3630ES1_1),
1740         .flags          = HWMOD_NO_IDLEST,
1741 };
1742
1743 /*
1744  * 'rfbi' class
1745  * remote frame buffer interface
1746  */
1747
1748 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1749         .rev_offs       = 0x0000,
1750         .sysc_offs      = 0x0010,
1751         .syss_offs      = 0x0014,
1752         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1753                            SYSC_HAS_AUTOIDLE),
1754         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1755         .sysc_fields    = &omap_hwmod_sysc_type1,
1756 };
1757
1758 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1759         .name = "rfbi",
1760         .sysc = &omap3xxx_rfbi_sysc,
1761 };
1762
1763 static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
1764         {
1765                 .pa_start       = 0x48050800,
1766                 .pa_end         = 0x48050BFF,
1767                 .flags          = ADDR_TYPE_RT
1768         },
1769         { }
1770 };
1771
1772 /* l4_core -> dss_rfbi */
1773 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1774         .master         = &omap3xxx_l4_core_hwmod,
1775         .slave          = &omap3xxx_dss_rfbi_hwmod,
1776         .clk            = "dss_ick",
1777         .addr           = omap3xxx_dss_rfbi_addrs,
1778         .fw = {
1779                 .omap2 = {
1780                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1781                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1782                         .flags  = OMAP_FIREWALL_L4,
1783                 }
1784         },
1785         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1786 };
1787
1788 /* dss_rfbi slave ports */
1789 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1790         &omap3xxx_l4_core__dss_rfbi,
1791 };
1792
1793 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1794         .name           = "dss_rfbi",
1795         .class          = &omap3xxx_rfbi_hwmod_class,
1796         .main_clk       = "dss1_alwon_fck",
1797         .prcm           = {
1798                 .omap2 = {
1799                         .prcm_reg_id = 1,
1800                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1801                         .module_offs = OMAP3430_DSS_MOD,
1802                 },
1803         },
1804         .slaves         = omap3xxx_dss_rfbi_slaves,
1805         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1806         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1807                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1808                                 CHIP_GE_OMAP3630ES1_1),
1809         .flags          = HWMOD_NO_IDLEST,
1810 };
1811
1812 /*
1813  * 'venc' class
1814  * video encoder
1815  */
1816
1817 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1818         .name = "venc",
1819 };
1820
1821 /* dss_venc */
1822 static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
1823         {
1824                 .pa_start       = 0x48050C00,
1825                 .pa_end         = 0x48050FFF,
1826                 .flags          = ADDR_TYPE_RT
1827         },
1828         { }
1829 };
1830
1831 /* l4_core -> dss_venc */
1832 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1833         .master         = &omap3xxx_l4_core_hwmod,
1834         .slave          = &omap3xxx_dss_venc_hwmod,
1835         .clk            = "dss_tv_fck",
1836         .addr           = omap3xxx_dss_venc_addrs,
1837         .fw = {
1838                 .omap2 = {
1839                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1840                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1841                         .flags  = OMAP_FIREWALL_L4,
1842                 }
1843         },
1844         .flags          = OCPIF_SWSUP_IDLE,
1845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1846 };
1847
1848 /* dss_venc slave ports */
1849 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1850         &omap3xxx_l4_core__dss_venc,
1851 };
1852
1853 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1854         .name           = "dss_venc",
1855         .class          = &omap3xxx_venc_hwmod_class,
1856         .main_clk       = "dss1_alwon_fck",
1857         .prcm           = {
1858                 .omap2 = {
1859                         .prcm_reg_id = 1,
1860                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1861                         .module_offs = OMAP3430_DSS_MOD,
1862                 },
1863         },
1864         .slaves         = omap3xxx_dss_venc_slaves,
1865         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1866         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1867                                 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1868                                 CHIP_GE_OMAP3630ES1_1),
1869         .flags          = HWMOD_NO_IDLEST,
1870 };
1871
1872 /* I2C1 */
1873
1874 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1875         .fifo_depth     = 8, /* bytes */
1876 };
1877
1878 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1879         { .irq = INT_24XX_I2C1_IRQ, },
1880 };
1881
1882 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1883         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1884         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1885 };
1886
1887 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1888         &omap3_l4_core__i2c1,
1889 };
1890
1891 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1892         .name           = "i2c1",
1893         .mpu_irqs       = i2c1_mpu_irqs,
1894         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
1895         .sdma_reqs      = i2c1_sdma_reqs,
1896         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1897         .main_clk       = "i2c1_fck",
1898         .prcm           = {
1899                 .omap2 = {
1900                         .module_offs = CORE_MOD,
1901                         .prcm_reg_id = 1,
1902                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1903                         .idlest_reg_id = 1,
1904                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1905                 },
1906         },
1907         .slaves         = omap3xxx_i2c1_slaves,
1908         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1909         .class          = &i2c_class,
1910         .dev_attr       = &i2c1_dev_attr,
1911         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1912 };
1913
1914 /* I2C2 */
1915
1916 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1917         .fifo_depth     = 8, /* bytes */
1918 };
1919
1920 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1921         { .irq = INT_24XX_I2C2_IRQ, },
1922 };
1923
1924 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1925         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1926         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1927 };
1928
1929 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1930         &omap3_l4_core__i2c2,
1931 };
1932
1933 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1934         .name           = "i2c2",
1935         .mpu_irqs       = i2c2_mpu_irqs,
1936         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
1937         .sdma_reqs      = i2c2_sdma_reqs,
1938         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1939         .main_clk       = "i2c2_fck",
1940         .prcm           = {
1941                 .omap2 = {
1942                         .module_offs = CORE_MOD,
1943                         .prcm_reg_id = 1,
1944                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1945                         .idlest_reg_id = 1,
1946                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1947                 },
1948         },
1949         .slaves         = omap3xxx_i2c2_slaves,
1950         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1951         .class          = &i2c_class,
1952         .dev_attr       = &i2c2_dev_attr,
1953         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1954 };
1955
1956 /* I2C3 */
1957
1958 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1959         .fifo_depth     = 64, /* bytes */
1960 };
1961
1962 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1963         { .irq = INT_34XX_I2C3_IRQ, },
1964 };
1965
1966 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1967         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1968         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1969 };
1970
1971 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1972         &omap3_l4_core__i2c3,
1973 };
1974
1975 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1976         .name           = "i2c3",
1977         .mpu_irqs       = i2c3_mpu_irqs,
1978         .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
1979         .sdma_reqs      = i2c3_sdma_reqs,
1980         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
1981         .main_clk       = "i2c3_fck",
1982         .prcm           = {
1983                 .omap2 = {
1984                         .module_offs = CORE_MOD,
1985                         .prcm_reg_id = 1,
1986                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1987                         .idlest_reg_id = 1,
1988                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1989                 },
1990         },
1991         .slaves         = omap3xxx_i2c3_slaves,
1992         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1993         .class          = &i2c_class,
1994         .dev_attr       = &i2c3_dev_attr,
1995         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1996 };
1997
1998 /* l4_wkup -> gpio1 */
1999 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2000         {
2001                 .pa_start       = 0x48310000,
2002                 .pa_end         = 0x483101ff,
2003                 .flags          = ADDR_TYPE_RT
2004         },
2005         { }
2006 };
2007
2008 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2009         .master         = &omap3xxx_l4_wkup_hwmod,
2010         .slave          = &omap3xxx_gpio1_hwmod,
2011         .addr           = omap3xxx_gpio1_addrs,
2012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2013 };
2014
2015 /* l4_per -> gpio2 */
2016 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2017         {
2018                 .pa_start       = 0x49050000,
2019                 .pa_end         = 0x490501ff,
2020                 .flags          = ADDR_TYPE_RT
2021         },
2022         { }
2023 };
2024
2025 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2026         .master         = &omap3xxx_l4_per_hwmod,
2027         .slave          = &omap3xxx_gpio2_hwmod,
2028         .addr           = omap3xxx_gpio2_addrs,
2029         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2030 };
2031
2032 /* l4_per -> gpio3 */
2033 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2034         {
2035                 .pa_start       = 0x49052000,
2036                 .pa_end         = 0x490521ff,
2037                 .flags          = ADDR_TYPE_RT
2038         },
2039         { }
2040 };
2041
2042 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2043         .master         = &omap3xxx_l4_per_hwmod,
2044         .slave          = &omap3xxx_gpio3_hwmod,
2045         .addr           = omap3xxx_gpio3_addrs,
2046         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2047 };
2048
2049 /* l4_per -> gpio4 */
2050 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2051         {
2052                 .pa_start       = 0x49054000,
2053                 .pa_end         = 0x490541ff,
2054                 .flags          = ADDR_TYPE_RT
2055         },
2056         { }
2057 };
2058
2059 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2060         .master         = &omap3xxx_l4_per_hwmod,
2061         .slave          = &omap3xxx_gpio4_hwmod,
2062         .addr           = omap3xxx_gpio4_addrs,
2063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2064 };
2065
2066 /* l4_per -> gpio5 */
2067 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2068         {
2069                 .pa_start       = 0x49056000,
2070                 .pa_end         = 0x490561ff,
2071                 .flags          = ADDR_TYPE_RT
2072         },
2073         { }
2074 };
2075
2076 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2077         .master         = &omap3xxx_l4_per_hwmod,
2078         .slave          = &omap3xxx_gpio5_hwmod,
2079         .addr           = omap3xxx_gpio5_addrs,
2080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2081 };
2082
2083 /* l4_per -> gpio6 */
2084 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2085         {
2086                 .pa_start       = 0x49058000,
2087                 .pa_end         = 0x490581ff,
2088                 .flags          = ADDR_TYPE_RT
2089         },
2090         { }
2091 };
2092
2093 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2094         .master         = &omap3xxx_l4_per_hwmod,
2095         .slave          = &omap3xxx_gpio6_hwmod,
2096         .addr           = omap3xxx_gpio6_addrs,
2097         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2098 };
2099
2100 /*
2101  * 'gpio' class
2102  * general purpose io module
2103  */
2104
2105 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
2106         .rev_offs       = 0x0000,
2107         .sysc_offs      = 0x0010,
2108         .syss_offs      = 0x0014,
2109         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2110                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
2111                            SYSS_HAS_RESET_STATUS),
2112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2113         .sysc_fields    = &omap_hwmod_sysc_type1,
2114 };
2115
2116 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
2117         .name = "gpio",
2118         .sysc = &omap3xxx_gpio_sysc,
2119         .rev = 1,
2120 };
2121
2122 /* gpio_dev_attr*/
2123 static struct omap_gpio_dev_attr gpio_dev_attr = {
2124         .bank_width = 32,
2125         .dbck_flag = true,
2126 };
2127
2128 /* gpio1 */
2129 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
2130         { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
2131 };
2132
2133 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
2134         { .role = "dbclk", .clk = "gpio1_dbck", },
2135 };
2136
2137 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
2138         &omap3xxx_l4_wkup__gpio1,
2139 };
2140
2141 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
2142         .name           = "gpio1",
2143         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2144         .mpu_irqs       = omap3xxx_gpio1_irqs,
2145         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
2146         .main_clk       = "gpio1_ick",
2147         .opt_clks       = gpio1_opt_clks,
2148         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
2149         .prcm           = {
2150                 .omap2 = {
2151                         .prcm_reg_id = 1,
2152                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
2153                         .module_offs = WKUP_MOD,
2154                         .idlest_reg_id = 1,
2155                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
2156                 },
2157         },
2158         .slaves         = omap3xxx_gpio1_slaves,
2159         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
2160         .class          = &omap3xxx_gpio_hwmod_class,
2161         .dev_attr       = &gpio_dev_attr,
2162         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2163 };
2164
2165 /* gpio2 */
2166 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
2167         { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
2168 };
2169
2170 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
2171         { .role = "dbclk", .clk = "gpio2_dbck", },
2172 };
2173
2174 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
2175         &omap3xxx_l4_per__gpio2,
2176 };
2177
2178 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2179         .name           = "gpio2",
2180         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2181         .mpu_irqs       = omap3xxx_gpio2_irqs,
2182         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
2183         .main_clk       = "gpio2_ick",
2184         .opt_clks       = gpio2_opt_clks,
2185         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
2186         .prcm           = {
2187                 .omap2 = {
2188                         .prcm_reg_id = 1,
2189                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2190                         .module_offs = OMAP3430_PER_MOD,
2191                         .idlest_reg_id = 1,
2192                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2193                 },
2194         },
2195         .slaves         = omap3xxx_gpio2_slaves,
2196         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2197         .class          = &omap3xxx_gpio_hwmod_class,
2198         .dev_attr       = &gpio_dev_attr,
2199         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2200 };
2201
2202 /* gpio3 */
2203 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
2204         { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
2205 };
2206
2207 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2208         { .role = "dbclk", .clk = "gpio3_dbck", },
2209 };
2210
2211 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2212         &omap3xxx_l4_per__gpio3,
2213 };
2214
2215 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2216         .name           = "gpio3",
2217         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2218         .mpu_irqs       = omap3xxx_gpio3_irqs,
2219         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
2220         .main_clk       = "gpio3_ick",
2221         .opt_clks       = gpio3_opt_clks,
2222         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
2223         .prcm           = {
2224                 .omap2 = {
2225                         .prcm_reg_id = 1,
2226                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2227                         .module_offs = OMAP3430_PER_MOD,
2228                         .idlest_reg_id = 1,
2229                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2230                 },
2231         },
2232         .slaves         = omap3xxx_gpio3_slaves,
2233         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2234         .class          = &omap3xxx_gpio_hwmod_class,
2235         .dev_attr       = &gpio_dev_attr,
2236         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2237 };
2238
2239 /* gpio4 */
2240 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
2241         { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
2242 };
2243
2244 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2245         { .role = "dbclk", .clk = "gpio4_dbck", },
2246 };
2247
2248 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2249         &omap3xxx_l4_per__gpio4,
2250 };
2251
2252 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2253         .name           = "gpio4",
2254         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2255         .mpu_irqs       = omap3xxx_gpio4_irqs,
2256         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
2257         .main_clk       = "gpio4_ick",
2258         .opt_clks       = gpio4_opt_clks,
2259         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2260         .prcm           = {
2261                 .omap2 = {
2262                         .prcm_reg_id = 1,
2263                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2264                         .module_offs = OMAP3430_PER_MOD,
2265                         .idlest_reg_id = 1,
2266                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2267                 },
2268         },
2269         .slaves         = omap3xxx_gpio4_slaves,
2270         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2271         .class          = &omap3xxx_gpio_hwmod_class,
2272         .dev_attr       = &gpio_dev_attr,
2273         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2274 };
2275
2276 /* gpio5 */
2277 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2278         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2279 };
2280
2281 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2282         { .role = "dbclk", .clk = "gpio5_dbck", },
2283 };
2284
2285 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2286         &omap3xxx_l4_per__gpio5,
2287 };
2288
2289 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2290         .name           = "gpio5",
2291         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2292         .mpu_irqs       = omap3xxx_gpio5_irqs,
2293         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
2294         .main_clk       = "gpio5_ick",
2295         .opt_clks       = gpio5_opt_clks,
2296         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2297         .prcm           = {
2298                 .omap2 = {
2299                         .prcm_reg_id = 1,
2300                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2301                         .module_offs = OMAP3430_PER_MOD,
2302                         .idlest_reg_id = 1,
2303                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2304                 },
2305         },
2306         .slaves         = omap3xxx_gpio5_slaves,
2307         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2308         .class          = &omap3xxx_gpio_hwmod_class,
2309         .dev_attr       = &gpio_dev_attr,
2310         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2311 };
2312
2313 /* gpio6 */
2314 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2315         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2316 };
2317
2318 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2319         { .role = "dbclk", .clk = "gpio6_dbck", },
2320 };
2321
2322 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2323         &omap3xxx_l4_per__gpio6,
2324 };
2325
2326 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2327         .name           = "gpio6",
2328         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2329         .mpu_irqs       = omap3xxx_gpio6_irqs,
2330         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
2331         .main_clk       = "gpio6_ick",
2332         .opt_clks       = gpio6_opt_clks,
2333         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2334         .prcm           = {
2335                 .omap2 = {
2336                         .prcm_reg_id = 1,
2337                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2338                         .module_offs = OMAP3430_PER_MOD,
2339                         .idlest_reg_id = 1,
2340                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2341                 },
2342         },
2343         .slaves         = omap3xxx_gpio6_slaves,
2344         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2345         .class          = &omap3xxx_gpio_hwmod_class,
2346         .dev_attr       = &gpio_dev_attr,
2347         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2348 };
2349
2350 /* dma_system -> L3 */
2351 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2352         .master         = &omap3xxx_dma_system_hwmod,
2353         .slave          = &omap3xxx_l3_main_hwmod,
2354         .clk            = "core_l3_ick",
2355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2356 };
2357
2358 /* dma attributes */
2359 static struct omap_dma_dev_attr dma_dev_attr = {
2360         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2361                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2362         .lch_count = 32,
2363 };
2364
2365 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2366         .rev_offs       = 0x0000,
2367         .sysc_offs      = 0x002c,
2368         .syss_offs      = 0x0028,
2369         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2370                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2371                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2372                            SYSS_HAS_RESET_STATUS),
2373         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2374                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2375         .sysc_fields    = &omap_hwmod_sysc_type1,
2376 };
2377
2378 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2379         .name = "dma",
2380         .sysc = &omap3xxx_dma_sysc,
2381 };
2382
2383 /* dma_system */
2384 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
2385         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
2386         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
2387         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
2388         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
2389 };
2390
2391 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2392         {
2393                 .pa_start       = 0x48056000,
2394                 .pa_end         = 0x48056fff,
2395                 .flags          = ADDR_TYPE_RT
2396         },
2397         { }
2398 };
2399
2400 /* dma_system master ports */
2401 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2402         &omap3xxx_dma_system__l3,
2403 };
2404
2405 /* l4_cfg -> dma_system */
2406 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2407         .master         = &omap3xxx_l4_core_hwmod,
2408         .slave          = &omap3xxx_dma_system_hwmod,
2409         .clk            = "core_l4_ick",
2410         .addr           = omap3xxx_dma_system_addrs,
2411         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2412 };
2413
2414 /* dma_system slave ports */
2415 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2416         &omap3xxx_l4_core__dma_system,
2417 };
2418
2419 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2420         .name           = "dma",
2421         .class          = &omap3xxx_dma_hwmod_class,
2422         .mpu_irqs       = omap3xxx_dma_system_irqs,
2423         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
2424         .main_clk       = "core_l3_ick",
2425         .prcm = {
2426                 .omap2 = {
2427                         .module_offs            = CORE_MOD,
2428                         .prcm_reg_id            = 1,
2429                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2430                         .idlest_reg_id          = 1,
2431                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2432                 },
2433         },
2434         .slaves         = omap3xxx_dma_system_slaves,
2435         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2436         .masters        = omap3xxx_dma_system_masters,
2437         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2438         .dev_attr       = &dma_dev_attr,
2439         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2440         .flags          = HWMOD_NO_IDLEST,
2441 };
2442
2443 /*
2444  * 'mcbsp' class
2445  * multi channel buffered serial port controller
2446  */
2447
2448 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2449         .sysc_offs      = 0x008c,
2450         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2451                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2452         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2453         .sysc_fields    = &omap_hwmod_sysc_type1,
2454         .clockact       = 0x2,
2455 };
2456
2457 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2458         .name = "mcbsp",
2459         .sysc = &omap3xxx_mcbsp_sysc,
2460         .rev  = MCBSP_CONFIG_TYPE3,
2461 };
2462
2463 /* mcbsp1 */
2464 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2465         { .name = "irq", .irq = 16 },
2466         { .name = "tx", .irq = 59 },
2467         { .name = "rx", .irq = 60 },
2468 };
2469
2470 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2471         { .name = "rx", .dma_req = 32 },
2472         { .name = "tx", .dma_req = 31 },
2473 };
2474
2475 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2476         {
2477                 .name           = "mpu",
2478                 .pa_start       = 0x48074000,
2479                 .pa_end         = 0x480740ff,
2480                 .flags          = ADDR_TYPE_RT
2481         },
2482         { }
2483 };
2484
2485 /* l4_core -> mcbsp1 */
2486 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2487         .master         = &omap3xxx_l4_core_hwmod,
2488         .slave          = &omap3xxx_mcbsp1_hwmod,
2489         .clk            = "mcbsp1_ick",
2490         .addr           = omap3xxx_mcbsp1_addrs,
2491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2492 };
2493
2494 /* mcbsp1 slave ports */
2495 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2496         &omap3xxx_l4_core__mcbsp1,
2497 };
2498
2499 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2500         .name           = "mcbsp1",
2501         .class          = &omap3xxx_mcbsp_hwmod_class,
2502         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2503         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2504         .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
2505         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2506         .main_clk       = "mcbsp1_fck",
2507         .prcm           = {
2508                 .omap2 = {
2509                         .prcm_reg_id = 1,
2510                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2511                         .module_offs = CORE_MOD,
2512                         .idlest_reg_id = 1,
2513                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2514                 },
2515         },
2516         .slaves         = omap3xxx_mcbsp1_slaves,
2517         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2518         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2519 };
2520
2521 /* mcbsp2 */
2522 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2523         { .name = "irq", .irq = 17 },
2524         { .name = "tx", .irq = 62 },
2525         { .name = "rx", .irq = 63 },
2526 };
2527
2528 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2529         { .name = "rx", .dma_req = 34 },
2530         { .name = "tx", .dma_req = 33 },
2531 };
2532
2533 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2534         {
2535                 .name           = "mpu",
2536                 .pa_start       = 0x49022000,
2537                 .pa_end         = 0x490220ff,
2538                 .flags          = ADDR_TYPE_RT
2539         },
2540         { }
2541 };
2542
2543 /* l4_per -> mcbsp2 */
2544 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2545         .master         = &omap3xxx_l4_per_hwmod,
2546         .slave          = &omap3xxx_mcbsp2_hwmod,
2547         .clk            = "mcbsp2_ick",
2548         .addr           = omap3xxx_mcbsp2_addrs,
2549
2550         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2551 };
2552
2553 /* mcbsp2 slave ports */
2554 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2555         &omap3xxx_l4_per__mcbsp2,
2556 };
2557
2558 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2559         .sidetone       = "mcbsp2_sidetone",
2560 };
2561
2562 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2563         .name           = "mcbsp2",
2564         .class          = &omap3xxx_mcbsp_hwmod_class,
2565         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2566         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2567         .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
2568         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2569         .main_clk       = "mcbsp2_fck",
2570         .prcm           = {
2571                 .omap2 = {
2572                         .prcm_reg_id = 1,
2573                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2574                         .module_offs = OMAP3430_PER_MOD,
2575                         .idlest_reg_id = 1,
2576                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2577                 },
2578         },
2579         .slaves         = omap3xxx_mcbsp2_slaves,
2580         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2581         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2582         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2583 };
2584
2585 /* mcbsp3 */
2586 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2587         { .name = "irq", .irq = 22 },
2588         { .name = "tx", .irq = 89 },
2589         { .name = "rx", .irq = 90 },
2590 };
2591
2592 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2593         { .name = "rx", .dma_req = 18 },
2594         { .name = "tx", .dma_req = 17 },
2595 };
2596
2597 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2598         {
2599                 .name           = "mpu",
2600                 .pa_start       = 0x49024000,
2601                 .pa_end         = 0x490240ff,
2602                 .flags          = ADDR_TYPE_RT
2603         },
2604         { }
2605 };
2606
2607 /* l4_per -> mcbsp3 */
2608 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2609         .master         = &omap3xxx_l4_per_hwmod,
2610         .slave          = &omap3xxx_mcbsp3_hwmod,
2611         .clk            = "mcbsp3_ick",
2612         .addr           = omap3xxx_mcbsp3_addrs,
2613         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2614 };
2615
2616 /* mcbsp3 slave ports */
2617 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2618         &omap3xxx_l4_per__mcbsp3,
2619 };
2620
2621 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2622         .sidetone       = "mcbsp3_sidetone",
2623 };
2624
2625 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2626         .name           = "mcbsp3",
2627         .class          = &omap3xxx_mcbsp_hwmod_class,
2628         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2629         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2630         .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
2631         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2632         .main_clk       = "mcbsp3_fck",
2633         .prcm           = {
2634                 .omap2 = {
2635                         .prcm_reg_id = 1,
2636                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2637                         .module_offs = OMAP3430_PER_MOD,
2638                         .idlest_reg_id = 1,
2639                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2640                 },
2641         },
2642         .slaves         = omap3xxx_mcbsp3_slaves,
2643         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2644         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2645         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2646 };
2647
2648 /* mcbsp4 */
2649 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2650         { .name = "irq", .irq = 23 },
2651         { .name = "tx", .irq = 54 },
2652         { .name = "rx", .irq = 55 },
2653 };
2654
2655 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2656         { .name = "rx", .dma_req = 20 },
2657         { .name = "tx", .dma_req = 19 },
2658 };
2659
2660 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2661         {
2662                 .name           = "mpu",
2663                 .pa_start       = 0x49026000,
2664                 .pa_end         = 0x490260ff,
2665                 .flags          = ADDR_TYPE_RT
2666         },
2667         { }
2668 };
2669
2670 /* l4_per -> mcbsp4 */
2671 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2672         .master         = &omap3xxx_l4_per_hwmod,
2673         .slave          = &omap3xxx_mcbsp4_hwmod,
2674         .clk            = "mcbsp4_ick",
2675         .addr           = omap3xxx_mcbsp4_addrs,
2676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2677 };
2678
2679 /* mcbsp4 slave ports */
2680 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2681         &omap3xxx_l4_per__mcbsp4,
2682 };
2683
2684 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2685         .name           = "mcbsp4",
2686         .class          = &omap3xxx_mcbsp_hwmod_class,
2687         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2688         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2689         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2690         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2691         .main_clk       = "mcbsp4_fck",
2692         .prcm           = {
2693                 .omap2 = {
2694                         .prcm_reg_id = 1,
2695                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2696                         .module_offs = OMAP3430_PER_MOD,
2697                         .idlest_reg_id = 1,
2698                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2699                 },
2700         },
2701         .slaves         = omap3xxx_mcbsp4_slaves,
2702         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2703         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2704 };
2705
2706 /* mcbsp5 */
2707 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2708         { .name = "irq", .irq = 27 },
2709         { .name = "tx", .irq = 81 },
2710         { .name = "rx", .irq = 82 },
2711 };
2712
2713 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2714         { .name = "rx", .dma_req = 22 },
2715         { .name = "tx", .dma_req = 21 },
2716 };
2717
2718 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2719         {
2720                 .name           = "mpu",
2721                 .pa_start       = 0x48096000,
2722                 .pa_end         = 0x480960ff,
2723                 .flags          = ADDR_TYPE_RT
2724         },
2725         { }
2726 };
2727
2728 /* l4_core -> mcbsp5 */
2729 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2730         .master         = &omap3xxx_l4_core_hwmod,
2731         .slave          = &omap3xxx_mcbsp5_hwmod,
2732         .clk            = "mcbsp5_ick",
2733         .addr           = omap3xxx_mcbsp5_addrs,
2734         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2735 };
2736
2737 /* mcbsp5 slave ports */
2738 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2739         &omap3xxx_l4_core__mcbsp5,
2740 };
2741
2742 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2743         .name           = "mcbsp5",
2744         .class          = &omap3xxx_mcbsp_hwmod_class,
2745         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2746         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2747         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2748         .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2749         .main_clk       = "mcbsp5_fck",
2750         .prcm           = {
2751                 .omap2 = {
2752                         .prcm_reg_id = 1,
2753                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2754                         .module_offs = CORE_MOD,
2755                         .idlest_reg_id = 1,
2756                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2757                 },
2758         },
2759         .slaves         = omap3xxx_mcbsp5_slaves,
2760         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2761         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2762 };
2763 /* 'mcbsp sidetone' class */
2764
2765 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2766         .sysc_offs      = 0x0010,
2767         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2768         .sysc_fields    = &omap_hwmod_sysc_type1,
2769 };
2770
2771 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2772         .name = "mcbsp_sidetone",
2773         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2774 };
2775
2776 /* mcbsp2_sidetone */
2777 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2778         { .name = "irq", .irq = 4 },
2779 };
2780
2781 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2782         {
2783                 .name           = "sidetone",
2784                 .pa_start       = 0x49028000,
2785                 .pa_end         = 0x490280ff,
2786                 .flags          = ADDR_TYPE_RT
2787         },
2788         { }
2789 };
2790
2791 /* l4_per -> mcbsp2_sidetone */
2792 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2793         .master         = &omap3xxx_l4_per_hwmod,
2794         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2795         .clk            = "mcbsp2_ick",
2796         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2797         .user           = OCP_USER_MPU,
2798 };
2799
2800 /* mcbsp2_sidetone slave ports */
2801 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2802         &omap3xxx_l4_per__mcbsp2_sidetone,
2803 };
2804
2805 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2806         .name           = "mcbsp2_sidetone",
2807         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2808         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2809         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2810         .main_clk       = "mcbsp2_fck",
2811         .prcm           = {
2812                 .omap2 = {
2813                         .prcm_reg_id = 1,
2814                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2815                         .module_offs = OMAP3430_PER_MOD,
2816                         .idlest_reg_id = 1,
2817                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2818                 },
2819         },
2820         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2821         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2822         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2823 };
2824
2825 /* mcbsp3_sidetone */
2826 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2827         { .name = "irq", .irq = 5 },
2828 };
2829
2830 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2831         {
2832                 .name           = "sidetone",
2833                 .pa_start       = 0x4902A000,
2834                 .pa_end         = 0x4902A0ff,
2835                 .flags          = ADDR_TYPE_RT
2836         },
2837         { }
2838 };
2839
2840 /* l4_per -> mcbsp3_sidetone */
2841 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2842         .master         = &omap3xxx_l4_per_hwmod,
2843         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2844         .clk            = "mcbsp3_ick",
2845         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2846         .user           = OCP_USER_MPU,
2847 };
2848
2849 /* mcbsp3_sidetone slave ports */
2850 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2851         &omap3xxx_l4_per__mcbsp3_sidetone,
2852 };
2853
2854 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2855         .name           = "mcbsp3_sidetone",
2856         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2857         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2858         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2859         .main_clk       = "mcbsp3_fck",
2860         .prcm           = {
2861                 .omap2 = {
2862                         .prcm_reg_id = 1,
2863                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2864                         .module_offs = OMAP3430_PER_MOD,
2865                         .idlest_reg_id = 1,
2866                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2867                 },
2868         },
2869         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2870         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2871         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2872 };
2873
2874
2875 /* SR common */
2876 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2877         .clkact_shift   = 20,
2878 };
2879
2880 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2881         .sysc_offs      = 0x24,
2882         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2883         .clockact       = CLOCKACT_TEST_ICLK,
2884         .sysc_fields    = &omap34xx_sr_sysc_fields,
2885 };
2886
2887 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2888         .name = "smartreflex",
2889         .sysc = &omap34xx_sr_sysc,
2890         .rev  = 1,
2891 };
2892
2893 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2894         .sidle_shift    = 24,
2895         .enwkup_shift   = 26
2896 };
2897
2898 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2899         .sysc_offs      = 0x38,
2900         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2901         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2902                         SYSC_NO_CACHE),
2903         .sysc_fields    = &omap36xx_sr_sysc_fields,
2904 };
2905
2906 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2907         .name = "smartreflex",
2908         .sysc = &omap36xx_sr_sysc,
2909         .rev  = 2,
2910 };
2911
2912 /* SR1 */
2913 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2914         &omap3_l4_core__sr1,
2915 };
2916
2917 static struct omap_hwmod omap34xx_sr1_hwmod = {
2918         .name           = "sr1_hwmod",
2919         .class          = &omap34xx_smartreflex_hwmod_class,
2920         .main_clk       = "sr1_fck",
2921         .vdd_name       = "mpu",
2922         .prcm           = {
2923                 .omap2 = {
2924                         .prcm_reg_id = 1,
2925                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2926                         .module_offs = WKUP_MOD,
2927                         .idlest_reg_id = 1,
2928                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2929                 },
2930         },
2931         .slaves         = omap3_sr1_slaves,
2932         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2933         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2934                                         CHIP_IS_OMAP3430ES3_0 |
2935                                         CHIP_IS_OMAP3430ES3_1),
2936         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2937 };
2938
2939 static struct omap_hwmod omap36xx_sr1_hwmod = {
2940         .name           = "sr1_hwmod",
2941         .class          = &omap36xx_smartreflex_hwmod_class,
2942         .main_clk       = "sr1_fck",
2943         .vdd_name       = "mpu",
2944         .prcm           = {
2945                 .omap2 = {
2946                         .prcm_reg_id = 1,
2947                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2948                         .module_offs = WKUP_MOD,
2949                         .idlest_reg_id = 1,
2950                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2951                 },
2952         },
2953         .slaves         = omap3_sr1_slaves,
2954         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2955         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2956 };
2957
2958 /* SR2 */
2959 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2960         &omap3_l4_core__sr2,
2961 };
2962
2963 static struct omap_hwmod omap34xx_sr2_hwmod = {
2964         .name           = "sr2_hwmod",
2965         .class          = &omap34xx_smartreflex_hwmod_class,
2966         .main_clk       = "sr2_fck",
2967         .vdd_name       = "core",
2968         .prcm           = {
2969                 .omap2 = {
2970                         .prcm_reg_id = 1,
2971                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2972                         .module_offs = WKUP_MOD,
2973                         .idlest_reg_id = 1,
2974                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2975                 },
2976         },
2977         .slaves         = omap3_sr2_slaves,
2978         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2979         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2980                                         CHIP_IS_OMAP3430ES3_0 |
2981                                         CHIP_IS_OMAP3430ES3_1),
2982         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2983 };
2984
2985 static struct omap_hwmod omap36xx_sr2_hwmod = {
2986         .name           = "sr2_hwmod",
2987         .class          = &omap36xx_smartreflex_hwmod_class,
2988         .main_clk       = "sr2_fck",
2989         .vdd_name       = "core",
2990         .prcm           = {
2991                 .omap2 = {
2992                         .prcm_reg_id = 1,
2993                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2994                         .module_offs = WKUP_MOD,
2995                         .idlest_reg_id = 1,
2996                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2997                 },
2998         },
2999         .slaves         = omap3_sr2_slaves,
3000         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
3001         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
3002 };
3003
3004 /*
3005  * 'mailbox' class
3006  * mailbox module allowing communication between the on-chip processors
3007  * using a queued mailbox-interrupt mechanism.
3008  */
3009
3010 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3011         .rev_offs       = 0x000,
3012         .sysc_offs      = 0x010,
3013         .syss_offs      = 0x014,
3014         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3015                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3016         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3017         .sysc_fields    = &omap_hwmod_sysc_type1,
3018 };
3019
3020 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3021         .name = "mailbox",
3022         .sysc = &omap3xxx_mailbox_sysc,
3023 };
3024
3025 static struct omap_hwmod omap3xxx_mailbox_hwmod;
3026 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3027         { .irq = 26 },
3028 };
3029
3030 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3031         {
3032                 .pa_start       = 0x48094000,
3033                 .pa_end         = 0x480941ff,
3034                 .flags          = ADDR_TYPE_RT,
3035         },
3036         { }
3037 };
3038
3039 /* l4_core -> mailbox */
3040 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3041         .master         = &omap3xxx_l4_core_hwmod,
3042         .slave          = &omap3xxx_mailbox_hwmod,
3043         .addr           = omap3xxx_mailbox_addrs,
3044         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3045 };
3046
3047 /* mailbox slave ports */
3048 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3049         &omap3xxx_l4_core__mailbox,
3050 };
3051
3052 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3053         .name           = "mailbox",
3054         .class          = &omap3xxx_mailbox_hwmod_class,
3055         .mpu_irqs       = omap3xxx_mailbox_irqs,
3056         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3057         .main_clk       = "mailboxes_ick",
3058         .prcm           = {
3059                 .omap2 = {
3060                         .prcm_reg_id = 1,
3061                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3062                         .module_offs = CORE_MOD,
3063                         .idlest_reg_id = 1,
3064                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3065                 },
3066         },
3067         .slaves         = omap3xxx_mailbox_slaves,
3068         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3069         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3070 };
3071
3072 /* l4 core -> mcspi1 interface */
3073 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
3074         {
3075                 .pa_start       = 0x48098000,
3076                 .pa_end         = 0x480980ff,
3077                 .flags          = ADDR_TYPE_RT,
3078         },
3079         { }
3080 };
3081
3082 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3083         .master         = &omap3xxx_l4_core_hwmod,
3084         .slave          = &omap34xx_mcspi1,
3085         .clk            = "mcspi1_ick",
3086         .addr           = omap34xx_mcspi1_addr_space,
3087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3088 };
3089
3090 /* l4 core -> mcspi2 interface */
3091 static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
3092         {
3093                 .pa_start       = 0x4809a000,
3094                 .pa_end         = 0x4809a0ff,
3095                 .flags          = ADDR_TYPE_RT,
3096         },
3097         { }
3098 };
3099
3100 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3101         .master         = &omap3xxx_l4_core_hwmod,
3102         .slave          = &omap34xx_mcspi2,
3103         .clk            = "mcspi2_ick",
3104         .addr           = omap34xx_mcspi2_addr_space,
3105         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3106 };
3107
3108 /* l4 core -> mcspi3 interface */
3109 static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
3110         {
3111                 .pa_start       = 0x480b8000,
3112                 .pa_end         = 0x480b80ff,
3113                 .flags          = ADDR_TYPE_RT,
3114         },
3115         { }
3116 };
3117
3118 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3119         .master         = &omap3xxx_l4_core_hwmod,
3120         .slave          = &omap34xx_mcspi3,
3121         .clk            = "mcspi3_ick",
3122         .addr           = omap34xx_mcspi3_addr_space,
3123         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3124 };
3125
3126 /* l4 core -> mcspi4 interface */
3127 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3128         {
3129                 .pa_start       = 0x480ba000,
3130                 .pa_end         = 0x480ba0ff,
3131                 .flags          = ADDR_TYPE_RT,
3132         },
3133         { }
3134 };
3135
3136 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3137         .master         = &omap3xxx_l4_core_hwmod,
3138         .slave          = &omap34xx_mcspi4,
3139         .clk            = "mcspi4_ick",
3140         .addr           = omap34xx_mcspi4_addr_space,
3141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3142 };
3143
3144 /*
3145  * 'mcspi' class
3146  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3147  * bus
3148  */
3149
3150 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
3151         .rev_offs       = 0x0000,
3152         .sysc_offs      = 0x0010,
3153         .syss_offs      = 0x0014,
3154         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3155                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3156                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3157         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3158         .sysc_fields    = &omap_hwmod_sysc_type1,
3159 };
3160
3161 static struct omap_hwmod_class omap34xx_mcspi_class = {
3162         .name = "mcspi",
3163         .sysc = &omap34xx_mcspi_sysc,
3164         .rev = OMAP3_MCSPI_REV,
3165 };
3166
3167 /* mcspi1 */
3168 static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
3169         { .name = "irq", .irq = 65 },
3170 };
3171
3172 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
3173         { .name = "tx0", .dma_req = 35 },
3174         { .name = "rx0", .dma_req = 36 },
3175         { .name = "tx1", .dma_req = 37 },
3176         { .name = "rx1", .dma_req = 38 },
3177         { .name = "tx2", .dma_req = 39 },
3178         { .name = "rx2", .dma_req = 40 },
3179         { .name = "tx3", .dma_req = 41 },
3180         { .name = "rx3", .dma_req = 42 },
3181 };
3182
3183 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
3184         &omap34xx_l4_core__mcspi1,
3185 };
3186
3187 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
3188         .num_chipselect = 4,
3189 };
3190
3191 static struct omap_hwmod omap34xx_mcspi1 = {
3192         .name           = "mcspi1",
3193         .mpu_irqs       = omap34xx_mcspi1_mpu_irqs,
3194         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
3195         .sdma_reqs      = omap34xx_mcspi1_sdma_reqs,
3196         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
3197         .main_clk       = "mcspi1_fck",
3198         .prcm           = {
3199                 .omap2 = {
3200                         .module_offs = CORE_MOD,
3201                         .prcm_reg_id = 1,
3202                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
3203                         .idlest_reg_id = 1,
3204                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
3205                 },
3206         },
3207         .slaves         = omap34xx_mcspi1_slaves,
3208         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
3209         .class          = &omap34xx_mcspi_class,
3210         .dev_attr       = &omap_mcspi1_dev_attr,
3211         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3212 };
3213
3214 /* mcspi2 */
3215 static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
3216         { .name = "irq", .irq = 66 },
3217 };
3218
3219 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
3220         { .name = "tx0", .dma_req = 43 },
3221         { .name = "rx0", .dma_req = 44 },
3222         { .name = "tx1", .dma_req = 45 },
3223         { .name = "rx1", .dma_req = 46 },
3224 };
3225
3226 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
3227         &omap34xx_l4_core__mcspi2,
3228 };
3229
3230 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
3231         .num_chipselect = 2,
3232 };
3233
3234 static struct omap_hwmod omap34xx_mcspi2 = {
3235         .name           = "mcspi2",
3236         .mpu_irqs       = omap34xx_mcspi2_mpu_irqs,
3237         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
3238         .sdma_reqs      = omap34xx_mcspi2_sdma_reqs,
3239         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3240         .main_clk       = "mcspi2_fck",
3241         .prcm           = {
3242                 .omap2 = {
3243                         .module_offs = CORE_MOD,
3244                         .prcm_reg_id = 1,
3245                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3246                         .idlest_reg_id = 1,
3247                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3248                 },
3249         },
3250         .slaves         = omap34xx_mcspi2_slaves,
3251         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3252         .class          = &omap34xx_mcspi_class,
3253         .dev_attr       = &omap_mcspi2_dev_attr,
3254         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3255 };
3256
3257 /* mcspi3 */
3258 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3259         { .name = "irq", .irq = 91 }, /* 91 */
3260 };
3261
3262 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3263         { .name = "tx0", .dma_req = 15 },
3264         { .name = "rx0", .dma_req = 16 },
3265         { .name = "tx1", .dma_req = 23 },
3266         { .name = "rx1", .dma_req = 24 },
3267 };
3268
3269 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3270         &omap34xx_l4_core__mcspi3,
3271 };
3272
3273 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3274         .num_chipselect = 2,
3275 };
3276
3277 static struct omap_hwmod omap34xx_mcspi3 = {
3278         .name           = "mcspi3",
3279         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
3280         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
3281         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
3282         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3283         .main_clk       = "mcspi3_fck",
3284         .prcm           = {
3285                 .omap2 = {
3286                         .module_offs = CORE_MOD,
3287                         .prcm_reg_id = 1,
3288                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3289                         .idlest_reg_id = 1,
3290                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3291                 },
3292         },
3293         .slaves         = omap34xx_mcspi3_slaves,
3294         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3295         .class          = &omap34xx_mcspi_class,
3296         .dev_attr       = &omap_mcspi3_dev_attr,
3297         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3298 };
3299
3300 /* SPI4 */
3301 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3302         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3303 };
3304
3305 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3306         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3307         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3308 };
3309
3310 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3311         &omap34xx_l4_core__mcspi4,
3312 };
3313
3314 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3315         .num_chipselect = 1,
3316 };
3317
3318 static struct omap_hwmod omap34xx_mcspi4 = {
3319         .name           = "mcspi4",
3320         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
3321         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
3322         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
3323         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3324         .main_clk       = "mcspi4_fck",
3325         .prcm           = {
3326                 .omap2 = {
3327                         .module_offs = CORE_MOD,
3328                         .prcm_reg_id = 1,
3329                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3330                         .idlest_reg_id = 1,
3331                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3332                 },
3333         },
3334         .slaves         = omap34xx_mcspi4_slaves,
3335         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3336         .class          = &omap34xx_mcspi_class,
3337         .dev_attr       = &omap_mcspi4_dev_attr,
3338         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3339 };
3340
3341 /*
3342  * usbhsotg
3343  */
3344 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3345         .rev_offs       = 0x0400,
3346         .sysc_offs      = 0x0404,
3347         .syss_offs      = 0x0408,
3348         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3349                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3350                           SYSC_HAS_AUTOIDLE),
3351         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3352                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3353         .sysc_fields    = &omap_hwmod_sysc_type1,
3354 };
3355
3356 static struct omap_hwmod_class usbotg_class = {
3357         .name = "usbotg",
3358         .sysc = &omap3xxx_usbhsotg_sysc,
3359 };
3360 /* usb_otg_hs */
3361 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3362
3363         { .name = "mc", .irq = 92 },
3364         { .name = "dma", .irq = 93 },
3365 };
3366
3367 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3368         .name           = "usb_otg_hs",
3369         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
3370         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
3371         .main_clk       = "hsotgusb_ick",
3372         .prcm           = {
3373                 .omap2 = {
3374                         .prcm_reg_id = 1,
3375                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3376                         .module_offs = CORE_MOD,
3377                         .idlest_reg_id = 1,
3378                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3379                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3380                 },
3381         },
3382         .masters        = omap3xxx_usbhsotg_masters,
3383         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3384         .slaves         = omap3xxx_usbhsotg_slaves,
3385         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3386         .class          = &usbotg_class,
3387
3388         /*
3389          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3390          * broken when autoidle is enabled
3391          * workaround is to disable the autoidle bit at module level.
3392          */
3393         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3394                                 | HWMOD_SWSUP_MSTANDBY,
3395         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3396 };
3397
3398 /* usb_otg_hs */
3399 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3400
3401         { .name = "mc", .irq = 71 },
3402 };
3403
3404 static struct omap_hwmod_class am35xx_usbotg_class = {
3405         .name = "am35xx_usbotg",
3406         .sysc = NULL,
3407 };
3408
3409 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3410         .name           = "am35x_otg_hs",
3411         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3412         .mpu_irqs_cnt   = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
3413         .main_clk       = NULL,
3414         .prcm = {
3415                 .omap2 = {
3416                 },
3417         },
3418         .masters        = am35xx_usbhsotg_masters,
3419         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3420         .slaves         = am35xx_usbhsotg_slaves,
3421         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3422         .class          = &am35xx_usbotg_class,
3423         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3424 };
3425
3426 /* MMC/SD/SDIO common */
3427
3428 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3429         .rev_offs       = 0x1fc,
3430         .sysc_offs      = 0x10,
3431         .syss_offs      = 0x14,
3432         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3433                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3434                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3435         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3436         .sysc_fields    = &omap_hwmod_sysc_type1,
3437 };
3438
3439 static struct omap_hwmod_class omap34xx_mmc_class = {
3440         .name = "mmc",
3441         .sysc = &omap34xx_mmc_sysc,
3442 };
3443
3444 /* MMC/SD/SDIO1 */
3445
3446 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3447         { .irq = 83, },
3448 };
3449
3450 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3451         { .name = "tx", .dma_req = 61, },
3452         { .name = "rx", .dma_req = 62, },
3453 };
3454
3455 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3456         { .role = "dbck", .clk = "omap_32k_fck", },
3457 };
3458
3459 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3460         &omap3xxx_l4_core__mmc1,
3461 };
3462
3463 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3464         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3465 };
3466
3467 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3468         .name           = "mmc1",
3469         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3470         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3471         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3472         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3473         .opt_clks       = omap34xx_mmc1_opt_clks,
3474         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3475         .main_clk       = "mmchs1_fck",
3476         .prcm           = {
3477                 .omap2 = {
3478                         .module_offs = CORE_MOD,
3479                         .prcm_reg_id = 1,
3480                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3481                         .idlest_reg_id = 1,
3482                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3483                 },
3484         },
3485         .dev_attr       = &mmc1_dev_attr,
3486         .slaves         = omap3xxx_mmc1_slaves,
3487         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3488         .class          = &omap34xx_mmc_class,
3489         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3490 };
3491
3492 /* MMC/SD/SDIO2 */
3493
3494 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3495         { .irq = INT_24XX_MMC2_IRQ, },
3496 };
3497
3498 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3499         { .name = "tx", .dma_req = 47, },
3500         { .name = "rx", .dma_req = 48, },
3501 };
3502
3503 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3504         { .role = "dbck", .clk = "omap_32k_fck", },
3505 };
3506
3507 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3508         &omap3xxx_l4_core__mmc2,
3509 };
3510
3511 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3512         .name           = "mmc2",
3513         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3514         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3515         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3516         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3517         .opt_clks       = omap34xx_mmc2_opt_clks,
3518         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3519         .main_clk       = "mmchs2_fck",
3520         .prcm           = {
3521                 .omap2 = {
3522                         .module_offs = CORE_MOD,
3523                         .prcm_reg_id = 1,
3524                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3525                         .idlest_reg_id = 1,
3526                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3527                 },
3528         },
3529         .slaves         = omap3xxx_mmc2_slaves,
3530         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3531         .class          = &omap34xx_mmc_class,
3532         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3533 };
3534
3535 /* MMC/SD/SDIO3 */
3536
3537 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3538         { .irq = 94, },
3539 };
3540
3541 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3542         { .name = "tx", .dma_req = 77, },
3543         { .name = "rx", .dma_req = 78, },
3544 };
3545
3546 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3547         { .role = "dbck", .clk = "omap_32k_fck", },
3548 };
3549
3550 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3551         &omap3xxx_l4_core__mmc3,
3552 };
3553
3554 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3555         .name           = "mmc3",
3556         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3557         .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3558         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3559         .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3560         .opt_clks       = omap34xx_mmc3_opt_clks,
3561         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3562         .main_clk       = "mmchs3_fck",
3563         .prcm           = {
3564                 .omap2 = {
3565                         .prcm_reg_id = 1,
3566                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3567                         .idlest_reg_id = 1,
3568                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3569                 },
3570         },
3571         .slaves         = omap3xxx_mmc3_slaves,
3572         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3573         .class          = &omap34xx_mmc_class,
3574         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3575 };
3576
3577 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3578         &omap3xxx_l3_main_hwmod,
3579         &omap3xxx_l4_core_hwmod,
3580         &omap3xxx_l4_per_hwmod,
3581         &omap3xxx_l4_wkup_hwmod,
3582         &omap3xxx_mmc1_hwmod,
3583         &omap3xxx_mmc2_hwmod,
3584         &omap3xxx_mmc3_hwmod,
3585         &omap3xxx_mpu_hwmod,
3586         &omap3xxx_iva_hwmod,
3587
3588         &omap3xxx_timer1_hwmod,
3589         &omap3xxx_timer2_hwmod,
3590         &omap3xxx_timer3_hwmod,
3591         &omap3xxx_timer4_hwmod,
3592         &omap3xxx_timer5_hwmod,
3593         &omap3xxx_timer6_hwmod,
3594         &omap3xxx_timer7_hwmod,
3595         &omap3xxx_timer8_hwmod,
3596         &omap3xxx_timer9_hwmod,
3597         &omap3xxx_timer10_hwmod,
3598         &omap3xxx_timer11_hwmod,
3599         &omap3xxx_timer12_hwmod,
3600
3601         &omap3xxx_wd_timer2_hwmod,
3602         &omap3xxx_uart1_hwmod,
3603         &omap3xxx_uart2_hwmod,
3604         &omap3xxx_uart3_hwmod,
3605         &omap3xxx_uart4_hwmod,
3606         /* dss class */
3607         &omap3430es1_dss_core_hwmod,
3608         &omap3xxx_dss_core_hwmod,
3609         &omap3xxx_dss_dispc_hwmod,
3610         &omap3xxx_dss_dsi1_hwmod,
3611         &omap3xxx_dss_rfbi_hwmod,
3612         &omap3xxx_dss_venc_hwmod,
3613
3614         /* i2c class */
3615         &omap3xxx_i2c1_hwmod,
3616         &omap3xxx_i2c2_hwmod,
3617         &omap3xxx_i2c3_hwmod,
3618         &omap34xx_sr1_hwmod,
3619         &omap34xx_sr2_hwmod,
3620         &omap36xx_sr1_hwmod,
3621         &omap36xx_sr2_hwmod,
3622
3623
3624         /* gpio class */
3625         &omap3xxx_gpio1_hwmod,
3626         &omap3xxx_gpio2_hwmod,
3627         &omap3xxx_gpio3_hwmod,
3628         &omap3xxx_gpio4_hwmod,
3629         &omap3xxx_gpio5_hwmod,
3630         &omap3xxx_gpio6_hwmod,
3631
3632         /* dma_system class*/
3633         &omap3xxx_dma_system_hwmod,
3634
3635         /* mcbsp class */
3636         &omap3xxx_mcbsp1_hwmod,
3637         &omap3xxx_mcbsp2_hwmod,
3638         &omap3xxx_mcbsp3_hwmod,
3639         &omap3xxx_mcbsp4_hwmod,
3640         &omap3xxx_mcbsp5_hwmod,
3641         &omap3xxx_mcbsp2_sidetone_hwmod,
3642         &omap3xxx_mcbsp3_sidetone_hwmod,
3643
3644         /* mailbox class */
3645         &omap3xxx_mailbox_hwmod,
3646
3647         /* mcspi class */
3648         &omap34xx_mcspi1,
3649         &omap34xx_mcspi2,
3650         &omap34xx_mcspi3,
3651         &omap34xx_mcspi4,
3652
3653         /* usbotg class */
3654         &omap3xxx_usbhsotg_hwmod,
3655
3656         /* usbotg for am35x */
3657         &am35xx_usbhsotg_hwmod,
3658
3659         NULL,
3660 };
3661
3662 int __init omap3xxx_hwmod_init(void)
3663 {
3664         return omap_hwmod_register(omap3xxx_hwmods);
3665 }