2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod_common_data.h"
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
35 #include <mach/am35xx.h>
38 * OMAP3xxx hardware module integration data
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
90 .master = &omap3xxx_l3_main_hwmod,
91 .slave = &omap3xxx_l4_core_hwmod,
92 .user = OCP_USER_MPU | OCP_USER_SDMA,
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
97 .master = &omap3xxx_l3_main_hwmod,
98 .slave = &omap3xxx_l4_per_hwmod,
99 .user = OCP_USER_MPU | OCP_USER_SDMA,
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ },
109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
118 /* MPU -> L3 interface */
119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
120 .master = &omap3xxx_mpu_hwmod,
121 .slave = &omap3xxx_l3_main_hwmod,
122 .addr = omap3xxx_l3_main_addrs,
123 .user = OCP_USER_MPU,
126 /* Slave interfaces on the L3 interconnect */
127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
128 &omap3xxx_mpu__l3_main,
132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
133 .master = &omap3xxx_dss_core_hwmod,
134 .slave = &omap3xxx_l3_main_hwmod,
137 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
138 .flags = OMAP_FIREWALL_L3,
141 .user = OCP_USER_MPU | OCP_USER_SDMA,
144 /* Master interfaces on the L3 interconnect */
145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
146 &omap3xxx_l3_main__l4_core,
147 &omap3xxx_l3_main__l4_per,
151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves,
158 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
160 .flags = HWMOD_NO_IDLEST,
163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
164 static struct omap_hwmod omap3xxx_uart1_hwmod;
165 static struct omap_hwmod omap3xxx_uart2_hwmod;
166 static struct omap_hwmod omap3xxx_uart3_hwmod;
167 static struct omap_hwmod omap3xxx_uart4_hwmod;
168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
170 /* l3_core -> usbhsotg interface */
171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
172 .master = &omap3xxx_usbhsotg_hwmod,
173 .slave = &omap3xxx_l3_main_hwmod,
174 .clk = "core_l3_ick",
175 .user = OCP_USER_MPU,
178 /* l3_core -> am35xx_usbhsotg interface */
179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
180 .master = &am35xx_usbhsotg_hwmod,
181 .slave = &omap3xxx_l3_main_hwmod,
182 .clk = "core_l3_ick",
183 .user = OCP_USER_MPU,
185 /* L4_CORE -> L4_WKUP interface */
186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
187 .master = &omap3xxx_l4_core_hwmod,
188 .slave = &omap3xxx_l4_wkup_hwmod,
189 .user = OCP_USER_MPU | OCP_USER_SDMA,
192 /* L4 CORE -> MMC1 interface */
193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
194 .master = &omap3xxx_l4_core_hwmod,
195 .slave = &omap3xxx_mmc1_hwmod,
197 .addr = omap2430_mmc1_addr_space,
198 .user = OCP_USER_MPU | OCP_USER_SDMA,
199 .flags = OMAP_FIREWALL_L4
202 /* L4 CORE -> MMC2 interface */
203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
204 .master = &omap3xxx_l4_core_hwmod,
205 .slave = &omap3xxx_mmc2_hwmod,
207 .addr = omap2430_mmc2_addr_space,
208 .user = OCP_USER_MPU | OCP_USER_SDMA,
209 .flags = OMAP_FIREWALL_L4
212 /* L4 CORE -> MMC3 interface */
213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
215 .pa_start = 0x480ad000,
216 .pa_end = 0x480ad1ff,
217 .flags = ADDR_TYPE_RT,
222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
223 .master = &omap3xxx_l4_core_hwmod,
224 .slave = &omap3xxx_mmc3_hwmod,
226 .addr = omap3xxx_mmc3_addr_space,
227 .user = OCP_USER_MPU | OCP_USER_SDMA,
228 .flags = OMAP_FIREWALL_L4
231 /* L4 CORE -> UART1 interface */
232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
234 .pa_start = OMAP3_UART1_BASE,
235 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
242 .master = &omap3xxx_l4_core_hwmod,
243 .slave = &omap3xxx_uart1_hwmod,
245 .addr = omap3xxx_uart1_addr_space,
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
249 /* L4 CORE -> UART2 interface */
250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
252 .pa_start = OMAP3_UART2_BASE,
253 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
260 .master = &omap3xxx_l4_core_hwmod,
261 .slave = &omap3xxx_uart2_hwmod,
263 .addr = omap3xxx_uart2_addr_space,
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
267 /* L4 PER -> UART3 interface */
268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
270 .pa_start = OMAP3_UART3_BASE,
271 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
278 .master = &omap3xxx_l4_per_hwmod,
279 .slave = &omap3xxx_uart3_hwmod,
281 .addr = omap3xxx_uart3_addr_space,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
285 /* L4 PER -> UART4 interface */
286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
288 .pa_start = OMAP3_UART4_BASE,
289 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
296 .master = &omap3xxx_l4_per_hwmod,
297 .slave = &omap3xxx_uart4_hwmod,
299 .addr = omap3xxx_uart4_addr_space,
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
303 /* L4 CORE -> I2C1 interface */
304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
305 .master = &omap3xxx_l4_core_hwmod,
306 .slave = &omap3xxx_i2c1_hwmod,
308 .addr = omap2_i2c1_addr_space,
311 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
313 .flags = OMAP_FIREWALL_L4,
316 .user = OCP_USER_MPU | OCP_USER_SDMA,
319 /* L4 CORE -> I2C2 interface */
320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
321 .master = &omap3xxx_l4_core_hwmod,
322 .slave = &omap3xxx_i2c2_hwmod,
324 .addr = omap2_i2c2_addr_space,
327 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
329 .flags = OMAP_FIREWALL_L4,
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
335 /* L4 CORE -> I2C3 interface */
336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
338 .pa_start = 0x48060000,
339 .pa_end = 0x48060000 + SZ_128 - 1,
340 .flags = ADDR_TYPE_RT,
345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
346 .master = &omap3xxx_l4_core_hwmod,
347 .slave = &omap3xxx_i2c3_hwmod,
349 .addr = omap3xxx_i2c3_addr_space,
352 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
354 .flags = OMAP_FIREWALL_L4,
357 .user = OCP_USER_MPU | OCP_USER_SDMA,
360 /* L4 CORE -> SR1 interface */
361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
363 .pa_start = OMAP34XX_SR1_BASE,
364 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
365 .flags = ADDR_TYPE_RT,
370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
371 .master = &omap3xxx_l4_core_hwmod,
372 .slave = &omap34xx_sr1_hwmod,
374 .addr = omap3_sr1_addr_space,
375 .user = OCP_USER_MPU,
378 /* L4 CORE -> SR1 interface */
379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
381 .pa_start = OMAP34XX_SR2_BASE,
382 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
383 .flags = ADDR_TYPE_RT,
388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
389 .master = &omap3xxx_l4_core_hwmod,
390 .slave = &omap34xx_sr2_hwmod,
392 .addr = omap3_sr2_addr_space,
393 .user = OCP_USER_MPU,
397 * usbhsotg interface data
400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
402 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
403 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
404 .flags = ADDR_TYPE_RT
409 /* l4_core -> usbhsotg */
410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
411 .master = &omap3xxx_l4_core_hwmod,
412 .slave = &omap3xxx_usbhsotg_hwmod,
414 .addr = omap3xxx_usbhsotg_addrs,
415 .user = OCP_USER_MPU,
418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
419 &omap3xxx_usbhsotg__l3,
422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
423 &omap3xxx_l4_core__usbhsotg,
426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
428 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
429 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
430 .flags = ADDR_TYPE_RT
435 /* l4_core -> usbhsotg */
436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
437 .master = &omap3xxx_l4_core_hwmod,
438 .slave = &am35xx_usbhsotg_hwmod,
440 .addr = am35xx_usbhsotg_addrs,
441 .user = OCP_USER_MPU,
444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
445 &am35xx_usbhsotg__l3,
448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
449 &am35xx_l4_core__usbhsotg,
451 /* Slave interfaces on the L4_CORE interconnect */
452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
453 &omap3xxx_l3_main__l4_core,
457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
459 .class = &l4_hwmod_class,
460 .slaves = omap3xxx_l4_core_slaves,
461 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
462 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
463 .flags = HWMOD_NO_IDLEST,
466 /* Slave interfaces on the L4_PER interconnect */
467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
468 &omap3xxx_l3_main__l4_per,
472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
474 .class = &l4_hwmod_class,
475 .slaves = omap3xxx_l4_per_slaves,
476 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
477 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
478 .flags = HWMOD_NO_IDLEST,
481 /* Slave interfaces on the L4_WKUP interconnect */
482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
483 &omap3xxx_l4_core__l4_wkup,
487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
489 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_wkup_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
493 .flags = HWMOD_NO_IDLEST,
496 /* Master interfaces on the MPU device */
497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
498 &omap3xxx_mpu__l3_main,
502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
504 .class = &mpu_hwmod_class,
505 .main_clk = "arm_fck",
506 .masters = omap3xxx_mpu_masters,
507 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
512 * IVA2_2 interface data
515 /* IVA2 <- L3 interface */
516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
517 .master = &omap3xxx_l3_main_hwmod,
518 .slave = &omap3xxx_iva_hwmod,
520 .user = OCP_USER_MPU | OCP_USER_SDMA,
523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
531 static struct omap_hwmod omap3xxx_iva_hwmod = {
533 .class = &iva_hwmod_class,
534 .masters = omap3xxx_iva_masters,
535 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
536 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
544 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
545 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
546 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
548 .sysc_fields = &omap_hwmod_sysc_type1,
551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
553 .sysc = &omap3xxx_timer_1ms_sysc,
554 .rev = OMAP_TIMER_IP_VERSION_1,
557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
561 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
562 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
564 .sysc_fields = &omap_hwmod_sysc_type1,
567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
569 .sysc = &omap3xxx_timer_sysc,
570 .rev = OMAP_TIMER_IP_VERSION_1,
574 static struct omap_hwmod omap3xxx_timer1_hwmod;
576 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
578 .pa_start = 0x48318000,
579 .pa_end = 0x48318000 + SZ_1K - 1,
580 .flags = ADDR_TYPE_RT
585 /* l4_wkup -> timer1 */
586 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
587 .master = &omap3xxx_l4_wkup_hwmod,
588 .slave = &omap3xxx_timer1_hwmod,
590 .addr = omap3xxx_timer1_addrs,
591 .user = OCP_USER_MPU | OCP_USER_SDMA,
594 /* timer1 slave port */
595 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
596 &omap3xxx_l4_wkup__timer1,
600 static struct omap_hwmod omap3xxx_timer1_hwmod = {
602 .mpu_irqs = omap2_timer1_mpu_irqs,
603 .main_clk = "gpt1_fck",
607 .module_bit = OMAP3430_EN_GPT1_SHIFT,
608 .module_offs = WKUP_MOD,
610 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
613 .slaves = omap3xxx_timer1_slaves,
614 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
615 .class = &omap3xxx_timer_1ms_hwmod_class,
616 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
620 static struct omap_hwmod omap3xxx_timer2_hwmod;
622 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
624 .pa_start = 0x49032000,
625 .pa_end = 0x49032000 + SZ_1K - 1,
626 .flags = ADDR_TYPE_RT
631 /* l4_per -> timer2 */
632 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
633 .master = &omap3xxx_l4_per_hwmod,
634 .slave = &omap3xxx_timer2_hwmod,
636 .addr = omap3xxx_timer2_addrs,
637 .user = OCP_USER_MPU | OCP_USER_SDMA,
640 /* timer2 slave port */
641 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
642 &omap3xxx_l4_per__timer2,
646 static struct omap_hwmod omap3xxx_timer2_hwmod = {
648 .mpu_irqs = omap2_timer2_mpu_irqs,
649 .main_clk = "gpt2_fck",
653 .module_bit = OMAP3430_EN_GPT2_SHIFT,
654 .module_offs = OMAP3430_PER_MOD,
656 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
659 .slaves = omap3xxx_timer2_slaves,
660 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
661 .class = &omap3xxx_timer_1ms_hwmod_class,
662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
666 static struct omap_hwmod omap3xxx_timer3_hwmod;
668 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
670 .pa_start = 0x49034000,
671 .pa_end = 0x49034000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
677 /* l4_per -> timer3 */
678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
679 .master = &omap3xxx_l4_per_hwmod,
680 .slave = &omap3xxx_timer3_hwmod,
682 .addr = omap3xxx_timer3_addrs,
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
686 /* timer3 slave port */
687 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
688 &omap3xxx_l4_per__timer3,
692 static struct omap_hwmod omap3xxx_timer3_hwmod = {
694 .mpu_irqs = omap2_timer3_mpu_irqs,
695 .main_clk = "gpt3_fck",
699 .module_bit = OMAP3430_EN_GPT3_SHIFT,
700 .module_offs = OMAP3430_PER_MOD,
702 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
705 .slaves = omap3xxx_timer3_slaves,
706 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
707 .class = &omap3xxx_timer_hwmod_class,
708 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
712 static struct omap_hwmod omap3xxx_timer4_hwmod;
714 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
716 .pa_start = 0x49036000,
717 .pa_end = 0x49036000 + SZ_1K - 1,
718 .flags = ADDR_TYPE_RT
723 /* l4_per -> timer4 */
724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
725 .master = &omap3xxx_l4_per_hwmod,
726 .slave = &omap3xxx_timer4_hwmod,
728 .addr = omap3xxx_timer4_addrs,
729 .user = OCP_USER_MPU | OCP_USER_SDMA,
732 /* timer4 slave port */
733 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
734 &omap3xxx_l4_per__timer4,
738 static struct omap_hwmod omap3xxx_timer4_hwmod = {
740 .mpu_irqs = omap2_timer4_mpu_irqs,
741 .main_clk = "gpt4_fck",
745 .module_bit = OMAP3430_EN_GPT4_SHIFT,
746 .module_offs = OMAP3430_PER_MOD,
748 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
751 .slaves = omap3xxx_timer4_slaves,
752 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
753 .class = &omap3xxx_timer_hwmod_class,
754 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
758 static struct omap_hwmod omap3xxx_timer5_hwmod;
760 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
762 .pa_start = 0x49038000,
763 .pa_end = 0x49038000 + SZ_1K - 1,
764 .flags = ADDR_TYPE_RT
769 /* l4_per -> timer5 */
770 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
771 .master = &omap3xxx_l4_per_hwmod,
772 .slave = &omap3xxx_timer5_hwmod,
774 .addr = omap3xxx_timer5_addrs,
775 .user = OCP_USER_MPU | OCP_USER_SDMA,
778 /* timer5 slave port */
779 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
780 &omap3xxx_l4_per__timer5,
784 static struct omap_hwmod omap3xxx_timer5_hwmod = {
786 .mpu_irqs = omap2_timer5_mpu_irqs,
787 .main_clk = "gpt5_fck",
791 .module_bit = OMAP3430_EN_GPT5_SHIFT,
792 .module_offs = OMAP3430_PER_MOD,
794 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
797 .slaves = omap3xxx_timer5_slaves,
798 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
799 .class = &omap3xxx_timer_hwmod_class,
800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
804 static struct omap_hwmod omap3xxx_timer6_hwmod;
806 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
808 .pa_start = 0x4903A000,
809 .pa_end = 0x4903A000 + SZ_1K - 1,
810 .flags = ADDR_TYPE_RT
815 /* l4_per -> timer6 */
816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
817 .master = &omap3xxx_l4_per_hwmod,
818 .slave = &omap3xxx_timer6_hwmod,
820 .addr = omap3xxx_timer6_addrs,
821 .user = OCP_USER_MPU | OCP_USER_SDMA,
824 /* timer6 slave port */
825 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
826 &omap3xxx_l4_per__timer6,
830 static struct omap_hwmod omap3xxx_timer6_hwmod = {
832 .mpu_irqs = omap2_timer6_mpu_irqs,
833 .main_clk = "gpt6_fck",
837 .module_bit = OMAP3430_EN_GPT6_SHIFT,
838 .module_offs = OMAP3430_PER_MOD,
840 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
843 .slaves = omap3xxx_timer6_slaves,
844 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
845 .class = &omap3xxx_timer_hwmod_class,
846 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
850 static struct omap_hwmod omap3xxx_timer7_hwmod;
852 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
854 .pa_start = 0x4903C000,
855 .pa_end = 0x4903C000 + SZ_1K - 1,
856 .flags = ADDR_TYPE_RT
861 /* l4_per -> timer7 */
862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
863 .master = &omap3xxx_l4_per_hwmod,
864 .slave = &omap3xxx_timer7_hwmod,
866 .addr = omap3xxx_timer7_addrs,
867 .user = OCP_USER_MPU | OCP_USER_SDMA,
870 /* timer7 slave port */
871 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
872 &omap3xxx_l4_per__timer7,
876 static struct omap_hwmod omap3xxx_timer7_hwmod = {
878 .mpu_irqs = omap2_timer7_mpu_irqs,
879 .main_clk = "gpt7_fck",
883 .module_bit = OMAP3430_EN_GPT7_SHIFT,
884 .module_offs = OMAP3430_PER_MOD,
886 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
889 .slaves = omap3xxx_timer7_slaves,
890 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
891 .class = &omap3xxx_timer_hwmod_class,
892 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
896 static struct omap_hwmod omap3xxx_timer8_hwmod;
898 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
900 .pa_start = 0x4903E000,
901 .pa_end = 0x4903E000 + SZ_1K - 1,
902 .flags = ADDR_TYPE_RT
907 /* l4_per -> timer8 */
908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
909 .master = &omap3xxx_l4_per_hwmod,
910 .slave = &omap3xxx_timer8_hwmod,
912 .addr = omap3xxx_timer8_addrs,
913 .user = OCP_USER_MPU | OCP_USER_SDMA,
916 /* timer8 slave port */
917 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
918 &omap3xxx_l4_per__timer8,
922 static struct omap_hwmod omap3xxx_timer8_hwmod = {
924 .mpu_irqs = omap2_timer8_mpu_irqs,
925 .main_clk = "gpt8_fck",
929 .module_bit = OMAP3430_EN_GPT8_SHIFT,
930 .module_offs = OMAP3430_PER_MOD,
932 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
935 .slaves = omap3xxx_timer8_slaves,
936 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
937 .class = &omap3xxx_timer_hwmod_class,
938 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
942 static struct omap_hwmod omap3xxx_timer9_hwmod;
944 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
946 .pa_start = 0x49040000,
947 .pa_end = 0x49040000 + SZ_1K - 1,
948 .flags = ADDR_TYPE_RT
953 /* l4_per -> timer9 */
954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
955 .master = &omap3xxx_l4_per_hwmod,
956 .slave = &omap3xxx_timer9_hwmod,
958 .addr = omap3xxx_timer9_addrs,
959 .user = OCP_USER_MPU | OCP_USER_SDMA,
962 /* timer9 slave port */
963 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
964 &omap3xxx_l4_per__timer9,
968 static struct omap_hwmod omap3xxx_timer9_hwmod = {
970 .mpu_irqs = omap2_timer9_mpu_irqs,
971 .main_clk = "gpt9_fck",
975 .module_bit = OMAP3430_EN_GPT9_SHIFT,
976 .module_offs = OMAP3430_PER_MOD,
978 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
981 .slaves = omap3xxx_timer9_slaves,
982 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
983 .class = &omap3xxx_timer_hwmod_class,
984 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
988 static struct omap_hwmod omap3xxx_timer10_hwmod;
990 /* l4_core -> timer10 */
991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
992 .master = &omap3xxx_l4_core_hwmod,
993 .slave = &omap3xxx_timer10_hwmod,
995 .addr = omap2_timer10_addrs,
996 .user = OCP_USER_MPU | OCP_USER_SDMA,
999 /* timer10 slave port */
1000 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1001 &omap3xxx_l4_core__timer10,
1005 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1007 .mpu_irqs = omap2_timer10_mpu_irqs,
1008 .main_clk = "gpt10_fck",
1012 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1013 .module_offs = CORE_MOD,
1015 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1018 .slaves = omap3xxx_timer10_slaves,
1019 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1020 .class = &omap3xxx_timer_1ms_hwmod_class,
1021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1025 static struct omap_hwmod omap3xxx_timer11_hwmod;
1027 /* l4_core -> timer11 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1029 .master = &omap3xxx_l4_core_hwmod,
1030 .slave = &omap3xxx_timer11_hwmod,
1032 .addr = omap2_timer11_addrs,
1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1036 /* timer11 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1038 &omap3xxx_l4_core__timer11,
1042 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1044 .mpu_irqs = omap2_timer11_mpu_irqs,
1045 .main_clk = "gpt11_fck",
1049 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1050 .module_offs = CORE_MOD,
1052 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1055 .slaves = omap3xxx_timer11_slaves,
1056 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1057 .class = &omap3xxx_timer_hwmod_class,
1058 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1062 static struct omap_hwmod omap3xxx_timer12_hwmod;
1063 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1068 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1070 .pa_start = 0x48304000,
1071 .pa_end = 0x48304000 + SZ_1K - 1,
1072 .flags = ADDR_TYPE_RT
1077 /* l4_core -> timer12 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1079 .master = &omap3xxx_l4_core_hwmod,
1080 .slave = &omap3xxx_timer12_hwmod,
1082 .addr = omap3xxx_timer12_addrs,
1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1086 /* timer12 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1088 &omap3xxx_l4_core__timer12,
1092 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1094 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1095 .main_clk = "gpt12_fck",
1099 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1100 .module_offs = WKUP_MOD,
1102 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1105 .slaves = omap3xxx_timer12_slaves,
1106 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1107 .class = &omap3xxx_timer_hwmod_class,
1108 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1111 /* l4_wkup -> wd_timer2 */
1112 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1114 .pa_start = 0x48314000,
1115 .pa_end = 0x4831407f,
1116 .flags = ADDR_TYPE_RT
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1122 .master = &omap3xxx_l4_wkup_hwmod,
1123 .slave = &omap3xxx_wd_timer2_hwmod,
1125 .addr = omap3xxx_wd_timer2_addrs,
1126 .user = OCP_USER_MPU | OCP_USER_SDMA,
1131 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1132 * overflow condition
1135 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1137 .sysc_offs = 0x0010,
1138 .syss_offs = 0x0014,
1139 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1140 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1141 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142 SYSS_HAS_RESET_STATUS),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144 .sysc_fields = &omap_hwmod_sysc_type1,
1148 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1152 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1153 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1154 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1156 .sysc_fields = &omap_hwmod_sysc_type1,
1159 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1161 .sysc = &omap3xxx_wd_timer_sysc,
1162 .pre_shutdown = &omap2_wd_timer_disable
1166 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1167 &omap3xxx_l4_wkup__wd_timer2,
1170 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1171 .name = "wd_timer2",
1172 .class = &omap3xxx_wd_timer_hwmod_class,
1173 .main_clk = "wdt2_fck",
1177 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1178 .module_offs = WKUP_MOD,
1180 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1183 .slaves = omap3xxx_wd_timer2_slaves,
1184 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1185 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1187 * XXX: Use software supervised mode, HW supervised smartidle seems to
1188 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1190 .flags = HWMOD_SWSUP_SIDLE,
1195 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1196 &omap3_l4_core__uart1,
1199 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1201 .mpu_irqs = omap2_uart1_mpu_irqs,
1202 .sdma_reqs = omap2_uart1_sdma_reqs,
1203 .main_clk = "uart1_fck",
1206 .module_offs = CORE_MOD,
1208 .module_bit = OMAP3430_EN_UART1_SHIFT,
1210 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1213 .slaves = omap3xxx_uart1_slaves,
1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1215 .class = &omap2_uart_class,
1216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1221 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1222 &omap3_l4_core__uart2,
1225 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1227 .mpu_irqs = omap2_uart2_mpu_irqs,
1228 .sdma_reqs = omap2_uart2_sdma_reqs,
1229 .main_clk = "uart2_fck",
1232 .module_offs = CORE_MOD,
1234 .module_bit = OMAP3430_EN_UART2_SHIFT,
1236 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1239 .slaves = omap3xxx_uart2_slaves,
1240 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1241 .class = &omap2_uart_class,
1242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1247 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1248 &omap3_l4_per__uart3,
1251 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1253 .mpu_irqs = omap2_uart3_mpu_irqs,
1254 .sdma_reqs = omap2_uart3_sdma_reqs,
1255 .main_clk = "uart3_fck",
1258 .module_offs = OMAP3430_PER_MOD,
1260 .module_bit = OMAP3430_EN_UART3_SHIFT,
1262 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1265 .slaves = omap3xxx_uart3_slaves,
1266 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1267 .class = &omap2_uart_class,
1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1273 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1274 { .irq = INT_36XX_UART4_IRQ, },
1278 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1279 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1280 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1284 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1285 &omap3_l4_per__uart4,
1288 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1290 .mpu_irqs = uart4_mpu_irqs,
1291 .sdma_reqs = uart4_sdma_reqs,
1292 .main_clk = "uart4_fck",
1295 .module_offs = OMAP3430_PER_MOD,
1297 .module_bit = OMAP3630_EN_UART4_SHIFT,
1299 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1302 .slaves = omap3xxx_uart4_slaves,
1303 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1304 .class = &omap2_uart_class,
1305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1308 static struct omap_hwmod_class i2c_class = {
1311 .rev = OMAP_I2C_IP_VERSION_1,
1314 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1315 { .name = "dispc", .dma_req = 5 },
1316 { .name = "dsi1", .dma_req = 74 },
1321 /* dss master ports */
1322 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1326 /* l4_core -> dss */
1327 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1328 .master = &omap3xxx_l4_core_hwmod,
1329 .slave = &omap3430es1_dss_core_hwmod,
1331 .addr = omap2_dss_addrs,
1334 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1335 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1336 .flags = OMAP_FIREWALL_L4,
1339 .user = OCP_USER_MPU | OCP_USER_SDMA,
1342 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1343 .master = &omap3xxx_l4_core_hwmod,
1344 .slave = &omap3xxx_dss_core_hwmod,
1346 .addr = omap2_dss_addrs,
1349 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1350 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1351 .flags = OMAP_FIREWALL_L4,
1354 .user = OCP_USER_MPU | OCP_USER_SDMA,
1357 /* dss slave ports */
1358 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1359 &omap3430es1_l4_core__dss,
1362 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1363 &omap3xxx_l4_core__dss,
1366 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1367 { .role = "tv_clk", .clk = "dss_tv_fck" },
1368 { .role = "video_clk", .clk = "dss_96m_fck" },
1369 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1372 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1374 .class = &omap2_dss_hwmod_class,
1375 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1376 .sdma_reqs = omap3xxx_dss_sdma_chs,
1380 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1381 .module_offs = OMAP3430_DSS_MOD,
1383 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1386 .opt_clks = dss_opt_clks,
1387 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1388 .slaves = omap3430es1_dss_slaves,
1389 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1390 .masters = omap3xxx_dss_masters,
1391 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1392 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1393 .flags = HWMOD_NO_IDLEST,
1396 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1398 .class = &omap2_dss_hwmod_class,
1399 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1400 .sdma_reqs = omap3xxx_dss_sdma_chs,
1404 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1405 .module_offs = OMAP3430_DSS_MOD,
1407 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1408 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1411 .opt_clks = dss_opt_clks,
1412 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1413 .slaves = omap3xxx_dss_slaves,
1414 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1415 .masters = omap3xxx_dss_masters,
1416 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1417 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1418 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1421 /* l4_core -> dss_dispc */
1422 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1423 .master = &omap3xxx_l4_core_hwmod,
1424 .slave = &omap3xxx_dss_dispc_hwmod,
1426 .addr = omap2_dss_dispc_addrs,
1429 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1430 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1431 .flags = OMAP_FIREWALL_L4,
1434 .user = OCP_USER_MPU | OCP_USER_SDMA,
1437 /* dss_dispc slave ports */
1438 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1439 &omap3xxx_l4_core__dss_dispc,
1442 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1443 .name = "dss_dispc",
1444 .class = &omap2_dispc_hwmod_class,
1445 .mpu_irqs = omap2_dispc_irqs,
1446 .main_clk = "dss1_alwon_fck",
1450 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1451 .module_offs = OMAP3430_DSS_MOD,
1454 .slaves = omap3xxx_dss_dispc_slaves,
1455 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1456 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1457 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1458 CHIP_GE_OMAP3630ES1_1),
1459 .flags = HWMOD_NO_IDLEST,
1464 * display serial interface controller
1467 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1471 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1477 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1479 .pa_start = 0x4804FC00,
1480 .pa_end = 0x4804FFFF,
1481 .flags = ADDR_TYPE_RT
1486 /* l4_core -> dss_dsi1 */
1487 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1488 .master = &omap3xxx_l4_core_hwmod,
1489 .slave = &omap3xxx_dss_dsi1_hwmod,
1490 .addr = omap3xxx_dss_dsi1_addrs,
1493 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1494 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1495 .flags = OMAP_FIREWALL_L4,
1498 .user = OCP_USER_MPU | OCP_USER_SDMA,
1501 /* dss_dsi1 slave ports */
1502 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1503 &omap3xxx_l4_core__dss_dsi1,
1506 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1508 .class = &omap3xxx_dsi_hwmod_class,
1509 .mpu_irqs = omap3xxx_dsi1_irqs,
1510 .main_clk = "dss1_alwon_fck",
1514 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1515 .module_offs = OMAP3430_DSS_MOD,
1518 .slaves = omap3xxx_dss_dsi1_slaves,
1519 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1520 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1521 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1522 CHIP_GE_OMAP3630ES1_1),
1523 .flags = HWMOD_NO_IDLEST,
1526 /* l4_core -> dss_rfbi */
1527 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1528 .master = &omap3xxx_l4_core_hwmod,
1529 .slave = &omap3xxx_dss_rfbi_hwmod,
1531 .addr = omap2_dss_rfbi_addrs,
1534 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1535 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1536 .flags = OMAP_FIREWALL_L4,
1539 .user = OCP_USER_MPU | OCP_USER_SDMA,
1542 /* dss_rfbi slave ports */
1543 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1544 &omap3xxx_l4_core__dss_rfbi,
1547 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1549 .class = &omap2_rfbi_hwmod_class,
1550 .main_clk = "dss1_alwon_fck",
1554 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1555 .module_offs = OMAP3430_DSS_MOD,
1558 .slaves = omap3xxx_dss_rfbi_slaves,
1559 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1560 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1561 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1562 CHIP_GE_OMAP3630ES1_1),
1563 .flags = HWMOD_NO_IDLEST,
1566 /* l4_core -> dss_venc */
1567 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1568 .master = &omap3xxx_l4_core_hwmod,
1569 .slave = &omap3xxx_dss_venc_hwmod,
1570 .clk = "dss_tv_fck",
1571 .addr = omap2_dss_venc_addrs,
1574 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1575 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1576 .flags = OMAP_FIREWALL_L4,
1579 .flags = OCPIF_SWSUP_IDLE,
1580 .user = OCP_USER_MPU | OCP_USER_SDMA,
1583 /* dss_venc slave ports */
1584 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1585 &omap3xxx_l4_core__dss_venc,
1588 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1590 .class = &omap2_venc_hwmod_class,
1591 .main_clk = "dss1_alwon_fck",
1595 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1596 .module_offs = OMAP3430_DSS_MOD,
1599 .slaves = omap3xxx_dss_venc_slaves,
1600 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1601 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1602 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1603 CHIP_GE_OMAP3630ES1_1),
1604 .flags = HWMOD_NO_IDLEST,
1609 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1610 .fifo_depth = 8, /* bytes */
1611 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1612 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1613 OMAP_I2C_FLAG_BUS_SHIFT_2,
1616 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1617 &omap3_l4_core__i2c1,
1620 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1622 .flags = HWMOD_16BIT_REG,
1623 .mpu_irqs = omap2_i2c1_mpu_irqs,
1624 .sdma_reqs = omap2_i2c1_sdma_reqs,
1625 .main_clk = "i2c1_fck",
1628 .module_offs = CORE_MOD,
1630 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1632 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1635 .slaves = omap3xxx_i2c1_slaves,
1636 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1637 .class = &i2c_class,
1638 .dev_attr = &i2c1_dev_attr,
1639 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1644 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1645 .fifo_depth = 8, /* bytes */
1646 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1647 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1648 OMAP_I2C_FLAG_BUS_SHIFT_2,
1651 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1652 &omap3_l4_core__i2c2,
1655 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1657 .flags = HWMOD_16BIT_REG,
1658 .mpu_irqs = omap2_i2c2_mpu_irqs,
1659 .sdma_reqs = omap2_i2c2_sdma_reqs,
1660 .main_clk = "i2c2_fck",
1663 .module_offs = CORE_MOD,
1665 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1667 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1670 .slaves = omap3xxx_i2c2_slaves,
1671 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1672 .class = &i2c_class,
1673 .dev_attr = &i2c2_dev_attr,
1674 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1679 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1680 .fifo_depth = 64, /* bytes */
1681 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1682 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1683 OMAP_I2C_FLAG_BUS_SHIFT_2,
1686 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1687 { .irq = INT_34XX_I2C3_IRQ, },
1691 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1692 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1693 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1697 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1698 &omap3_l4_core__i2c3,
1701 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1703 .flags = HWMOD_16BIT_REG,
1704 .mpu_irqs = i2c3_mpu_irqs,
1705 .sdma_reqs = i2c3_sdma_reqs,
1706 .main_clk = "i2c3_fck",
1709 .module_offs = CORE_MOD,
1711 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1713 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1716 .slaves = omap3xxx_i2c3_slaves,
1717 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1718 .class = &i2c_class,
1719 .dev_attr = &i2c3_dev_attr,
1720 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1723 /* l4_wkup -> gpio1 */
1724 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1726 .pa_start = 0x48310000,
1727 .pa_end = 0x483101ff,
1728 .flags = ADDR_TYPE_RT
1733 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1734 .master = &omap3xxx_l4_wkup_hwmod,
1735 .slave = &omap3xxx_gpio1_hwmod,
1736 .addr = omap3xxx_gpio1_addrs,
1737 .user = OCP_USER_MPU | OCP_USER_SDMA,
1740 /* l4_per -> gpio2 */
1741 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1743 .pa_start = 0x49050000,
1744 .pa_end = 0x490501ff,
1745 .flags = ADDR_TYPE_RT
1750 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1751 .master = &omap3xxx_l4_per_hwmod,
1752 .slave = &omap3xxx_gpio2_hwmod,
1753 .addr = omap3xxx_gpio2_addrs,
1754 .user = OCP_USER_MPU | OCP_USER_SDMA,
1757 /* l4_per -> gpio3 */
1758 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1760 .pa_start = 0x49052000,
1761 .pa_end = 0x490521ff,
1762 .flags = ADDR_TYPE_RT
1767 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1768 .master = &omap3xxx_l4_per_hwmod,
1769 .slave = &omap3xxx_gpio3_hwmod,
1770 .addr = omap3xxx_gpio3_addrs,
1771 .user = OCP_USER_MPU | OCP_USER_SDMA,
1774 /* l4_per -> gpio4 */
1775 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1777 .pa_start = 0x49054000,
1778 .pa_end = 0x490541ff,
1779 .flags = ADDR_TYPE_RT
1784 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1785 .master = &omap3xxx_l4_per_hwmod,
1786 .slave = &omap3xxx_gpio4_hwmod,
1787 .addr = omap3xxx_gpio4_addrs,
1788 .user = OCP_USER_MPU | OCP_USER_SDMA,
1791 /* l4_per -> gpio5 */
1792 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1794 .pa_start = 0x49056000,
1795 .pa_end = 0x490561ff,
1796 .flags = ADDR_TYPE_RT
1801 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1802 .master = &omap3xxx_l4_per_hwmod,
1803 .slave = &omap3xxx_gpio5_hwmod,
1804 .addr = omap3xxx_gpio5_addrs,
1805 .user = OCP_USER_MPU | OCP_USER_SDMA,
1808 /* l4_per -> gpio6 */
1809 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1811 .pa_start = 0x49058000,
1812 .pa_end = 0x490581ff,
1813 .flags = ADDR_TYPE_RT
1818 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1819 .master = &omap3xxx_l4_per_hwmod,
1820 .slave = &omap3xxx_gpio6_hwmod,
1821 .addr = omap3xxx_gpio6_addrs,
1822 .user = OCP_USER_MPU | OCP_USER_SDMA,
1827 * general purpose io module
1830 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1832 .sysc_offs = 0x0010,
1833 .syss_offs = 0x0014,
1834 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1835 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1836 SYSS_HAS_RESET_STATUS),
1837 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1838 .sysc_fields = &omap_hwmod_sysc_type1,
1841 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1843 .sysc = &omap3xxx_gpio_sysc,
1848 static struct omap_gpio_dev_attr gpio_dev_attr = {
1854 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1855 { .role = "dbclk", .clk = "gpio1_dbck", },
1858 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1859 &omap3xxx_l4_wkup__gpio1,
1862 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1864 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1865 .mpu_irqs = omap2_gpio1_irqs,
1866 .main_clk = "gpio1_ick",
1867 .opt_clks = gpio1_opt_clks,
1868 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1872 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1873 .module_offs = WKUP_MOD,
1875 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1878 .slaves = omap3xxx_gpio1_slaves,
1879 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1880 .class = &omap3xxx_gpio_hwmod_class,
1881 .dev_attr = &gpio_dev_attr,
1882 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1886 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1887 { .role = "dbclk", .clk = "gpio2_dbck", },
1890 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1891 &omap3xxx_l4_per__gpio2,
1894 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1896 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1897 .mpu_irqs = omap2_gpio2_irqs,
1898 .main_clk = "gpio2_ick",
1899 .opt_clks = gpio2_opt_clks,
1900 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1904 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1905 .module_offs = OMAP3430_PER_MOD,
1907 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1910 .slaves = omap3xxx_gpio2_slaves,
1911 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1912 .class = &omap3xxx_gpio_hwmod_class,
1913 .dev_attr = &gpio_dev_attr,
1914 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1918 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1919 { .role = "dbclk", .clk = "gpio3_dbck", },
1922 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1923 &omap3xxx_l4_per__gpio3,
1926 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1928 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1929 .mpu_irqs = omap2_gpio3_irqs,
1930 .main_clk = "gpio3_ick",
1931 .opt_clks = gpio3_opt_clks,
1932 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1936 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1937 .module_offs = OMAP3430_PER_MOD,
1939 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1942 .slaves = omap3xxx_gpio3_slaves,
1943 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1944 .class = &omap3xxx_gpio_hwmod_class,
1945 .dev_attr = &gpio_dev_attr,
1946 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1950 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1951 { .role = "dbclk", .clk = "gpio4_dbck", },
1954 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1955 &omap3xxx_l4_per__gpio4,
1958 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1960 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1961 .mpu_irqs = omap2_gpio4_irqs,
1962 .main_clk = "gpio4_ick",
1963 .opt_clks = gpio4_opt_clks,
1964 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1968 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1969 .module_offs = OMAP3430_PER_MOD,
1971 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1974 .slaves = omap3xxx_gpio4_slaves,
1975 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1976 .class = &omap3xxx_gpio_hwmod_class,
1977 .dev_attr = &gpio_dev_attr,
1978 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1982 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1983 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1987 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1988 { .role = "dbclk", .clk = "gpio5_dbck", },
1991 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1992 &omap3xxx_l4_per__gpio5,
1995 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1997 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1998 .mpu_irqs = omap3xxx_gpio5_irqs,
1999 .main_clk = "gpio5_ick",
2000 .opt_clks = gpio5_opt_clks,
2001 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2005 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2006 .module_offs = OMAP3430_PER_MOD,
2008 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2011 .slaves = omap3xxx_gpio5_slaves,
2012 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2013 .class = &omap3xxx_gpio_hwmod_class,
2014 .dev_attr = &gpio_dev_attr,
2015 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2019 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2020 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2024 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2025 { .role = "dbclk", .clk = "gpio6_dbck", },
2028 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2029 &omap3xxx_l4_per__gpio6,
2032 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2034 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2035 .mpu_irqs = omap3xxx_gpio6_irqs,
2036 .main_clk = "gpio6_ick",
2037 .opt_clks = gpio6_opt_clks,
2038 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2042 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2043 .module_offs = OMAP3430_PER_MOD,
2045 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2048 .slaves = omap3xxx_gpio6_slaves,
2049 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2050 .class = &omap3xxx_gpio_hwmod_class,
2051 .dev_attr = &gpio_dev_attr,
2052 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2055 /* dma_system -> L3 */
2056 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2057 .master = &omap3xxx_dma_system_hwmod,
2058 .slave = &omap3xxx_l3_main_hwmod,
2059 .clk = "core_l3_ick",
2060 .user = OCP_USER_MPU | OCP_USER_SDMA,
2063 /* dma attributes */
2064 static struct omap_dma_dev_attr dma_dev_attr = {
2065 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2066 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2070 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2072 .sysc_offs = 0x002c,
2073 .syss_offs = 0x0028,
2074 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2075 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2076 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2077 SYSS_HAS_RESET_STATUS),
2078 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2079 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2080 .sysc_fields = &omap_hwmod_sysc_type1,
2083 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2085 .sysc = &omap3xxx_dma_sysc,
2089 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2091 .pa_start = 0x48056000,
2092 .pa_end = 0x48056fff,
2093 .flags = ADDR_TYPE_RT
2098 /* dma_system master ports */
2099 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2100 &omap3xxx_dma_system__l3,
2103 /* l4_cfg -> dma_system */
2104 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2105 .master = &omap3xxx_l4_core_hwmod,
2106 .slave = &omap3xxx_dma_system_hwmod,
2107 .clk = "core_l4_ick",
2108 .addr = omap3xxx_dma_system_addrs,
2109 .user = OCP_USER_MPU | OCP_USER_SDMA,
2112 /* dma_system slave ports */
2113 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2114 &omap3xxx_l4_core__dma_system,
2117 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2119 .class = &omap3xxx_dma_hwmod_class,
2120 .mpu_irqs = omap2_dma_system_irqs,
2121 .main_clk = "core_l3_ick",
2124 .module_offs = CORE_MOD,
2126 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2128 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2131 .slaves = omap3xxx_dma_system_slaves,
2132 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2133 .masters = omap3xxx_dma_system_masters,
2134 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2135 .dev_attr = &dma_dev_attr,
2136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2137 .flags = HWMOD_NO_IDLEST,
2142 * multi channel buffered serial port controller
2145 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2146 .sysc_offs = 0x008c,
2147 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2148 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2149 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2150 .sysc_fields = &omap_hwmod_sysc_type1,
2154 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2156 .sysc = &omap3xxx_mcbsp_sysc,
2157 .rev = MCBSP_CONFIG_TYPE3,
2161 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2162 { .name = "irq", .irq = 16 },
2163 { .name = "tx", .irq = 59 },
2164 { .name = "rx", .irq = 60 },
2168 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2171 .pa_start = 0x48074000,
2172 .pa_end = 0x480740ff,
2173 .flags = ADDR_TYPE_RT
2178 /* l4_core -> mcbsp1 */
2179 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2180 .master = &omap3xxx_l4_core_hwmod,
2181 .slave = &omap3xxx_mcbsp1_hwmod,
2182 .clk = "mcbsp1_ick",
2183 .addr = omap3xxx_mcbsp1_addrs,
2184 .user = OCP_USER_MPU | OCP_USER_SDMA,
2187 /* mcbsp1 slave ports */
2188 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2189 &omap3xxx_l4_core__mcbsp1,
2192 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2194 .class = &omap3xxx_mcbsp_hwmod_class,
2195 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2196 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2197 .main_clk = "mcbsp1_fck",
2201 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2202 .module_offs = CORE_MOD,
2204 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2207 .slaves = omap3xxx_mcbsp1_slaves,
2208 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2209 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2213 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2214 { .name = "irq", .irq = 17 },
2215 { .name = "tx", .irq = 62 },
2216 { .name = "rx", .irq = 63 },
2220 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2223 .pa_start = 0x49022000,
2224 .pa_end = 0x490220ff,
2225 .flags = ADDR_TYPE_RT
2230 /* l4_per -> mcbsp2 */
2231 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2232 .master = &omap3xxx_l4_per_hwmod,
2233 .slave = &omap3xxx_mcbsp2_hwmod,
2234 .clk = "mcbsp2_ick",
2235 .addr = omap3xxx_mcbsp2_addrs,
2236 .user = OCP_USER_MPU | OCP_USER_SDMA,
2239 /* mcbsp2 slave ports */
2240 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2241 &omap3xxx_l4_per__mcbsp2,
2244 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2245 .sidetone = "mcbsp2_sidetone",
2248 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2250 .class = &omap3xxx_mcbsp_hwmod_class,
2251 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2252 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2253 .main_clk = "mcbsp2_fck",
2257 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2258 .module_offs = OMAP3430_PER_MOD,
2260 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2263 .slaves = omap3xxx_mcbsp2_slaves,
2264 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2265 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2266 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2270 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2271 { .name = "irq", .irq = 22 },
2272 { .name = "tx", .irq = 89 },
2273 { .name = "rx", .irq = 90 },
2277 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2280 .pa_start = 0x49024000,
2281 .pa_end = 0x490240ff,
2282 .flags = ADDR_TYPE_RT
2287 /* l4_per -> mcbsp3 */
2288 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2289 .master = &omap3xxx_l4_per_hwmod,
2290 .slave = &omap3xxx_mcbsp3_hwmod,
2291 .clk = "mcbsp3_ick",
2292 .addr = omap3xxx_mcbsp3_addrs,
2293 .user = OCP_USER_MPU | OCP_USER_SDMA,
2296 /* mcbsp3 slave ports */
2297 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2298 &omap3xxx_l4_per__mcbsp3,
2301 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2302 .sidetone = "mcbsp3_sidetone",
2305 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2307 .class = &omap3xxx_mcbsp_hwmod_class,
2308 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2309 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2310 .main_clk = "mcbsp3_fck",
2314 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2315 .module_offs = OMAP3430_PER_MOD,
2317 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2320 .slaves = omap3xxx_mcbsp3_slaves,
2321 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2322 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2323 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2327 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2328 { .name = "irq", .irq = 23 },
2329 { .name = "tx", .irq = 54 },
2330 { .name = "rx", .irq = 55 },
2334 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2335 { .name = "rx", .dma_req = 20 },
2336 { .name = "tx", .dma_req = 19 },
2340 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2343 .pa_start = 0x49026000,
2344 .pa_end = 0x490260ff,
2345 .flags = ADDR_TYPE_RT
2350 /* l4_per -> mcbsp4 */
2351 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2352 .master = &omap3xxx_l4_per_hwmod,
2353 .slave = &omap3xxx_mcbsp4_hwmod,
2354 .clk = "mcbsp4_ick",
2355 .addr = omap3xxx_mcbsp4_addrs,
2356 .user = OCP_USER_MPU | OCP_USER_SDMA,
2359 /* mcbsp4 slave ports */
2360 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2361 &omap3xxx_l4_per__mcbsp4,
2364 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2366 .class = &omap3xxx_mcbsp_hwmod_class,
2367 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2368 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2369 .main_clk = "mcbsp4_fck",
2373 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2374 .module_offs = OMAP3430_PER_MOD,
2376 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2379 .slaves = omap3xxx_mcbsp4_slaves,
2380 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2381 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2385 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2386 { .name = "irq", .irq = 27 },
2387 { .name = "tx", .irq = 81 },
2388 { .name = "rx", .irq = 82 },
2392 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2393 { .name = "rx", .dma_req = 22 },
2394 { .name = "tx", .dma_req = 21 },
2398 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2401 .pa_start = 0x48096000,
2402 .pa_end = 0x480960ff,
2403 .flags = ADDR_TYPE_RT
2408 /* l4_core -> mcbsp5 */
2409 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2410 .master = &omap3xxx_l4_core_hwmod,
2411 .slave = &omap3xxx_mcbsp5_hwmod,
2412 .clk = "mcbsp5_ick",
2413 .addr = omap3xxx_mcbsp5_addrs,
2414 .user = OCP_USER_MPU | OCP_USER_SDMA,
2417 /* mcbsp5 slave ports */
2418 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2419 &omap3xxx_l4_core__mcbsp5,
2422 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2424 .class = &omap3xxx_mcbsp_hwmod_class,
2425 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2426 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2427 .main_clk = "mcbsp5_fck",
2431 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2432 .module_offs = CORE_MOD,
2434 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2437 .slaves = omap3xxx_mcbsp5_slaves,
2438 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2439 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2441 /* 'mcbsp sidetone' class */
2443 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2444 .sysc_offs = 0x0010,
2445 .sysc_flags = SYSC_HAS_AUTOIDLE,
2446 .sysc_fields = &omap_hwmod_sysc_type1,
2449 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2450 .name = "mcbsp_sidetone",
2451 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2454 /* mcbsp2_sidetone */
2455 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2456 { .name = "irq", .irq = 4 },
2460 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2463 .pa_start = 0x49028000,
2464 .pa_end = 0x490280ff,
2465 .flags = ADDR_TYPE_RT
2470 /* l4_per -> mcbsp2_sidetone */
2471 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2472 .master = &omap3xxx_l4_per_hwmod,
2473 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2474 .clk = "mcbsp2_ick",
2475 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2476 .user = OCP_USER_MPU,
2479 /* mcbsp2_sidetone slave ports */
2480 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2481 &omap3xxx_l4_per__mcbsp2_sidetone,
2484 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2485 .name = "mcbsp2_sidetone",
2486 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2487 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2488 .main_clk = "mcbsp2_fck",
2492 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2493 .module_offs = OMAP3430_PER_MOD,
2495 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2498 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2499 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2500 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2503 /* mcbsp3_sidetone */
2504 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2505 { .name = "irq", .irq = 5 },
2509 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2512 .pa_start = 0x4902A000,
2513 .pa_end = 0x4902A0ff,
2514 .flags = ADDR_TYPE_RT
2519 /* l4_per -> mcbsp3_sidetone */
2520 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2521 .master = &omap3xxx_l4_per_hwmod,
2522 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2523 .clk = "mcbsp3_ick",
2524 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2525 .user = OCP_USER_MPU,
2528 /* mcbsp3_sidetone slave ports */
2529 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2530 &omap3xxx_l4_per__mcbsp3_sidetone,
2533 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2534 .name = "mcbsp3_sidetone",
2535 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2536 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2537 .main_clk = "mcbsp3_fck",
2541 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2542 .module_offs = OMAP3430_PER_MOD,
2544 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2547 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2548 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2549 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2554 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2558 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2560 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2561 .clockact = CLOCKACT_TEST_ICLK,
2562 .sysc_fields = &omap34xx_sr_sysc_fields,
2565 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2566 .name = "smartreflex",
2567 .sysc = &omap34xx_sr_sysc,
2571 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2576 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2578 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2579 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2581 .sysc_fields = &omap36xx_sr_sysc_fields,
2584 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2585 .name = "smartreflex",
2586 .sysc = &omap36xx_sr_sysc,
2591 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2592 &omap3_l4_core__sr1,
2595 static struct omap_hwmod omap34xx_sr1_hwmod = {
2596 .name = "sr1_hwmod",
2597 .class = &omap34xx_smartreflex_hwmod_class,
2598 .main_clk = "sr1_fck",
2603 .module_bit = OMAP3430_EN_SR1_SHIFT,
2604 .module_offs = WKUP_MOD,
2606 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2609 .slaves = omap3_sr1_slaves,
2610 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2611 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2612 CHIP_IS_OMAP3430ES3_0 |
2613 CHIP_IS_OMAP3430ES3_1),
2614 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2617 static struct omap_hwmod omap36xx_sr1_hwmod = {
2618 .name = "sr1_hwmod",
2619 .class = &omap36xx_smartreflex_hwmod_class,
2620 .main_clk = "sr1_fck",
2625 .module_bit = OMAP3430_EN_SR1_SHIFT,
2626 .module_offs = WKUP_MOD,
2628 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2631 .slaves = omap3_sr1_slaves,
2632 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2633 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2637 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2638 &omap3_l4_core__sr2,
2641 static struct omap_hwmod omap34xx_sr2_hwmod = {
2642 .name = "sr2_hwmod",
2643 .class = &omap34xx_smartreflex_hwmod_class,
2644 .main_clk = "sr2_fck",
2649 .module_bit = OMAP3430_EN_SR2_SHIFT,
2650 .module_offs = WKUP_MOD,
2652 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2655 .slaves = omap3_sr2_slaves,
2656 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2657 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2658 CHIP_IS_OMAP3430ES3_0 |
2659 CHIP_IS_OMAP3430ES3_1),
2660 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2663 static struct omap_hwmod omap36xx_sr2_hwmod = {
2664 .name = "sr2_hwmod",
2665 .class = &omap36xx_smartreflex_hwmod_class,
2666 .main_clk = "sr2_fck",
2671 .module_bit = OMAP3430_EN_SR2_SHIFT,
2672 .module_offs = WKUP_MOD,
2674 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2677 .slaves = omap3_sr2_slaves,
2678 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2679 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2684 * mailbox module allowing communication between the on-chip processors
2685 * using a queued mailbox-interrupt mechanism.
2688 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2692 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2693 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2694 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2695 .sysc_fields = &omap_hwmod_sysc_type1,
2698 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2700 .sysc = &omap3xxx_mailbox_sysc,
2703 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2704 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2709 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2711 .pa_start = 0x48094000,
2712 .pa_end = 0x480941ff,
2713 .flags = ADDR_TYPE_RT,
2718 /* l4_core -> mailbox */
2719 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2720 .master = &omap3xxx_l4_core_hwmod,
2721 .slave = &omap3xxx_mailbox_hwmod,
2722 .addr = omap3xxx_mailbox_addrs,
2723 .user = OCP_USER_MPU | OCP_USER_SDMA,
2726 /* mailbox slave ports */
2727 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2728 &omap3xxx_l4_core__mailbox,
2731 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2733 .class = &omap3xxx_mailbox_hwmod_class,
2734 .mpu_irqs = omap3xxx_mailbox_irqs,
2735 .main_clk = "mailboxes_ick",
2739 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2740 .module_offs = CORE_MOD,
2742 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2745 .slaves = omap3xxx_mailbox_slaves,
2746 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2747 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2750 /* l4 core -> mcspi1 interface */
2751 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2752 .master = &omap3xxx_l4_core_hwmod,
2753 .slave = &omap34xx_mcspi1,
2754 .clk = "mcspi1_ick",
2755 .addr = omap2_mcspi1_addr_space,
2756 .user = OCP_USER_MPU | OCP_USER_SDMA,
2759 /* l4 core -> mcspi2 interface */
2760 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2761 .master = &omap3xxx_l4_core_hwmod,
2762 .slave = &omap34xx_mcspi2,
2763 .clk = "mcspi2_ick",
2764 .addr = omap2_mcspi2_addr_space,
2765 .user = OCP_USER_MPU | OCP_USER_SDMA,
2768 /* l4 core -> mcspi3 interface */
2769 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2770 .master = &omap3xxx_l4_core_hwmod,
2771 .slave = &omap34xx_mcspi3,
2772 .clk = "mcspi3_ick",
2773 .addr = omap2430_mcspi3_addr_space,
2774 .user = OCP_USER_MPU | OCP_USER_SDMA,
2777 /* l4 core -> mcspi4 interface */
2778 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2780 .pa_start = 0x480ba000,
2781 .pa_end = 0x480ba0ff,
2782 .flags = ADDR_TYPE_RT,
2787 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2788 .master = &omap3xxx_l4_core_hwmod,
2789 .slave = &omap34xx_mcspi4,
2790 .clk = "mcspi4_ick",
2791 .addr = omap34xx_mcspi4_addr_space,
2792 .user = OCP_USER_MPU | OCP_USER_SDMA,
2797 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2801 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2803 .sysc_offs = 0x0010,
2804 .syss_offs = 0x0014,
2805 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2806 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2807 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2808 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2809 .sysc_fields = &omap_hwmod_sysc_type1,
2812 static struct omap_hwmod_class omap34xx_mcspi_class = {
2814 .sysc = &omap34xx_mcspi_sysc,
2815 .rev = OMAP3_MCSPI_REV,
2819 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2820 &omap34xx_l4_core__mcspi1,
2823 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2824 .num_chipselect = 4,
2827 static struct omap_hwmod omap34xx_mcspi1 = {
2829 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2830 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2831 .main_clk = "mcspi1_fck",
2834 .module_offs = CORE_MOD,
2836 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2838 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2841 .slaves = omap34xx_mcspi1_slaves,
2842 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2843 .class = &omap34xx_mcspi_class,
2844 .dev_attr = &omap_mcspi1_dev_attr,
2845 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2849 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2850 &omap34xx_l4_core__mcspi2,
2853 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2854 .num_chipselect = 2,
2857 static struct omap_hwmod omap34xx_mcspi2 = {
2859 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2860 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2861 .main_clk = "mcspi2_fck",
2864 .module_offs = CORE_MOD,
2866 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2868 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2871 .slaves = omap34xx_mcspi2_slaves,
2872 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2873 .class = &omap34xx_mcspi_class,
2874 .dev_attr = &omap_mcspi2_dev_attr,
2875 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2879 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2880 { .name = "irq", .irq = 91 }, /* 91 */
2884 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2885 { .name = "tx0", .dma_req = 15 },
2886 { .name = "rx0", .dma_req = 16 },
2887 { .name = "tx1", .dma_req = 23 },
2888 { .name = "rx1", .dma_req = 24 },
2892 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2893 &omap34xx_l4_core__mcspi3,
2896 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2897 .num_chipselect = 2,
2900 static struct omap_hwmod omap34xx_mcspi3 = {
2902 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2903 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2904 .main_clk = "mcspi3_fck",
2907 .module_offs = CORE_MOD,
2909 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2911 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2914 .slaves = omap34xx_mcspi3_slaves,
2915 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2916 .class = &omap34xx_mcspi_class,
2917 .dev_attr = &omap_mcspi3_dev_attr,
2918 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2922 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2923 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2927 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2928 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2929 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2933 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2934 &omap34xx_l4_core__mcspi4,
2937 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2938 .num_chipselect = 1,
2941 static struct omap_hwmod omap34xx_mcspi4 = {
2943 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
2944 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
2945 .main_clk = "mcspi4_fck",
2948 .module_offs = CORE_MOD,
2950 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2952 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2955 .slaves = omap34xx_mcspi4_slaves,
2956 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2957 .class = &omap34xx_mcspi_class,
2958 .dev_attr = &omap_mcspi4_dev_attr,
2959 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2965 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2967 .sysc_offs = 0x0404,
2968 .syss_offs = 0x0408,
2969 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2970 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2972 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2973 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2974 .sysc_fields = &omap_hwmod_sysc_type1,
2977 static struct omap_hwmod_class usbotg_class = {
2979 .sysc = &omap3xxx_usbhsotg_sysc,
2982 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2984 { .name = "mc", .irq = 92 },
2985 { .name = "dma", .irq = 93 },
2989 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2990 .name = "usb_otg_hs",
2991 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
2992 .main_clk = "hsotgusb_ick",
2996 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2997 .module_offs = CORE_MOD,
2999 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3000 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3003 .masters = omap3xxx_usbhsotg_masters,
3004 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3005 .slaves = omap3xxx_usbhsotg_slaves,
3006 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3007 .class = &usbotg_class,
3010 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3011 * broken when autoidle is enabled
3012 * workaround is to disable the autoidle bit at module level.
3014 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3015 | HWMOD_SWSUP_MSTANDBY,
3016 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3020 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3022 { .name = "mc", .irq = 71 },
3026 static struct omap_hwmod_class am35xx_usbotg_class = {
3027 .name = "am35xx_usbotg",
3031 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3032 .name = "am35x_otg_hs",
3033 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3039 .masters = am35xx_usbhsotg_masters,
3040 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3041 .slaves = am35xx_usbhsotg_slaves,
3042 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3043 .class = &am35xx_usbotg_class,
3044 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3047 /* MMC/SD/SDIO common */
3049 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3053 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3054 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3055 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3056 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3057 .sysc_fields = &omap_hwmod_sysc_type1,
3060 static struct omap_hwmod_class omap34xx_mmc_class = {
3062 .sysc = &omap34xx_mmc_sysc,
3067 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3072 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3073 { .name = "tx", .dma_req = 61, },
3074 { .name = "rx", .dma_req = 62, },
3078 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3079 { .role = "dbck", .clk = "omap_32k_fck", },
3082 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3083 &omap3xxx_l4_core__mmc1,
3086 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3087 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3090 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3092 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3093 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3094 .opt_clks = omap34xx_mmc1_opt_clks,
3095 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3096 .main_clk = "mmchs1_fck",
3099 .module_offs = CORE_MOD,
3101 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3103 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3106 .dev_attr = &mmc1_dev_attr,
3107 .slaves = omap3xxx_mmc1_slaves,
3108 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3109 .class = &omap34xx_mmc_class,
3110 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3115 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3116 { .irq = INT_24XX_MMC2_IRQ, },
3120 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3121 { .name = "tx", .dma_req = 47, },
3122 { .name = "rx", .dma_req = 48, },
3126 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3127 { .role = "dbck", .clk = "omap_32k_fck", },
3130 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3131 &omap3xxx_l4_core__mmc2,
3134 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3136 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3137 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3138 .opt_clks = omap34xx_mmc2_opt_clks,
3139 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3140 .main_clk = "mmchs2_fck",
3143 .module_offs = CORE_MOD,
3145 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3147 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3150 .slaves = omap3xxx_mmc2_slaves,
3151 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3152 .class = &omap34xx_mmc_class,
3153 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3158 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3163 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3164 { .name = "tx", .dma_req = 77, },
3165 { .name = "rx", .dma_req = 78, },
3169 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3170 { .role = "dbck", .clk = "omap_32k_fck", },
3173 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3174 &omap3xxx_l4_core__mmc3,
3177 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3179 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3180 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3181 .opt_clks = omap34xx_mmc3_opt_clks,
3182 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3183 .main_clk = "mmchs3_fck",
3187 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3189 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3192 .slaves = omap3xxx_mmc3_slaves,
3193 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3194 .class = &omap34xx_mmc_class,
3195 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3198 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3199 &omap3xxx_l3_main_hwmod,
3200 &omap3xxx_l4_core_hwmod,
3201 &omap3xxx_l4_per_hwmod,
3202 &omap3xxx_l4_wkup_hwmod,
3203 &omap3xxx_mmc1_hwmod,
3204 &omap3xxx_mmc2_hwmod,
3205 &omap3xxx_mmc3_hwmod,
3206 &omap3xxx_mpu_hwmod,
3207 &omap3xxx_iva_hwmod,
3209 &omap3xxx_timer1_hwmod,
3210 &omap3xxx_timer2_hwmod,
3211 &omap3xxx_timer3_hwmod,
3212 &omap3xxx_timer4_hwmod,
3213 &omap3xxx_timer5_hwmod,
3214 &omap3xxx_timer6_hwmod,
3215 &omap3xxx_timer7_hwmod,
3216 &omap3xxx_timer8_hwmod,
3217 &omap3xxx_timer9_hwmod,
3218 &omap3xxx_timer10_hwmod,
3219 &omap3xxx_timer11_hwmod,
3220 &omap3xxx_timer12_hwmod,
3222 &omap3xxx_wd_timer2_hwmod,
3223 &omap3xxx_uart1_hwmod,
3224 &omap3xxx_uart2_hwmod,
3225 &omap3xxx_uart3_hwmod,
3226 &omap3xxx_uart4_hwmod,
3228 &omap3430es1_dss_core_hwmod,
3229 &omap3xxx_dss_core_hwmod,
3230 &omap3xxx_dss_dispc_hwmod,
3231 &omap3xxx_dss_dsi1_hwmod,
3232 &omap3xxx_dss_rfbi_hwmod,
3233 &omap3xxx_dss_venc_hwmod,
3236 &omap3xxx_i2c1_hwmod,
3237 &omap3xxx_i2c2_hwmod,
3238 &omap3xxx_i2c3_hwmod,
3239 &omap34xx_sr1_hwmod,
3240 &omap34xx_sr2_hwmod,
3241 &omap36xx_sr1_hwmod,
3242 &omap36xx_sr2_hwmod,
3246 &omap3xxx_gpio1_hwmod,
3247 &omap3xxx_gpio2_hwmod,
3248 &omap3xxx_gpio3_hwmod,
3249 &omap3xxx_gpio4_hwmod,
3250 &omap3xxx_gpio5_hwmod,
3251 &omap3xxx_gpio6_hwmod,
3253 /* dma_system class*/
3254 &omap3xxx_dma_system_hwmod,
3257 &omap3xxx_mcbsp1_hwmod,
3258 &omap3xxx_mcbsp2_hwmod,
3259 &omap3xxx_mcbsp3_hwmod,
3260 &omap3xxx_mcbsp4_hwmod,
3261 &omap3xxx_mcbsp5_hwmod,
3262 &omap3xxx_mcbsp2_sidetone_hwmod,
3263 &omap3xxx_mcbsp3_sidetone_hwmod,
3266 &omap3xxx_mailbox_hwmod,
3275 &omap3xxx_usbhsotg_hwmod,
3277 /* usbotg for am35x */
3278 &am35xx_usbhsotg_hwmod,
3283 int __init omap3xxx_hwmod_init(void)
3285 return omap_hwmod_register(omap3xxx_hwmods);