arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21
  22 #include "omap_hwmod_common_data.h"
  23
  24 #include "prm-regbits-34xx.h"
  25
  26 /*
  27  * OMAP3xxx hardware module integration data
  28  *
  29  * ALl of the data in this section should be autogeneratable from the
  30  * TI hardware database or other technical documentation.  Data that
  31  * is driver-specific or driver-kernel integration-specific belongs
  32  * elsewhere.
  33  */
  34
  35 static struct omap_hwmod omap3xxx_mpu_hwmod;
  36 static struct omap_hwmod omap3xxx_iva_hwmod;
  37 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  38 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  39 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  40
  41 /* L3 -> L4_CORE interface */
  42 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  43         .master = &omap3xxx_l3_main_hwmod,
  44         .slave  = &omap3xxx_l4_core_hwmod,
  45         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  46 };
  47
  48 /* L3 -> L4_PER interface */
  49 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  50         .master = &omap3xxx_l3_main_hwmod,
  51         .slave  = &omap3xxx_l4_per_hwmod,
  52         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  53 };
  54
  55 /* MPU -> L3 interface */
  56 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
  57         .master = &omap3xxx_mpu_hwmod,
  58         .slave  = &omap3xxx_l3_main_hwmod,
  59         .user   = OCP_USER_MPU,
  60 };
  61
  62 /* Slave interfaces on the L3 interconnect */
  63 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
  64         &omap3xxx_mpu__l3_main,
  65 };
  66
  67 /* Master interfaces on the L3 interconnect */
  68 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
  69         &omap3xxx_l3_main__l4_core,
  70         &omap3xxx_l3_main__l4_per,
  71 };
  72
  73 /* L3 */
  74 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  75         .name           = "l3_main",
  76         .class          = &l3_hwmod_class,
  77         .masters        = omap3xxx_l3_main_masters,
  78         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
  79         .slaves         = omap3xxx_l3_main_slaves,
  80         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
  81         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  82         .flags          = HWMOD_NO_IDLEST,
  83 };
  84
  85 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
  86 static struct omap_hwmod omap3xxx_uart1_hwmod;
  87 static struct omap_hwmod omap3xxx_uart2_hwmod;
  88 static struct omap_hwmod omap3xxx_uart3_hwmod;
  89 static struct omap_hwmod omap3xxx_uart4_hwmod;
  90
  91 /* L4_CORE -> L4_WKUP interface */
  92 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
  93         .master = &omap3xxx_l4_core_hwmod,
  94         .slave  = &omap3xxx_l4_wkup_hwmod,
  95         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  96 };
  97
  98 /* L4 CORE -> UART1 interface */
  99 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 100         {
 101                 .pa_start       = OMAP3_UART1_BASE,
 102                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 103                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 104         },
 105 };
 106
 107 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 108         .master         = &omap3xxx_l4_core_hwmod,
 109         .slave          = &omap3xxx_uart1_hwmod,
 110         .clk            = "uart1_ick",
 111         .addr           = omap3xxx_uart1_addr_space,
 112         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
 113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 114 };
 115
 116 /* L4 CORE -> UART2 interface */
 117 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 118         {
 119                 .pa_start       = OMAP3_UART2_BASE,
 120                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 121                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 122         },
 123 };
 124
 125 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 126         .master         = &omap3xxx_l4_core_hwmod,
 127         .slave          = &omap3xxx_uart2_hwmod,
 128         .clk            = "uart2_ick",
 129         .addr           = omap3xxx_uart2_addr_space,
 130         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
 131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 132 };
 133
 134 /* L4 PER -> UART3 interface */
 135 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 136         {
 137                 .pa_start       = OMAP3_UART3_BASE,
 138                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 139                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 140         },
 141 };
 142
 143 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 144         .master         = &omap3xxx_l4_per_hwmod,
 145         .slave          = &omap3xxx_uart3_hwmod,
 146         .clk            = "uart3_ick",
 147         .addr           = omap3xxx_uart3_addr_space,
 148         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
 149         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 150 };
 151
 152 /* L4 PER -> UART4 interface */
 153 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 154         {
 155                 .pa_start       = OMAP3_UART4_BASE,
 156                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 157                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 158         },
 159 };
 160
 161 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 162         .master         = &omap3xxx_l4_per_hwmod,
 163         .slave          = &omap3xxx_uart4_hwmod,
 164         .clk            = "uart4_ick",
 165         .addr           = omap3xxx_uart4_addr_space,
 166         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
 167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 168 };
 169
 170 /* Slave interfaces on the L4_CORE interconnect */
 171 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 172         &omap3xxx_l3_main__l4_core,
 173 };
 174
 175 /* Master interfaces on the L4_CORE interconnect */
 176 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 177         &omap3xxx_l4_core__l4_wkup,
 178         &omap3_l4_core__uart1,
 179         &omap3_l4_core__uart2,
 180 };
 181
 182 /* L4 CORE */
 183 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 184         .name           = "l4_core",
 185         .class          = &l4_hwmod_class,
 186         .masters        = omap3xxx_l4_core_masters,
 187         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
 188         .slaves         = omap3xxx_l4_core_slaves,
 189         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 190         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 191         .flags          = HWMOD_NO_IDLEST,
 192 };
 193
 194 /* Slave interfaces on the L4_PER interconnect */
 195 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 196         &omap3xxx_l3_main__l4_per,
 197 };
 198
 199 /* Master interfaces on the L4_PER interconnect */
 200 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
 201         &omap3_l4_per__uart3,
 202         &omap3_l4_per__uart4,
 203 };
 204
 205 /* L4 PER */
 206 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 207         .name           = "l4_per",
 208         .class          = &l4_hwmod_class,
 209         .masters        = omap3xxx_l4_per_masters,
 210         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
 211         .slaves         = omap3xxx_l4_per_slaves,
 212         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 213         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 214         .flags          = HWMOD_NO_IDLEST,
 215 };
 216
 217 /* Slave interfaces on the L4_WKUP interconnect */
 218 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 219         &omap3xxx_l4_core__l4_wkup,
 220 };
 221
 222 /* Master interfaces on the L4_WKUP interconnect */
 223 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
 224 };
 225
 226 /* L4 WKUP */
 227 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 228         .name           = "l4_wkup",
 229         .class          = &l4_hwmod_class,
 230         .masters        = omap3xxx_l4_wkup_masters,
 231         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
 232         .slaves         = omap3xxx_l4_wkup_slaves,
 233         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 234         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 235         .flags          = HWMOD_NO_IDLEST,
 236 };
 237
 238 /* Master interfaces on the MPU device */
 239 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 240         &omap3xxx_mpu__l3_main,
 241 };
 242
 243 /* MPU */
 244 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 245         .name           = "mpu",
 246         .class          = &mpu_hwmod_class,
 247         .main_clk       = "arm_fck",
 248         .masters        = omap3xxx_mpu_masters,
 249         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 250         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 251 };
 252
 253 /*
 254  * IVA2_2 interface data
 255  */
 256
 257 /* IVA2 <- L3 interface */
 258 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 259         .master         = &omap3xxx_l3_main_hwmod,
 260         .slave          = &omap3xxx_iva_hwmod,
 261         .clk            = "iva2_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 266         &omap3xxx_l3__iva,
 267 };
 268
 269 /*
 270  * IVA2 (IVA2)
 271  */
 272
 273 static struct omap_hwmod omap3xxx_iva_hwmod = {
 274         .name           = "iva",
 275         .class          = &iva_hwmod_class,
 276         .masters        = omap3xxx_iva_masters,
 277         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 278         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 279 };
 280
 281 /* UART common */
 282
 283 static struct omap_hwmod_class_sysconfig uart_sysc = {
 284         .rev_offs       = 0x50,
 285         .sysc_offs      = 0x54,
 286         .syss_offs      = 0x58,
 287         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 288                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 289                            SYSC_HAS_AUTOIDLE),
 290         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 291         .sysc_fields    = &omap_hwmod_sysc_type1,
 292 };
 293
 294 static struct omap_hwmod_class uart_class = {
 295         .name = "uart",
 296         .sysc = &uart_sysc,
 297 };
 298
 299 /* UART1 */
 300
 301 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 302         { .irq = INT_24XX_UART1_IRQ, },
 303 };
 304
 305 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 306         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 307         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 308 };
 309
 310 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
 311         &omap3_l4_core__uart1,
 312 };
 313
 314 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 315         .name           = "uart1",
 316         .mpu_irqs       = uart1_mpu_irqs,
 317         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 318         .sdma_reqs      = uart1_sdma_reqs,
 319         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 320         .main_clk       = "uart1_fck",
 321         .prcm           = {
 322                 .omap2 = {
 323                         .module_offs = CORE_MOD,
 324                         .prcm_reg_id = 1,
 325                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 326                         .idlest_reg_id = 1,
 327                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 328                 },
 329         },
 330         .slaves         = omap3xxx_uart1_slaves,
 331         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
 332         .class          = &uart_class,
 333         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 334 };
 335
 336 /* UART2 */
 337
 338 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 339         { .irq = INT_24XX_UART2_IRQ, },
 340 };
 341
 342 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 343         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 344         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 345 };
 346
 347 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
 348         &omap3_l4_core__uart2,
 349 };
 350
 351 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 352         .name           = "uart2",
 353         .mpu_irqs       = uart2_mpu_irqs,
 354         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 355         .sdma_reqs      = uart2_sdma_reqs,
 356         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 357         .main_clk       = "uart2_fck",
 358         .prcm           = {
 359                 .omap2 = {
 360                         .module_offs = CORE_MOD,
 361                         .prcm_reg_id = 1,
 362                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 363                         .idlest_reg_id = 1,
 364                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 365                 },
 366         },
 367         .slaves         = omap3xxx_uart2_slaves,
 368         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
 369         .class          = &uart_class,
 370         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 371 };
 372
 373 /* UART3 */
 374
 375 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 376         { .irq = INT_24XX_UART3_IRQ, },
 377 };
 378
 379 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 380         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 381         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 382 };
 383
 384 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
 385         &omap3_l4_per__uart3,
 386 };
 387
 388 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 389         .name           = "uart3",
 390         .mpu_irqs       = uart3_mpu_irqs,
 391         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 392         .sdma_reqs      = uart3_sdma_reqs,
 393         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 394         .main_clk       = "uart3_fck",
 395         .prcm           = {
 396                 .omap2 = {
 397                         .module_offs = OMAP3430_PER_MOD,
 398                         .prcm_reg_id = 1,
 399                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 400                         .idlest_reg_id = 1,
 401                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 402                 },
 403         },
 404         .slaves         = omap3xxx_uart3_slaves,
 405         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
 406         .class          = &uart_class,
 407         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 408 };
 409
 410 /* UART4 */
 411
 412 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 413         { .irq = INT_36XX_UART4_IRQ, },
 414 };
 415
 416 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 417         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 418         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 419 };
 420
 421 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
 422         &omap3_l4_per__uart4,
 423 };
 424
 425 static struct omap_hwmod omap3xxx_uart4_hwmod = {
 426         .name           = "uart4",
 427         .mpu_irqs       = uart4_mpu_irqs,
 428         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
 429         .sdma_reqs      = uart4_sdma_reqs,
 430         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
 431         .main_clk       = "uart4_fck",
 432         .prcm           = {
 433                 .omap2 = {
 434                         .module_offs = OMAP3430_PER_MOD,
 435                         .prcm_reg_id = 1,
 436                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 437                         .idlest_reg_id = 1,
 438                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 439                 },
 440         },
 441         .slaves         = omap3xxx_uart4_slaves,
 442         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
 443         .class          = &uart_class,
 444         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 445 };
 446
 447 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 448         &omap3xxx_l3_main_hwmod,
 449         &omap3xxx_l4_core_hwmod,
 450         &omap3xxx_l4_per_hwmod,
 451         &omap3xxx_l4_wkup_hwmod,
 452         &omap3xxx_mpu_hwmod,
 453         &omap3xxx_iva_hwmod,
 454         &omap3xxx_uart1_hwmod,
 455         &omap3xxx_uart2_hwmod,
 456         &omap3xxx_uart3_hwmod,
 457         &omap3xxx_uart4_hwmod,
 458         NULL,
 459 };
 460
 461 int __init omap3xxx_hwmod_init(void)
 462 {
 463         return omap_hwmod_init(omap3xxx_hwmods);
 464 }