arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l3_3xxx.h>
  22 #include <plat/l4_3xxx.h>
  23 #include <plat/i2c.h>
  24 #include <plat/gpio.h>
  25 #include <plat/mmc.h>
  26 #include <plat/mcbsp.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/dmtimer.h>
  29
  30 #include "omap_hwmod_common_data.h"
  31
  32 #include "prm-regbits-34xx.h"
  33 #include "cm-regbits-34xx.h"
  34 #include "wd_timer.h"
  35 #include <mach/am35xx.h>
  36
  37 /*
  38  * OMAP3xxx hardware module integration data
  39  *
  40  * ALl of the data in this section should be autogeneratable from the
  41  * TI hardware database or other technical documentation.  Data that
  42  * is driver-specific or driver-kernel integration-specific belongs
  43  * elsewhere.
  44  */
  45
  46 static struct omap_hwmod omap3xxx_mpu_hwmod;
  47 static struct omap_hwmod omap3xxx_iva_hwmod;
  48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
  53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
  54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
  55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
  56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
  57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
  58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  67 static struct omap_hwmod omap34xx_sr1_hwmod;
  68 static struct omap_hwmod omap34xx_sr2_hwmod;
  69 static struct omap_hwmod omap34xx_mcspi1;
  70 static struct omap_hwmod omap34xx_mcspi2;
  71 static struct omap_hwmod omap34xx_mcspi3;
  72 static struct omap_hwmod omap34xx_mcspi4;
  73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
  74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
  75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
  76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
  77
  78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  79
  80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
  81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
  82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
  83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
  84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
  85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
  86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
  87
  88 /* L3 -> L4_CORE interface */
  89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  90         .master = &omap3xxx_l3_main_hwmod,
  91         .slave  = &omap3xxx_l4_core_hwmod,
  92         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  93 };
  94
  95 /* L3 -> L4_PER interface */
  96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  97         .master = &omap3xxx_l3_main_hwmod,
  98         .slave  = &omap3xxx_l4_per_hwmod,
  99         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 100 };
 101
 102 /* L3 taret configuration and error log registers */
 103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
 104         { .irq = INT_34XX_L3_DBG_IRQ },
 105         { .irq = INT_34XX_L3_APP_IRQ },
 106         { .irq = -1 }
 107 };
 108
 109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
 110         {
 111                 .pa_start       = 0x68000000,
 112                 .pa_end         = 0x6800ffff,
 113                 .flags          = ADDR_TYPE_RT,
 114         },
 115         { }
 116 };
 117
 118 /* MPU -> L3 interface */
 119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
 120         .master   = &omap3xxx_mpu_hwmod,
 121         .slave    = &omap3xxx_l3_main_hwmod,
 122         .addr     = omap3xxx_l3_main_addrs,
 123         .user   = OCP_USER_MPU,
 124 };
 125
 126 /* Slave interfaces on the L3 interconnect */
 127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
 128         &omap3xxx_mpu__l3_main,
 129 };
 130
 131 /* DSS -> l3 */
 132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
 133         .master         = &omap3xxx_dss_core_hwmod,
 134         .slave          = &omap3xxx_l3_main_hwmod,
 135         .fw = {
 136                 .omap2 = {
 137                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
 138                         .flags  = OMAP_FIREWALL_L3,
 139                 }
 140         },
 141         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 142 };
 143
 144 /* Master interfaces on the L3 interconnect */
 145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 146         &omap3xxx_l3_main__l4_core,
 147         &omap3xxx_l3_main__l4_per,
 148 };
 149
 150 /* L3 */
 151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
 152         .name           = "l3_main",
 153         .class          = &l3_hwmod_class,
 154         .mpu_irqs       = omap3xxx_l3_main_irqs,
 155         .masters        = omap3xxx_l3_main_masters,
 156         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
 157         .slaves         = omap3xxx_l3_main_slaves,
 158         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
 159         .flags          = HWMOD_NO_IDLEST,
 160 };
 161
 162 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 163 static struct omap_hwmod omap3xxx_uart1_hwmod;
 164 static struct omap_hwmod omap3xxx_uart2_hwmod;
 165 static struct omap_hwmod omap3xxx_uart3_hwmod;
 166 static struct omap_hwmod omap3xxx_uart4_hwmod;
 167 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
 168
 169 /* l3_core -> usbhsotg interface */
 170 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 171         .master         = &omap3xxx_usbhsotg_hwmod,
 172         .slave          = &omap3xxx_l3_main_hwmod,
 173         .clk            = "core_l3_ick",
 174         .user           = OCP_USER_MPU,
 175 };
 176
 177 /* l3_core -> am35xx_usbhsotg interface */
 178 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
 179         .master         = &am35xx_usbhsotg_hwmod,
 180         .slave          = &omap3xxx_l3_main_hwmod,
 181         .clk            = "core_l3_ick",
 182         .user           = OCP_USER_MPU,
 183 };
 184 /* L4_CORE -> L4_WKUP interface */
 185 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 186         .master = &omap3xxx_l4_core_hwmod,
 187         .slave  = &omap3xxx_l4_wkup_hwmod,
 188         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 189 };
 190
 191 /* L4 CORE -> MMC1 interface */
 192 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
 193         .master         = &omap3xxx_l4_core_hwmod,
 194         .slave          = &omap3xxx_mmc1_hwmod,
 195         .clk            = "mmchs1_ick",
 196         .addr           = omap2430_mmc1_addr_space,
 197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 198         .flags          = OMAP_FIREWALL_L4
 199 };
 200
 201 /* L4 CORE -> MMC2 interface */
 202 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
 203         .master         = &omap3xxx_l4_core_hwmod,
 204         .slave          = &omap3xxx_mmc2_hwmod,
 205         .clk            = "mmchs2_ick",
 206         .addr           = omap2430_mmc2_addr_space,
 207         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 208         .flags          = OMAP_FIREWALL_L4
 209 };
 210
 211 /* L4 CORE -> MMC3 interface */
 212 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
 213         {
 214                 .pa_start       = 0x480ad000,
 215                 .pa_end         = 0x480ad1ff,
 216                 .flags          = ADDR_TYPE_RT,
 217         },
 218         { }
 219 };
 220
 221 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
 222         .master         = &omap3xxx_l4_core_hwmod,
 223         .slave          = &omap3xxx_mmc3_hwmod,
 224         .clk            = "mmchs3_ick",
 225         .addr           = omap3xxx_mmc3_addr_space,
 226         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 227         .flags          = OMAP_FIREWALL_L4
 228 };
 229
 230 /* L4 CORE -> UART1 interface */
 231 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 232         {
 233                 .pa_start       = OMAP3_UART1_BASE,
 234                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 235                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 236         },
 237         { }
 238 };
 239
 240 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 241         .master         = &omap3xxx_l4_core_hwmod,
 242         .slave          = &omap3xxx_uart1_hwmod,
 243         .clk            = "uart1_ick",
 244         .addr           = omap3xxx_uart1_addr_space,
 245         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 246 };
 247
 248 /* L4 CORE -> UART2 interface */
 249 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 250         {
 251                 .pa_start       = OMAP3_UART2_BASE,
 252                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 253                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 254         },
 255         { }
 256 };
 257
 258 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 259         .master         = &omap3xxx_l4_core_hwmod,
 260         .slave          = &omap3xxx_uart2_hwmod,
 261         .clk            = "uart2_ick",
 262         .addr           = omap3xxx_uart2_addr_space,
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* L4 PER -> UART3 interface */
 267 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 268         {
 269                 .pa_start       = OMAP3_UART3_BASE,
 270                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 271                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 272         },
 273         { }
 274 };
 275
 276 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 277         .master         = &omap3xxx_l4_per_hwmod,
 278         .slave          = &omap3xxx_uart3_hwmod,
 279         .clk            = "uart3_ick",
 280         .addr           = omap3xxx_uart3_addr_space,
 281         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 282 };
 283
 284 /* L4 PER -> UART4 interface */
 285 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 286         {
 287                 .pa_start       = OMAP3_UART4_BASE,
 288                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 289                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 290         },
 291         { }
 292 };
 293
 294 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 295         .master         = &omap3xxx_l4_per_hwmod,
 296         .slave          = &omap3xxx_uart4_hwmod,
 297         .clk            = "uart4_ick",
 298         .addr           = omap3xxx_uart4_addr_space,
 299         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 300 };
 301
 302 /* L4 CORE -> I2C1 interface */
 303 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 304         .master         = &omap3xxx_l4_core_hwmod,
 305         .slave          = &omap3xxx_i2c1_hwmod,
 306         .clk            = "i2c1_ick",
 307         .addr           = omap2_i2c1_addr_space,
 308         .fw = {
 309                 .omap2 = {
 310                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 311                         .l4_prot_group = 7,
 312                         .flags  = OMAP_FIREWALL_L4,
 313                 }
 314         },
 315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 316 };
 317
 318 /* L4 CORE -> I2C2 interface */
 319 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 320         .master         = &omap3xxx_l4_core_hwmod,
 321         .slave          = &omap3xxx_i2c2_hwmod,
 322         .clk            = "i2c2_ick",
 323         .addr           = omap2_i2c2_addr_space,
 324         .fw = {
 325                 .omap2 = {
 326                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 327                         .l4_prot_group = 7,
 328                         .flags = OMAP_FIREWALL_L4,
 329                 }
 330         },
 331         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 332 };
 333
 334 /* L4 CORE -> I2C3 interface */
 335 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 336         {
 337                 .pa_start       = 0x48060000,
 338                 .pa_end         = 0x48060000 + SZ_128 - 1,
 339                 .flags          = ADDR_TYPE_RT,
 340         },
 341         { }
 342 };
 343
 344 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 345         .master         = &omap3xxx_l4_core_hwmod,
 346         .slave          = &omap3xxx_i2c3_hwmod,
 347         .clk            = "i2c3_ick",
 348         .addr           = omap3xxx_i2c3_addr_space,
 349         .fw = {
 350                 .omap2 = {
 351                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 352                         .l4_prot_group = 7,
 353                         .flags = OMAP_FIREWALL_L4,
 354                 }
 355         },
 356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 357 };
 358
 359 /* L4 CORE -> SR1 interface */
 360 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
 361         {
 362                 .pa_start       = OMAP34XX_SR1_BASE,
 363                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
 364                 .flags          = ADDR_TYPE_RT,
 365         },
 366         { }
 367 };
 368
 369 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
 370         .master         = &omap3xxx_l4_core_hwmod,
 371         .slave          = &omap34xx_sr1_hwmod,
 372         .clk            = "sr_l4_ick",
 373         .addr           = omap3_sr1_addr_space,
 374         .user           = OCP_USER_MPU,
 375 };
 376
 377 /* L4 CORE -> SR1 interface */
 378 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
 379         {
 380                 .pa_start       = OMAP34XX_SR2_BASE,
 381                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
 382                 .flags          = ADDR_TYPE_RT,
 383         },
 384         { }
 385 };
 386
 387 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
 388         .master         = &omap3xxx_l4_core_hwmod,
 389         .slave          = &omap34xx_sr2_hwmod,
 390         .clk            = "sr_l4_ick",
 391         .addr           = omap3_sr2_addr_space,
 392         .user           = OCP_USER_MPU,
 393 };
 394
 395 /*
 396 * usbhsotg interface data
 397 */
 398
 399 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
 400         {
 401                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
 402                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
 403                 .flags          = ADDR_TYPE_RT
 404         },
 405         { }
 406 };
 407
 408 /* l4_core -> usbhsotg  */
 409 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
 410         .master         = &omap3xxx_l4_core_hwmod,
 411         .slave          = &omap3xxx_usbhsotg_hwmod,
 412         .clk            = "l4_ick",
 413         .addr           = omap3xxx_usbhsotg_addrs,
 414         .user           = OCP_USER_MPU,
 415 };
 416
 417 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
 418         &omap3xxx_usbhsotg__l3,
 419 };
 420
 421 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
 422         &omap3xxx_l4_core__usbhsotg,
 423 };
 424
 425 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 426         {
 427                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
 428                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
 429                 .flags          = ADDR_TYPE_RT
 430         },
 431         { }
 432 };
 433
 434 /* l4_core -> usbhsotg  */
 435 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
 436         .master         = &omap3xxx_l4_core_hwmod,
 437         .slave          = &am35xx_usbhsotg_hwmod,
 438         .clk            = "l4_ick",
 439         .addr           = am35xx_usbhsotg_addrs,
 440         .user           = OCP_USER_MPU,
 441 };
 442
 443 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
 444         &am35xx_usbhsotg__l3,
 445 };
 446
 447 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 448         &am35xx_l4_core__usbhsotg,
 449 };
 450 /* Slave interfaces on the L4_CORE interconnect */
 451 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 452         &omap3xxx_l3_main__l4_core,
 453 };
 454
 455 /* L4 CORE */
 456 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 457         .name           = "l4_core",
 458         .class          = &l4_hwmod_class,
 459         .slaves         = omap3xxx_l4_core_slaves,
 460         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 461         .flags          = HWMOD_NO_IDLEST,
 462 };
 463
 464 /* Slave interfaces on the L4_PER interconnect */
 465 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 466         &omap3xxx_l3_main__l4_per,
 467 };
 468
 469 /* L4 PER */
 470 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 471         .name           = "l4_per",
 472         .class          = &l4_hwmod_class,
 473         .slaves         = omap3xxx_l4_per_slaves,
 474         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 475         .flags          = HWMOD_NO_IDLEST,
 476 };
 477
 478 /* Slave interfaces on the L4_WKUP interconnect */
 479 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 480         &omap3xxx_l4_core__l4_wkup,
 481 };
 482
 483 /* L4 WKUP */
 484 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 485         .name           = "l4_wkup",
 486         .class          = &l4_hwmod_class,
 487         .slaves         = omap3xxx_l4_wkup_slaves,
 488         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 489         .flags          = HWMOD_NO_IDLEST,
 490 };
 491
 492 /* Master interfaces on the MPU device */
 493 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 494         &omap3xxx_mpu__l3_main,
 495 };
 496
 497 /* MPU */
 498 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 499         .name           = "mpu",
 500         .class          = &mpu_hwmod_class,
 501         .main_clk       = "arm_fck",
 502         .masters        = omap3xxx_mpu_masters,
 503         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 504 };
 505
 506 /*
 507  * IVA2_2 interface data
 508  */
 509
 510 /* IVA2 <- L3 interface */
 511 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 512         .master         = &omap3xxx_l3_main_hwmod,
 513         .slave          = &omap3xxx_iva_hwmod,
 514         .clk            = "iva2_ck",
 515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 516 };
 517
 518 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 519         &omap3xxx_l3__iva,
 520 };
 521
 522 /*
 523  * IVA2 (IVA2)
 524  */
 525
 526 static struct omap_hwmod omap3xxx_iva_hwmod = {
 527         .name           = "iva",
 528         .class          = &iva_hwmod_class,
 529         .masters        = omap3xxx_iva_masters,
 530         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 531 };
 532
 533 /* timer class */
 534 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 535         .rev_offs       = 0x0000,
 536         .sysc_offs      = 0x0010,
 537         .syss_offs      = 0x0014,
 538         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 539                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 540                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 542         .sysc_fields    = &omap_hwmod_sysc_type1,
 543 };
 544
 545 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 546         .name = "timer",
 547         .sysc = &omap3xxx_timer_1ms_sysc,
 548         .rev = OMAP_TIMER_IP_VERSION_1,
 549 };
 550
 551 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 552         .rev_offs       = 0x0000,
 553         .sysc_offs      = 0x0010,
 554         .syss_offs      = 0x0014,
 555         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 556                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 557         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 558         .sysc_fields    = &omap_hwmod_sysc_type1,
 559 };
 560
 561 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 562         .name = "timer",
 563         .sysc = &omap3xxx_timer_sysc,
 564         .rev =  OMAP_TIMER_IP_VERSION_1,
 565 };
 566
 567 /* secure timers dev attribute */
 568 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 569         .timer_capability       = OMAP_TIMER_SECURE,
 570 };
 571
 572 /* always-on timers dev attribute */
 573 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 574         .timer_capability       = OMAP_TIMER_ALWON,
 575 };
 576
 577 /* pwm timers dev attribute */
 578 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 579         .timer_capability       = OMAP_TIMER_HAS_PWM,
 580 };
 581
 582 /* timer1 */
 583 static struct omap_hwmod omap3xxx_timer1_hwmod;
 584
 585 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
 586         {
 587                 .pa_start       = 0x48318000,
 588                 .pa_end         = 0x48318000 + SZ_1K - 1,
 589                 .flags          = ADDR_TYPE_RT
 590         },
 591         { }
 592 };
 593
 594 /* l4_wkup -> timer1 */
 595 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
 596         .master         = &omap3xxx_l4_wkup_hwmod,
 597         .slave          = &omap3xxx_timer1_hwmod,
 598         .clk            = "gpt1_ick",
 599         .addr           = omap3xxx_timer1_addrs,
 600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 601 };
 602
 603 /* timer1 slave port */
 604 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
 605         &omap3xxx_l4_wkup__timer1,
 606 };
 607
 608 /* timer1 hwmod */
 609 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 610         .name           = "timer1",
 611         .mpu_irqs       = omap2_timer1_mpu_irqs,
 612         .main_clk       = "gpt1_fck",
 613         .prcm           = {
 614                 .omap2 = {
 615                         .prcm_reg_id = 1,
 616                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 617                         .module_offs = WKUP_MOD,
 618                         .idlest_reg_id = 1,
 619                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 620                 },
 621         },
 622         .dev_attr       = &capability_alwon_dev_attr,
 623         .slaves         = omap3xxx_timer1_slaves,
 624         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
 625         .class          = &omap3xxx_timer_1ms_hwmod_class,
 626 };
 627
 628 /* timer2 */
 629 static struct omap_hwmod omap3xxx_timer2_hwmod;
 630
 631 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
 632         {
 633                 .pa_start       = 0x49032000,
 634                 .pa_end         = 0x49032000 + SZ_1K - 1,
 635                 .flags          = ADDR_TYPE_RT
 636         },
 637         { }
 638 };
 639
 640 /* l4_per -> timer2 */
 641 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
 642         .master         = &omap3xxx_l4_per_hwmod,
 643         .slave          = &omap3xxx_timer2_hwmod,
 644         .clk            = "gpt2_ick",
 645         .addr           = omap3xxx_timer2_addrs,
 646         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 647 };
 648
 649 /* timer2 slave port */
 650 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
 651         &omap3xxx_l4_per__timer2,
 652 };
 653
 654 /* timer2 hwmod */
 655 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 656         .name           = "timer2",
 657         .mpu_irqs       = omap2_timer2_mpu_irqs,
 658         .main_clk       = "gpt2_fck",
 659         .prcm           = {
 660                 .omap2 = {
 661                         .prcm_reg_id = 1,
 662                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 663                         .module_offs = OMAP3430_PER_MOD,
 664                         .idlest_reg_id = 1,
 665                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 666                 },
 667         },
 668         .dev_attr       = &capability_alwon_dev_attr,
 669         .slaves         = omap3xxx_timer2_slaves,
 670         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
 671         .class          = &omap3xxx_timer_1ms_hwmod_class,
 672 };
 673
 674 /* timer3 */
 675 static struct omap_hwmod omap3xxx_timer3_hwmod;
 676
 677 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
 678         {
 679                 .pa_start       = 0x49034000,
 680                 .pa_end         = 0x49034000 + SZ_1K - 1,
 681                 .flags          = ADDR_TYPE_RT
 682         },
 683         { }
 684 };
 685
 686 /* l4_per -> timer3 */
 687 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
 688         .master         = &omap3xxx_l4_per_hwmod,
 689         .slave          = &omap3xxx_timer3_hwmod,
 690         .clk            = "gpt3_ick",
 691         .addr           = omap3xxx_timer3_addrs,
 692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 693 };
 694
 695 /* timer3 slave port */
 696 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
 697         &omap3xxx_l4_per__timer3,
 698 };
 699
 700 /* timer3 hwmod */
 701 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 702         .name           = "timer3",
 703         .mpu_irqs       = omap2_timer3_mpu_irqs,
 704         .main_clk       = "gpt3_fck",
 705         .prcm           = {
 706                 .omap2 = {
 707                         .prcm_reg_id = 1,
 708                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 709                         .module_offs = OMAP3430_PER_MOD,
 710                         .idlest_reg_id = 1,
 711                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 712                 },
 713         },
 714         .dev_attr       = &capability_alwon_dev_attr,
 715         .slaves         = omap3xxx_timer3_slaves,
 716         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
 717         .class          = &omap3xxx_timer_hwmod_class,
 718 };
 719
 720 /* timer4 */
 721 static struct omap_hwmod omap3xxx_timer4_hwmod;
 722
 723 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
 724         {
 725                 .pa_start       = 0x49036000,
 726                 .pa_end         = 0x49036000 + SZ_1K - 1,
 727                 .flags          = ADDR_TYPE_RT
 728         },
 729         { }
 730 };
 731
 732 /* l4_per -> timer4 */
 733 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
 734         .master         = &omap3xxx_l4_per_hwmod,
 735         .slave          = &omap3xxx_timer4_hwmod,
 736         .clk            = "gpt4_ick",
 737         .addr           = omap3xxx_timer4_addrs,
 738         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 739 };
 740
 741 /* timer4 slave port */
 742 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
 743         &omap3xxx_l4_per__timer4,
 744 };
 745
 746 /* timer4 hwmod */
 747 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 748         .name           = "timer4",
 749         .mpu_irqs       = omap2_timer4_mpu_irqs,
 750         .main_clk       = "gpt4_fck",
 751         .prcm           = {
 752                 .omap2 = {
 753                         .prcm_reg_id = 1,
 754                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 755                         .module_offs = OMAP3430_PER_MOD,
 756                         .idlest_reg_id = 1,
 757                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 758                 },
 759         },
 760         .dev_attr       = &capability_alwon_dev_attr,
 761         .slaves         = omap3xxx_timer4_slaves,
 762         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
 763         .class          = &omap3xxx_timer_hwmod_class,
 764 };
 765
 766 /* timer5 */
 767 static struct omap_hwmod omap3xxx_timer5_hwmod;
 768
 769 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
 770         {
 771                 .pa_start       = 0x49038000,
 772                 .pa_end         = 0x49038000 + SZ_1K - 1,
 773                 .flags          = ADDR_TYPE_RT
 774         },
 775         { }
 776 };
 777
 778 /* l4_per -> timer5 */
 779 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
 780         .master         = &omap3xxx_l4_per_hwmod,
 781         .slave          = &omap3xxx_timer5_hwmod,
 782         .clk            = "gpt5_ick",
 783         .addr           = omap3xxx_timer5_addrs,
 784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 785 };
 786
 787 /* timer5 slave port */
 788 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
 789         &omap3xxx_l4_per__timer5,
 790 };
 791
 792 /* timer5 hwmod */
 793 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 794         .name           = "timer5",
 795         .mpu_irqs       = omap2_timer5_mpu_irqs,
 796         .main_clk       = "gpt5_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 801                         .module_offs = OMAP3430_PER_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 804                 },
 805         },
 806         .dev_attr       = &capability_alwon_dev_attr,
 807         .slaves         = omap3xxx_timer5_slaves,
 808         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
 809         .class          = &omap3xxx_timer_hwmod_class,
 810 };
 811
 812 /* timer6 */
 813 static struct omap_hwmod omap3xxx_timer6_hwmod;
 814
 815 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
 816         {
 817                 .pa_start       = 0x4903A000,
 818                 .pa_end         = 0x4903A000 + SZ_1K - 1,
 819                 .flags          = ADDR_TYPE_RT
 820         },
 821         { }
 822 };
 823
 824 /* l4_per -> timer6 */
 825 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
 826         .master         = &omap3xxx_l4_per_hwmod,
 827         .slave          = &omap3xxx_timer6_hwmod,
 828         .clk            = "gpt6_ick",
 829         .addr           = omap3xxx_timer6_addrs,
 830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 831 };
 832
 833 /* timer6 slave port */
 834 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
 835         &omap3xxx_l4_per__timer6,
 836 };
 837
 838 /* timer6 hwmod */
 839 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 840         .name           = "timer6",
 841         .mpu_irqs       = omap2_timer6_mpu_irqs,
 842         .main_clk       = "gpt6_fck",
 843         .prcm           = {
 844                 .omap2 = {
 845                         .prcm_reg_id = 1,
 846                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 847                         .module_offs = OMAP3430_PER_MOD,
 848                         .idlest_reg_id = 1,
 849                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 850                 },
 851         },
 852         .dev_attr       = &capability_alwon_dev_attr,
 853         .slaves         = omap3xxx_timer6_slaves,
 854         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
 855         .class          = &omap3xxx_timer_hwmod_class,
 856 };
 857
 858 /* timer7 */
 859 static struct omap_hwmod omap3xxx_timer7_hwmod;
 860
 861 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
 862         {
 863                 .pa_start       = 0x4903C000,
 864                 .pa_end         = 0x4903C000 + SZ_1K - 1,
 865                 .flags          = ADDR_TYPE_RT
 866         },
 867         { }
 868 };
 869
 870 /* l4_per -> timer7 */
 871 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
 872         .master         = &omap3xxx_l4_per_hwmod,
 873         .slave          = &omap3xxx_timer7_hwmod,
 874         .clk            = "gpt7_ick",
 875         .addr           = omap3xxx_timer7_addrs,
 876         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 877 };
 878
 879 /* timer7 slave port */
 880 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
 881         &omap3xxx_l4_per__timer7,
 882 };
 883
 884 /* timer7 hwmod */
 885 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 886         .name           = "timer7",
 887         .mpu_irqs       = omap2_timer7_mpu_irqs,
 888         .main_clk       = "gpt7_fck",
 889         .prcm           = {
 890                 .omap2 = {
 891                         .prcm_reg_id = 1,
 892                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 893                         .module_offs = OMAP3430_PER_MOD,
 894                         .idlest_reg_id = 1,
 895                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 896                 },
 897         },
 898         .dev_attr       = &capability_alwon_dev_attr,
 899         .slaves         = omap3xxx_timer7_slaves,
 900         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
 901         .class          = &omap3xxx_timer_hwmod_class,
 902 };
 903
 904 /* timer8 */
 905 static struct omap_hwmod omap3xxx_timer8_hwmod;
 906
 907 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
 908         {
 909                 .pa_start       = 0x4903E000,
 910                 .pa_end         = 0x4903E000 + SZ_1K - 1,
 911                 .flags          = ADDR_TYPE_RT
 912         },
 913         { }
 914 };
 915
 916 /* l4_per -> timer8 */
 917 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
 918         .master         = &omap3xxx_l4_per_hwmod,
 919         .slave          = &omap3xxx_timer8_hwmod,
 920         .clk            = "gpt8_ick",
 921         .addr           = omap3xxx_timer8_addrs,
 922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 923 };
 924
 925 /* timer8 slave port */
 926 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
 927         &omap3xxx_l4_per__timer8,
 928 };
 929
 930 /* timer8 hwmod */
 931 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 932         .name           = "timer8",
 933         .mpu_irqs       = omap2_timer8_mpu_irqs,
 934         .main_clk       = "gpt8_fck",
 935         .prcm           = {
 936                 .omap2 = {
 937                         .prcm_reg_id = 1,
 938                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 939                         .module_offs = OMAP3430_PER_MOD,
 940                         .idlest_reg_id = 1,
 941                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 942                 },
 943         },
 944         .dev_attr       = &capability_pwm_dev_attr,
 945         .slaves         = omap3xxx_timer8_slaves,
 946         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
 947         .class          = &omap3xxx_timer_hwmod_class,
 948 };
 949
 950 /* timer9 */
 951 static struct omap_hwmod omap3xxx_timer9_hwmod;
 952
 953 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
 954         {
 955                 .pa_start       = 0x49040000,
 956                 .pa_end         = 0x49040000 + SZ_1K - 1,
 957                 .flags          = ADDR_TYPE_RT
 958         },
 959         { }
 960 };
 961
 962 /* l4_per -> timer9 */
 963 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
 964         .master         = &omap3xxx_l4_per_hwmod,
 965         .slave          = &omap3xxx_timer9_hwmod,
 966         .clk            = "gpt9_ick",
 967         .addr           = omap3xxx_timer9_addrs,
 968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 969 };
 970
 971 /* timer9 slave port */
 972 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
 973         &omap3xxx_l4_per__timer9,
 974 };
 975
 976 /* timer9 hwmod */
 977 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 978         .name           = "timer9",
 979         .mpu_irqs       = omap2_timer9_mpu_irqs,
 980         .main_clk       = "gpt9_fck",
 981         .prcm           = {
 982                 .omap2 = {
 983                         .prcm_reg_id = 1,
 984                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 985                         .module_offs = OMAP3430_PER_MOD,
 986                         .idlest_reg_id = 1,
 987                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 988                 },
 989         },
 990         .dev_attr       = &capability_pwm_dev_attr,
 991         .slaves         = omap3xxx_timer9_slaves,
 992         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
 993         .class          = &omap3xxx_timer_hwmod_class,
 994 };
 995
 996 /* timer10 */
 997 static struct omap_hwmod omap3xxx_timer10_hwmod;
 998
 999 /* l4_core -> timer10 */
1000 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
1001         .master         = &omap3xxx_l4_core_hwmod,
1002         .slave          = &omap3xxx_timer10_hwmod,
1003         .clk            = "gpt10_ick",
1004         .addr           = omap2_timer10_addrs,
1005         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1006 };
1007
1008 /* timer10 slave port */
1009 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1010         &omap3xxx_l4_core__timer10,
1011 };
1012
1013 /* timer10 hwmod */
1014 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1015         .name           = "timer10",
1016         .mpu_irqs       = omap2_timer10_mpu_irqs,
1017         .main_clk       = "gpt10_fck",
1018         .prcm           = {
1019                 .omap2 = {
1020                         .prcm_reg_id = 1,
1021                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
1022                         .module_offs = CORE_MOD,
1023                         .idlest_reg_id = 1,
1024                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1025                 },
1026         },
1027         .dev_attr       = &capability_pwm_dev_attr,
1028         .slaves         = omap3xxx_timer10_slaves,
1029         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
1030         .class          = &omap3xxx_timer_1ms_hwmod_class,
1031 };
1032
1033 /* timer11 */
1034 static struct omap_hwmod omap3xxx_timer11_hwmod;
1035
1036 /* l4_core -> timer11 */
1037 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1038         .master         = &omap3xxx_l4_core_hwmod,
1039         .slave          = &omap3xxx_timer11_hwmod,
1040         .clk            = "gpt11_ick",
1041         .addr           = omap2_timer11_addrs,
1042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1043 };
1044
1045 /* timer11 slave port */
1046 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1047         &omap3xxx_l4_core__timer11,
1048 };
1049
1050 /* timer11 hwmod */
1051 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1052         .name           = "timer11",
1053         .mpu_irqs       = omap2_timer11_mpu_irqs,
1054         .main_clk       = "gpt11_fck",
1055         .prcm           = {
1056                 .omap2 = {
1057                         .prcm_reg_id = 1,
1058                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
1059                         .module_offs = CORE_MOD,
1060                         .idlest_reg_id = 1,
1061                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1062                 },
1063         },
1064         .dev_attr       = &capability_pwm_dev_attr,
1065         .slaves         = omap3xxx_timer11_slaves,
1066         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
1067         .class          = &omap3xxx_timer_hwmod_class,
1068 };
1069
1070 /* timer12*/
1071 static struct omap_hwmod omap3xxx_timer12_hwmod;
1072 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1073         { .irq = 95, },
1074         { .irq = -1 }
1075 };
1076
1077 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1078         {
1079                 .pa_start       = 0x48304000,
1080                 .pa_end         = 0x48304000 + SZ_1K - 1,
1081                 .flags          = ADDR_TYPE_RT
1082         },
1083         { }
1084 };
1085
1086 /* l4_core -> timer12 */
1087 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1088         .master         = &omap3xxx_l4_core_hwmod,
1089         .slave          = &omap3xxx_timer12_hwmod,
1090         .clk            = "gpt12_ick",
1091         .addr           = omap3xxx_timer12_addrs,
1092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1093 };
1094
1095 /* timer12 slave port */
1096 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1097         &omap3xxx_l4_core__timer12,
1098 };
1099
1100 /* timer12 hwmod */
1101 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1102         .name           = "timer12",
1103         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
1104         .main_clk       = "gpt12_fck",
1105         .prcm           = {
1106                 .omap2 = {
1107                         .prcm_reg_id = 1,
1108                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
1109                         .module_offs = WKUP_MOD,
1110                         .idlest_reg_id = 1,
1111                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1112                 },
1113         },
1114         .dev_attr       = &capability_secure_dev_attr,
1115         .slaves         = omap3xxx_timer12_slaves,
1116         .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
1117         .class          = &omap3xxx_timer_hwmod_class,
1118 };
1119
1120 /* l4_wkup -> wd_timer2 */
1121 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1122         {
1123                 .pa_start       = 0x48314000,
1124                 .pa_end         = 0x4831407f,
1125                 .flags          = ADDR_TYPE_RT
1126         },
1127         { }
1128 };
1129
1130 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1131         .master         = &omap3xxx_l4_wkup_hwmod,
1132         .slave          = &omap3xxx_wd_timer2_hwmod,
1133         .clk            = "wdt2_ick",
1134         .addr           = omap3xxx_wd_timer2_addrs,
1135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1136 };
1137
1138 /*
1139  * 'wd_timer' class
1140  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1141  * overflow condition
1142  */
1143
1144 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1145         .rev_offs       = 0x0000,
1146         .sysc_offs      = 0x0010,
1147         .syss_offs      = 0x0014,
1148         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1149                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1150                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1151                            SYSS_HAS_RESET_STATUS),
1152         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1153         .sysc_fields    = &omap_hwmod_sysc_type1,
1154 };
1155
1156 /* I2C common */
1157 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1158         .rev_offs       = 0x00,
1159         .sysc_offs      = 0x20,
1160         .syss_offs      = 0x10,
1161         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1162                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1163                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1164         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1165         .sysc_fields    = &omap_hwmod_sysc_type1,
1166 };
1167
1168 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1169         .name           = "wd_timer",
1170         .sysc           = &omap3xxx_wd_timer_sysc,
1171         .pre_shutdown   = &omap2_wd_timer_disable
1172 };
1173
1174 /* wd_timer2 */
1175 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1176         &omap3xxx_l4_wkup__wd_timer2,
1177 };
1178
1179 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1180         .name           = "wd_timer2",
1181         .class          = &omap3xxx_wd_timer_hwmod_class,
1182         .main_clk       = "wdt2_fck",
1183         .prcm           = {
1184                 .omap2 = {
1185                         .prcm_reg_id = 1,
1186                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
1187                         .module_offs = WKUP_MOD,
1188                         .idlest_reg_id = 1,
1189                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1190                 },
1191         },
1192         .slaves         = omap3xxx_wd_timer2_slaves,
1193         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1194         /*
1195          * XXX: Use software supervised mode, HW supervised smartidle seems to
1196          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1197          */
1198         .flags          = HWMOD_SWSUP_SIDLE,
1199 };
1200
1201 /* UART1 */
1202
1203 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1204         &omap3_l4_core__uart1,
1205 };
1206
1207 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1208         .name           = "uart1",
1209         .mpu_irqs       = omap2_uart1_mpu_irqs,
1210         .sdma_reqs      = omap2_uart1_sdma_reqs,
1211         .main_clk       = "uart1_fck",
1212         .prcm           = {
1213                 .omap2 = {
1214                         .module_offs = CORE_MOD,
1215                         .prcm_reg_id = 1,
1216                         .module_bit = OMAP3430_EN_UART1_SHIFT,
1217                         .idlest_reg_id = 1,
1218                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1219                 },
1220         },
1221         .slaves         = omap3xxx_uart1_slaves,
1222         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
1223         .class          = &omap2_uart_class,
1224 };
1225
1226 /* UART2 */
1227
1228 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1229         &omap3_l4_core__uart2,
1230 };
1231
1232 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1233         .name           = "uart2",
1234         .mpu_irqs       = omap2_uart2_mpu_irqs,
1235         .sdma_reqs      = omap2_uart2_sdma_reqs,
1236         .main_clk       = "uart2_fck",
1237         .prcm           = {
1238                 .omap2 = {
1239                         .module_offs = CORE_MOD,
1240                         .prcm_reg_id = 1,
1241                         .module_bit = OMAP3430_EN_UART2_SHIFT,
1242                         .idlest_reg_id = 1,
1243                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1244                 },
1245         },
1246         .slaves         = omap3xxx_uart2_slaves,
1247         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
1248         .class          = &omap2_uart_class,
1249 };
1250
1251 /* UART3 */
1252
1253 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1254         &omap3_l4_per__uart3,
1255 };
1256
1257 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1258         .name           = "uart3",
1259         .mpu_irqs       = omap2_uart3_mpu_irqs,
1260         .sdma_reqs      = omap2_uart3_sdma_reqs,
1261         .main_clk       = "uart3_fck",
1262         .prcm           = {
1263                 .omap2 = {
1264                         .module_offs = OMAP3430_PER_MOD,
1265                         .prcm_reg_id = 1,
1266                         .module_bit = OMAP3430_EN_UART3_SHIFT,
1267                         .idlest_reg_id = 1,
1268                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1269                 },
1270         },
1271         .slaves         = omap3xxx_uart3_slaves,
1272         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
1273         .class          = &omap2_uart_class,
1274 };
1275
1276 /* UART4 */
1277
1278 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1279         { .irq = INT_36XX_UART4_IRQ, },
1280         { .irq = -1 }
1281 };
1282
1283 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1284         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1285         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1286         { .dma_req = -1 }
1287 };
1288
1289 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1290         &omap3_l4_per__uart4,
1291 };
1292
1293 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1294         .name           = "uart4",
1295         .mpu_irqs       = uart4_mpu_irqs,
1296         .sdma_reqs      = uart4_sdma_reqs,
1297         .main_clk       = "uart4_fck",
1298         .prcm           = {
1299                 .omap2 = {
1300                         .module_offs = OMAP3430_PER_MOD,
1301                         .prcm_reg_id = 1,
1302                         .module_bit = OMAP3630_EN_UART4_SHIFT,
1303                         .idlest_reg_id = 1,
1304                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1305                 },
1306         },
1307         .slaves         = omap3xxx_uart4_slaves,
1308         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
1309         .class          = &omap2_uart_class,
1310 };
1311
1312 static struct omap_hwmod_class i2c_class = {
1313         .name   = "i2c",
1314         .sysc   = &i2c_sysc,
1315         .rev    = OMAP_I2C_IP_VERSION_1,
1316         .reset  = &omap_i2c_reset,
1317 };
1318
1319 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1320         { .name = "dispc", .dma_req = 5 },
1321         { .name = "dsi1", .dma_req = 74 },
1322         { .dma_req = -1 }
1323 };
1324
1325 /* dss */
1326 /* dss master ports */
1327 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1328         &omap3xxx_dss__l3,
1329 };
1330
1331 /* l4_core -> dss */
1332 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1333         .master         = &omap3xxx_l4_core_hwmod,
1334         .slave          = &omap3430es1_dss_core_hwmod,
1335         .clk            = "dss_ick",
1336         .addr           = omap2_dss_addrs,
1337         .fw = {
1338                 .omap2 = {
1339                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1340                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1341                         .flags  = OMAP_FIREWALL_L4,
1342                 }
1343         },
1344         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1345 };
1346
1347 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1348         .master         = &omap3xxx_l4_core_hwmod,
1349         .slave          = &omap3xxx_dss_core_hwmod,
1350         .clk            = "dss_ick",
1351         .addr           = omap2_dss_addrs,
1352         .fw = {
1353                 .omap2 = {
1354                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1355                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1356                         .flags  = OMAP_FIREWALL_L4,
1357                 }
1358         },
1359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1360 };
1361
1362 /* dss slave ports */
1363 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1364         &omap3430es1_l4_core__dss,
1365 };
1366
1367 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1368         &omap3xxx_l4_core__dss,
1369 };
1370
1371 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1372         /*
1373          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
1374          * driver does not use these clocks.
1375          */
1376         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1377         { .role = "tv_clk", .clk = "dss_tv_fck" },
1378         /* required only on OMAP3430 */
1379         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1380 };
1381
1382 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1383         .name           = "dss_core",
1384         .class          = &omap2_dss_hwmod_class,
1385         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1386         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1387         .prcm           = {
1388                 .omap2 = {
1389                         .prcm_reg_id = 1,
1390                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1391                         .module_offs = OMAP3430_DSS_MOD,
1392                         .idlest_reg_id = 1,
1393                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1394                 },
1395         },
1396         .opt_clks       = dss_opt_clks,
1397         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1398         .slaves         = omap3430es1_dss_slaves,
1399         .slaves_cnt     = ARRAY_SIZE(omap3430es1_dss_slaves),
1400         .masters        = omap3xxx_dss_masters,
1401         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1402         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1403 };
1404
1405 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1406         .name           = "dss_core",
1407         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1408         .class          = &omap2_dss_hwmod_class,
1409         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
1410         .sdma_reqs      = omap3xxx_dss_sdma_chs,
1411         .prcm           = {
1412                 .omap2 = {
1413                         .prcm_reg_id = 1,
1414                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1415                         .module_offs = OMAP3430_DSS_MOD,
1416                         .idlest_reg_id = 1,
1417                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1418                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1419                 },
1420         },
1421         .opt_clks       = dss_opt_clks,
1422         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1423         .slaves         = omap3xxx_dss_slaves,
1424         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_slaves),
1425         .masters        = omap3xxx_dss_masters,
1426         .masters_cnt    = ARRAY_SIZE(omap3xxx_dss_masters),
1427 };
1428
1429 /* l4_core -> dss_dispc */
1430 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1431         .master         = &omap3xxx_l4_core_hwmod,
1432         .slave          = &omap3xxx_dss_dispc_hwmod,
1433         .clk            = "dss_ick",
1434         .addr           = omap2_dss_dispc_addrs,
1435         .fw = {
1436                 .omap2 = {
1437                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1438                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1439                         .flags  = OMAP_FIREWALL_L4,
1440                 }
1441         },
1442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1443 };
1444
1445 /* dss_dispc slave ports */
1446 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1447         &omap3xxx_l4_core__dss_dispc,
1448 };
1449
1450 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1451         .name           = "dss_dispc",
1452         .class          = &omap2_dispc_hwmod_class,
1453         .mpu_irqs       = omap2_dispc_irqs,
1454         .main_clk       = "dss1_alwon_fck",
1455         .prcm           = {
1456                 .omap2 = {
1457                         .prcm_reg_id = 1,
1458                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1459                         .module_offs = OMAP3430_DSS_MOD,
1460                 },
1461         },
1462         .slaves         = omap3xxx_dss_dispc_slaves,
1463         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1464         .flags          = HWMOD_NO_IDLEST,
1465         .dev_attr       = &omap2_3_dss_dispc_dev_attr
1466 };
1467
1468 /*
1469  * 'dsi' class
1470  * display serial interface controller
1471  */
1472
1473 static struct omap_hwmod_class_sysconfig omap3xxx_dsi_sysc = {
1474         .rev_offs       = 0x0000,
1475         .sysc_offs      = 0x0010,
1476         .syss_offs      = 0x0014,
1477         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1478                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1479                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1480         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1481         .sysc_fields    = &omap_hwmod_sysc_type1,
1482 };
1483
1484 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1485         .name = "dsi",
1486         .sysc   = &omap3xxx_dsi_sysc,
1487 };
1488
1489 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1490         { .irq = 25 },
1491         { .irq = -1 }
1492 };
1493
1494 /* dss_dsi1 */
1495 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1496         {
1497                 .pa_start       = 0x4804FC00,
1498                 .pa_end         = 0x4804FFFF,
1499                 .flags          = ADDR_TYPE_RT
1500         },
1501         { }
1502 };
1503
1504 /* l4_core -> dss_dsi1 */
1505 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1506         .master         = &omap3xxx_l4_core_hwmod,
1507         .slave          = &omap3xxx_dss_dsi1_hwmod,
1508         .clk            = "dss_ick",
1509         .addr           = omap3xxx_dss_dsi1_addrs,
1510         .fw = {
1511                 .omap2 = {
1512                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1513                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1514                         .flags  = OMAP_FIREWALL_L4,
1515                 }
1516         },
1517         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1518 };
1519
1520 /* dss_dsi1 slave ports */
1521 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1522         &omap3xxx_l4_core__dss_dsi1,
1523 };
1524
1525 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1526         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1527 };
1528
1529 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1530         .name           = "dss_dsi1",
1531         .class          = &omap3xxx_dsi_hwmod_class,
1532         .mpu_irqs       = omap3xxx_dsi1_irqs,
1533         .main_clk       = "dss1_alwon_fck",
1534         .prcm           = {
1535                 .omap2 = {
1536                         .prcm_reg_id = 1,
1537                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1538                         .module_offs = OMAP3430_DSS_MOD,
1539                 },
1540         },
1541         .opt_clks       = dss_dsi1_opt_clks,
1542         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1543         .slaves         = omap3xxx_dss_dsi1_slaves,
1544         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1545         .flags          = HWMOD_NO_IDLEST,
1546 };
1547
1548 /* l4_core -> dss_rfbi */
1549 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1550         .master         = &omap3xxx_l4_core_hwmod,
1551         .slave          = &omap3xxx_dss_rfbi_hwmod,
1552         .clk            = "dss_ick",
1553         .addr           = omap2_dss_rfbi_addrs,
1554         .fw = {
1555                 .omap2 = {
1556                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1557                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1558                         .flags  = OMAP_FIREWALL_L4,
1559                 }
1560         },
1561         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1562 };
1563
1564 /* dss_rfbi slave ports */
1565 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1566         &omap3xxx_l4_core__dss_rfbi,
1567 };
1568
1569 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1570         { .role = "ick", .clk = "dss_ick" },
1571 };
1572
1573 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1574         .name           = "dss_rfbi",
1575         .class          = &omap2_rfbi_hwmod_class,
1576         .main_clk       = "dss1_alwon_fck",
1577         .prcm           = {
1578                 .omap2 = {
1579                         .prcm_reg_id = 1,
1580                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1581                         .module_offs = OMAP3430_DSS_MOD,
1582                 },
1583         },
1584         .opt_clks       = dss_rfbi_opt_clks,
1585         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1586         .slaves         = omap3xxx_dss_rfbi_slaves,
1587         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1588         .flags          = HWMOD_NO_IDLEST,
1589 };
1590
1591 /* l4_core -> dss_venc */
1592 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1593         .master         = &omap3xxx_l4_core_hwmod,
1594         .slave          = &omap3xxx_dss_venc_hwmod,
1595         .clk            = "dss_ick",
1596         .addr           = omap2_dss_venc_addrs,
1597         .fw = {
1598                 .omap2 = {
1599                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1600                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1601                         .flags  = OMAP_FIREWALL_L4,
1602                 }
1603         },
1604         .flags          = OCPIF_SWSUP_IDLE,
1605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1606 };
1607
1608 /* dss_venc slave ports */
1609 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1610         &omap3xxx_l4_core__dss_venc,
1611 };
1612
1613 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
1614         /* required only on OMAP3430 */
1615         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
1616 };
1617
1618 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1619         .name           = "dss_venc",
1620         .class          = &omap2_venc_hwmod_class,
1621         .main_clk       = "dss_tv_fck",
1622         .prcm           = {
1623                 .omap2 = {
1624                         .prcm_reg_id = 1,
1625                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
1626                         .module_offs = OMAP3430_DSS_MOD,
1627                 },
1628         },
1629         .opt_clks       = dss_venc_opt_clks,
1630         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
1631         .slaves         = omap3xxx_dss_venc_slaves,
1632         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1633         .flags          = HWMOD_NO_IDLEST,
1634 };
1635
1636 /* I2C1 */
1637
1638 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1639         .fifo_depth     = 8, /* bytes */
1640         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1641                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1642                           OMAP_I2C_FLAG_BUS_SHIFT_2,
1643 };
1644
1645 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1646         &omap3_l4_core__i2c1,
1647 };
1648
1649 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1650         .name           = "i2c1",
1651         .flags          = HWMOD_16BIT_REG,
1652         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1653         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1654         .main_clk       = "i2c1_fck",
1655         .prcm           = {
1656                 .omap2 = {
1657                         .module_offs = CORE_MOD,
1658                         .prcm_reg_id = 1,
1659                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
1660                         .idlest_reg_id = 1,
1661                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1662                 },
1663         },
1664         .slaves         = omap3xxx_i2c1_slaves,
1665         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1666         .class          = &i2c_class,
1667         .dev_attr       = &i2c1_dev_attr,
1668 };
1669
1670 /* I2C2 */
1671
1672 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1673         .fifo_depth     = 8, /* bytes */
1674         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1675                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1676                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1677 };
1678
1679 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1680         &omap3_l4_core__i2c2,
1681 };
1682
1683 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1684         .name           = "i2c2",
1685         .flags          = HWMOD_16BIT_REG,
1686         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1687         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1688         .main_clk       = "i2c2_fck",
1689         .prcm           = {
1690                 .omap2 = {
1691                         .module_offs = CORE_MOD,
1692                         .prcm_reg_id = 1,
1693                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
1694                         .idlest_reg_id = 1,
1695                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1696                 },
1697         },
1698         .slaves         = omap3xxx_i2c2_slaves,
1699         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1700         .class          = &i2c_class,
1701         .dev_attr       = &i2c2_dev_attr,
1702 };
1703
1704 /* I2C3 */
1705
1706 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1707         .fifo_depth     = 64, /* bytes */
1708         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
1709                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1710                  OMAP_I2C_FLAG_BUS_SHIFT_2,
1711 };
1712
1713 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1714         { .irq = INT_34XX_I2C3_IRQ, },
1715         { .irq = -1 }
1716 };
1717
1718 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1719         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1720         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1721         { .dma_req = -1 }
1722 };
1723
1724 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1725         &omap3_l4_core__i2c3,
1726 };
1727
1728 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1729         .name           = "i2c3",
1730         .flags          = HWMOD_16BIT_REG,
1731         .mpu_irqs       = i2c3_mpu_irqs,
1732         .sdma_reqs      = i2c3_sdma_reqs,
1733         .main_clk       = "i2c3_fck",
1734         .prcm           = {
1735                 .omap2 = {
1736                         .module_offs = CORE_MOD,
1737                         .prcm_reg_id = 1,
1738                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
1739                         .idlest_reg_id = 1,
1740                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1741                 },
1742         },
1743         .slaves         = omap3xxx_i2c3_slaves,
1744         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1745         .class          = &i2c_class,
1746         .dev_attr       = &i2c3_dev_attr,
1747 };
1748
1749 /* l4_wkup -> gpio1 */
1750 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1751         {
1752                 .pa_start       = 0x48310000,
1753                 .pa_end         = 0x483101ff,
1754                 .flags          = ADDR_TYPE_RT
1755         },
1756         { }
1757 };
1758
1759 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1760         .master         = &omap3xxx_l4_wkup_hwmod,
1761         .slave          = &omap3xxx_gpio1_hwmod,
1762         .addr           = omap3xxx_gpio1_addrs,
1763         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1764 };
1765
1766 /* l4_per -> gpio2 */
1767 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1768         {
1769                 .pa_start       = 0x49050000,
1770                 .pa_end         = 0x490501ff,
1771                 .flags          = ADDR_TYPE_RT
1772         },
1773         { }
1774 };
1775
1776 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1777         .master         = &omap3xxx_l4_per_hwmod,
1778         .slave          = &omap3xxx_gpio2_hwmod,
1779         .addr           = omap3xxx_gpio2_addrs,
1780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1781 };
1782
1783 /* l4_per -> gpio3 */
1784 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1785         {
1786                 .pa_start       = 0x49052000,
1787                 .pa_end         = 0x490521ff,
1788                 .flags          = ADDR_TYPE_RT
1789         },
1790         { }
1791 };
1792
1793 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1794         .master         = &omap3xxx_l4_per_hwmod,
1795         .slave          = &omap3xxx_gpio3_hwmod,
1796         .addr           = omap3xxx_gpio3_addrs,
1797         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1798 };
1799
1800 /* l4_per -> gpio4 */
1801 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1802         {
1803                 .pa_start       = 0x49054000,
1804                 .pa_end         = 0x490541ff,
1805                 .flags          = ADDR_TYPE_RT
1806         },
1807         { }
1808 };
1809
1810 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1811         .master         = &omap3xxx_l4_per_hwmod,
1812         .slave          = &omap3xxx_gpio4_hwmod,
1813         .addr           = omap3xxx_gpio4_addrs,
1814         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1815 };
1816
1817 /* l4_per -> gpio5 */
1818 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1819         {
1820                 .pa_start       = 0x49056000,
1821                 .pa_end         = 0x490561ff,
1822                 .flags          = ADDR_TYPE_RT
1823         },
1824         { }
1825 };
1826
1827 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1828         .master         = &omap3xxx_l4_per_hwmod,
1829         .slave          = &omap3xxx_gpio5_hwmod,
1830         .addr           = omap3xxx_gpio5_addrs,
1831         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1832 };
1833
1834 /* l4_per -> gpio6 */
1835 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1836         {
1837                 .pa_start       = 0x49058000,
1838                 .pa_end         = 0x490581ff,
1839                 .flags          = ADDR_TYPE_RT
1840         },
1841         { }
1842 };
1843
1844 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1845         .master         = &omap3xxx_l4_per_hwmod,
1846         .slave          = &omap3xxx_gpio6_hwmod,
1847         .addr           = omap3xxx_gpio6_addrs,
1848         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1849 };
1850
1851 /*
1852  * 'gpio' class
1853  * general purpose io module
1854  */
1855
1856 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1857         .rev_offs       = 0x0000,
1858         .sysc_offs      = 0x0010,
1859         .syss_offs      = 0x0014,
1860         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1861                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1862                            SYSS_HAS_RESET_STATUS),
1863         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1864         .sysc_fields    = &omap_hwmod_sysc_type1,
1865 };
1866
1867 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1868         .name = "gpio",
1869         .sysc = &omap3xxx_gpio_sysc,
1870         .rev = 1,
1871 };
1872
1873 /* gpio_dev_attr*/
1874 static struct omap_gpio_dev_attr gpio_dev_attr = {
1875         .bank_width = 32,
1876         .dbck_flag = true,
1877 };
1878
1879 /* gpio1 */
1880 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1881         { .role = "dbclk", .clk = "gpio1_dbck", },
1882 };
1883
1884 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1885         &omap3xxx_l4_wkup__gpio1,
1886 };
1887
1888 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1889         .name           = "gpio1",
1890         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1891         .mpu_irqs       = omap2_gpio1_irqs,
1892         .main_clk       = "gpio1_ick",
1893         .opt_clks       = gpio1_opt_clks,
1894         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1895         .prcm           = {
1896                 .omap2 = {
1897                         .prcm_reg_id = 1,
1898                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1899                         .module_offs = WKUP_MOD,
1900                         .idlest_reg_id = 1,
1901                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1902                 },
1903         },
1904         .slaves         = omap3xxx_gpio1_slaves,
1905         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1906         .class          = &omap3xxx_gpio_hwmod_class,
1907         .dev_attr       = &gpio_dev_attr,
1908 };
1909
1910 /* gpio2 */
1911 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1912         { .role = "dbclk", .clk = "gpio2_dbck", },
1913 };
1914
1915 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1916         &omap3xxx_l4_per__gpio2,
1917 };
1918
1919 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1920         .name           = "gpio2",
1921         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1922         .mpu_irqs       = omap2_gpio2_irqs,
1923         .main_clk       = "gpio2_ick",
1924         .opt_clks       = gpio2_opt_clks,
1925         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1926         .prcm           = {
1927                 .omap2 = {
1928                         .prcm_reg_id = 1,
1929                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1930                         .module_offs = OMAP3430_PER_MOD,
1931                         .idlest_reg_id = 1,
1932                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1933                 },
1934         },
1935         .slaves         = omap3xxx_gpio2_slaves,
1936         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1937         .class          = &omap3xxx_gpio_hwmod_class,
1938         .dev_attr       = &gpio_dev_attr,
1939 };
1940
1941 /* gpio3 */
1942 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1943         { .role = "dbclk", .clk = "gpio3_dbck", },
1944 };
1945
1946 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1947         &omap3xxx_l4_per__gpio3,
1948 };
1949
1950 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1951         .name           = "gpio3",
1952         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1953         .mpu_irqs       = omap2_gpio3_irqs,
1954         .main_clk       = "gpio3_ick",
1955         .opt_clks       = gpio3_opt_clks,
1956         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1957         .prcm           = {
1958                 .omap2 = {
1959                         .prcm_reg_id = 1,
1960                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1961                         .module_offs = OMAP3430_PER_MOD,
1962                         .idlest_reg_id = 1,
1963                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1964                 },
1965         },
1966         .slaves         = omap3xxx_gpio3_slaves,
1967         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1968         .class          = &omap3xxx_gpio_hwmod_class,
1969         .dev_attr       = &gpio_dev_attr,
1970 };
1971
1972 /* gpio4 */
1973 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1974         { .role = "dbclk", .clk = "gpio4_dbck", },
1975 };
1976
1977 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1978         &omap3xxx_l4_per__gpio4,
1979 };
1980
1981 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1982         .name           = "gpio4",
1983         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1984         .mpu_irqs       = omap2_gpio4_irqs,
1985         .main_clk       = "gpio4_ick",
1986         .opt_clks       = gpio4_opt_clks,
1987         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1988         .prcm           = {
1989                 .omap2 = {
1990                         .prcm_reg_id = 1,
1991                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1992                         .module_offs = OMAP3430_PER_MOD,
1993                         .idlest_reg_id = 1,
1994                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1995                 },
1996         },
1997         .slaves         = omap3xxx_gpio4_slaves,
1998         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1999         .class          = &omap3xxx_gpio_hwmod_class,
2000         .dev_attr       = &gpio_dev_attr,
2001 };
2002
2003 /* gpio5 */
2004 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2005         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2006         { .irq = -1 }
2007 };
2008
2009 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2010         { .role = "dbclk", .clk = "gpio5_dbck", },
2011 };
2012
2013 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2014         &omap3xxx_l4_per__gpio5,
2015 };
2016
2017 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2018         .name           = "gpio5",
2019         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2020         .mpu_irqs       = omap3xxx_gpio5_irqs,
2021         .main_clk       = "gpio5_ick",
2022         .opt_clks       = gpio5_opt_clks,
2023         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2024         .prcm           = {
2025                 .omap2 = {
2026                         .prcm_reg_id = 1,
2027                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2028                         .module_offs = OMAP3430_PER_MOD,
2029                         .idlest_reg_id = 1,
2030                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2031                 },
2032         },
2033         .slaves         = omap3xxx_gpio5_slaves,
2034         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2035         .class          = &omap3xxx_gpio_hwmod_class,
2036         .dev_attr       = &gpio_dev_attr,
2037 };
2038
2039 /* gpio6 */
2040 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2041         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2042         { .irq = -1 }
2043 };
2044
2045 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2046         { .role = "dbclk", .clk = "gpio6_dbck", },
2047 };
2048
2049 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2050         &omap3xxx_l4_per__gpio6,
2051 };
2052
2053 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2054         .name           = "gpio6",
2055         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2056         .mpu_irqs       = omap3xxx_gpio6_irqs,
2057         .main_clk       = "gpio6_ick",
2058         .opt_clks       = gpio6_opt_clks,
2059         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2060         .prcm           = {
2061                 .omap2 = {
2062                         .prcm_reg_id = 1,
2063                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2064                         .module_offs = OMAP3430_PER_MOD,
2065                         .idlest_reg_id = 1,
2066                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2067                 },
2068         },
2069         .slaves         = omap3xxx_gpio6_slaves,
2070         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2071         .class          = &omap3xxx_gpio_hwmod_class,
2072         .dev_attr       = &gpio_dev_attr,
2073 };
2074
2075 /* dma_system -> L3 */
2076 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2077         .master         = &omap3xxx_dma_system_hwmod,
2078         .slave          = &omap3xxx_l3_main_hwmod,
2079         .clk            = "core_l3_ick",
2080         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2081 };
2082
2083 /* dma attributes */
2084 static struct omap_dma_dev_attr dma_dev_attr = {
2085         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2086                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2087         .lch_count = 32,
2088 };
2089
2090 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2091         .rev_offs       = 0x0000,
2092         .sysc_offs      = 0x002c,
2093         .syss_offs      = 0x0028,
2094         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2095                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2096                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2097                            SYSS_HAS_RESET_STATUS),
2098         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2099                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2100         .sysc_fields    = &omap_hwmod_sysc_type1,
2101 };
2102
2103 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2104         .name = "dma",
2105         .sysc = &omap3xxx_dma_sysc,
2106 };
2107
2108 /* dma_system */
2109 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2110         {
2111                 .pa_start       = 0x48056000,
2112                 .pa_end         = 0x48056fff,
2113                 .flags          = ADDR_TYPE_RT
2114         },
2115         { }
2116 };
2117
2118 /* dma_system master ports */
2119 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2120         &omap3xxx_dma_system__l3,
2121 };
2122
2123 /* l4_cfg -> dma_system */
2124 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2125         .master         = &omap3xxx_l4_core_hwmod,
2126         .slave          = &omap3xxx_dma_system_hwmod,
2127         .clk            = "core_l4_ick",
2128         .addr           = omap3xxx_dma_system_addrs,
2129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2130 };
2131
2132 /* dma_system slave ports */
2133 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2134         &omap3xxx_l4_core__dma_system,
2135 };
2136
2137 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2138         .name           = "dma",
2139         .class          = &omap3xxx_dma_hwmod_class,
2140         .mpu_irqs       = omap2_dma_system_irqs,
2141         .main_clk       = "core_l3_ick",
2142         .prcm = {
2143                 .omap2 = {
2144                         .module_offs            = CORE_MOD,
2145                         .prcm_reg_id            = 1,
2146                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
2147                         .idlest_reg_id          = 1,
2148                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
2149                 },
2150         },
2151         .slaves         = omap3xxx_dma_system_slaves,
2152         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2153         .masters        = omap3xxx_dma_system_masters,
2154         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
2155         .dev_attr       = &dma_dev_attr,
2156         .flags          = HWMOD_NO_IDLEST,
2157 };
2158
2159 /*
2160  * 'mcbsp' class
2161  * multi channel buffered serial port controller
2162  */
2163
2164 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2165         .sysc_offs      = 0x008c,
2166         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2167                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2168         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2169         .sysc_fields    = &omap_hwmod_sysc_type1,
2170         .clockact       = 0x2,
2171 };
2172
2173 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2174         .name = "mcbsp",
2175         .sysc = &omap3xxx_mcbsp_sysc,
2176         .rev  = MCBSP_CONFIG_TYPE3,
2177 };
2178
2179 /* mcbsp1 */
2180 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2181         { .name = "irq", .irq = 16 },
2182         { .name = "tx", .irq = 59 },
2183         { .name = "rx", .irq = 60 },
2184         { .irq = -1 }
2185 };
2186
2187 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2188         {
2189                 .name           = "mpu",
2190                 .pa_start       = 0x48074000,
2191                 .pa_end         = 0x480740ff,
2192                 .flags          = ADDR_TYPE_RT
2193         },
2194         { }
2195 };
2196
2197 /* l4_core -> mcbsp1 */
2198 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2199         .master         = &omap3xxx_l4_core_hwmod,
2200         .slave          = &omap3xxx_mcbsp1_hwmod,
2201         .clk            = "mcbsp1_ick",
2202         .addr           = omap3xxx_mcbsp1_addrs,
2203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2204 };
2205
2206 /* mcbsp1 slave ports */
2207 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2208         &omap3xxx_l4_core__mcbsp1,
2209 };
2210
2211 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2212         .name           = "mcbsp1",
2213         .class          = &omap3xxx_mcbsp_hwmod_class,
2214         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
2215         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
2216         .main_clk       = "mcbsp1_fck",
2217         .prcm           = {
2218                 .omap2 = {
2219                         .prcm_reg_id = 1,
2220                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2221                         .module_offs = CORE_MOD,
2222                         .idlest_reg_id = 1,
2223                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2224                 },
2225         },
2226         .slaves         = omap3xxx_mcbsp1_slaves,
2227         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2228 };
2229
2230 /* mcbsp2 */
2231 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2232         { .name = "irq", .irq = 17 },
2233         { .name = "tx", .irq = 62 },
2234         { .name = "rx", .irq = 63 },
2235         { .irq = -1 }
2236 };
2237
2238 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2239         {
2240                 .name           = "mpu",
2241                 .pa_start       = 0x49022000,
2242                 .pa_end         = 0x490220ff,
2243                 .flags          = ADDR_TYPE_RT
2244         },
2245         { }
2246 };
2247
2248 /* l4_per -> mcbsp2 */
2249 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2250         .master         = &omap3xxx_l4_per_hwmod,
2251         .slave          = &omap3xxx_mcbsp2_hwmod,
2252         .clk            = "mcbsp2_ick",
2253         .addr           = omap3xxx_mcbsp2_addrs,
2254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2255 };
2256
2257 /* mcbsp2 slave ports */
2258 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2259         &omap3xxx_l4_per__mcbsp2,
2260 };
2261
2262 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2263         .sidetone       = "mcbsp2_sidetone",
2264 };
2265
2266 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2267         .name           = "mcbsp2",
2268         .class          = &omap3xxx_mcbsp_hwmod_class,
2269         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
2270         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
2271         .main_clk       = "mcbsp2_fck",
2272         .prcm           = {
2273                 .omap2 = {
2274                         .prcm_reg_id = 1,
2275                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2276                         .module_offs = OMAP3430_PER_MOD,
2277                         .idlest_reg_id = 1,
2278                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2279                 },
2280         },
2281         .slaves         = omap3xxx_mcbsp2_slaves,
2282         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2283         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
2284 };
2285
2286 /* mcbsp3 */
2287 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2288         { .name = "irq", .irq = 22 },
2289         { .name = "tx", .irq = 89 },
2290         { .name = "rx", .irq = 90 },
2291         { .irq = -1 }
2292 };
2293
2294 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2295         {
2296                 .name           = "mpu",
2297                 .pa_start       = 0x49024000,
2298                 .pa_end         = 0x490240ff,
2299                 .flags          = ADDR_TYPE_RT
2300         },
2301         { }
2302 };
2303
2304 /* l4_per -> mcbsp3 */
2305 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2306         .master         = &omap3xxx_l4_per_hwmod,
2307         .slave          = &omap3xxx_mcbsp3_hwmod,
2308         .clk            = "mcbsp3_ick",
2309         .addr           = omap3xxx_mcbsp3_addrs,
2310         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2311 };
2312
2313 /* mcbsp3 slave ports */
2314 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2315         &omap3xxx_l4_per__mcbsp3,
2316 };
2317
2318 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2319         .sidetone       = "mcbsp3_sidetone",
2320 };
2321
2322 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2323         .name           = "mcbsp3",
2324         .class          = &omap3xxx_mcbsp_hwmod_class,
2325         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
2326         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
2327         .main_clk       = "mcbsp3_fck",
2328         .prcm           = {
2329                 .omap2 = {
2330                         .prcm_reg_id = 1,
2331                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2332                         .module_offs = OMAP3430_PER_MOD,
2333                         .idlest_reg_id = 1,
2334                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2335                 },
2336         },
2337         .slaves         = omap3xxx_mcbsp3_slaves,
2338         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2339         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
2340 };
2341
2342 /* mcbsp4 */
2343 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2344         { .name = "irq", .irq = 23 },
2345         { .name = "tx", .irq = 54 },
2346         { .name = "rx", .irq = 55 },
2347         { .irq = -1 }
2348 };
2349
2350 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2351         { .name = "rx", .dma_req = 20 },
2352         { .name = "tx", .dma_req = 19 },
2353         { .dma_req = -1 }
2354 };
2355
2356 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2357         {
2358                 .name           = "mpu",
2359                 .pa_start       = 0x49026000,
2360                 .pa_end         = 0x490260ff,
2361                 .flags          = ADDR_TYPE_RT
2362         },
2363         { }
2364 };
2365
2366 /* l4_per -> mcbsp4 */
2367 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2368         .master         = &omap3xxx_l4_per_hwmod,
2369         .slave          = &omap3xxx_mcbsp4_hwmod,
2370         .clk            = "mcbsp4_ick",
2371         .addr           = omap3xxx_mcbsp4_addrs,
2372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2373 };
2374
2375 /* mcbsp4 slave ports */
2376 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2377         &omap3xxx_l4_per__mcbsp4,
2378 };
2379
2380 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2381         .name           = "mcbsp4",
2382         .class          = &omap3xxx_mcbsp_hwmod_class,
2383         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
2384         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
2385         .main_clk       = "mcbsp4_fck",
2386         .prcm           = {
2387                 .omap2 = {
2388                         .prcm_reg_id = 1,
2389                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2390                         .module_offs = OMAP3430_PER_MOD,
2391                         .idlest_reg_id = 1,
2392                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2393                 },
2394         },
2395         .slaves         = omap3xxx_mcbsp4_slaves,
2396         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2397 };
2398
2399 /* mcbsp5 */
2400 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2401         { .name = "irq", .irq = 27 },
2402         { .name = "tx", .irq = 81 },
2403         { .name = "rx", .irq = 82 },
2404         { .irq = -1 }
2405 };
2406
2407 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2408         { .name = "rx", .dma_req = 22 },
2409         { .name = "tx", .dma_req = 21 },
2410         { .dma_req = -1 }
2411 };
2412
2413 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2414         {
2415                 .name           = "mpu",
2416                 .pa_start       = 0x48096000,
2417                 .pa_end         = 0x480960ff,
2418                 .flags          = ADDR_TYPE_RT
2419         },
2420         { }
2421 };
2422
2423 /* l4_core -> mcbsp5 */
2424 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2425         .master         = &omap3xxx_l4_core_hwmod,
2426         .slave          = &omap3xxx_mcbsp5_hwmod,
2427         .clk            = "mcbsp5_ick",
2428         .addr           = omap3xxx_mcbsp5_addrs,
2429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2430 };
2431
2432 /* mcbsp5 slave ports */
2433 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2434         &omap3xxx_l4_core__mcbsp5,
2435 };
2436
2437 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2438         .name           = "mcbsp5",
2439         .class          = &omap3xxx_mcbsp_hwmod_class,
2440         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
2441         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
2442         .main_clk       = "mcbsp5_fck",
2443         .prcm           = {
2444                 .omap2 = {
2445                         .prcm_reg_id = 1,
2446                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2447                         .module_offs = CORE_MOD,
2448                         .idlest_reg_id = 1,
2449                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2450                 },
2451         },
2452         .slaves         = omap3xxx_mcbsp5_slaves,
2453         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2454 };
2455 /* 'mcbsp sidetone' class */
2456
2457 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2458         .sysc_offs      = 0x0010,
2459         .sysc_flags     = SYSC_HAS_AUTOIDLE,
2460         .sysc_fields    = &omap_hwmod_sysc_type1,
2461 };
2462
2463 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2464         .name = "mcbsp_sidetone",
2465         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2466 };
2467
2468 /* mcbsp2_sidetone */
2469 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2470         { .name = "irq", .irq = 4 },
2471         { .irq = -1 }
2472 };
2473
2474 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2475         {
2476                 .name           = "sidetone",
2477                 .pa_start       = 0x49028000,
2478                 .pa_end         = 0x490280ff,
2479                 .flags          = ADDR_TYPE_RT
2480         },
2481         { }
2482 };
2483
2484 /* l4_per -> mcbsp2_sidetone */
2485 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2486         .master         = &omap3xxx_l4_per_hwmod,
2487         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2488         .clk            = "mcbsp2_ick",
2489         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2490         .user           = OCP_USER_MPU,
2491 };
2492
2493 /* mcbsp2_sidetone slave ports */
2494 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2495         &omap3xxx_l4_per__mcbsp2_sidetone,
2496 };
2497
2498 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2499         .name           = "mcbsp2_sidetone",
2500         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2501         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
2502         .main_clk       = "mcbsp2_fck",
2503         .prcm           = {
2504                 .omap2 = {
2505                         .prcm_reg_id = 1,
2506                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2507                         .module_offs = OMAP3430_PER_MOD,
2508                         .idlest_reg_id = 1,
2509                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2510                 },
2511         },
2512         .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
2513         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2514 };
2515
2516 /* mcbsp3_sidetone */
2517 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2518         { .name = "irq", .irq = 5 },
2519         { .irq = -1 }
2520 };
2521
2522 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2523         {
2524                 .name           = "sidetone",
2525                 .pa_start       = 0x4902A000,
2526                 .pa_end         = 0x4902A0ff,
2527                 .flags          = ADDR_TYPE_RT
2528         },
2529         { }
2530 };
2531
2532 /* l4_per -> mcbsp3_sidetone */
2533 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2534         .master         = &omap3xxx_l4_per_hwmod,
2535         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2536         .clk            = "mcbsp3_ick",
2537         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2538         .user           = OCP_USER_MPU,
2539 };
2540
2541 /* mcbsp3_sidetone slave ports */
2542 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2543         &omap3xxx_l4_per__mcbsp3_sidetone,
2544 };
2545
2546 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2547         .name           = "mcbsp3_sidetone",
2548         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
2549         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
2550         .main_clk       = "mcbsp3_fck",
2551         .prcm           = {
2552                 .omap2 = {
2553                         .prcm_reg_id = 1,
2554                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2555                         .module_offs = OMAP3430_PER_MOD,
2556                         .idlest_reg_id = 1,
2557                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2558                 },
2559         },
2560         .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
2561         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2562 };
2563
2564
2565 /* SR common */
2566 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2567         .clkact_shift   = 20,
2568 };
2569
2570 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2571         .sysc_offs      = 0x24,
2572         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2573         .clockact       = CLOCKACT_TEST_ICLK,
2574         .sysc_fields    = &omap34xx_sr_sysc_fields,
2575 };
2576
2577 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2578         .name = "smartreflex",
2579         .sysc = &omap34xx_sr_sysc,
2580         .rev  = 1,
2581 };
2582
2583 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2584         .sidle_shift    = 24,
2585         .enwkup_shift   = 26
2586 };
2587
2588 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2589         .sysc_offs      = 0x38,
2590         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2591         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2592                         SYSC_NO_CACHE),
2593         .sysc_fields    = &omap36xx_sr_sysc_fields,
2594 };
2595
2596 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2597         .name = "smartreflex",
2598         .sysc = &omap36xx_sr_sysc,
2599         .rev  = 2,
2600 };
2601
2602 /* SR1 */
2603 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2604         &omap3_l4_core__sr1,
2605 };
2606
2607 static struct omap_hwmod omap34xx_sr1_hwmod = {
2608         .name           = "sr1_hwmod",
2609         .class          = &omap34xx_smartreflex_hwmod_class,
2610         .main_clk       = "sr1_fck",
2611         .vdd_name       = "mpu_iva",
2612         .prcm           = {
2613                 .omap2 = {
2614                         .prcm_reg_id = 1,
2615                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2616                         .module_offs = WKUP_MOD,
2617                         .idlest_reg_id = 1,
2618                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2619                 },
2620         },
2621         .slaves         = omap3_sr1_slaves,
2622         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2623         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2624 };
2625
2626 static struct omap_hwmod omap36xx_sr1_hwmod = {
2627         .name           = "sr1_hwmod",
2628         .class          = &omap36xx_smartreflex_hwmod_class,
2629         .main_clk       = "sr1_fck",
2630         .vdd_name       = "mpu_iva",
2631         .prcm           = {
2632                 .omap2 = {
2633                         .prcm_reg_id = 1,
2634                         .module_bit = OMAP3430_EN_SR1_SHIFT,
2635                         .module_offs = WKUP_MOD,
2636                         .idlest_reg_id = 1,
2637                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2638                 },
2639         },
2640         .slaves         = omap3_sr1_slaves,
2641         .slaves_cnt     = ARRAY_SIZE(omap3_sr1_slaves),
2642 };
2643
2644 /* SR2 */
2645 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2646         &omap3_l4_core__sr2,
2647 };
2648
2649 static struct omap_hwmod omap34xx_sr2_hwmod = {
2650         .name           = "sr2_hwmod",
2651         .class          = &omap34xx_smartreflex_hwmod_class,
2652         .main_clk       = "sr2_fck",
2653         .vdd_name       = "core",
2654         .prcm           = {
2655                 .omap2 = {
2656                         .prcm_reg_id = 1,
2657                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2658                         .module_offs = WKUP_MOD,
2659                         .idlest_reg_id = 1,
2660                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2661                 },
2662         },
2663         .slaves         = omap3_sr2_slaves,
2664         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2665         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
2666 };
2667
2668 static struct omap_hwmod omap36xx_sr2_hwmod = {
2669         .name           = "sr2_hwmod",
2670         .class          = &omap36xx_smartreflex_hwmod_class,
2671         .main_clk       = "sr2_fck",
2672         .vdd_name       = "core",
2673         .prcm           = {
2674                 .omap2 = {
2675                         .prcm_reg_id = 1,
2676                         .module_bit = OMAP3430_EN_SR2_SHIFT,
2677                         .module_offs = WKUP_MOD,
2678                         .idlest_reg_id = 1,
2679                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2680                 },
2681         },
2682         .slaves         = omap3_sr2_slaves,
2683         .slaves_cnt     = ARRAY_SIZE(omap3_sr2_slaves),
2684 };
2685
2686 /*
2687  * 'mailbox' class
2688  * mailbox module allowing communication between the on-chip processors
2689  * using a queued mailbox-interrupt mechanism.
2690  */
2691
2692 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2693         .rev_offs       = 0x000,
2694         .sysc_offs      = 0x010,
2695         .syss_offs      = 0x014,
2696         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2697                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2698         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2699         .sysc_fields    = &omap_hwmod_sysc_type1,
2700 };
2701
2702 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2703         .name = "mailbox",
2704         .sysc = &omap3xxx_mailbox_sysc,
2705 };
2706
2707 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2708 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2709         { .irq = 26 },
2710         { .irq = -1 }
2711 };
2712
2713 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2714         {
2715                 .pa_start       = 0x48094000,
2716                 .pa_end         = 0x480941ff,
2717                 .flags          = ADDR_TYPE_RT,
2718         },
2719         { }
2720 };
2721
2722 /* l4_core -> mailbox */
2723 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2724         .master         = &omap3xxx_l4_core_hwmod,
2725         .slave          = &omap3xxx_mailbox_hwmod,
2726         .addr           = omap3xxx_mailbox_addrs,
2727         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2728 };
2729
2730 /* mailbox slave ports */
2731 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2732         &omap3xxx_l4_core__mailbox,
2733 };
2734
2735 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2736         .name           = "mailbox",
2737         .class          = &omap3xxx_mailbox_hwmod_class,
2738         .mpu_irqs       = omap3xxx_mailbox_irqs,
2739         .main_clk       = "mailboxes_ick",
2740         .prcm           = {
2741                 .omap2 = {
2742                         .prcm_reg_id = 1,
2743                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2744                         .module_offs = CORE_MOD,
2745                         .idlest_reg_id = 1,
2746                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2747                 },
2748         },
2749         .slaves         = omap3xxx_mailbox_slaves,
2750         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2751 };
2752
2753 /* l4 core -> mcspi1 interface */
2754 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2755         .master         = &omap3xxx_l4_core_hwmod,
2756         .slave          = &omap34xx_mcspi1,
2757         .clk            = "mcspi1_ick",
2758         .addr           = omap2_mcspi1_addr_space,
2759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2760 };
2761
2762 /* l4 core -> mcspi2 interface */
2763 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2764         .master         = &omap3xxx_l4_core_hwmod,
2765         .slave          = &omap34xx_mcspi2,
2766         .clk            = "mcspi2_ick",
2767         .addr           = omap2_mcspi2_addr_space,
2768         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2769 };
2770
2771 /* l4 core -> mcspi3 interface */
2772 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2773         .master         = &omap3xxx_l4_core_hwmod,
2774         .slave          = &omap34xx_mcspi3,
2775         .clk            = "mcspi3_ick",
2776         .addr           = omap2430_mcspi3_addr_space,
2777         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2778 };
2779
2780 /* l4 core -> mcspi4 interface */
2781 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2782         {
2783                 .pa_start       = 0x480ba000,
2784                 .pa_end         = 0x480ba0ff,
2785                 .flags          = ADDR_TYPE_RT,
2786         },
2787         { }
2788 };
2789
2790 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2791         .master         = &omap3xxx_l4_core_hwmod,
2792         .slave          = &omap34xx_mcspi4,
2793         .clk            = "mcspi4_ick",
2794         .addr           = omap34xx_mcspi4_addr_space,
2795         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2796 };
2797
2798 /*
2799  * 'mcspi' class
2800  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2801  * bus
2802  */
2803
2804 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2805         .rev_offs       = 0x0000,
2806         .sysc_offs      = 0x0010,
2807         .syss_offs      = 0x0014,
2808         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2809                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2810                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2811         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2812         .sysc_fields    = &omap_hwmod_sysc_type1,
2813 };
2814
2815 static struct omap_hwmod_class omap34xx_mcspi_class = {
2816         .name = "mcspi",
2817         .sysc = &omap34xx_mcspi_sysc,
2818         .rev = OMAP3_MCSPI_REV,
2819 };
2820
2821 /* mcspi1 */
2822 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2823         &omap34xx_l4_core__mcspi1,
2824 };
2825
2826 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2827         .num_chipselect = 4,
2828 };
2829
2830 static struct omap_hwmod omap34xx_mcspi1 = {
2831         .name           = "mcspi1",
2832         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
2833         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
2834         .main_clk       = "mcspi1_fck",
2835         .prcm           = {
2836                 .omap2 = {
2837                         .module_offs = CORE_MOD,
2838                         .prcm_reg_id = 1,
2839                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2840                         .idlest_reg_id = 1,
2841                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2842                 },
2843         },
2844         .slaves         = omap34xx_mcspi1_slaves,
2845         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2846         .class          = &omap34xx_mcspi_class,
2847         .dev_attr       = &omap_mcspi1_dev_attr,
2848 };
2849
2850 /* mcspi2 */
2851 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2852         &omap34xx_l4_core__mcspi2,
2853 };
2854
2855 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2856         .num_chipselect = 2,
2857 };
2858
2859 static struct omap_hwmod omap34xx_mcspi2 = {
2860         .name           = "mcspi2",
2861         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
2862         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
2863         .main_clk       = "mcspi2_fck",
2864         .prcm           = {
2865                 .omap2 = {
2866                         .module_offs = CORE_MOD,
2867                         .prcm_reg_id = 1,
2868                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2869                         .idlest_reg_id = 1,
2870                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2871                 },
2872         },
2873         .slaves         = omap34xx_mcspi2_slaves,
2874         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2875         .class          = &omap34xx_mcspi_class,
2876         .dev_attr       = &omap_mcspi2_dev_attr,
2877 };
2878
2879 /* mcspi3 */
2880 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2881         { .name = "irq", .irq = 91 }, /* 91 */
2882         { .irq = -1 }
2883 };
2884
2885 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2886         { .name = "tx0", .dma_req = 15 },
2887         { .name = "rx0", .dma_req = 16 },
2888         { .name = "tx1", .dma_req = 23 },
2889         { .name = "rx1", .dma_req = 24 },
2890         { .dma_req = -1 }
2891 };
2892
2893 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2894         &omap34xx_l4_core__mcspi3,
2895 };
2896
2897 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2898         .num_chipselect = 2,
2899 };
2900
2901 static struct omap_hwmod omap34xx_mcspi3 = {
2902         .name           = "mcspi3",
2903         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
2904         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
2905         .main_clk       = "mcspi3_fck",
2906         .prcm           = {
2907                 .omap2 = {
2908                         .module_offs = CORE_MOD,
2909                         .prcm_reg_id = 1,
2910                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2911                         .idlest_reg_id = 1,
2912                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2913                 },
2914         },
2915         .slaves         = omap34xx_mcspi3_slaves,
2916         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2917         .class          = &omap34xx_mcspi_class,
2918         .dev_attr       = &omap_mcspi3_dev_attr,
2919 };
2920
2921 /* SPI4 */
2922 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2923         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2924         { .irq = -1 }
2925 };
2926
2927 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2928         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2929         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2930         { .dma_req = -1 }
2931 };
2932
2933 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2934         &omap34xx_l4_core__mcspi4,
2935 };
2936
2937 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2938         .num_chipselect = 1,
2939 };
2940
2941 static struct omap_hwmod omap34xx_mcspi4 = {
2942         .name           = "mcspi4",
2943         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
2944         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
2945         .main_clk       = "mcspi4_fck",
2946         .prcm           = {
2947                 .omap2 = {
2948                         .module_offs = CORE_MOD,
2949                         .prcm_reg_id = 1,
2950                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2951                         .idlest_reg_id = 1,
2952                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2953                 },
2954         },
2955         .slaves         = omap34xx_mcspi4_slaves,
2956         .slaves_cnt     = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2957         .class          = &omap34xx_mcspi_class,
2958         .dev_attr       = &omap_mcspi4_dev_attr,
2959 };
2960
2961 /*
2962  * usbhsotg
2963  */
2964 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2965         .rev_offs       = 0x0400,
2966         .sysc_offs      = 0x0404,
2967         .syss_offs      = 0x0408,
2968         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2969                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2970                           SYSC_HAS_AUTOIDLE),
2971         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2972                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2973         .sysc_fields    = &omap_hwmod_sysc_type1,
2974 };
2975
2976 static struct omap_hwmod_class usbotg_class = {
2977         .name = "usbotg",
2978         .sysc = &omap3xxx_usbhsotg_sysc,
2979 };
2980 /* usb_otg_hs */
2981 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2982
2983         { .name = "mc", .irq = 92 },
2984         { .name = "dma", .irq = 93 },
2985         { .irq = -1 }
2986 };
2987
2988 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2989         .name           = "usb_otg_hs",
2990         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
2991         .main_clk       = "hsotgusb_ick",
2992         .prcm           = {
2993                 .omap2 = {
2994                         .prcm_reg_id = 1,
2995                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2996                         .module_offs = CORE_MOD,
2997                         .idlest_reg_id = 1,
2998                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2999                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3000                 },
3001         },
3002         .masters        = omap3xxx_usbhsotg_masters,
3003         .masters_cnt    = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3004         .slaves         = omap3xxx_usbhsotg_slaves,
3005         .slaves_cnt     = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3006         .class          = &usbotg_class,
3007
3008         /*
3009          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
3010          * broken when autoidle is enabled
3011          * workaround is to disable the autoidle bit at module level.
3012          */
3013         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3014                                 | HWMOD_SWSUP_MSTANDBY,
3015 };
3016
3017 /* usb_otg_hs */
3018 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3019
3020         { .name = "mc", .irq = 71 },
3021         { .irq = -1 }
3022 };
3023
3024 static struct omap_hwmod_class am35xx_usbotg_class = {
3025         .name = "am35xx_usbotg",
3026         .sysc = NULL,
3027 };
3028
3029 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3030         .name           = "am35x_otg_hs",
3031         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
3032         .main_clk       = NULL,
3033         .prcm = {
3034                 .omap2 = {
3035                 },
3036         },
3037         .masters        = am35xx_usbhsotg_masters,
3038         .masters_cnt    = ARRAY_SIZE(am35xx_usbhsotg_masters),
3039         .slaves         = am35xx_usbhsotg_slaves,
3040         .slaves_cnt     = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3041         .class          = &am35xx_usbotg_class,
3042 };
3043
3044 /* MMC/SD/SDIO common */
3045
3046 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3047         .rev_offs       = 0x1fc,
3048         .sysc_offs      = 0x10,
3049         .syss_offs      = 0x14,
3050         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3051                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3052                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3053         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3054         .sysc_fields    = &omap_hwmod_sysc_type1,
3055 };
3056
3057 static struct omap_hwmod_class omap34xx_mmc_class = {
3058         .name = "mmc",
3059         .sysc = &omap34xx_mmc_sysc,
3060 };
3061
3062 /* MMC/SD/SDIO1 */
3063
3064 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3065         { .irq = 83, },
3066         { .irq = -1 }
3067 };
3068
3069 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3070         { .name = "tx", .dma_req = 61, },
3071         { .name = "rx", .dma_req = 62, },
3072         { .dma_req = -1 }
3073 };
3074
3075 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3076         { .role = "dbck", .clk = "omap_32k_fck", },
3077 };
3078
3079 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3080         &omap3xxx_l4_core__mmc1,
3081 };
3082
3083 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3084         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3085 };
3086
3087 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3088         .name           = "mmc1",
3089         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
3090         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
3091         .opt_clks       = omap34xx_mmc1_opt_clks,
3092         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3093         .main_clk       = "mmchs1_fck",
3094         .prcm           = {
3095                 .omap2 = {
3096                         .module_offs = CORE_MOD,
3097                         .prcm_reg_id = 1,
3098                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
3099                         .idlest_reg_id = 1,
3100                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3101                 },
3102         },
3103         .dev_attr       = &mmc1_dev_attr,
3104         .slaves         = omap3xxx_mmc1_slaves,
3105         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3106         .class          = &omap34xx_mmc_class,
3107 };
3108
3109 /* MMC/SD/SDIO2 */
3110
3111 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3112         { .irq = INT_24XX_MMC2_IRQ, },
3113         { .irq = -1 }
3114 };
3115
3116 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3117         { .name = "tx", .dma_req = 47, },
3118         { .name = "rx", .dma_req = 48, },
3119         { .dma_req = -1 }
3120 };
3121
3122 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3123         { .role = "dbck", .clk = "omap_32k_fck", },
3124 };
3125
3126 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3127         &omap3xxx_l4_core__mmc2,
3128 };
3129
3130 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3131         .name           = "mmc2",
3132         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
3133         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
3134         .opt_clks       = omap34xx_mmc2_opt_clks,
3135         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3136         .main_clk       = "mmchs2_fck",
3137         .prcm           = {
3138                 .omap2 = {
3139                         .module_offs = CORE_MOD,
3140                         .prcm_reg_id = 1,
3141                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
3142                         .idlest_reg_id = 1,
3143                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3144                 },
3145         },
3146         .slaves         = omap3xxx_mmc2_slaves,
3147         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3148         .class          = &omap34xx_mmc_class,
3149 };
3150
3151 /* MMC/SD/SDIO3 */
3152
3153 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3154         { .irq = 94, },
3155         { .irq = -1 }
3156 };
3157
3158 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3159         { .name = "tx", .dma_req = 77, },
3160         { .name = "rx", .dma_req = 78, },
3161         { .dma_req = -1 }
3162 };
3163
3164 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3165         { .role = "dbck", .clk = "omap_32k_fck", },
3166 };
3167
3168 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3169         &omap3xxx_l4_core__mmc3,
3170 };
3171
3172 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3173         .name           = "mmc3",
3174         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
3175         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
3176         .opt_clks       = omap34xx_mmc3_opt_clks,
3177         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3178         .main_clk       = "mmchs3_fck",
3179         .prcm           = {
3180                 .omap2 = {
3181                         .prcm_reg_id = 1,
3182                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
3183                         .idlest_reg_id = 1,
3184                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3185                 },
3186         },
3187         .slaves         = omap3xxx_mmc3_slaves,
3188         .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3189         .class          = &omap34xx_mmc_class,
3190 };
3191
3192 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3193         &omap3xxx_l3_main_hwmod,
3194         &omap3xxx_l4_core_hwmod,
3195         &omap3xxx_l4_per_hwmod,
3196         &omap3xxx_l4_wkup_hwmod,
3197         &omap3xxx_mmc1_hwmod,
3198         &omap3xxx_mmc2_hwmod,
3199         &omap3xxx_mmc3_hwmod,
3200         &omap3xxx_mpu_hwmod,
3201
3202         &omap3xxx_timer1_hwmod,
3203         &omap3xxx_timer2_hwmod,
3204         &omap3xxx_timer3_hwmod,
3205         &omap3xxx_timer4_hwmod,
3206         &omap3xxx_timer5_hwmod,
3207         &omap3xxx_timer6_hwmod,
3208         &omap3xxx_timer7_hwmod,
3209         &omap3xxx_timer8_hwmod,
3210         &omap3xxx_timer9_hwmod,
3211         &omap3xxx_timer10_hwmod,
3212         &omap3xxx_timer11_hwmod,
3213         &omap3xxx_timer12_hwmod,
3214
3215         &omap3xxx_wd_timer2_hwmod,
3216         &omap3xxx_uart1_hwmod,
3217         &omap3xxx_uart2_hwmod,
3218         &omap3xxx_uart3_hwmod,
3219         /* dss class */
3220         &omap3xxx_dss_dispc_hwmod,
3221         &omap3xxx_dss_dsi1_hwmod,
3222         &omap3xxx_dss_rfbi_hwmod,
3223         &omap3xxx_dss_venc_hwmod,
3224
3225         /* i2c class */
3226         &omap3xxx_i2c1_hwmod,
3227         &omap3xxx_i2c2_hwmod,
3228         &omap3xxx_i2c3_hwmod,
3229
3230         /* gpio class */
3231         &omap3xxx_gpio1_hwmod,
3232         &omap3xxx_gpio2_hwmod,
3233         &omap3xxx_gpio3_hwmod,
3234         &omap3xxx_gpio4_hwmod,
3235         &omap3xxx_gpio5_hwmod,
3236         &omap3xxx_gpio6_hwmod,
3237
3238         /* dma_system class*/
3239         &omap3xxx_dma_system_hwmod,
3240
3241         /* mcbsp class */
3242         &omap3xxx_mcbsp1_hwmod,
3243         &omap3xxx_mcbsp2_hwmod,
3244         &omap3xxx_mcbsp3_hwmod,
3245         &omap3xxx_mcbsp4_hwmod,
3246         &omap3xxx_mcbsp5_hwmod,
3247         &omap3xxx_mcbsp2_sidetone_hwmod,
3248         &omap3xxx_mcbsp3_sidetone_hwmod,
3249
3250
3251         /* mcspi class */
3252         &omap34xx_mcspi1,
3253         &omap34xx_mcspi2,
3254         &omap34xx_mcspi3,
3255         &omap34xx_mcspi4,
3256
3257         NULL,
3258 };
3259
3260 /* 3430ES1-only hwmods */
3261 static __initdata struct omap_hwmod *omap3430es1_hwmods[] = {
3262         &omap3430es1_dss_core_hwmod,
3263         NULL
3264 };
3265
3266 /* 3430ES2+-only hwmods */
3267 static __initdata struct omap_hwmod *omap3430es2plus_hwmods[] = {
3268         &omap3xxx_dss_core_hwmod,
3269         &omap3xxx_usbhsotg_hwmod,
3270         NULL
3271 };
3272
3273 /* 34xx-only hwmods (all ES revisions) */
3274 static __initdata struct omap_hwmod *omap34xx_hwmods[] = {
3275         &omap3xxx_iva_hwmod,
3276         &omap34xx_sr1_hwmod,
3277         &omap34xx_sr2_hwmod,
3278         &omap3xxx_mailbox_hwmod,
3279         NULL
3280 };
3281
3282 /* 36xx-only hwmods (all ES revisions) */
3283 static __initdata struct omap_hwmod *omap36xx_hwmods[] = {
3284         &omap3xxx_iva_hwmod,
3285         &omap3xxx_uart4_hwmod,
3286         &omap3xxx_dss_core_hwmod,
3287         &omap36xx_sr1_hwmod,
3288         &omap36xx_sr2_hwmod,
3289         &omap3xxx_usbhsotg_hwmod,
3290         &omap3xxx_mailbox_hwmod,
3291         NULL
3292 };
3293
3294 static __initdata struct omap_hwmod *am35xx_hwmods[] = {
3295         &omap3xxx_dss_core_hwmod, /* XXX ??? */
3296         &am35xx_usbhsotg_hwmod,
3297         NULL
3298 };
3299
3300 int __init omap3xxx_hwmod_init(void)
3301 {
3302         int r;
3303         struct omap_hwmod **h = NULL;
3304         unsigned int rev;
3305
3306         /* Register hwmods common to all OMAP3 */
3307         r = omap_hwmod_register(omap3xxx_hwmods);
3308         if (r < 0)
3309                 return r;
3310
3311         rev = omap_rev();
3312
3313         /*
3314          * Register hwmods common to individual OMAP3 families, all
3315          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3316          * All possible revisions should be included in this conditional.
3317          */
3318         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3319             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3320             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3321                 h = omap34xx_hwmods;
3322         } else if (rev == OMAP3517_REV_ES1_0 || rev == OMAP3517_REV_ES1_1) {
3323                 h = am35xx_hwmods;
3324         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3325                    rev == OMAP3630_REV_ES1_2) {
3326                 h = omap36xx_hwmods;
3327         } else {
3328                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3329                 return -EINVAL;
3330         };
3331
3332         r = omap_hwmod_register(h);
3333         if (r < 0)
3334                 return r;
3335
3336         /*
3337          * Register hwmods specific to certain ES levels of a
3338          * particular family of silicon (e.g., 34xx ES1.0)
3339          */
3340         h = NULL;
3341         if (rev == OMAP3430_REV_ES1_0) {
3342                 h = omap3430es1_hwmods;
3343         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3344                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3345                    rev == OMAP3430_REV_ES3_1_2) {
3346                 h = omap3430es2plus_hwmods;
3347         };
3348
3349         if (h)
3350                 r = omap_hwmod_register(h);
3351
3352         return r;
3353 }