arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2010 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * The data in this file should be completely autogeneratable from
  12  * the TI hardware database or other technical documentation.
  13  *
  14  * XXX these should be marked initdata for multi-OMAP kernels
  15  */
  16 #include <plat/omap_hwmod.h>
  17 #include <mach/irqs.h>
  18 #include <plat/cpu.h>
  19 #include <plat/dma.h>
  20 #include <plat/serial.h>
  21 #include <plat/l4_3xxx.h>
  22 #include <plat/i2c.h>
  23 #include <plat/gpio.h>
  24
  25 #include "omap_hwmod_common_data.h"
  26
  27 #include "prm-regbits-34xx.h"
  28 #include "cm-regbits-34xx.h"
  29
  30 /*
  31  * OMAP3xxx hardware module integration data
  32  *
  33  * ALl of the data in this section should be autogeneratable from the
  34  * TI hardware database or other technical documentation.  Data that
  35  * is driver-specific or driver-kernel integration-specific belongs
  36  * elsewhere.
  37  */
  38
  39 static struct omap_hwmod omap3xxx_mpu_hwmod;
  40 static struct omap_hwmod omap3xxx_iva_hwmod;
  41 static struct omap_hwmod omap3xxx_l3_main_hwmod;
  42 static struct omap_hwmod omap3xxx_l4_core_hwmod;
  43 static struct omap_hwmod omap3xxx_l4_per_hwmod;
  44 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
  45 static struct omap_hwmod omap3xxx_i2c1_hwmod;
  46 static struct omap_hwmod omap3xxx_i2c2_hwmod;
  47 static struct omap_hwmod omap3xxx_i2c3_hwmod;
  48 static struct omap_hwmod omap3xxx_gpio1_hwmod;
  49 static struct omap_hwmod omap3xxx_gpio2_hwmod;
  50 static struct omap_hwmod omap3xxx_gpio3_hwmod;
  51 static struct omap_hwmod omap3xxx_gpio4_hwmod;
  52 static struct omap_hwmod omap3xxx_gpio5_hwmod;
  53 static struct omap_hwmod omap3xxx_gpio6_hwmod;
  54
  55 static struct omap_hwmod omap3xxx_dma_system_hwmod;
  56
  57 /* L3 -> L4_CORE interface */
  58 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
  59         .master = &omap3xxx_l3_main_hwmod,
  60         .slave  = &omap3xxx_l4_core_hwmod,
  61         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  62 };
  63
  64 /* L3 -> L4_PER interface */
  65 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
  66         .master = &omap3xxx_l3_main_hwmod,
  67         .slave  = &omap3xxx_l4_per_hwmod,
  68         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  69 };
  70
  71 /* MPU -> L3 interface */
  72 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
  73         .master = &omap3xxx_mpu_hwmod,
  74         .slave  = &omap3xxx_l3_main_hwmod,
  75         .user   = OCP_USER_MPU,
  76 };
  77
  78 /* Slave interfaces on the L3 interconnect */
  79 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
  80         &omap3xxx_mpu__l3_main,
  81 };
  82
  83 /* Master interfaces on the L3 interconnect */
  84 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
  85         &omap3xxx_l3_main__l4_core,
  86         &omap3xxx_l3_main__l4_per,
  87 };
  88
  89 /* L3 */
  90 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  91         .name           = "l3_main",
  92         .class          = &l3_hwmod_class,
  93         .masters        = omap3xxx_l3_main_masters,
  94         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
  95         .slaves         = omap3xxx_l3_main_slaves,
  96         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l3_main_slaves),
  97         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  98         .flags          = HWMOD_NO_IDLEST,
  99 };
 100
 101 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
 102 static struct omap_hwmod omap3xxx_uart1_hwmod;
 103 static struct omap_hwmod omap3xxx_uart2_hwmod;
 104 static struct omap_hwmod omap3xxx_uart3_hwmod;
 105 static struct omap_hwmod omap3xxx_uart4_hwmod;
 106
 107 /* L4_CORE -> L4_WKUP interface */
 108 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
 109         .master = &omap3xxx_l4_core_hwmod,
 110         .slave  = &omap3xxx_l4_wkup_hwmod,
 111         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 112 };
 113
 114 /* L4 CORE -> UART1 interface */
 115 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
 116         {
 117                 .pa_start       = OMAP3_UART1_BASE,
 118                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
 119                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 120         },
 121 };
 122
 123 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
 124         .master         = &omap3xxx_l4_core_hwmod,
 125         .slave          = &omap3xxx_uart1_hwmod,
 126         .clk            = "uart1_ick",
 127         .addr           = omap3xxx_uart1_addr_space,
 128         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart1_addr_space),
 129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 130 };
 131
 132 /* L4 CORE -> UART2 interface */
 133 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
 134         {
 135                 .pa_start       = OMAP3_UART2_BASE,
 136                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
 137                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 138         },
 139 };
 140
 141 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
 142         .master         = &omap3xxx_l4_core_hwmod,
 143         .slave          = &omap3xxx_uart2_hwmod,
 144         .clk            = "uart2_ick",
 145         .addr           = omap3xxx_uart2_addr_space,
 146         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart2_addr_space),
 147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 148 };
 149
 150 /* L4 PER -> UART3 interface */
 151 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
 152         {
 153                 .pa_start       = OMAP3_UART3_BASE,
 154                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
 155                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 156         },
 157 };
 158
 159 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
 160         .master         = &omap3xxx_l4_per_hwmod,
 161         .slave          = &omap3xxx_uart3_hwmod,
 162         .clk            = "uart3_ick",
 163         .addr           = omap3xxx_uart3_addr_space,
 164         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart3_addr_space),
 165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 166 };
 167
 168 /* L4 PER -> UART4 interface */
 169 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
 170         {
 171                 .pa_start       = OMAP3_UART4_BASE,
 172                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
 173                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
 174         },
 175 };
 176
 177 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
 178         .master         = &omap3xxx_l4_per_hwmod,
 179         .slave          = &omap3xxx_uart4_hwmod,
 180         .clk            = "uart4_ick",
 181         .addr           = omap3xxx_uart4_addr_space,
 182         .addr_cnt       = ARRAY_SIZE(omap3xxx_uart4_addr_space),
 183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 184 };
 185
 186 /* I2C IP block address space length (in bytes) */
 187 #define OMAP2_I2C_AS_LEN                128
 188
 189 /* L4 CORE -> I2C1 interface */
 190 static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
 191         {
 192                 .pa_start       = 0x48070000,
 193                 .pa_end         = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
 194                 .flags          = ADDR_TYPE_RT,
 195         },
 196 };
 197
 198 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
 199         .master         = &omap3xxx_l4_core_hwmod,
 200         .slave          = &omap3xxx_i2c1_hwmod,
 201         .clk            = "i2c1_ick",
 202         .addr           = omap3xxx_i2c1_addr_space,
 203         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
 204         .fw = {
 205                 .omap2 = {
 206                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
 207                         .l4_prot_group = 7,
 208                         .flags  = OMAP_FIREWALL_L4,
 209                 }
 210         },
 211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 212 };
 213
 214 /* L4 CORE -> I2C2 interface */
 215 static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
 216         {
 217                 .pa_start       = 0x48072000,
 218                 .pa_end         = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
 219                 .flags          = ADDR_TYPE_RT,
 220         },
 221 };
 222
 223 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
 224         .master         = &omap3xxx_l4_core_hwmod,
 225         .slave          = &omap3xxx_i2c2_hwmod,
 226         .clk            = "i2c2_ick",
 227         .addr           = omap3xxx_i2c2_addr_space,
 228         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
 229         .fw = {
 230                 .omap2 = {
 231                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
 232                         .l4_prot_group = 7,
 233                         .flags = OMAP_FIREWALL_L4,
 234                 }
 235         },
 236         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 237 };
 238
 239 /* L4 CORE -> I2C3 interface */
 240 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
 241         {
 242                 .pa_start       = 0x48060000,
 243                 .pa_end         = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
 244                 .flags          = ADDR_TYPE_RT,
 245         },
 246 };
 247
 248 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
 249         .master         = &omap3xxx_l4_core_hwmod,
 250         .slave          = &omap3xxx_i2c3_hwmod,
 251         .clk            = "i2c3_ick",
 252         .addr           = omap3xxx_i2c3_addr_space,
 253         .addr_cnt       = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
 254         .fw = {
 255                 .omap2 = {
 256                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
 257                         .l4_prot_group = 7,
 258                         .flags = OMAP_FIREWALL_L4,
 259                 }
 260         },
 261         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 262 };
 263
 264 /* Slave interfaces on the L4_CORE interconnect */
 265 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
 266         &omap3xxx_l3_main__l4_core,
 267 };
 268
 269 /* Master interfaces on the L4_CORE interconnect */
 270 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
 271         &omap3xxx_l4_core__l4_wkup,
 272         &omap3_l4_core__uart1,
 273         &omap3_l4_core__uart2,
 274         &omap3_l4_core__i2c1,
 275         &omap3_l4_core__i2c2,
 276         &omap3_l4_core__i2c3,
 277 };
 278
 279 /* L4 CORE */
 280 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
 281         .name           = "l4_core",
 282         .class          = &l4_hwmod_class,
 283         .masters        = omap3xxx_l4_core_masters,
 284         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
 285         .slaves         = omap3xxx_l4_core_slaves,
 286         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
 287         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 288         .flags          = HWMOD_NO_IDLEST,
 289 };
 290
 291 /* Slave interfaces on the L4_PER interconnect */
 292 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
 293         &omap3xxx_l3_main__l4_per,
 294 };
 295
 296 /* Master interfaces on the L4_PER interconnect */
 297 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
 298         &omap3_l4_per__uart3,
 299         &omap3_l4_per__uart4,
 300 };
 301
 302 /* L4 PER */
 303 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
 304         .name           = "l4_per",
 305         .class          = &l4_hwmod_class,
 306         .masters        = omap3xxx_l4_per_masters,
 307         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
 308         .slaves         = omap3xxx_l4_per_slaves,
 309         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
 310         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 311         .flags          = HWMOD_NO_IDLEST,
 312 };
 313
 314 /* Slave interfaces on the L4_WKUP interconnect */
 315 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
 316         &omap3xxx_l4_core__l4_wkup,
 317 };
 318
 319 /* Master interfaces on the L4_WKUP interconnect */
 320 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
 321 };
 322
 323 /* L4 WKUP */
 324 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
 325         .name           = "l4_wkup",
 326         .class          = &l4_hwmod_class,
 327         .masters        = omap3xxx_l4_wkup_masters,
 328         .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
 329         .slaves         = omap3xxx_l4_wkup_slaves,
 330         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
 331         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 332         .flags          = HWMOD_NO_IDLEST,
 333 };
 334
 335 /* Master interfaces on the MPU device */
 336 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
 337         &omap3xxx_mpu__l3_main,
 338 };
 339
 340 /* MPU */
 341 static struct omap_hwmod omap3xxx_mpu_hwmod = {
 342         .name           = "mpu",
 343         .class          = &mpu_hwmod_class,
 344         .main_clk       = "arm_fck",
 345         .masters        = omap3xxx_mpu_masters,
 346         .masters_cnt    = ARRAY_SIZE(omap3xxx_mpu_masters),
 347         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 348 };
 349
 350 /*
 351  * IVA2_2 interface data
 352  */
 353
 354 /* IVA2 <- L3 interface */
 355 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
 356         .master         = &omap3xxx_l3_main_hwmod,
 357         .slave          = &omap3xxx_iva_hwmod,
 358         .clk            = "iva2_ck",
 359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 360 };
 361
 362 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
 363         &omap3xxx_l3__iva,
 364 };
 365
 366 /*
 367  * IVA2 (IVA2)
 368  */
 369
 370 static struct omap_hwmod omap3xxx_iva_hwmod = {
 371         .name           = "iva",
 372         .class          = &iva_hwmod_class,
 373         .masters        = omap3xxx_iva_masters,
 374         .masters_cnt    = ARRAY_SIZE(omap3xxx_iva_masters),
 375         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 376 };
 377
 378 /* l4_wkup -> wd_timer2 */
 379 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
 380         {
 381                 .pa_start       = 0x48314000,
 382                 .pa_end         = 0x4831407f,
 383                 .flags          = ADDR_TYPE_RT
 384         },
 385 };
 386
 387 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
 388         .master         = &omap3xxx_l4_wkup_hwmod,
 389         .slave          = &omap3xxx_wd_timer2_hwmod,
 390         .clk            = "wdt2_ick",
 391         .addr           = omap3xxx_wd_timer2_addrs,
 392         .addr_cnt       = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
 393         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 394 };
 395
 396 /*
 397  * 'wd_timer' class
 398  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 399  * overflow condition
 400  */
 401
 402 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 403         .rev_offs       = 0x0000,
 404         .sysc_offs      = 0x0010,
 405         .syss_offs      = 0x0014,
 406         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 407                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 408                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY),
 409         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 410         .sysc_fields    = &omap_hwmod_sysc_type1,
 411 };
 412
 413 /* I2C common */
 414 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 415         .rev_offs       = 0x00,
 416         .sysc_offs      = 0x20,
 417         .syss_offs      = 0x10,
 418         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 419                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 420                            SYSC_HAS_AUTOIDLE),
 421         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 422         .sysc_fields    = &omap_hwmod_sysc_type1,
 423 };
 424
 425 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 426         .name = "wd_timer",
 427         .sysc = &omap3xxx_wd_timer_sysc,
 428 };
 429
 430 /* wd_timer2 */
 431 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
 432         &omap3xxx_l4_wkup__wd_timer2,
 433 };
 434
 435 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 436         .name           = "wd_timer2",
 437         .class          = &omap3xxx_wd_timer_hwmod_class,
 438         .main_clk       = "wdt2_fck",
 439         .prcm           = {
 440                 .omap2 = {
 441                         .prcm_reg_id = 1,
 442                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 443                         .module_offs = WKUP_MOD,
 444                         .idlest_reg_id = 1,
 445                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 446                 },
 447         },
 448         .slaves         = omap3xxx_wd_timer2_slaves,
 449         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
 450         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 451 };
 452
 453 /* UART common */
 454
 455 static struct omap_hwmod_class_sysconfig uart_sysc = {
 456         .rev_offs       = 0x50,
 457         .sysc_offs      = 0x54,
 458         .syss_offs      = 0x58,
 459         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 460                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 461                            SYSC_HAS_AUTOIDLE),
 462         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 463         .sysc_fields    = &omap_hwmod_sysc_type1,
 464 };
 465
 466 static struct omap_hwmod_class uart_class = {
 467         .name = "uart",
 468         .sysc = &uart_sysc,
 469 };
 470
 471 /* UART1 */
 472
 473 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
 474         { .irq = INT_24XX_UART1_IRQ, },
 475 };
 476
 477 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 478         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 479         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 480 };
 481
 482 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
 483         &omap3_l4_core__uart1,
 484 };
 485
 486 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 487         .name           = "uart1",
 488         .mpu_irqs       = uart1_mpu_irqs,
 489         .mpu_irqs_cnt   = ARRAY_SIZE(uart1_mpu_irqs),
 490         .sdma_reqs      = uart1_sdma_reqs,
 491         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 492         .main_clk       = "uart1_fck",
 493         .prcm           = {
 494                 .omap2 = {
 495                         .module_offs = CORE_MOD,
 496                         .prcm_reg_id = 1,
 497                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 498                         .idlest_reg_id = 1,
 499                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 500                 },
 501         },
 502         .slaves         = omap3xxx_uart1_slaves,
 503         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart1_slaves),
 504         .class          = &uart_class,
 505         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 506 };
 507
 508 /* UART2 */
 509
 510 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
 511         { .irq = INT_24XX_UART2_IRQ, },
 512 };
 513
 514 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 515         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 516         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 517 };
 518
 519 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
 520         &omap3_l4_core__uart2,
 521 };
 522
 523 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 524         .name           = "uart2",
 525         .mpu_irqs       = uart2_mpu_irqs,
 526         .mpu_irqs_cnt   = ARRAY_SIZE(uart2_mpu_irqs),
 527         .sdma_reqs      = uart2_sdma_reqs,
 528         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 529         .main_clk       = "uart2_fck",
 530         .prcm           = {
 531                 .omap2 = {
 532                         .module_offs = CORE_MOD,
 533                         .prcm_reg_id = 1,
 534                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 535                         .idlest_reg_id = 1,
 536                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 537                 },
 538         },
 539         .slaves         = omap3xxx_uart2_slaves,
 540         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart2_slaves),
 541         .class          = &uart_class,
 542         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 543 };
 544
 545 /* UART3 */
 546
 547 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
 548         { .irq = INT_24XX_UART3_IRQ, },
 549 };
 550
 551 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 552         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 553         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 554 };
 555
 556 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
 557         &omap3_l4_per__uart3,
 558 };
 559
 560 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 561         .name           = "uart3",
 562         .mpu_irqs       = uart3_mpu_irqs,
 563         .mpu_irqs_cnt   = ARRAY_SIZE(uart3_mpu_irqs),
 564         .sdma_reqs      = uart3_sdma_reqs,
 565         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 566         .main_clk       = "uart3_fck",
 567         .prcm           = {
 568                 .omap2 = {
 569                         .module_offs = OMAP3430_PER_MOD,
 570                         .prcm_reg_id = 1,
 571                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 572                         .idlest_reg_id = 1,
 573                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 574                 },
 575         },
 576         .slaves         = omap3xxx_uart3_slaves,
 577         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart3_slaves),
 578         .class          = &uart_class,
 579         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 580 };
 581
 582 /* UART4 */
 583
 584 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 585         { .irq = INT_36XX_UART4_IRQ, },
 586 };
 587
 588 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 589         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 590         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 591 };
 592
 593 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
 594         &omap3_l4_per__uart4,
 595 };
 596
 597 static struct omap_hwmod omap3xxx_uart4_hwmod = {
 598         .name           = "uart4",
 599         .mpu_irqs       = uart4_mpu_irqs,
 600         .mpu_irqs_cnt   = ARRAY_SIZE(uart4_mpu_irqs),
 601         .sdma_reqs      = uart4_sdma_reqs,
 602         .sdma_reqs_cnt  = ARRAY_SIZE(uart4_sdma_reqs),
 603         .main_clk       = "uart4_fck",
 604         .prcm           = {
 605                 .omap2 = {
 606                         .module_offs = OMAP3430_PER_MOD,
 607                         .prcm_reg_id = 1,
 608                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 609                         .idlest_reg_id = 1,
 610                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 611                 },
 612         },
 613         .slaves         = omap3xxx_uart4_slaves,
 614         .slaves_cnt     = ARRAY_SIZE(omap3xxx_uart4_slaves),
 615         .class          = &uart_class,
 616         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 617 };
 618
 619 static struct omap_hwmod_class i2c_class = {
 620         .name = "i2c",
 621         .sysc = &i2c_sysc,
 622 };
 623
 624 /* I2C1 */
 625
 626 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 627         .fifo_depth     = 8, /* bytes */
 628 };
 629
 630 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
 631         { .irq = INT_24XX_I2C1_IRQ, },
 632 };
 633
 634 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
 635         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
 636         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
 637 };
 638
 639 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
 640         &omap3_l4_core__i2c1,
 641 };
 642
 643 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 644         .name           = "i2c1",
 645         .mpu_irqs       = i2c1_mpu_irqs,
 646         .mpu_irqs_cnt   = ARRAY_SIZE(i2c1_mpu_irqs),
 647         .sdma_reqs      = i2c1_sdma_reqs,
 648         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
 649         .main_clk       = "i2c1_fck",
 650         .prcm           = {
 651                 .omap2 = {
 652                         .module_offs = CORE_MOD,
 653                         .prcm_reg_id = 1,
 654                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 655                         .idlest_reg_id = 1,
 656                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 657                 },
 658         },
 659         .slaves         = omap3xxx_i2c1_slaves,
 660         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c1_slaves),
 661         .class          = &i2c_class,
 662         .dev_attr       = &i2c1_dev_attr,
 663         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 664 };
 665
 666 /* I2C2 */
 667
 668 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 669         .fifo_depth     = 8, /* bytes */
 670 };
 671
 672 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
 673         { .irq = INT_24XX_I2C2_IRQ, },
 674 };
 675
 676 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
 677         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 678         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 679 };
 680
 681 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
 682         &omap3_l4_core__i2c2,
 683 };
 684
 685 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 686         .name           = "i2c2",
 687         .mpu_irqs       = i2c2_mpu_irqs,
 688         .mpu_irqs_cnt   = ARRAY_SIZE(i2c2_mpu_irqs),
 689         .sdma_reqs      = i2c2_sdma_reqs,
 690         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
 691         .main_clk       = "i2c2_fck",
 692         .prcm           = {
 693                 .omap2 = {
 694                         .module_offs = CORE_MOD,
 695                         .prcm_reg_id = 1,
 696                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 697                         .idlest_reg_id = 1,
 698                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 699                 },
 700         },
 701         .slaves         = omap3xxx_i2c2_slaves,
 702         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c2_slaves),
 703         .class          = &i2c_class,
 704         .dev_attr       = &i2c2_dev_attr,
 705         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 706 };
 707
 708 /* I2C3 */
 709
 710 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 711         .fifo_depth     = 64, /* bytes */
 712 };
 713
 714 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 715         { .irq = INT_34XX_I2C3_IRQ, },
 716 };
 717
 718 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 719         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 720         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 721 };
 722
 723 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
 724         &omap3_l4_core__i2c3,
 725 };
 726
 727 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 728         .name           = "i2c3",
 729         .mpu_irqs       = i2c3_mpu_irqs,
 730         .mpu_irqs_cnt   = ARRAY_SIZE(i2c3_mpu_irqs),
 731         .sdma_reqs      = i2c3_sdma_reqs,
 732         .sdma_reqs_cnt  = ARRAY_SIZE(i2c3_sdma_reqs),
 733         .main_clk       = "i2c3_fck",
 734         .prcm           = {
 735                 .omap2 = {
 736                         .module_offs = CORE_MOD,
 737                         .prcm_reg_id = 1,
 738                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 739                         .idlest_reg_id = 1,
 740                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 741                 },
 742         },
 743         .slaves         = omap3xxx_i2c3_slaves,
 744         .slaves_cnt     = ARRAY_SIZE(omap3xxx_i2c3_slaves),
 745         .class          = &i2c_class,
 746         .dev_attr       = &i2c3_dev_attr,
 747         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 748 };
 749
 750 /* l4_wkup -> gpio1 */
 751 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
 752         {
 753                 .pa_start       = 0x48310000,
 754                 .pa_end         = 0x483101ff,
 755                 .flags          = ADDR_TYPE_RT
 756         },
 757 };
 758
 759 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
 760         .master         = &omap3xxx_l4_wkup_hwmod,
 761         .slave          = &omap3xxx_gpio1_hwmod,
 762         .addr           = omap3xxx_gpio1_addrs,
 763         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio1_addrs),
 764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 765 };
 766
 767 /* l4_per -> gpio2 */
 768 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
 769         {
 770                 .pa_start       = 0x49050000,
 771                 .pa_end         = 0x490501ff,
 772                 .flags          = ADDR_TYPE_RT
 773         },
 774 };
 775
 776 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
 777         .master         = &omap3xxx_l4_per_hwmod,
 778         .slave          = &omap3xxx_gpio2_hwmod,
 779         .addr           = omap3xxx_gpio2_addrs,
 780         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio2_addrs),
 781         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 782 };
 783
 784 /* l4_per -> gpio3 */
 785 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
 786         {
 787                 .pa_start       = 0x49052000,
 788                 .pa_end         = 0x490521ff,
 789                 .flags          = ADDR_TYPE_RT
 790         },
 791 };
 792
 793 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
 794         .master         = &omap3xxx_l4_per_hwmod,
 795         .slave          = &omap3xxx_gpio3_hwmod,
 796         .addr           = omap3xxx_gpio3_addrs,
 797         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio3_addrs),
 798         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 799 };
 800
 801 /* l4_per -> gpio4 */
 802 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
 803         {
 804                 .pa_start       = 0x49054000,
 805                 .pa_end         = 0x490541ff,
 806                 .flags          = ADDR_TYPE_RT
 807         },
 808 };
 809
 810 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
 811         .master         = &omap3xxx_l4_per_hwmod,
 812         .slave          = &omap3xxx_gpio4_hwmod,
 813         .addr           = omap3xxx_gpio4_addrs,
 814         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio4_addrs),
 815         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 816 };
 817
 818 /* l4_per -> gpio5 */
 819 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
 820         {
 821                 .pa_start       = 0x49056000,
 822                 .pa_end         = 0x490561ff,
 823                 .flags          = ADDR_TYPE_RT
 824         },
 825 };
 826
 827 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
 828         .master         = &omap3xxx_l4_per_hwmod,
 829         .slave          = &omap3xxx_gpio5_hwmod,
 830         .addr           = omap3xxx_gpio5_addrs,
 831         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio5_addrs),
 832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 833 };
 834
 835 /* l4_per -> gpio6 */
 836 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
 837         {
 838                 .pa_start       = 0x49058000,
 839                 .pa_end         = 0x490581ff,
 840                 .flags          = ADDR_TYPE_RT
 841         },
 842 };
 843
 844 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
 845         .master         = &omap3xxx_l4_per_hwmod,
 846         .slave          = &omap3xxx_gpio6_hwmod,
 847         .addr           = omap3xxx_gpio6_addrs,
 848         .addr_cnt       = ARRAY_SIZE(omap3xxx_gpio6_addrs),
 849         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 850 };
 851
 852 /*
 853  * 'gpio' class
 854  * general purpose io module
 855  */
 856
 857 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 858         .rev_offs       = 0x0000,
 859         .sysc_offs      = 0x0010,
 860         .syss_offs      = 0x0014,
 861         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 862                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 863         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 864         .sysc_fields    = &omap_hwmod_sysc_type1,
 865 };
 866
 867 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 868         .name = "gpio",
 869         .sysc = &omap3xxx_gpio_sysc,
 870         .rev = 1,
 871 };
 872
 873 /* gpio_dev_attr*/
 874 static struct omap_gpio_dev_attr gpio_dev_attr = {
 875         .bank_width = 32,
 876         .dbck_flag = true,
 877 };
 878
 879 /* gpio1 */
 880 static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
 881         { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
 882 };
 883
 884 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 885         { .role = "dbclk", .clk = "gpio1_dbck", },
 886 };
 887
 888 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
 889         &omap3xxx_l4_wkup__gpio1,
 890 };
 891
 892 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 893         .name           = "gpio1",
 894         .mpu_irqs       = omap3xxx_gpio1_irqs,
 895         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio1_irqs),
 896         .main_clk       = "gpio1_ick",
 897         .opt_clks       = gpio1_opt_clks,
 898         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 899         .prcm           = {
 900                 .omap2 = {
 901                         .prcm_reg_id = 1,
 902                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 903                         .module_offs = WKUP_MOD,
 904                         .idlest_reg_id = 1,
 905                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 906                 },
 907         },
 908         .slaves         = omap3xxx_gpio1_slaves,
 909         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio1_slaves),
 910         .class          = &omap3xxx_gpio_hwmod_class,
 911         .dev_attr       = &gpio_dev_attr,
 912         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 913 };
 914
 915 /* gpio2 */
 916 static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
 917         { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
 918 };
 919
 920 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 921         { .role = "dbclk", .clk = "gpio2_dbck", },
 922 };
 923
 924 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
 925         &omap3xxx_l4_per__gpio2,
 926 };
 927
 928 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 929         .name           = "gpio2",
 930         .mpu_irqs       = omap3xxx_gpio2_irqs,
 931         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio2_irqs),
 932         .main_clk       = "gpio2_ick",
 933         .opt_clks       = gpio2_opt_clks,
 934         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 935         .prcm           = {
 936                 .omap2 = {
 937                         .prcm_reg_id = 1,
 938                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 939                         .module_offs = OMAP3430_PER_MOD,
 940                         .idlest_reg_id = 1,
 941                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 942                 },
 943         },
 944         .slaves         = omap3xxx_gpio2_slaves,
 945         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio2_slaves),
 946         .class          = &omap3xxx_gpio_hwmod_class,
 947         .dev_attr       = &gpio_dev_attr,
 948         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 949 };
 950
 951 /* gpio3 */
 952 static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
 953         { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
 954 };
 955
 956 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 957         { .role = "dbclk", .clk = "gpio3_dbck", },
 958 };
 959
 960 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
 961         &omap3xxx_l4_per__gpio3,
 962 };
 963
 964 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 965         .name           = "gpio3",
 966         .mpu_irqs       = omap3xxx_gpio3_irqs,
 967         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio3_irqs),
 968         .main_clk       = "gpio3_ick",
 969         .opt_clks       = gpio3_opt_clks,
 970         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 971         .prcm           = {
 972                 .omap2 = {
 973                         .prcm_reg_id = 1,
 974                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 975                         .module_offs = OMAP3430_PER_MOD,
 976                         .idlest_reg_id = 1,
 977                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 978                 },
 979         },
 980         .slaves         = omap3xxx_gpio3_slaves,
 981         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio3_slaves),
 982         .class          = &omap3xxx_gpio_hwmod_class,
 983         .dev_attr       = &gpio_dev_attr,
 984         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 985 };
 986
 987 /* gpio4 */
 988 static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
 989         { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
 990 };
 991
 992 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 993         { .role = "dbclk", .clk = "gpio4_dbck", },
 994 };
 995
 996 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
 997         &omap3xxx_l4_per__gpio4,
 998 };
 999
1000 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1001         .name           = "gpio4",
1002         .mpu_irqs       = omap3xxx_gpio4_irqs,
1003         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio4_irqs),
1004         .main_clk       = "gpio4_ick",
1005         .opt_clks       = gpio4_opt_clks,
1006         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1007         .prcm           = {
1008                 .omap2 = {
1009                         .prcm_reg_id = 1,
1010                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1011                         .module_offs = OMAP3430_PER_MOD,
1012                         .idlest_reg_id = 1,
1013                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1014                 },
1015         },
1016         .slaves         = omap3xxx_gpio4_slaves,
1017         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1018         .class          = &omap3xxx_gpio_hwmod_class,
1019         .dev_attr       = &gpio_dev_attr,
1020         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1021 };
1022
1023 /* gpio5 */
1024 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1025         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1026 };
1027
1028 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1029         { .role = "dbclk", .clk = "gpio5_dbck", },
1030 };
1031
1032 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1033         &omap3xxx_l4_per__gpio5,
1034 };
1035
1036 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1037         .name           = "gpio5",
1038         .mpu_irqs       = omap3xxx_gpio5_irqs,
1039         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio5_irqs),
1040         .main_clk       = "gpio5_ick",
1041         .opt_clks       = gpio5_opt_clks,
1042         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1043         .prcm           = {
1044                 .omap2 = {
1045                         .prcm_reg_id = 1,
1046                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1047                         .module_offs = OMAP3430_PER_MOD,
1048                         .idlest_reg_id = 1,
1049                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1050                 },
1051         },
1052         .slaves         = omap3xxx_gpio5_slaves,
1053         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio5_slaves),
1054         .class          = &omap3xxx_gpio_hwmod_class,
1055         .dev_attr       = &gpio_dev_attr,
1056         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1057 };
1058
1059 /* gpio6 */
1060 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1061         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1062 };
1063
1064 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1065         { .role = "dbclk", .clk = "gpio6_dbck", },
1066 };
1067
1068 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
1069         &omap3xxx_l4_per__gpio6,
1070 };
1071
1072 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1073         .name           = "gpio6",
1074         .mpu_irqs       = omap3xxx_gpio6_irqs,
1075         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_gpio6_irqs),
1076         .main_clk       = "gpio6_ick",
1077         .opt_clks       = gpio6_opt_clks,
1078         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1079         .prcm           = {
1080                 .omap2 = {
1081                         .prcm_reg_id = 1,
1082                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1083                         .module_offs = OMAP3430_PER_MOD,
1084                         .idlest_reg_id = 1,
1085                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1086                 },
1087         },
1088         .slaves         = omap3xxx_gpio6_slaves,
1089         .slaves_cnt     = ARRAY_SIZE(omap3xxx_gpio6_slaves),
1090         .class          = &omap3xxx_gpio_hwmod_class,
1091         .dev_attr       = &gpio_dev_attr,
1092         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1093 };
1094
1095 /* dma_system -> L3 */
1096 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
1097         .master         = &omap3xxx_dma_system_hwmod,
1098         .slave          = &omap3xxx_l3_main_hwmod,
1099         .clk            = "core_l3_ick",
1100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1101 };
1102
1103 /* dma attributes */
1104 static struct omap_dma_dev_attr dma_dev_attr = {
1105         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1106                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1107         .lch_count = 32,
1108 };
1109
1110 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1111         .rev_offs       = 0x0000,
1112         .sysc_offs      = 0x002c,
1113         .syss_offs      = 0x0028,
1114         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1115                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1116                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
1117         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1118                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1119         .sysc_fields    = &omap_hwmod_sysc_type1,
1120 };
1121
1122 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1123         .name = "dma",
1124         .sysc = &omap3xxx_dma_sysc,
1125 };
1126
1127 /* dma_system */
1128 static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
1129         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
1130         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
1131         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
1132         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
1133 };
1134
1135 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
1136         {
1137                 .pa_start       = 0x48056000,
1138                 .pa_end         = 0x4a0560ff,
1139                 .flags          = ADDR_TYPE_RT
1140         },
1141 };
1142
1143 /* dma_system master ports */
1144 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
1145         &omap3xxx_dma_system__l3,
1146 };
1147
1148 /* l4_cfg -> dma_system */
1149 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
1150         .master         = &omap3xxx_l4_core_hwmod,
1151         .slave          = &omap3xxx_dma_system_hwmod,
1152         .clk            = "core_l4_ick",
1153         .addr           = omap3xxx_dma_system_addrs,
1154         .addr_cnt       = ARRAY_SIZE(omap3xxx_dma_system_addrs),
1155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1156 };
1157
1158 /* dma_system slave ports */
1159 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
1160         &omap3xxx_l4_core__dma_system,
1161 };
1162
1163 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1164         .name           = "dma",
1165         .class          = &omap3xxx_dma_hwmod_class,
1166         .mpu_irqs       = omap3xxx_dma_system_irqs,
1167         .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_dma_system_irqs),
1168         .main_clk       = "core_l3_ick",
1169         .prcm = {
1170                 .omap2 = {
1171                         .module_offs            = CORE_MOD,
1172                         .prcm_reg_id            = 1,
1173                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1174                         .idlest_reg_id          = 1,
1175                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1176                 },
1177         },
1178         .slaves         = omap3xxx_dma_system_slaves,
1179         .slaves_cnt     = ARRAY_SIZE(omap3xxx_dma_system_slaves),
1180         .masters        = omap3xxx_dma_system_masters,
1181         .masters_cnt    = ARRAY_SIZE(omap3xxx_dma_system_masters),
1182         .dev_attr       = &dma_dev_attr,
1183         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1184         .flags          = HWMOD_NO_IDLEST,
1185 };
1186
1187 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
1188         &omap3xxx_l3_main_hwmod,
1189         &omap3xxx_l4_core_hwmod,
1190         &omap3xxx_l4_per_hwmod,
1191         &omap3xxx_l4_wkup_hwmod,
1192         &omap3xxx_mpu_hwmod,
1193         &omap3xxx_iva_hwmod,
1194         &omap3xxx_wd_timer2_hwmod,
1195         &omap3xxx_uart1_hwmod,
1196         &omap3xxx_uart2_hwmod,
1197         &omap3xxx_uart3_hwmod,
1198         &omap3xxx_uart4_hwmod,
1199         &omap3xxx_i2c1_hwmod,
1200         &omap3xxx_i2c2_hwmod,
1201         &omap3xxx_i2c3_hwmod,
1202
1203         /* gpio class */
1204         &omap3xxx_gpio1_hwmod,
1205         &omap3xxx_gpio2_hwmod,
1206         &omap3xxx_gpio3_hwmod,
1207         &omap3xxx_gpio4_hwmod,
1208         &omap3xxx_gpio5_hwmod,
1209         &omap3xxx_gpio6_hwmod,
1210
1211         /* dma_system class*/
1212         &omap3xxx_dma_system_hwmod,
1213         NULL,
1214 };
1215
1216 int __init omap3xxx_hwmod_init(void)
1217 {
1218         return omap_hwmod_init(omap3xxx_hwmods);
1219 }