2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod_common_data.h"
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
35 #include <mach/am35xx.h>
38 * OMAP3xxx hardware module integration data
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
90 .master = &omap3xxx_l3_main_hwmod,
91 .slave = &omap3xxx_l4_core_hwmod,
92 .user = OCP_USER_MPU | OCP_USER_SDMA,
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
97 .master = &omap3xxx_l3_main_hwmod,
98 .slave = &omap3xxx_l4_per_hwmod,
99 .user = OCP_USER_MPU | OCP_USER_SDMA,
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ },
109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
118 /* MPU -> L3 interface */
119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
120 .master = &omap3xxx_mpu_hwmod,
121 .slave = &omap3xxx_l3_main_hwmod,
122 .addr = omap3xxx_l3_main_addrs,
123 .user = OCP_USER_MPU,
126 /* Slave interfaces on the L3 interconnect */
127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
128 &omap3xxx_mpu__l3_main,
132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
133 .master = &omap3xxx_dss_core_hwmod,
134 .slave = &omap3xxx_l3_main_hwmod,
137 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
138 .flags = OMAP_FIREWALL_L3,
141 .user = OCP_USER_MPU | OCP_USER_SDMA,
144 /* Master interfaces on the L3 interconnect */
145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
146 &omap3xxx_l3_main__l4_core,
147 &omap3xxx_l3_main__l4_per,
151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves,
158 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
160 .flags = HWMOD_NO_IDLEST,
163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
164 static struct omap_hwmod omap3xxx_uart1_hwmod;
165 static struct omap_hwmod omap3xxx_uart2_hwmod;
166 static struct omap_hwmod omap3xxx_uart3_hwmod;
167 static struct omap_hwmod omap3xxx_uart4_hwmod;
168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
170 /* l3_core -> usbhsotg interface */
171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
172 .master = &omap3xxx_usbhsotg_hwmod,
173 .slave = &omap3xxx_l3_main_hwmod,
174 .clk = "core_l3_ick",
175 .user = OCP_USER_MPU,
178 /* l3_core -> am35xx_usbhsotg interface */
179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
180 .master = &am35xx_usbhsotg_hwmod,
181 .slave = &omap3xxx_l3_main_hwmod,
182 .clk = "core_l3_ick",
183 .user = OCP_USER_MPU,
185 /* L4_CORE -> L4_WKUP interface */
186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
187 .master = &omap3xxx_l4_core_hwmod,
188 .slave = &omap3xxx_l4_wkup_hwmod,
189 .user = OCP_USER_MPU | OCP_USER_SDMA,
192 /* L4 CORE -> MMC1 interface */
193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
194 .master = &omap3xxx_l4_core_hwmod,
195 .slave = &omap3xxx_mmc1_hwmod,
197 .addr = omap2430_mmc1_addr_space,
198 .user = OCP_USER_MPU | OCP_USER_SDMA,
199 .flags = OMAP_FIREWALL_L4
202 /* L4 CORE -> MMC2 interface */
203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
204 .master = &omap3xxx_l4_core_hwmod,
205 .slave = &omap3xxx_mmc2_hwmod,
207 .addr = omap2430_mmc2_addr_space,
208 .user = OCP_USER_MPU | OCP_USER_SDMA,
209 .flags = OMAP_FIREWALL_L4
212 /* L4 CORE -> MMC3 interface */
213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
215 .pa_start = 0x480ad000,
216 .pa_end = 0x480ad1ff,
217 .flags = ADDR_TYPE_RT,
222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
223 .master = &omap3xxx_l4_core_hwmod,
224 .slave = &omap3xxx_mmc3_hwmod,
226 .addr = omap3xxx_mmc3_addr_space,
227 .user = OCP_USER_MPU | OCP_USER_SDMA,
228 .flags = OMAP_FIREWALL_L4
231 /* L4 CORE -> UART1 interface */
232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
234 .pa_start = OMAP3_UART1_BASE,
235 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
242 .master = &omap3xxx_l4_core_hwmod,
243 .slave = &omap3xxx_uart1_hwmod,
245 .addr = omap3xxx_uart1_addr_space,
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
249 /* L4 CORE -> UART2 interface */
250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
252 .pa_start = OMAP3_UART2_BASE,
253 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
260 .master = &omap3xxx_l4_core_hwmod,
261 .slave = &omap3xxx_uart2_hwmod,
263 .addr = omap3xxx_uart2_addr_space,
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
267 /* L4 PER -> UART3 interface */
268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
270 .pa_start = OMAP3_UART3_BASE,
271 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
278 .master = &omap3xxx_l4_per_hwmod,
279 .slave = &omap3xxx_uart3_hwmod,
281 .addr = omap3xxx_uart3_addr_space,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
285 /* L4 PER -> UART4 interface */
286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
288 .pa_start = OMAP3_UART4_BASE,
289 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
296 .master = &omap3xxx_l4_per_hwmod,
297 .slave = &omap3xxx_uart4_hwmod,
299 .addr = omap3xxx_uart4_addr_space,
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
303 /* L4 CORE -> I2C1 interface */
304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
305 .master = &omap3xxx_l4_core_hwmod,
306 .slave = &omap3xxx_i2c1_hwmod,
308 .addr = omap2_i2c1_addr_space,
311 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
313 .flags = OMAP_FIREWALL_L4,
316 .user = OCP_USER_MPU | OCP_USER_SDMA,
319 /* L4 CORE -> I2C2 interface */
320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
321 .master = &omap3xxx_l4_core_hwmod,
322 .slave = &omap3xxx_i2c2_hwmod,
324 .addr = omap2_i2c2_addr_space,
327 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
329 .flags = OMAP_FIREWALL_L4,
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
335 /* L4 CORE -> I2C3 interface */
336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
338 .pa_start = 0x48060000,
339 .pa_end = 0x48060000 + SZ_128 - 1,
340 .flags = ADDR_TYPE_RT,
345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
346 .master = &omap3xxx_l4_core_hwmod,
347 .slave = &omap3xxx_i2c3_hwmod,
349 .addr = omap3xxx_i2c3_addr_space,
352 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
354 .flags = OMAP_FIREWALL_L4,
357 .user = OCP_USER_MPU | OCP_USER_SDMA,
360 /* L4 CORE -> SR1 interface */
361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
363 .pa_start = OMAP34XX_SR1_BASE,
364 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
365 .flags = ADDR_TYPE_RT,
370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
371 .master = &omap3xxx_l4_core_hwmod,
372 .slave = &omap34xx_sr1_hwmod,
374 .addr = omap3_sr1_addr_space,
375 .user = OCP_USER_MPU,
378 /* L4 CORE -> SR1 interface */
379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
381 .pa_start = OMAP34XX_SR2_BASE,
382 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
383 .flags = ADDR_TYPE_RT,
388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
389 .master = &omap3xxx_l4_core_hwmod,
390 .slave = &omap34xx_sr2_hwmod,
392 .addr = omap3_sr2_addr_space,
393 .user = OCP_USER_MPU,
397 * usbhsotg interface data
400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
402 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
403 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
404 .flags = ADDR_TYPE_RT
409 /* l4_core -> usbhsotg */
410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
411 .master = &omap3xxx_l4_core_hwmod,
412 .slave = &omap3xxx_usbhsotg_hwmod,
414 .addr = omap3xxx_usbhsotg_addrs,
415 .user = OCP_USER_MPU,
418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
419 &omap3xxx_usbhsotg__l3,
422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
423 &omap3xxx_l4_core__usbhsotg,
426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
428 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
429 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
430 .flags = ADDR_TYPE_RT
435 /* l4_core -> usbhsotg */
436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
437 .master = &omap3xxx_l4_core_hwmod,
438 .slave = &am35xx_usbhsotg_hwmod,
440 .addr = am35xx_usbhsotg_addrs,
441 .user = OCP_USER_MPU,
444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
445 &am35xx_usbhsotg__l3,
448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
449 &am35xx_l4_core__usbhsotg,
451 /* Slave interfaces on the L4_CORE interconnect */
452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
453 &omap3xxx_l3_main__l4_core,
457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
459 .class = &l4_hwmod_class,
460 .slaves = omap3xxx_l4_core_slaves,
461 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
462 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
463 .flags = HWMOD_NO_IDLEST,
466 /* Slave interfaces on the L4_PER interconnect */
467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
468 &omap3xxx_l3_main__l4_per,
472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
474 .class = &l4_hwmod_class,
475 .slaves = omap3xxx_l4_per_slaves,
476 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
477 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
478 .flags = HWMOD_NO_IDLEST,
481 /* Slave interfaces on the L4_WKUP interconnect */
482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
483 &omap3xxx_l4_core__l4_wkup,
487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
489 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_wkup_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
493 .flags = HWMOD_NO_IDLEST,
496 /* Master interfaces on the MPU device */
497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
498 &omap3xxx_mpu__l3_main,
502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
504 .class = &mpu_hwmod_class,
505 .main_clk = "arm_fck",
506 .masters = omap3xxx_mpu_masters,
507 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
512 * IVA2_2 interface data
515 /* IVA2 <- L3 interface */
516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
517 .master = &omap3xxx_l3_main_hwmod,
518 .slave = &omap3xxx_iva_hwmod,
520 .user = OCP_USER_MPU | OCP_USER_SDMA,
523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
531 static struct omap_hwmod omap3xxx_iva_hwmod = {
533 .class = &iva_hwmod_class,
534 .masters = omap3xxx_iva_masters,
535 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
536 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
544 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
545 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
546 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
548 .sysc_fields = &omap_hwmod_sysc_type1,
551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
553 .sysc = &omap3xxx_timer_1ms_sysc,
554 .rev = OMAP_TIMER_IP_VERSION_1,
557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
561 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
562 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
564 .sysc_fields = &omap_hwmod_sysc_type1,
567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
569 .sysc = &omap3xxx_timer_sysc,
570 .rev = OMAP_TIMER_IP_VERSION_1,
574 static struct omap_hwmod omap3xxx_timer1_hwmod;
576 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
578 .pa_start = 0x48318000,
579 .pa_end = 0x48318000 + SZ_1K - 1,
580 .flags = ADDR_TYPE_RT
585 /* l4_wkup -> timer1 */
586 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
587 .master = &omap3xxx_l4_wkup_hwmod,
588 .slave = &omap3xxx_timer1_hwmod,
590 .addr = omap3xxx_timer1_addrs,
591 .user = OCP_USER_MPU | OCP_USER_SDMA,
594 /* timer1 slave port */
595 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
596 &omap3xxx_l4_wkup__timer1,
600 static struct omap_hwmod omap3xxx_timer1_hwmod = {
602 .mpu_irqs = omap2_timer1_mpu_irqs,
603 .main_clk = "gpt1_fck",
607 .module_bit = OMAP3430_EN_GPT1_SHIFT,
608 .module_offs = WKUP_MOD,
610 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
613 .slaves = omap3xxx_timer1_slaves,
614 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
615 .class = &omap3xxx_timer_1ms_hwmod_class,
616 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
620 static struct omap_hwmod omap3xxx_timer2_hwmod;
622 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
624 .pa_start = 0x49032000,
625 .pa_end = 0x49032000 + SZ_1K - 1,
626 .flags = ADDR_TYPE_RT
631 /* l4_per -> timer2 */
632 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
633 .master = &omap3xxx_l4_per_hwmod,
634 .slave = &omap3xxx_timer2_hwmod,
636 .addr = omap3xxx_timer2_addrs,
637 .user = OCP_USER_MPU | OCP_USER_SDMA,
640 /* timer2 slave port */
641 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
642 &omap3xxx_l4_per__timer2,
646 static struct omap_hwmod omap3xxx_timer2_hwmod = {
648 .mpu_irqs = omap2_timer2_mpu_irqs,
649 .main_clk = "gpt2_fck",
653 .module_bit = OMAP3430_EN_GPT2_SHIFT,
654 .module_offs = OMAP3430_PER_MOD,
656 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
659 .slaves = omap3xxx_timer2_slaves,
660 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
661 .class = &omap3xxx_timer_1ms_hwmod_class,
662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
666 static struct omap_hwmod omap3xxx_timer3_hwmod;
668 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
670 .pa_start = 0x49034000,
671 .pa_end = 0x49034000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
677 /* l4_per -> timer3 */
678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
679 .master = &omap3xxx_l4_per_hwmod,
680 .slave = &omap3xxx_timer3_hwmod,
682 .addr = omap3xxx_timer3_addrs,
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
686 /* timer3 slave port */
687 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
688 &omap3xxx_l4_per__timer3,
692 static struct omap_hwmod omap3xxx_timer3_hwmod = {
694 .mpu_irqs = omap2_timer3_mpu_irqs,
695 .main_clk = "gpt3_fck",
699 .module_bit = OMAP3430_EN_GPT3_SHIFT,
700 .module_offs = OMAP3430_PER_MOD,
702 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
705 .slaves = omap3xxx_timer3_slaves,
706 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
707 .class = &omap3xxx_timer_hwmod_class,
708 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
712 static struct omap_hwmod omap3xxx_timer4_hwmod;
714 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
716 .pa_start = 0x49036000,
717 .pa_end = 0x49036000 + SZ_1K - 1,
718 .flags = ADDR_TYPE_RT
723 /* l4_per -> timer4 */
724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
725 .master = &omap3xxx_l4_per_hwmod,
726 .slave = &omap3xxx_timer4_hwmod,
728 .addr = omap3xxx_timer4_addrs,
729 .user = OCP_USER_MPU | OCP_USER_SDMA,
732 /* timer4 slave port */
733 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
734 &omap3xxx_l4_per__timer4,
738 static struct omap_hwmod omap3xxx_timer4_hwmod = {
740 .mpu_irqs = omap2_timer4_mpu_irqs,
741 .main_clk = "gpt4_fck",
745 .module_bit = OMAP3430_EN_GPT4_SHIFT,
746 .module_offs = OMAP3430_PER_MOD,
748 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
751 .slaves = omap3xxx_timer4_slaves,
752 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
753 .class = &omap3xxx_timer_hwmod_class,
754 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
758 static struct omap_hwmod omap3xxx_timer5_hwmod;
760 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
762 .pa_start = 0x49038000,
763 .pa_end = 0x49038000 + SZ_1K - 1,
764 .flags = ADDR_TYPE_RT
769 /* l4_per -> timer5 */
770 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
771 .master = &omap3xxx_l4_per_hwmod,
772 .slave = &omap3xxx_timer5_hwmod,
774 .addr = omap3xxx_timer5_addrs,
775 .user = OCP_USER_MPU | OCP_USER_SDMA,
778 /* timer5 slave port */
779 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
780 &omap3xxx_l4_per__timer5,
784 static struct omap_hwmod omap3xxx_timer5_hwmod = {
786 .mpu_irqs = omap2_timer5_mpu_irqs,
787 .main_clk = "gpt5_fck",
791 .module_bit = OMAP3430_EN_GPT5_SHIFT,
792 .module_offs = OMAP3430_PER_MOD,
794 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
797 .slaves = omap3xxx_timer5_slaves,
798 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
799 .class = &omap3xxx_timer_hwmod_class,
800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
804 static struct omap_hwmod omap3xxx_timer6_hwmod;
806 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
808 .pa_start = 0x4903A000,
809 .pa_end = 0x4903A000 + SZ_1K - 1,
810 .flags = ADDR_TYPE_RT
815 /* l4_per -> timer6 */
816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
817 .master = &omap3xxx_l4_per_hwmod,
818 .slave = &omap3xxx_timer6_hwmod,
820 .addr = omap3xxx_timer6_addrs,
821 .user = OCP_USER_MPU | OCP_USER_SDMA,
824 /* timer6 slave port */
825 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
826 &omap3xxx_l4_per__timer6,
830 static struct omap_hwmod omap3xxx_timer6_hwmod = {
832 .mpu_irqs = omap2_timer6_mpu_irqs,
833 .main_clk = "gpt6_fck",
837 .module_bit = OMAP3430_EN_GPT6_SHIFT,
838 .module_offs = OMAP3430_PER_MOD,
840 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
843 .slaves = omap3xxx_timer6_slaves,
844 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
845 .class = &omap3xxx_timer_hwmod_class,
846 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
850 static struct omap_hwmod omap3xxx_timer7_hwmod;
852 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
854 .pa_start = 0x4903C000,
855 .pa_end = 0x4903C000 + SZ_1K - 1,
856 .flags = ADDR_TYPE_RT
861 /* l4_per -> timer7 */
862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
863 .master = &omap3xxx_l4_per_hwmod,
864 .slave = &omap3xxx_timer7_hwmod,
866 .addr = omap3xxx_timer7_addrs,
867 .user = OCP_USER_MPU | OCP_USER_SDMA,
870 /* timer7 slave port */
871 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
872 &omap3xxx_l4_per__timer7,
876 static struct omap_hwmod omap3xxx_timer7_hwmod = {
878 .mpu_irqs = omap2_timer7_mpu_irqs,
879 .main_clk = "gpt7_fck",
883 .module_bit = OMAP3430_EN_GPT7_SHIFT,
884 .module_offs = OMAP3430_PER_MOD,
886 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
889 .slaves = omap3xxx_timer7_slaves,
890 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
891 .class = &omap3xxx_timer_hwmod_class,
892 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
896 static struct omap_hwmod omap3xxx_timer8_hwmod;
898 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
900 .pa_start = 0x4903E000,
901 .pa_end = 0x4903E000 + SZ_1K - 1,
902 .flags = ADDR_TYPE_RT
907 /* l4_per -> timer8 */
908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
909 .master = &omap3xxx_l4_per_hwmod,
910 .slave = &omap3xxx_timer8_hwmod,
912 .addr = omap3xxx_timer8_addrs,
913 .user = OCP_USER_MPU | OCP_USER_SDMA,
916 /* timer8 slave port */
917 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
918 &omap3xxx_l4_per__timer8,
922 static struct omap_hwmod omap3xxx_timer8_hwmod = {
924 .mpu_irqs = omap2_timer8_mpu_irqs,
925 .main_clk = "gpt8_fck",
929 .module_bit = OMAP3430_EN_GPT8_SHIFT,
930 .module_offs = OMAP3430_PER_MOD,
932 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
935 .slaves = omap3xxx_timer8_slaves,
936 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
937 .class = &omap3xxx_timer_hwmod_class,
938 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
942 static struct omap_hwmod omap3xxx_timer9_hwmod;
944 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
946 .pa_start = 0x49040000,
947 .pa_end = 0x49040000 + SZ_1K - 1,
948 .flags = ADDR_TYPE_RT
953 /* l4_per -> timer9 */
954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
955 .master = &omap3xxx_l4_per_hwmod,
956 .slave = &omap3xxx_timer9_hwmod,
958 .addr = omap3xxx_timer9_addrs,
959 .user = OCP_USER_MPU | OCP_USER_SDMA,
962 /* timer9 slave port */
963 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
964 &omap3xxx_l4_per__timer9,
968 static struct omap_hwmod omap3xxx_timer9_hwmod = {
970 .mpu_irqs = omap2_timer9_mpu_irqs,
971 .main_clk = "gpt9_fck",
975 .module_bit = OMAP3430_EN_GPT9_SHIFT,
976 .module_offs = OMAP3430_PER_MOD,
978 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
981 .slaves = omap3xxx_timer9_slaves,
982 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
983 .class = &omap3xxx_timer_hwmod_class,
984 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
988 static struct omap_hwmod omap3xxx_timer10_hwmod;
990 /* l4_core -> timer10 */
991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
992 .master = &omap3xxx_l4_core_hwmod,
993 .slave = &omap3xxx_timer10_hwmod,
995 .addr = omap2_timer10_addrs,
996 .user = OCP_USER_MPU | OCP_USER_SDMA,
999 /* timer10 slave port */
1000 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1001 &omap3xxx_l4_core__timer10,
1005 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1007 .mpu_irqs = omap2_timer10_mpu_irqs,
1008 .main_clk = "gpt10_fck",
1012 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1013 .module_offs = CORE_MOD,
1015 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1018 .slaves = omap3xxx_timer10_slaves,
1019 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1020 .class = &omap3xxx_timer_1ms_hwmod_class,
1021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1025 static struct omap_hwmod omap3xxx_timer11_hwmod;
1027 /* l4_core -> timer11 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1029 .master = &omap3xxx_l4_core_hwmod,
1030 .slave = &omap3xxx_timer11_hwmod,
1032 .addr = omap2_timer11_addrs,
1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1036 /* timer11 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1038 &omap3xxx_l4_core__timer11,
1042 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1044 .mpu_irqs = omap2_timer11_mpu_irqs,
1045 .main_clk = "gpt11_fck",
1049 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1050 .module_offs = CORE_MOD,
1052 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1055 .slaves = omap3xxx_timer11_slaves,
1056 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1057 .class = &omap3xxx_timer_hwmod_class,
1058 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1062 static struct omap_hwmod omap3xxx_timer12_hwmod;
1063 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1068 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1070 .pa_start = 0x48304000,
1071 .pa_end = 0x48304000 + SZ_1K - 1,
1072 .flags = ADDR_TYPE_RT
1077 /* l4_core -> timer12 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1079 .master = &omap3xxx_l4_core_hwmod,
1080 .slave = &omap3xxx_timer12_hwmod,
1082 .addr = omap3xxx_timer12_addrs,
1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1086 /* timer12 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1088 &omap3xxx_l4_core__timer12,
1092 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1094 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1095 .main_clk = "gpt12_fck",
1099 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1100 .module_offs = WKUP_MOD,
1102 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1105 .slaves = omap3xxx_timer12_slaves,
1106 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1107 .class = &omap3xxx_timer_hwmod_class,
1108 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1111 /* l4_wkup -> wd_timer2 */
1112 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1114 .pa_start = 0x48314000,
1115 .pa_end = 0x4831407f,
1116 .flags = ADDR_TYPE_RT
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1122 .master = &omap3xxx_l4_wkup_hwmod,
1123 .slave = &omap3xxx_wd_timer2_hwmod,
1125 .addr = omap3xxx_wd_timer2_addrs,
1126 .user = OCP_USER_MPU | OCP_USER_SDMA,
1131 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1132 * overflow condition
1135 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1137 .sysc_offs = 0x0010,
1138 .syss_offs = 0x0014,
1139 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1140 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1141 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142 SYSS_HAS_RESET_STATUS),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144 .sysc_fields = &omap_hwmod_sysc_type1,
1148 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1152 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1153 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1154 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1156 .sysc_fields = &omap_hwmod_sysc_type1,
1159 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1161 .sysc = &omap3xxx_wd_timer_sysc,
1162 .pre_shutdown = &omap2_wd_timer_disable
1166 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1167 &omap3xxx_l4_wkup__wd_timer2,
1170 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1171 .name = "wd_timer2",
1172 .class = &omap3xxx_wd_timer_hwmod_class,
1173 .main_clk = "wdt2_fck",
1177 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1178 .module_offs = WKUP_MOD,
1180 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1183 .slaves = omap3xxx_wd_timer2_slaves,
1184 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1185 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1187 * XXX: Use software supervised mode, HW supervised smartidle seems to
1188 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1190 .flags = HWMOD_SWSUP_SIDLE,
1195 static struct omap_hwmod_class_sysconfig uart_sysc = {
1199 .sysc_flags = (SYSC_HAS_SIDLEMODE |
1200 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1201 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1202 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1203 .sysc_fields = &omap_hwmod_sysc_type1,
1206 static struct omap_hwmod_class uart_class = {
1213 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
1214 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
1215 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
1218 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1219 &omap3_l4_core__uart1,
1222 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1224 .mpu_irqs = omap2_uart1_mpu_irqs,
1225 .sdma_reqs = uart1_sdma_reqs,
1226 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
1227 .main_clk = "uart1_fck",
1230 .module_offs = CORE_MOD,
1232 .module_bit = OMAP3430_EN_UART1_SHIFT,
1234 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1237 .slaves = omap3xxx_uart1_slaves,
1238 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1239 .class = &uart_class,
1240 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1245 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
1246 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
1247 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
1250 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1251 &omap3_l4_core__uart2,
1254 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1256 .mpu_irqs = omap2_uart2_mpu_irqs,
1257 .sdma_reqs = uart2_sdma_reqs,
1258 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
1259 .main_clk = "uart2_fck",
1262 .module_offs = CORE_MOD,
1264 .module_bit = OMAP3430_EN_UART2_SHIFT,
1266 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1269 .slaves = omap3xxx_uart2_slaves,
1270 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1271 .class = &uart_class,
1272 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1277 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
1278 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
1279 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
1282 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1283 &omap3_l4_per__uart3,
1286 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1288 .mpu_irqs = omap2_uart3_mpu_irqs,
1289 .sdma_reqs = uart3_sdma_reqs,
1290 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
1291 .main_clk = "uart3_fck",
1294 .module_offs = OMAP3430_PER_MOD,
1296 .module_bit = OMAP3430_EN_UART3_SHIFT,
1298 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1301 .slaves = omap3xxx_uart3_slaves,
1302 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1303 .class = &uart_class,
1304 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1309 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1310 { .irq = INT_36XX_UART4_IRQ, },
1314 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1315 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1316 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1319 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1320 &omap3_l4_per__uart4,
1323 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1325 .mpu_irqs = uart4_mpu_irqs,
1326 .sdma_reqs = uart4_sdma_reqs,
1327 .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
1328 .main_clk = "uart4_fck",
1331 .module_offs = OMAP3430_PER_MOD,
1333 .module_bit = OMAP3630_EN_UART4_SHIFT,
1335 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1338 .slaves = omap3xxx_uart4_slaves,
1339 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1340 .class = &uart_class,
1341 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1344 static struct omap_hwmod_class i2c_class = {
1351 * display sub-system
1354 static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
1356 .sysc_offs = 0x0010,
1357 .syss_offs = 0x0014,
1358 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1359 .sysc_fields = &omap_hwmod_sysc_type1,
1362 static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
1364 .sysc = &omap3xxx_dss_sysc,
1367 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1368 { .name = "dispc", .dma_req = 5 },
1369 { .name = "dsi1", .dma_req = 74 },
1373 /* dss master ports */
1374 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1378 /* l4_core -> dss */
1379 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1380 .master = &omap3xxx_l4_core_hwmod,
1381 .slave = &omap3430es1_dss_core_hwmod,
1383 .addr = omap2_dss_addrs,
1386 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1387 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1388 .flags = OMAP_FIREWALL_L4,
1391 .user = OCP_USER_MPU | OCP_USER_SDMA,
1394 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1395 .master = &omap3xxx_l4_core_hwmod,
1396 .slave = &omap3xxx_dss_core_hwmod,
1398 .addr = omap2_dss_addrs,
1401 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1402 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1403 .flags = OMAP_FIREWALL_L4,
1406 .user = OCP_USER_MPU | OCP_USER_SDMA,
1409 /* dss slave ports */
1410 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1411 &omap3430es1_l4_core__dss,
1414 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1415 &omap3xxx_l4_core__dss,
1418 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1419 { .role = "tv_clk", .clk = "dss_tv_fck" },
1420 { .role = "video_clk", .clk = "dss_96m_fck" },
1421 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1424 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1426 .class = &omap3xxx_dss_hwmod_class,
1427 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1428 .sdma_reqs = omap3xxx_dss_sdma_chs,
1429 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1434 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1435 .module_offs = OMAP3430_DSS_MOD,
1437 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1440 .opt_clks = dss_opt_clks,
1441 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1442 .slaves = omap3430es1_dss_slaves,
1443 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1444 .masters = omap3xxx_dss_masters,
1445 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1446 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1447 .flags = HWMOD_NO_IDLEST,
1450 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1452 .class = &omap3xxx_dss_hwmod_class,
1453 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1454 .sdma_reqs = omap3xxx_dss_sdma_chs,
1455 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
1460 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1461 .module_offs = OMAP3430_DSS_MOD,
1463 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1464 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1467 .opt_clks = dss_opt_clks,
1468 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1469 .slaves = omap3xxx_dss_slaves,
1470 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1471 .masters = omap3xxx_dss_masters,
1472 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1473 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1474 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1479 * display controller
1482 static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
1484 .sysc_offs = 0x0010,
1485 .syss_offs = 0x0014,
1486 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1487 SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
1488 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1489 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1490 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1491 .sysc_fields = &omap_hwmod_sysc_type1,
1494 static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
1496 .sysc = &omap3xxx_dispc_sysc,
1499 /* l4_core -> dss_dispc */
1500 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1501 .master = &omap3xxx_l4_core_hwmod,
1502 .slave = &omap3xxx_dss_dispc_hwmod,
1504 .addr = omap2_dss_dispc_addrs,
1507 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1508 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1509 .flags = OMAP_FIREWALL_L4,
1512 .user = OCP_USER_MPU | OCP_USER_SDMA,
1515 /* dss_dispc slave ports */
1516 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1517 &omap3xxx_l4_core__dss_dispc,
1520 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1521 .name = "dss_dispc",
1522 .class = &omap3xxx_dispc_hwmod_class,
1523 .mpu_irqs = omap2_dispc_irqs,
1524 .main_clk = "dss1_alwon_fck",
1528 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1529 .module_offs = OMAP3430_DSS_MOD,
1532 .slaves = omap3xxx_dss_dispc_slaves,
1533 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1534 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1535 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1536 CHIP_GE_OMAP3630ES1_1),
1537 .flags = HWMOD_NO_IDLEST,
1542 * display serial interface controller
1545 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1549 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1555 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1557 .pa_start = 0x4804FC00,
1558 .pa_end = 0x4804FFFF,
1559 .flags = ADDR_TYPE_RT
1564 /* l4_core -> dss_dsi1 */
1565 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1566 .master = &omap3xxx_l4_core_hwmod,
1567 .slave = &omap3xxx_dss_dsi1_hwmod,
1568 .addr = omap3xxx_dss_dsi1_addrs,
1571 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1572 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1573 .flags = OMAP_FIREWALL_L4,
1576 .user = OCP_USER_MPU | OCP_USER_SDMA,
1579 /* dss_dsi1 slave ports */
1580 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1581 &omap3xxx_l4_core__dss_dsi1,
1584 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1586 .class = &omap3xxx_dsi_hwmod_class,
1587 .mpu_irqs = omap3xxx_dsi1_irqs,
1588 .main_clk = "dss1_alwon_fck",
1592 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1593 .module_offs = OMAP3430_DSS_MOD,
1596 .slaves = omap3xxx_dss_dsi1_slaves,
1597 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1598 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1599 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1600 CHIP_GE_OMAP3630ES1_1),
1601 .flags = HWMOD_NO_IDLEST,
1606 * remote frame buffer interface
1609 static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
1611 .sysc_offs = 0x0010,
1612 .syss_offs = 0x0014,
1613 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1615 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1616 .sysc_fields = &omap_hwmod_sysc_type1,
1619 static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
1621 .sysc = &omap3xxx_rfbi_sysc,
1624 /* l4_core -> dss_rfbi */
1625 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1626 .master = &omap3xxx_l4_core_hwmod,
1627 .slave = &omap3xxx_dss_rfbi_hwmod,
1629 .addr = omap2_dss_rfbi_addrs,
1632 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1633 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1634 .flags = OMAP_FIREWALL_L4,
1637 .user = OCP_USER_MPU | OCP_USER_SDMA,
1640 /* dss_rfbi slave ports */
1641 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1642 &omap3xxx_l4_core__dss_rfbi,
1645 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1647 .class = &omap3xxx_rfbi_hwmod_class,
1648 .main_clk = "dss1_alwon_fck",
1652 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1653 .module_offs = OMAP3430_DSS_MOD,
1656 .slaves = omap3xxx_dss_rfbi_slaves,
1657 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1658 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1659 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1660 CHIP_GE_OMAP3630ES1_1),
1661 .flags = HWMOD_NO_IDLEST,
1669 static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
1673 /* l4_core -> dss_venc */
1674 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1675 .master = &omap3xxx_l4_core_hwmod,
1676 .slave = &omap3xxx_dss_venc_hwmod,
1677 .clk = "dss_tv_fck",
1678 .addr = omap2_dss_venc_addrs,
1681 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1682 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1683 .flags = OMAP_FIREWALL_L4,
1686 .flags = OCPIF_SWSUP_IDLE,
1687 .user = OCP_USER_MPU | OCP_USER_SDMA,
1690 /* dss_venc slave ports */
1691 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1692 &omap3xxx_l4_core__dss_venc,
1695 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1697 .class = &omap3xxx_venc_hwmod_class,
1698 .main_clk = "dss1_alwon_fck",
1702 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1703 .module_offs = OMAP3430_DSS_MOD,
1706 .slaves = omap3xxx_dss_venc_slaves,
1707 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1708 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1709 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1710 CHIP_GE_OMAP3630ES1_1),
1711 .flags = HWMOD_NO_IDLEST,
1716 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1717 .fifo_depth = 8, /* bytes */
1720 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1721 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1722 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1725 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1726 &omap3_l4_core__i2c1,
1729 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1731 .mpu_irqs = omap2_i2c1_mpu_irqs,
1732 .sdma_reqs = i2c1_sdma_reqs,
1733 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
1734 .main_clk = "i2c1_fck",
1737 .module_offs = CORE_MOD,
1739 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1741 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1744 .slaves = omap3xxx_i2c1_slaves,
1745 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1746 .class = &i2c_class,
1747 .dev_attr = &i2c1_dev_attr,
1748 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1753 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1754 .fifo_depth = 8, /* bytes */
1757 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1758 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1759 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1762 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1763 &omap3_l4_core__i2c2,
1766 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1768 .mpu_irqs = omap2_i2c2_mpu_irqs,
1769 .sdma_reqs = i2c2_sdma_reqs,
1770 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
1771 .main_clk = "i2c2_fck",
1774 .module_offs = CORE_MOD,
1776 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1778 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1781 .slaves = omap3xxx_i2c2_slaves,
1782 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1783 .class = &i2c_class,
1784 .dev_attr = &i2c2_dev_attr,
1785 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1790 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1791 .fifo_depth = 64, /* bytes */
1794 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1795 { .irq = INT_34XX_I2C3_IRQ, },
1799 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1800 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1801 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1804 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1805 &omap3_l4_core__i2c3,
1808 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1810 .mpu_irqs = i2c3_mpu_irqs,
1811 .sdma_reqs = i2c3_sdma_reqs,
1812 .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
1813 .main_clk = "i2c3_fck",
1816 .module_offs = CORE_MOD,
1818 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1820 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1823 .slaves = omap3xxx_i2c3_slaves,
1824 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1825 .class = &i2c_class,
1826 .dev_attr = &i2c3_dev_attr,
1827 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1830 /* l4_wkup -> gpio1 */
1831 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1833 .pa_start = 0x48310000,
1834 .pa_end = 0x483101ff,
1835 .flags = ADDR_TYPE_RT
1840 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1841 .master = &omap3xxx_l4_wkup_hwmod,
1842 .slave = &omap3xxx_gpio1_hwmod,
1843 .addr = omap3xxx_gpio1_addrs,
1844 .user = OCP_USER_MPU | OCP_USER_SDMA,
1847 /* l4_per -> gpio2 */
1848 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1850 .pa_start = 0x49050000,
1851 .pa_end = 0x490501ff,
1852 .flags = ADDR_TYPE_RT
1857 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1858 .master = &omap3xxx_l4_per_hwmod,
1859 .slave = &omap3xxx_gpio2_hwmod,
1860 .addr = omap3xxx_gpio2_addrs,
1861 .user = OCP_USER_MPU | OCP_USER_SDMA,
1864 /* l4_per -> gpio3 */
1865 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1867 .pa_start = 0x49052000,
1868 .pa_end = 0x490521ff,
1869 .flags = ADDR_TYPE_RT
1874 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1875 .master = &omap3xxx_l4_per_hwmod,
1876 .slave = &omap3xxx_gpio3_hwmod,
1877 .addr = omap3xxx_gpio3_addrs,
1878 .user = OCP_USER_MPU | OCP_USER_SDMA,
1881 /* l4_per -> gpio4 */
1882 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1884 .pa_start = 0x49054000,
1885 .pa_end = 0x490541ff,
1886 .flags = ADDR_TYPE_RT
1891 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1892 .master = &omap3xxx_l4_per_hwmod,
1893 .slave = &omap3xxx_gpio4_hwmod,
1894 .addr = omap3xxx_gpio4_addrs,
1895 .user = OCP_USER_MPU | OCP_USER_SDMA,
1898 /* l4_per -> gpio5 */
1899 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1901 .pa_start = 0x49056000,
1902 .pa_end = 0x490561ff,
1903 .flags = ADDR_TYPE_RT
1908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1909 .master = &omap3xxx_l4_per_hwmod,
1910 .slave = &omap3xxx_gpio5_hwmod,
1911 .addr = omap3xxx_gpio5_addrs,
1912 .user = OCP_USER_MPU | OCP_USER_SDMA,
1915 /* l4_per -> gpio6 */
1916 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1918 .pa_start = 0x49058000,
1919 .pa_end = 0x490581ff,
1920 .flags = ADDR_TYPE_RT
1925 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1926 .master = &omap3xxx_l4_per_hwmod,
1927 .slave = &omap3xxx_gpio6_hwmod,
1928 .addr = omap3xxx_gpio6_addrs,
1929 .user = OCP_USER_MPU | OCP_USER_SDMA,
1934 * general purpose io module
1937 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1939 .sysc_offs = 0x0010,
1940 .syss_offs = 0x0014,
1941 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1942 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1943 SYSS_HAS_RESET_STATUS),
1944 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1945 .sysc_fields = &omap_hwmod_sysc_type1,
1948 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1950 .sysc = &omap3xxx_gpio_sysc,
1955 static struct omap_gpio_dev_attr gpio_dev_attr = {
1961 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1962 { .role = "dbclk", .clk = "gpio1_dbck", },
1965 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1966 &omap3xxx_l4_wkup__gpio1,
1969 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1971 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1972 .mpu_irqs = omap2_gpio1_irqs,
1973 .main_clk = "gpio1_ick",
1974 .opt_clks = gpio1_opt_clks,
1975 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1979 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1980 .module_offs = WKUP_MOD,
1982 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1985 .slaves = omap3xxx_gpio1_slaves,
1986 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1987 .class = &omap3xxx_gpio_hwmod_class,
1988 .dev_attr = &gpio_dev_attr,
1989 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1993 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1994 { .role = "dbclk", .clk = "gpio2_dbck", },
1997 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1998 &omap3xxx_l4_per__gpio2,
2001 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
2003 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2004 .mpu_irqs = omap2_gpio2_irqs,
2005 .main_clk = "gpio2_ick",
2006 .opt_clks = gpio2_opt_clks,
2007 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
2011 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
2012 .module_offs = OMAP3430_PER_MOD,
2014 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
2017 .slaves = omap3xxx_gpio2_slaves,
2018 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
2019 .class = &omap3xxx_gpio_hwmod_class,
2020 .dev_attr = &gpio_dev_attr,
2021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2025 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
2026 { .role = "dbclk", .clk = "gpio3_dbck", },
2029 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
2030 &omap3xxx_l4_per__gpio3,
2033 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
2035 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2036 .mpu_irqs = omap2_gpio3_irqs,
2037 .main_clk = "gpio3_ick",
2038 .opt_clks = gpio3_opt_clks,
2039 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
2043 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
2044 .module_offs = OMAP3430_PER_MOD,
2046 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
2049 .slaves = omap3xxx_gpio3_slaves,
2050 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
2051 .class = &omap3xxx_gpio_hwmod_class,
2052 .dev_attr = &gpio_dev_attr,
2053 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2057 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2058 { .role = "dbclk", .clk = "gpio4_dbck", },
2061 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
2062 &omap3xxx_l4_per__gpio4,
2065 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
2067 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2068 .mpu_irqs = omap2_gpio4_irqs,
2069 .main_clk = "gpio4_ick",
2070 .opt_clks = gpio4_opt_clks,
2071 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2075 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
2076 .module_offs = OMAP3430_PER_MOD,
2078 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
2081 .slaves = omap3xxx_gpio4_slaves,
2082 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
2083 .class = &omap3xxx_gpio_hwmod_class,
2084 .dev_attr = &gpio_dev_attr,
2085 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2089 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
2090 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
2094 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2095 { .role = "dbclk", .clk = "gpio5_dbck", },
2098 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
2099 &omap3xxx_l4_per__gpio5,
2102 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
2104 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2105 .mpu_irqs = omap3xxx_gpio5_irqs,
2106 .main_clk = "gpio5_ick",
2107 .opt_clks = gpio5_opt_clks,
2108 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2112 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
2113 .module_offs = OMAP3430_PER_MOD,
2115 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
2118 .slaves = omap3xxx_gpio5_slaves,
2119 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2120 .class = &omap3xxx_gpio_hwmod_class,
2121 .dev_attr = &gpio_dev_attr,
2122 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2126 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2127 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2131 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2132 { .role = "dbclk", .clk = "gpio6_dbck", },
2135 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2136 &omap3xxx_l4_per__gpio6,
2139 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2141 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2142 .mpu_irqs = omap3xxx_gpio6_irqs,
2143 .main_clk = "gpio6_ick",
2144 .opt_clks = gpio6_opt_clks,
2145 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2149 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2150 .module_offs = OMAP3430_PER_MOD,
2152 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2155 .slaves = omap3xxx_gpio6_slaves,
2156 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2157 .class = &omap3xxx_gpio_hwmod_class,
2158 .dev_attr = &gpio_dev_attr,
2159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2162 /* dma_system -> L3 */
2163 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2164 .master = &omap3xxx_dma_system_hwmod,
2165 .slave = &omap3xxx_l3_main_hwmod,
2166 .clk = "core_l3_ick",
2167 .user = OCP_USER_MPU | OCP_USER_SDMA,
2170 /* dma attributes */
2171 static struct omap_dma_dev_attr dma_dev_attr = {
2172 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2173 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2177 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2179 .sysc_offs = 0x002c,
2180 .syss_offs = 0x0028,
2181 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2182 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2183 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2184 SYSS_HAS_RESET_STATUS),
2185 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2186 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2187 .sysc_fields = &omap_hwmod_sysc_type1,
2190 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2192 .sysc = &omap3xxx_dma_sysc,
2196 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2198 .pa_start = 0x48056000,
2199 .pa_end = 0x48056fff,
2200 .flags = ADDR_TYPE_RT
2205 /* dma_system master ports */
2206 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2207 &omap3xxx_dma_system__l3,
2210 /* l4_cfg -> dma_system */
2211 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2212 .master = &omap3xxx_l4_core_hwmod,
2213 .slave = &omap3xxx_dma_system_hwmod,
2214 .clk = "core_l4_ick",
2215 .addr = omap3xxx_dma_system_addrs,
2216 .user = OCP_USER_MPU | OCP_USER_SDMA,
2219 /* dma_system slave ports */
2220 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2221 &omap3xxx_l4_core__dma_system,
2224 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2226 .class = &omap3xxx_dma_hwmod_class,
2227 .mpu_irqs = omap2_dma_system_irqs,
2228 .main_clk = "core_l3_ick",
2231 .module_offs = CORE_MOD,
2233 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2235 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2238 .slaves = omap3xxx_dma_system_slaves,
2239 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2240 .masters = omap3xxx_dma_system_masters,
2241 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2242 .dev_attr = &dma_dev_attr,
2243 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2244 .flags = HWMOD_NO_IDLEST,
2249 * multi channel buffered serial port controller
2252 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2253 .sysc_offs = 0x008c,
2254 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2255 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2256 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2257 .sysc_fields = &omap_hwmod_sysc_type1,
2261 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2263 .sysc = &omap3xxx_mcbsp_sysc,
2264 .rev = MCBSP_CONFIG_TYPE3,
2268 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2269 { .name = "irq", .irq = 16 },
2270 { .name = "tx", .irq = 59 },
2271 { .name = "rx", .irq = 60 },
2275 static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2276 { .name = "rx", .dma_req = 32 },
2277 { .name = "tx", .dma_req = 31 },
2280 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2283 .pa_start = 0x48074000,
2284 .pa_end = 0x480740ff,
2285 .flags = ADDR_TYPE_RT
2290 /* l4_core -> mcbsp1 */
2291 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2292 .master = &omap3xxx_l4_core_hwmod,
2293 .slave = &omap3xxx_mcbsp1_hwmod,
2294 .clk = "mcbsp1_ick",
2295 .addr = omap3xxx_mcbsp1_addrs,
2296 .user = OCP_USER_MPU | OCP_USER_SDMA,
2299 /* mcbsp1 slave ports */
2300 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2301 &omap3xxx_l4_core__mcbsp1,
2304 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2306 .class = &omap3xxx_mcbsp_hwmod_class,
2307 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2308 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2309 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2310 .main_clk = "mcbsp1_fck",
2314 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2315 .module_offs = CORE_MOD,
2317 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2320 .slaves = omap3xxx_mcbsp1_slaves,
2321 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2322 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2326 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2327 { .name = "irq", .irq = 17 },
2328 { .name = "tx", .irq = 62 },
2329 { .name = "rx", .irq = 63 },
2333 static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2334 { .name = "rx", .dma_req = 34 },
2335 { .name = "tx", .dma_req = 33 },
2338 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2341 .pa_start = 0x49022000,
2342 .pa_end = 0x490220ff,
2343 .flags = ADDR_TYPE_RT
2348 /* l4_per -> mcbsp2 */
2349 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2350 .master = &omap3xxx_l4_per_hwmod,
2351 .slave = &omap3xxx_mcbsp2_hwmod,
2352 .clk = "mcbsp2_ick",
2353 .addr = omap3xxx_mcbsp2_addrs,
2355 .user = OCP_USER_MPU | OCP_USER_SDMA,
2358 /* mcbsp2 slave ports */
2359 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2360 &omap3xxx_l4_per__mcbsp2,
2363 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2364 .sidetone = "mcbsp2_sidetone",
2367 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2369 .class = &omap3xxx_mcbsp_hwmod_class,
2370 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2371 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2372 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2373 .main_clk = "mcbsp2_fck",
2377 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2378 .module_offs = OMAP3430_PER_MOD,
2380 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2383 .slaves = omap3xxx_mcbsp2_slaves,
2384 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2385 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2386 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2390 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2391 { .name = "irq", .irq = 22 },
2392 { .name = "tx", .irq = 89 },
2393 { .name = "rx", .irq = 90 },
2397 static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2398 { .name = "rx", .dma_req = 18 },
2399 { .name = "tx", .dma_req = 17 },
2402 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2405 .pa_start = 0x49024000,
2406 .pa_end = 0x490240ff,
2407 .flags = ADDR_TYPE_RT
2412 /* l4_per -> mcbsp3 */
2413 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2414 .master = &omap3xxx_l4_per_hwmod,
2415 .slave = &omap3xxx_mcbsp3_hwmod,
2416 .clk = "mcbsp3_ick",
2417 .addr = omap3xxx_mcbsp3_addrs,
2418 .user = OCP_USER_MPU | OCP_USER_SDMA,
2421 /* mcbsp3 slave ports */
2422 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2423 &omap3xxx_l4_per__mcbsp3,
2426 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2427 .sidetone = "mcbsp3_sidetone",
2430 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2432 .class = &omap3xxx_mcbsp_hwmod_class,
2433 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2434 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2435 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2436 .main_clk = "mcbsp3_fck",
2440 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2441 .module_offs = OMAP3430_PER_MOD,
2443 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2446 .slaves = omap3xxx_mcbsp3_slaves,
2447 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2448 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2449 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2453 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2454 { .name = "irq", .irq = 23 },
2455 { .name = "tx", .irq = 54 },
2456 { .name = "rx", .irq = 55 },
2460 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2461 { .name = "rx", .dma_req = 20 },
2462 { .name = "tx", .dma_req = 19 },
2465 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2468 .pa_start = 0x49026000,
2469 .pa_end = 0x490260ff,
2470 .flags = ADDR_TYPE_RT
2475 /* l4_per -> mcbsp4 */
2476 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2477 .master = &omap3xxx_l4_per_hwmod,
2478 .slave = &omap3xxx_mcbsp4_hwmod,
2479 .clk = "mcbsp4_ick",
2480 .addr = omap3xxx_mcbsp4_addrs,
2481 .user = OCP_USER_MPU | OCP_USER_SDMA,
2484 /* mcbsp4 slave ports */
2485 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2486 &omap3xxx_l4_per__mcbsp4,
2489 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2491 .class = &omap3xxx_mcbsp_hwmod_class,
2492 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2493 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2494 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2495 .main_clk = "mcbsp4_fck",
2499 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2500 .module_offs = OMAP3430_PER_MOD,
2502 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2505 .slaves = omap3xxx_mcbsp4_slaves,
2506 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2507 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2511 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2512 { .name = "irq", .irq = 27 },
2513 { .name = "tx", .irq = 81 },
2514 { .name = "rx", .irq = 82 },
2518 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2519 { .name = "rx", .dma_req = 22 },
2520 { .name = "tx", .dma_req = 21 },
2523 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2526 .pa_start = 0x48096000,
2527 .pa_end = 0x480960ff,
2528 .flags = ADDR_TYPE_RT
2533 /* l4_core -> mcbsp5 */
2534 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2535 .master = &omap3xxx_l4_core_hwmod,
2536 .slave = &omap3xxx_mcbsp5_hwmod,
2537 .clk = "mcbsp5_ick",
2538 .addr = omap3xxx_mcbsp5_addrs,
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2542 /* mcbsp5 slave ports */
2543 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2544 &omap3xxx_l4_core__mcbsp5,
2547 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2549 .class = &omap3xxx_mcbsp_hwmod_class,
2550 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2551 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2552 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2553 .main_clk = "mcbsp5_fck",
2557 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2558 .module_offs = CORE_MOD,
2560 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2563 .slaves = omap3xxx_mcbsp5_slaves,
2564 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2565 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2567 /* 'mcbsp sidetone' class */
2569 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2570 .sysc_offs = 0x0010,
2571 .sysc_flags = SYSC_HAS_AUTOIDLE,
2572 .sysc_fields = &omap_hwmod_sysc_type1,
2575 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2576 .name = "mcbsp_sidetone",
2577 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2580 /* mcbsp2_sidetone */
2581 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2582 { .name = "irq", .irq = 4 },
2586 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2589 .pa_start = 0x49028000,
2590 .pa_end = 0x490280ff,
2591 .flags = ADDR_TYPE_RT
2596 /* l4_per -> mcbsp2_sidetone */
2597 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2598 .master = &omap3xxx_l4_per_hwmod,
2599 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2600 .clk = "mcbsp2_ick",
2601 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2602 .user = OCP_USER_MPU,
2605 /* mcbsp2_sidetone slave ports */
2606 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2607 &omap3xxx_l4_per__mcbsp2_sidetone,
2610 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2611 .name = "mcbsp2_sidetone",
2612 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2613 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2614 .main_clk = "mcbsp2_fck",
2618 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2619 .module_offs = OMAP3430_PER_MOD,
2621 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2624 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2625 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2626 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2629 /* mcbsp3_sidetone */
2630 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2631 { .name = "irq", .irq = 5 },
2635 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2638 .pa_start = 0x4902A000,
2639 .pa_end = 0x4902A0ff,
2640 .flags = ADDR_TYPE_RT
2645 /* l4_per -> mcbsp3_sidetone */
2646 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2647 .master = &omap3xxx_l4_per_hwmod,
2648 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2649 .clk = "mcbsp3_ick",
2650 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2651 .user = OCP_USER_MPU,
2654 /* mcbsp3_sidetone slave ports */
2655 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2656 &omap3xxx_l4_per__mcbsp3_sidetone,
2659 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2660 .name = "mcbsp3_sidetone",
2661 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2662 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2663 .main_clk = "mcbsp3_fck",
2667 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2668 .module_offs = OMAP3430_PER_MOD,
2670 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2673 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2674 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2675 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2680 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2684 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2686 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2687 .clockact = CLOCKACT_TEST_ICLK,
2688 .sysc_fields = &omap34xx_sr_sysc_fields,
2691 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2692 .name = "smartreflex",
2693 .sysc = &omap34xx_sr_sysc,
2697 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2702 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2704 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2705 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2707 .sysc_fields = &omap36xx_sr_sysc_fields,
2710 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2711 .name = "smartreflex",
2712 .sysc = &omap36xx_sr_sysc,
2717 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2718 &omap3_l4_core__sr1,
2721 static struct omap_hwmod omap34xx_sr1_hwmod = {
2722 .name = "sr1_hwmod",
2723 .class = &omap34xx_smartreflex_hwmod_class,
2724 .main_clk = "sr1_fck",
2729 .module_bit = OMAP3430_EN_SR1_SHIFT,
2730 .module_offs = WKUP_MOD,
2732 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2735 .slaves = omap3_sr1_slaves,
2736 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2737 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2738 CHIP_IS_OMAP3430ES3_0 |
2739 CHIP_IS_OMAP3430ES3_1),
2740 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2743 static struct omap_hwmod omap36xx_sr1_hwmod = {
2744 .name = "sr1_hwmod",
2745 .class = &omap36xx_smartreflex_hwmod_class,
2746 .main_clk = "sr1_fck",
2751 .module_bit = OMAP3430_EN_SR1_SHIFT,
2752 .module_offs = WKUP_MOD,
2754 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2757 .slaves = omap3_sr1_slaves,
2758 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2759 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2763 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2764 &omap3_l4_core__sr2,
2767 static struct omap_hwmod omap34xx_sr2_hwmod = {
2768 .name = "sr2_hwmod",
2769 .class = &omap34xx_smartreflex_hwmod_class,
2770 .main_clk = "sr2_fck",
2775 .module_bit = OMAP3430_EN_SR2_SHIFT,
2776 .module_offs = WKUP_MOD,
2778 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2781 .slaves = omap3_sr2_slaves,
2782 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2783 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2784 CHIP_IS_OMAP3430ES3_0 |
2785 CHIP_IS_OMAP3430ES3_1),
2786 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2789 static struct omap_hwmod omap36xx_sr2_hwmod = {
2790 .name = "sr2_hwmod",
2791 .class = &omap36xx_smartreflex_hwmod_class,
2792 .main_clk = "sr2_fck",
2797 .module_bit = OMAP3430_EN_SR2_SHIFT,
2798 .module_offs = WKUP_MOD,
2800 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2803 .slaves = omap3_sr2_slaves,
2804 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2805 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2810 * mailbox module allowing communication between the on-chip processors
2811 * using a queued mailbox-interrupt mechanism.
2814 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2818 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2819 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2820 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2821 .sysc_fields = &omap_hwmod_sysc_type1,
2824 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2826 .sysc = &omap3xxx_mailbox_sysc,
2829 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2830 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2835 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2837 .pa_start = 0x48094000,
2838 .pa_end = 0x480941ff,
2839 .flags = ADDR_TYPE_RT,
2844 /* l4_core -> mailbox */
2845 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2846 .master = &omap3xxx_l4_core_hwmod,
2847 .slave = &omap3xxx_mailbox_hwmod,
2848 .addr = omap3xxx_mailbox_addrs,
2849 .user = OCP_USER_MPU | OCP_USER_SDMA,
2852 /* mailbox slave ports */
2853 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2854 &omap3xxx_l4_core__mailbox,
2857 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2859 .class = &omap3xxx_mailbox_hwmod_class,
2860 .mpu_irqs = omap3xxx_mailbox_irqs,
2861 .main_clk = "mailboxes_ick",
2865 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2866 .module_offs = CORE_MOD,
2868 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2871 .slaves = omap3xxx_mailbox_slaves,
2872 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2873 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2876 /* l4 core -> mcspi1 interface */
2877 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2878 .master = &omap3xxx_l4_core_hwmod,
2879 .slave = &omap34xx_mcspi1,
2880 .clk = "mcspi1_ick",
2881 .addr = omap2_mcspi1_addr_space,
2882 .user = OCP_USER_MPU | OCP_USER_SDMA,
2885 /* l4 core -> mcspi2 interface */
2886 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2887 .master = &omap3xxx_l4_core_hwmod,
2888 .slave = &omap34xx_mcspi2,
2889 .clk = "mcspi2_ick",
2890 .addr = omap2_mcspi2_addr_space,
2891 .user = OCP_USER_MPU | OCP_USER_SDMA,
2894 /* l4 core -> mcspi3 interface */
2895 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2896 .master = &omap3xxx_l4_core_hwmod,
2897 .slave = &omap34xx_mcspi3,
2898 .clk = "mcspi3_ick",
2899 .addr = omap2430_mcspi3_addr_space,
2900 .user = OCP_USER_MPU | OCP_USER_SDMA,
2903 /* l4 core -> mcspi4 interface */
2904 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2906 .pa_start = 0x480ba000,
2907 .pa_end = 0x480ba0ff,
2908 .flags = ADDR_TYPE_RT,
2913 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2914 .master = &omap3xxx_l4_core_hwmod,
2915 .slave = &omap34xx_mcspi4,
2916 .clk = "mcspi4_ick",
2917 .addr = omap34xx_mcspi4_addr_space,
2918 .user = OCP_USER_MPU | OCP_USER_SDMA,
2923 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2927 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2929 .sysc_offs = 0x0010,
2930 .syss_offs = 0x0014,
2931 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2932 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2933 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2934 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2935 .sysc_fields = &omap_hwmod_sysc_type1,
2938 static struct omap_hwmod_class omap34xx_mcspi_class = {
2940 .sysc = &omap34xx_mcspi_sysc,
2941 .rev = OMAP3_MCSPI_REV,
2945 static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
2946 { .name = "tx0", .dma_req = 35 },
2947 { .name = "rx0", .dma_req = 36 },
2948 { .name = "tx1", .dma_req = 37 },
2949 { .name = "rx1", .dma_req = 38 },
2950 { .name = "tx2", .dma_req = 39 },
2951 { .name = "rx2", .dma_req = 40 },
2952 { .name = "tx3", .dma_req = 41 },
2953 { .name = "rx3", .dma_req = 42 },
2956 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2957 &omap34xx_l4_core__mcspi1,
2960 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2961 .num_chipselect = 4,
2964 static struct omap_hwmod omap34xx_mcspi1 = {
2966 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2967 .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
2968 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
2969 .main_clk = "mcspi1_fck",
2972 .module_offs = CORE_MOD,
2974 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2976 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2979 .slaves = omap34xx_mcspi1_slaves,
2980 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2981 .class = &omap34xx_mcspi_class,
2982 .dev_attr = &omap_mcspi1_dev_attr,
2983 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2987 static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
2988 { .name = "tx0", .dma_req = 43 },
2989 { .name = "rx0", .dma_req = 44 },
2990 { .name = "tx1", .dma_req = 45 },
2991 { .name = "rx1", .dma_req = 46 },
2994 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2995 &omap34xx_l4_core__mcspi2,
2998 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2999 .num_chipselect = 2,
3002 static struct omap_hwmod omap34xx_mcspi2 = {
3004 .mpu_irqs = omap2_mcspi2_mpu_irqs,
3005 .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
3006 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
3007 .main_clk = "mcspi2_fck",
3010 .module_offs = CORE_MOD,
3012 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
3014 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
3017 .slaves = omap34xx_mcspi2_slaves,
3018 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
3019 .class = &omap34xx_mcspi_class,
3020 .dev_attr = &omap_mcspi2_dev_attr,
3021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3025 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
3026 { .name = "irq", .irq = 91 }, /* 91 */
3030 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
3031 { .name = "tx0", .dma_req = 15 },
3032 { .name = "rx0", .dma_req = 16 },
3033 { .name = "tx1", .dma_req = 23 },
3034 { .name = "rx1", .dma_req = 24 },
3037 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
3038 &omap34xx_l4_core__mcspi3,
3041 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
3042 .num_chipselect = 2,
3045 static struct omap_hwmod omap34xx_mcspi3 = {
3047 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
3048 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
3049 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
3050 .main_clk = "mcspi3_fck",
3053 .module_offs = CORE_MOD,
3055 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
3057 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
3060 .slaves = omap34xx_mcspi3_slaves,
3061 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
3062 .class = &omap34xx_mcspi_class,
3063 .dev_attr = &omap_mcspi3_dev_attr,
3064 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3068 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
3069 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
3073 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
3074 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
3075 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
3078 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
3079 &omap34xx_l4_core__mcspi4,
3082 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
3083 .num_chipselect = 1,
3086 static struct omap_hwmod omap34xx_mcspi4 = {
3088 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
3089 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
3090 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
3091 .main_clk = "mcspi4_fck",
3094 .module_offs = CORE_MOD,
3096 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
3098 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
3101 .slaves = omap34xx_mcspi4_slaves,
3102 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
3103 .class = &omap34xx_mcspi_class,
3104 .dev_attr = &omap_mcspi4_dev_attr,
3105 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3111 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
3113 .sysc_offs = 0x0404,
3114 .syss_offs = 0x0408,
3115 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
3116 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3118 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3119 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
3120 .sysc_fields = &omap_hwmod_sysc_type1,
3123 static struct omap_hwmod_class usbotg_class = {
3125 .sysc = &omap3xxx_usbhsotg_sysc,
3128 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
3130 { .name = "mc", .irq = 92 },
3131 { .name = "dma", .irq = 93 },
3135 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
3136 .name = "usb_otg_hs",
3137 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
3138 .main_clk = "hsotgusb_ick",
3142 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
3143 .module_offs = CORE_MOD,
3145 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
3146 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
3149 .masters = omap3xxx_usbhsotg_masters,
3150 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
3151 .slaves = omap3xxx_usbhsotg_slaves,
3152 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
3153 .class = &usbotg_class,
3156 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
3157 * broken when autoidle is enabled
3158 * workaround is to disable the autoidle bit at module level.
3160 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3161 | HWMOD_SWSUP_MSTANDBY,
3162 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3166 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3168 { .name = "mc", .irq = 71 },
3172 static struct omap_hwmod_class am35xx_usbotg_class = {
3173 .name = "am35xx_usbotg",
3177 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3178 .name = "am35x_otg_hs",
3179 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3185 .masters = am35xx_usbhsotg_masters,
3186 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3187 .slaves = am35xx_usbhsotg_slaves,
3188 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3189 .class = &am35xx_usbotg_class,
3190 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3193 /* MMC/SD/SDIO common */
3195 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3199 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3200 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3201 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3202 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3203 .sysc_fields = &omap_hwmod_sysc_type1,
3206 static struct omap_hwmod_class omap34xx_mmc_class = {
3208 .sysc = &omap34xx_mmc_sysc,
3213 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3218 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3219 { .name = "tx", .dma_req = 61, },
3220 { .name = "rx", .dma_req = 62, },
3223 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3224 { .role = "dbck", .clk = "omap_32k_fck", },
3227 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3228 &omap3xxx_l4_core__mmc1,
3231 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3232 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3235 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3237 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3238 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3239 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3240 .opt_clks = omap34xx_mmc1_opt_clks,
3241 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3242 .main_clk = "mmchs1_fck",
3245 .module_offs = CORE_MOD,
3247 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3249 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3252 .dev_attr = &mmc1_dev_attr,
3253 .slaves = omap3xxx_mmc1_slaves,
3254 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3255 .class = &omap34xx_mmc_class,
3256 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3261 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3262 { .irq = INT_24XX_MMC2_IRQ, },
3266 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3267 { .name = "tx", .dma_req = 47, },
3268 { .name = "rx", .dma_req = 48, },
3271 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3272 { .role = "dbck", .clk = "omap_32k_fck", },
3275 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3276 &omap3xxx_l4_core__mmc2,
3279 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3281 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3282 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3283 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3284 .opt_clks = omap34xx_mmc2_opt_clks,
3285 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3286 .main_clk = "mmchs2_fck",
3289 .module_offs = CORE_MOD,
3291 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3293 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3296 .slaves = omap3xxx_mmc2_slaves,
3297 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3298 .class = &omap34xx_mmc_class,
3299 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3304 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3309 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3310 { .name = "tx", .dma_req = 77, },
3311 { .name = "rx", .dma_req = 78, },
3314 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3315 { .role = "dbck", .clk = "omap_32k_fck", },
3318 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3319 &omap3xxx_l4_core__mmc3,
3322 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3324 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3325 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3326 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3327 .opt_clks = omap34xx_mmc3_opt_clks,
3328 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3329 .main_clk = "mmchs3_fck",
3333 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3335 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3338 .slaves = omap3xxx_mmc3_slaves,
3339 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3340 .class = &omap34xx_mmc_class,
3341 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3344 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3345 &omap3xxx_l3_main_hwmod,
3346 &omap3xxx_l4_core_hwmod,
3347 &omap3xxx_l4_per_hwmod,
3348 &omap3xxx_l4_wkup_hwmod,
3349 &omap3xxx_mmc1_hwmod,
3350 &omap3xxx_mmc2_hwmod,
3351 &omap3xxx_mmc3_hwmod,
3352 &omap3xxx_mpu_hwmod,
3353 &omap3xxx_iva_hwmod,
3355 &omap3xxx_timer1_hwmod,
3356 &omap3xxx_timer2_hwmod,
3357 &omap3xxx_timer3_hwmod,
3358 &omap3xxx_timer4_hwmod,
3359 &omap3xxx_timer5_hwmod,
3360 &omap3xxx_timer6_hwmod,
3361 &omap3xxx_timer7_hwmod,
3362 &omap3xxx_timer8_hwmod,
3363 &omap3xxx_timer9_hwmod,
3364 &omap3xxx_timer10_hwmod,
3365 &omap3xxx_timer11_hwmod,
3366 &omap3xxx_timer12_hwmod,
3368 &omap3xxx_wd_timer2_hwmod,
3369 &omap3xxx_uart1_hwmod,
3370 &omap3xxx_uart2_hwmod,
3371 &omap3xxx_uart3_hwmod,
3372 &omap3xxx_uart4_hwmod,
3374 &omap3430es1_dss_core_hwmod,
3375 &omap3xxx_dss_core_hwmod,
3376 &omap3xxx_dss_dispc_hwmod,
3377 &omap3xxx_dss_dsi1_hwmod,
3378 &omap3xxx_dss_rfbi_hwmod,
3379 &omap3xxx_dss_venc_hwmod,
3382 &omap3xxx_i2c1_hwmod,
3383 &omap3xxx_i2c2_hwmod,
3384 &omap3xxx_i2c3_hwmod,
3385 &omap34xx_sr1_hwmod,
3386 &omap34xx_sr2_hwmod,
3387 &omap36xx_sr1_hwmod,
3388 &omap36xx_sr2_hwmod,
3392 &omap3xxx_gpio1_hwmod,
3393 &omap3xxx_gpio2_hwmod,
3394 &omap3xxx_gpio3_hwmod,
3395 &omap3xxx_gpio4_hwmod,
3396 &omap3xxx_gpio5_hwmod,
3397 &omap3xxx_gpio6_hwmod,
3399 /* dma_system class*/
3400 &omap3xxx_dma_system_hwmod,
3403 &omap3xxx_mcbsp1_hwmod,
3404 &omap3xxx_mcbsp2_hwmod,
3405 &omap3xxx_mcbsp3_hwmod,
3406 &omap3xxx_mcbsp4_hwmod,
3407 &omap3xxx_mcbsp5_hwmod,
3408 &omap3xxx_mcbsp2_sidetone_hwmod,
3409 &omap3xxx_mcbsp3_sidetone_hwmod,
3412 &omap3xxx_mailbox_hwmod,
3421 &omap3xxx_usbhsotg_hwmod,
3423 /* usbotg for am35x */
3424 &am35xx_usbhsotg_hwmod,
3429 int __init omap3xxx_hwmod_init(void)
3431 return omap_hwmod_register(omap3xxx_hwmods);