2 * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
4 * Copyright (C) 2009-2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * The data in this file should be completely autogeneratable from
12 * the TI hardware database or other technical documentation.
14 * XXX these should be marked initdata for multi-OMAP kernels
16 #include <plat/omap_hwmod.h>
17 #include <mach/irqs.h>
20 #include <plat/serial.h>
21 #include <plat/l3_3xxx.h>
22 #include <plat/l4_3xxx.h>
24 #include <plat/gpio.h>
26 #include <plat/mcbsp.h>
27 #include <plat/mcspi.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod_common_data.h"
32 #include "prm-regbits-34xx.h"
33 #include "cm-regbits-34xx.h"
35 #include <mach/am35xx.h>
38 * OMAP3xxx hardware module integration data
40 * ALl of the data in this section should be autogeneratable from the
41 * TI hardware database or other technical documentation. Data that
42 * is driver-specific or driver-kernel integration-specific belongs
46 static struct omap_hwmod omap3xxx_mpu_hwmod;
47 static struct omap_hwmod omap3xxx_iva_hwmod;
48 static struct omap_hwmod omap3xxx_l3_main_hwmod;
49 static struct omap_hwmod omap3xxx_l4_core_hwmod;
50 static struct omap_hwmod omap3xxx_l4_per_hwmod;
51 static struct omap_hwmod omap3xxx_wd_timer2_hwmod;
52 static struct omap_hwmod omap3430es1_dss_core_hwmod;
53 static struct omap_hwmod omap3xxx_dss_core_hwmod;
54 static struct omap_hwmod omap3xxx_dss_dispc_hwmod;
55 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod;
56 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod;
57 static struct omap_hwmod omap3xxx_dss_venc_hwmod;
58 static struct omap_hwmod omap3xxx_i2c1_hwmod;
59 static struct omap_hwmod omap3xxx_i2c2_hwmod;
60 static struct omap_hwmod omap3xxx_i2c3_hwmod;
61 static struct omap_hwmod omap3xxx_gpio1_hwmod;
62 static struct omap_hwmod omap3xxx_gpio2_hwmod;
63 static struct omap_hwmod omap3xxx_gpio3_hwmod;
64 static struct omap_hwmod omap3xxx_gpio4_hwmod;
65 static struct omap_hwmod omap3xxx_gpio5_hwmod;
66 static struct omap_hwmod omap3xxx_gpio6_hwmod;
67 static struct omap_hwmod omap34xx_sr1_hwmod;
68 static struct omap_hwmod omap34xx_sr2_hwmod;
69 static struct omap_hwmod omap34xx_mcspi1;
70 static struct omap_hwmod omap34xx_mcspi2;
71 static struct omap_hwmod omap34xx_mcspi3;
72 static struct omap_hwmod omap34xx_mcspi4;
73 static struct omap_hwmod omap3xxx_mmc1_hwmod;
74 static struct omap_hwmod omap3xxx_mmc2_hwmod;
75 static struct omap_hwmod omap3xxx_mmc3_hwmod;
76 static struct omap_hwmod am35xx_usbhsotg_hwmod;
78 static struct omap_hwmod omap3xxx_dma_system_hwmod;
80 static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
81 static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
82 static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
83 static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
84 static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
85 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
86 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88 /* L3 -> L4_CORE interface */
89 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
90 .master = &omap3xxx_l3_main_hwmod,
91 .slave = &omap3xxx_l4_core_hwmod,
92 .user = OCP_USER_MPU | OCP_USER_SDMA,
95 /* L3 -> L4_PER interface */
96 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
97 .master = &omap3xxx_l3_main_hwmod,
98 .slave = &omap3xxx_l4_per_hwmod,
99 .user = OCP_USER_MPU | OCP_USER_SDMA,
102 /* L3 taret configuration and error log registers */
103 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
104 { .irq = INT_34XX_L3_DBG_IRQ },
105 { .irq = INT_34XX_L3_APP_IRQ },
109 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
111 .pa_start = 0x68000000,
112 .pa_end = 0x6800ffff,
113 .flags = ADDR_TYPE_RT,
118 /* MPU -> L3 interface */
119 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
120 .master = &omap3xxx_mpu_hwmod,
121 .slave = &omap3xxx_l3_main_hwmod,
122 .addr = omap3xxx_l3_main_addrs,
123 .user = OCP_USER_MPU,
126 /* Slave interfaces on the L3 interconnect */
127 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_slaves[] = {
128 &omap3xxx_mpu__l3_main,
132 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
133 .master = &omap3xxx_dss_core_hwmod,
134 .slave = &omap3xxx_l3_main_hwmod,
137 .l3_perm_bit = OMAP3_L3_CORE_FW_INIT_ID_DSS,
138 .flags = OMAP_FIREWALL_L3,
141 .user = OCP_USER_MPU | OCP_USER_SDMA,
144 /* Master interfaces on the L3 interconnect */
145 static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
146 &omap3xxx_l3_main__l4_core,
147 &omap3xxx_l3_main__l4_per,
151 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
153 .class = &l3_hwmod_class,
154 .mpu_irqs = omap3xxx_l3_main_irqs,
155 .masters = omap3xxx_l3_main_masters,
156 .masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
157 .slaves = omap3xxx_l3_main_slaves,
158 .slaves_cnt = ARRAY_SIZE(omap3xxx_l3_main_slaves),
159 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
160 .flags = HWMOD_NO_IDLEST,
163 static struct omap_hwmod omap3xxx_l4_wkup_hwmod;
164 static struct omap_hwmod omap3xxx_uart1_hwmod;
165 static struct omap_hwmod omap3xxx_uart2_hwmod;
166 static struct omap_hwmod omap3xxx_uart3_hwmod;
167 static struct omap_hwmod omap3xxx_uart4_hwmod;
168 static struct omap_hwmod omap3xxx_usbhsotg_hwmod;
170 /* l3_core -> usbhsotg interface */
171 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
172 .master = &omap3xxx_usbhsotg_hwmod,
173 .slave = &omap3xxx_l3_main_hwmod,
174 .clk = "core_l3_ick",
175 .user = OCP_USER_MPU,
178 /* l3_core -> am35xx_usbhsotg interface */
179 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
180 .master = &am35xx_usbhsotg_hwmod,
181 .slave = &omap3xxx_l3_main_hwmod,
182 .clk = "core_l3_ick",
183 .user = OCP_USER_MPU,
185 /* L4_CORE -> L4_WKUP interface */
186 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
187 .master = &omap3xxx_l4_core_hwmod,
188 .slave = &omap3xxx_l4_wkup_hwmod,
189 .user = OCP_USER_MPU | OCP_USER_SDMA,
192 /* L4 CORE -> MMC1 interface */
193 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
194 .master = &omap3xxx_l4_core_hwmod,
195 .slave = &omap3xxx_mmc1_hwmod,
197 .addr = omap2430_mmc1_addr_space,
198 .user = OCP_USER_MPU | OCP_USER_SDMA,
199 .flags = OMAP_FIREWALL_L4
202 /* L4 CORE -> MMC2 interface */
203 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
204 .master = &omap3xxx_l4_core_hwmod,
205 .slave = &omap3xxx_mmc2_hwmod,
207 .addr = omap2430_mmc2_addr_space,
208 .user = OCP_USER_MPU | OCP_USER_SDMA,
209 .flags = OMAP_FIREWALL_L4
212 /* L4 CORE -> MMC3 interface */
213 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
215 .pa_start = 0x480ad000,
216 .pa_end = 0x480ad1ff,
217 .flags = ADDR_TYPE_RT,
222 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
223 .master = &omap3xxx_l4_core_hwmod,
224 .slave = &omap3xxx_mmc3_hwmod,
226 .addr = omap3xxx_mmc3_addr_space,
227 .user = OCP_USER_MPU | OCP_USER_SDMA,
228 .flags = OMAP_FIREWALL_L4
231 /* L4 CORE -> UART1 interface */
232 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
234 .pa_start = OMAP3_UART1_BASE,
235 .pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
236 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
241 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
242 .master = &omap3xxx_l4_core_hwmod,
243 .slave = &omap3xxx_uart1_hwmod,
245 .addr = omap3xxx_uart1_addr_space,
246 .user = OCP_USER_MPU | OCP_USER_SDMA,
249 /* L4 CORE -> UART2 interface */
250 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
252 .pa_start = OMAP3_UART2_BASE,
253 .pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
254 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
259 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
260 .master = &omap3xxx_l4_core_hwmod,
261 .slave = &omap3xxx_uart2_hwmod,
263 .addr = omap3xxx_uart2_addr_space,
264 .user = OCP_USER_MPU | OCP_USER_SDMA,
267 /* L4 PER -> UART3 interface */
268 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
270 .pa_start = OMAP3_UART3_BASE,
271 .pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
272 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
277 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
278 .master = &omap3xxx_l4_per_hwmod,
279 .slave = &omap3xxx_uart3_hwmod,
281 .addr = omap3xxx_uart3_addr_space,
282 .user = OCP_USER_MPU | OCP_USER_SDMA,
285 /* L4 PER -> UART4 interface */
286 static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
288 .pa_start = OMAP3_UART4_BASE,
289 .pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
290 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
295 static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
296 .master = &omap3xxx_l4_per_hwmod,
297 .slave = &omap3xxx_uart4_hwmod,
299 .addr = omap3xxx_uart4_addr_space,
300 .user = OCP_USER_MPU | OCP_USER_SDMA,
303 /* L4 CORE -> I2C1 interface */
304 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
305 .master = &omap3xxx_l4_core_hwmod,
306 .slave = &omap3xxx_i2c1_hwmod,
308 .addr = omap2_i2c1_addr_space,
311 .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
313 .flags = OMAP_FIREWALL_L4,
316 .user = OCP_USER_MPU | OCP_USER_SDMA,
319 /* L4 CORE -> I2C2 interface */
320 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
321 .master = &omap3xxx_l4_core_hwmod,
322 .slave = &omap3xxx_i2c2_hwmod,
324 .addr = omap2_i2c2_addr_space,
327 .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
329 .flags = OMAP_FIREWALL_L4,
332 .user = OCP_USER_MPU | OCP_USER_SDMA,
335 /* L4 CORE -> I2C3 interface */
336 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
338 .pa_start = 0x48060000,
339 .pa_end = 0x48060000 + SZ_128 - 1,
340 .flags = ADDR_TYPE_RT,
345 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
346 .master = &omap3xxx_l4_core_hwmod,
347 .slave = &omap3xxx_i2c3_hwmod,
349 .addr = omap3xxx_i2c3_addr_space,
352 .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
354 .flags = OMAP_FIREWALL_L4,
357 .user = OCP_USER_MPU | OCP_USER_SDMA,
360 /* L4 CORE -> SR1 interface */
361 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
363 .pa_start = OMAP34XX_SR1_BASE,
364 .pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
365 .flags = ADDR_TYPE_RT,
370 static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
371 .master = &omap3xxx_l4_core_hwmod,
372 .slave = &omap34xx_sr1_hwmod,
374 .addr = omap3_sr1_addr_space,
375 .user = OCP_USER_MPU,
378 /* L4 CORE -> SR1 interface */
379 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
381 .pa_start = OMAP34XX_SR2_BASE,
382 .pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
383 .flags = ADDR_TYPE_RT,
388 static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
389 .master = &omap3xxx_l4_core_hwmod,
390 .slave = &omap34xx_sr2_hwmod,
392 .addr = omap3_sr2_addr_space,
393 .user = OCP_USER_MPU,
397 * usbhsotg interface data
400 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
402 .pa_start = OMAP34XX_HSUSB_OTG_BASE,
403 .pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
404 .flags = ADDR_TYPE_RT
409 /* l4_core -> usbhsotg */
410 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
411 .master = &omap3xxx_l4_core_hwmod,
412 .slave = &omap3xxx_usbhsotg_hwmod,
414 .addr = omap3xxx_usbhsotg_addrs,
415 .user = OCP_USER_MPU,
418 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_masters[] = {
419 &omap3xxx_usbhsotg__l3,
422 static struct omap_hwmod_ocp_if *omap3xxx_usbhsotg_slaves[] = {
423 &omap3xxx_l4_core__usbhsotg,
426 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
428 .pa_start = AM35XX_IPSS_USBOTGSS_BASE,
429 .pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
430 .flags = ADDR_TYPE_RT
435 /* l4_core -> usbhsotg */
436 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
437 .master = &omap3xxx_l4_core_hwmod,
438 .slave = &am35xx_usbhsotg_hwmod,
440 .addr = am35xx_usbhsotg_addrs,
441 .user = OCP_USER_MPU,
444 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_masters[] = {
445 &am35xx_usbhsotg__l3,
448 static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
449 &am35xx_l4_core__usbhsotg,
451 /* Slave interfaces on the L4_CORE interconnect */
452 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
453 &omap3xxx_l3_main__l4_core,
457 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
459 .class = &l4_hwmod_class,
460 .slaves = omap3xxx_l4_core_slaves,
461 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_core_slaves),
462 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
463 .flags = HWMOD_NO_IDLEST,
466 /* Slave interfaces on the L4_PER interconnect */
467 static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
468 &omap3xxx_l3_main__l4_per,
472 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
474 .class = &l4_hwmod_class,
475 .slaves = omap3xxx_l4_per_slaves,
476 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_per_slaves),
477 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
478 .flags = HWMOD_NO_IDLEST,
481 /* Slave interfaces on the L4_WKUP interconnect */
482 static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
483 &omap3xxx_l4_core__l4_wkup,
487 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
489 .class = &l4_hwmod_class,
490 .slaves = omap3xxx_l4_wkup_slaves,
491 .slaves_cnt = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
493 .flags = HWMOD_NO_IDLEST,
496 /* Master interfaces on the MPU device */
497 static struct omap_hwmod_ocp_if *omap3xxx_mpu_masters[] = {
498 &omap3xxx_mpu__l3_main,
502 static struct omap_hwmod omap3xxx_mpu_hwmod = {
504 .class = &mpu_hwmod_class,
505 .main_clk = "arm_fck",
506 .masters = omap3xxx_mpu_masters,
507 .masters_cnt = ARRAY_SIZE(omap3xxx_mpu_masters),
508 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
512 * IVA2_2 interface data
515 /* IVA2 <- L3 interface */
516 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
517 .master = &omap3xxx_l3_main_hwmod,
518 .slave = &omap3xxx_iva_hwmod,
520 .user = OCP_USER_MPU | OCP_USER_SDMA,
523 static struct omap_hwmod_ocp_if *omap3xxx_iva_masters[] = {
531 static struct omap_hwmod omap3xxx_iva_hwmod = {
533 .class = &iva_hwmod_class,
534 .masters = omap3xxx_iva_masters,
535 .masters_cnt = ARRAY_SIZE(omap3xxx_iva_masters),
536 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
540 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
544 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
545 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
546 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
547 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
548 .sysc_fields = &omap_hwmod_sysc_type1,
551 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
553 .sysc = &omap3xxx_timer_1ms_sysc,
554 .rev = OMAP_TIMER_IP_VERSION_1,
557 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
561 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
562 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
563 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
564 .sysc_fields = &omap_hwmod_sysc_type1,
567 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
569 .sysc = &omap3xxx_timer_sysc,
570 .rev = OMAP_TIMER_IP_VERSION_1,
574 static struct omap_hwmod omap3xxx_timer1_hwmod;
576 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
578 .pa_start = 0x48318000,
579 .pa_end = 0x48318000 + SZ_1K - 1,
580 .flags = ADDR_TYPE_RT
585 /* l4_wkup -> timer1 */
586 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
587 .master = &omap3xxx_l4_wkup_hwmod,
588 .slave = &omap3xxx_timer1_hwmod,
590 .addr = omap3xxx_timer1_addrs,
591 .user = OCP_USER_MPU | OCP_USER_SDMA,
594 /* timer1 slave port */
595 static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
596 &omap3xxx_l4_wkup__timer1,
600 static struct omap_hwmod omap3xxx_timer1_hwmod = {
602 .mpu_irqs = omap2_timer1_mpu_irqs,
603 .main_clk = "gpt1_fck",
607 .module_bit = OMAP3430_EN_GPT1_SHIFT,
608 .module_offs = WKUP_MOD,
610 .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
613 .slaves = omap3xxx_timer1_slaves,
614 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer1_slaves),
615 .class = &omap3xxx_timer_1ms_hwmod_class,
616 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
620 static struct omap_hwmod omap3xxx_timer2_hwmod;
622 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
624 .pa_start = 0x49032000,
625 .pa_end = 0x49032000 + SZ_1K - 1,
626 .flags = ADDR_TYPE_RT
631 /* l4_per -> timer2 */
632 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
633 .master = &omap3xxx_l4_per_hwmod,
634 .slave = &omap3xxx_timer2_hwmod,
636 .addr = omap3xxx_timer2_addrs,
637 .user = OCP_USER_MPU | OCP_USER_SDMA,
640 /* timer2 slave port */
641 static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
642 &omap3xxx_l4_per__timer2,
646 static struct omap_hwmod omap3xxx_timer2_hwmod = {
648 .mpu_irqs = omap2_timer2_mpu_irqs,
649 .main_clk = "gpt2_fck",
653 .module_bit = OMAP3430_EN_GPT2_SHIFT,
654 .module_offs = OMAP3430_PER_MOD,
656 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
659 .slaves = omap3xxx_timer2_slaves,
660 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer2_slaves),
661 .class = &omap3xxx_timer_1ms_hwmod_class,
662 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
666 static struct omap_hwmod omap3xxx_timer3_hwmod;
668 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
670 .pa_start = 0x49034000,
671 .pa_end = 0x49034000 + SZ_1K - 1,
672 .flags = ADDR_TYPE_RT
677 /* l4_per -> timer3 */
678 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
679 .master = &omap3xxx_l4_per_hwmod,
680 .slave = &omap3xxx_timer3_hwmod,
682 .addr = omap3xxx_timer3_addrs,
683 .user = OCP_USER_MPU | OCP_USER_SDMA,
686 /* timer3 slave port */
687 static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
688 &omap3xxx_l4_per__timer3,
692 static struct omap_hwmod omap3xxx_timer3_hwmod = {
694 .mpu_irqs = omap2_timer3_mpu_irqs,
695 .main_clk = "gpt3_fck",
699 .module_bit = OMAP3430_EN_GPT3_SHIFT,
700 .module_offs = OMAP3430_PER_MOD,
702 .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
705 .slaves = omap3xxx_timer3_slaves,
706 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer3_slaves),
707 .class = &omap3xxx_timer_hwmod_class,
708 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
712 static struct omap_hwmod omap3xxx_timer4_hwmod;
714 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
716 .pa_start = 0x49036000,
717 .pa_end = 0x49036000 + SZ_1K - 1,
718 .flags = ADDR_TYPE_RT
723 /* l4_per -> timer4 */
724 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
725 .master = &omap3xxx_l4_per_hwmod,
726 .slave = &omap3xxx_timer4_hwmod,
728 .addr = omap3xxx_timer4_addrs,
729 .user = OCP_USER_MPU | OCP_USER_SDMA,
732 /* timer4 slave port */
733 static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
734 &omap3xxx_l4_per__timer4,
738 static struct omap_hwmod omap3xxx_timer4_hwmod = {
740 .mpu_irqs = omap2_timer4_mpu_irqs,
741 .main_clk = "gpt4_fck",
745 .module_bit = OMAP3430_EN_GPT4_SHIFT,
746 .module_offs = OMAP3430_PER_MOD,
748 .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
751 .slaves = omap3xxx_timer4_slaves,
752 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer4_slaves),
753 .class = &omap3xxx_timer_hwmod_class,
754 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
758 static struct omap_hwmod omap3xxx_timer5_hwmod;
760 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
762 .pa_start = 0x49038000,
763 .pa_end = 0x49038000 + SZ_1K - 1,
764 .flags = ADDR_TYPE_RT
769 /* l4_per -> timer5 */
770 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
771 .master = &omap3xxx_l4_per_hwmod,
772 .slave = &omap3xxx_timer5_hwmod,
774 .addr = omap3xxx_timer5_addrs,
775 .user = OCP_USER_MPU | OCP_USER_SDMA,
778 /* timer5 slave port */
779 static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
780 &omap3xxx_l4_per__timer5,
784 static struct omap_hwmod omap3xxx_timer5_hwmod = {
786 .mpu_irqs = omap2_timer5_mpu_irqs,
787 .main_clk = "gpt5_fck",
791 .module_bit = OMAP3430_EN_GPT5_SHIFT,
792 .module_offs = OMAP3430_PER_MOD,
794 .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
797 .slaves = omap3xxx_timer5_slaves,
798 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer5_slaves),
799 .class = &omap3xxx_timer_hwmod_class,
800 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
804 static struct omap_hwmod omap3xxx_timer6_hwmod;
806 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
808 .pa_start = 0x4903A000,
809 .pa_end = 0x4903A000 + SZ_1K - 1,
810 .flags = ADDR_TYPE_RT
815 /* l4_per -> timer6 */
816 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
817 .master = &omap3xxx_l4_per_hwmod,
818 .slave = &omap3xxx_timer6_hwmod,
820 .addr = omap3xxx_timer6_addrs,
821 .user = OCP_USER_MPU | OCP_USER_SDMA,
824 /* timer6 slave port */
825 static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
826 &omap3xxx_l4_per__timer6,
830 static struct omap_hwmod omap3xxx_timer6_hwmod = {
832 .mpu_irqs = omap2_timer6_mpu_irqs,
833 .main_clk = "gpt6_fck",
837 .module_bit = OMAP3430_EN_GPT6_SHIFT,
838 .module_offs = OMAP3430_PER_MOD,
840 .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
843 .slaves = omap3xxx_timer6_slaves,
844 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer6_slaves),
845 .class = &omap3xxx_timer_hwmod_class,
846 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
850 static struct omap_hwmod omap3xxx_timer7_hwmod;
852 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
854 .pa_start = 0x4903C000,
855 .pa_end = 0x4903C000 + SZ_1K - 1,
856 .flags = ADDR_TYPE_RT
861 /* l4_per -> timer7 */
862 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
863 .master = &omap3xxx_l4_per_hwmod,
864 .slave = &omap3xxx_timer7_hwmod,
866 .addr = omap3xxx_timer7_addrs,
867 .user = OCP_USER_MPU | OCP_USER_SDMA,
870 /* timer7 slave port */
871 static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
872 &omap3xxx_l4_per__timer7,
876 static struct omap_hwmod omap3xxx_timer7_hwmod = {
878 .mpu_irqs = omap2_timer7_mpu_irqs,
879 .main_clk = "gpt7_fck",
883 .module_bit = OMAP3430_EN_GPT7_SHIFT,
884 .module_offs = OMAP3430_PER_MOD,
886 .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
889 .slaves = omap3xxx_timer7_slaves,
890 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer7_slaves),
891 .class = &omap3xxx_timer_hwmod_class,
892 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
896 static struct omap_hwmod omap3xxx_timer8_hwmod;
898 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
900 .pa_start = 0x4903E000,
901 .pa_end = 0x4903E000 + SZ_1K - 1,
902 .flags = ADDR_TYPE_RT
907 /* l4_per -> timer8 */
908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
909 .master = &omap3xxx_l4_per_hwmod,
910 .slave = &omap3xxx_timer8_hwmod,
912 .addr = omap3xxx_timer8_addrs,
913 .user = OCP_USER_MPU | OCP_USER_SDMA,
916 /* timer8 slave port */
917 static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
918 &omap3xxx_l4_per__timer8,
922 static struct omap_hwmod omap3xxx_timer8_hwmod = {
924 .mpu_irqs = omap2_timer8_mpu_irqs,
925 .main_clk = "gpt8_fck",
929 .module_bit = OMAP3430_EN_GPT8_SHIFT,
930 .module_offs = OMAP3430_PER_MOD,
932 .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
935 .slaves = omap3xxx_timer8_slaves,
936 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer8_slaves),
937 .class = &omap3xxx_timer_hwmod_class,
938 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
942 static struct omap_hwmod omap3xxx_timer9_hwmod;
944 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
946 .pa_start = 0x49040000,
947 .pa_end = 0x49040000 + SZ_1K - 1,
948 .flags = ADDR_TYPE_RT
953 /* l4_per -> timer9 */
954 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
955 .master = &omap3xxx_l4_per_hwmod,
956 .slave = &omap3xxx_timer9_hwmod,
958 .addr = omap3xxx_timer9_addrs,
959 .user = OCP_USER_MPU | OCP_USER_SDMA,
962 /* timer9 slave port */
963 static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
964 &omap3xxx_l4_per__timer9,
968 static struct omap_hwmod omap3xxx_timer9_hwmod = {
970 .mpu_irqs = omap2_timer9_mpu_irqs,
971 .main_clk = "gpt9_fck",
975 .module_bit = OMAP3430_EN_GPT9_SHIFT,
976 .module_offs = OMAP3430_PER_MOD,
978 .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
981 .slaves = omap3xxx_timer9_slaves,
982 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer9_slaves),
983 .class = &omap3xxx_timer_hwmod_class,
984 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
988 static struct omap_hwmod omap3xxx_timer10_hwmod;
990 /* l4_core -> timer10 */
991 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
992 .master = &omap3xxx_l4_core_hwmod,
993 .slave = &omap3xxx_timer10_hwmod,
995 .addr = omap2_timer10_addrs,
996 .user = OCP_USER_MPU | OCP_USER_SDMA,
999 /* timer10 slave port */
1000 static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
1001 &omap3xxx_l4_core__timer10,
1005 static struct omap_hwmod omap3xxx_timer10_hwmod = {
1007 .mpu_irqs = omap2_timer10_mpu_irqs,
1008 .main_clk = "gpt10_fck",
1012 .module_bit = OMAP3430_EN_GPT10_SHIFT,
1013 .module_offs = CORE_MOD,
1015 .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
1018 .slaves = omap3xxx_timer10_slaves,
1019 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer10_slaves),
1020 .class = &omap3xxx_timer_1ms_hwmod_class,
1021 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1025 static struct omap_hwmod omap3xxx_timer11_hwmod;
1027 /* l4_core -> timer11 */
1028 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
1029 .master = &omap3xxx_l4_core_hwmod,
1030 .slave = &omap3xxx_timer11_hwmod,
1032 .addr = omap2_timer11_addrs,
1033 .user = OCP_USER_MPU | OCP_USER_SDMA,
1036 /* timer11 slave port */
1037 static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
1038 &omap3xxx_l4_core__timer11,
1042 static struct omap_hwmod omap3xxx_timer11_hwmod = {
1044 .mpu_irqs = omap2_timer11_mpu_irqs,
1045 .main_clk = "gpt11_fck",
1049 .module_bit = OMAP3430_EN_GPT11_SHIFT,
1050 .module_offs = CORE_MOD,
1052 .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
1055 .slaves = omap3xxx_timer11_slaves,
1056 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer11_slaves),
1057 .class = &omap3xxx_timer_hwmod_class,
1058 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1062 static struct omap_hwmod omap3xxx_timer12_hwmod;
1063 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
1068 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
1070 .pa_start = 0x48304000,
1071 .pa_end = 0x48304000 + SZ_1K - 1,
1072 .flags = ADDR_TYPE_RT
1077 /* l4_core -> timer12 */
1078 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
1079 .master = &omap3xxx_l4_core_hwmod,
1080 .slave = &omap3xxx_timer12_hwmod,
1082 .addr = omap3xxx_timer12_addrs,
1083 .user = OCP_USER_MPU | OCP_USER_SDMA,
1086 /* timer12 slave port */
1087 static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
1088 &omap3xxx_l4_core__timer12,
1092 static struct omap_hwmod omap3xxx_timer12_hwmod = {
1094 .mpu_irqs = omap3xxx_timer12_mpu_irqs,
1095 .main_clk = "gpt12_fck",
1099 .module_bit = OMAP3430_EN_GPT12_SHIFT,
1100 .module_offs = WKUP_MOD,
1102 .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
1105 .slaves = omap3xxx_timer12_slaves,
1106 .slaves_cnt = ARRAY_SIZE(omap3xxx_timer12_slaves),
1107 .class = &omap3xxx_timer_hwmod_class,
1108 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
1111 /* l4_wkup -> wd_timer2 */
1112 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
1114 .pa_start = 0x48314000,
1115 .pa_end = 0x4831407f,
1116 .flags = ADDR_TYPE_RT
1121 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
1122 .master = &omap3xxx_l4_wkup_hwmod,
1123 .slave = &omap3xxx_wd_timer2_hwmod,
1125 .addr = omap3xxx_wd_timer2_addrs,
1126 .user = OCP_USER_MPU | OCP_USER_SDMA,
1131 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1132 * overflow condition
1135 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
1137 .sysc_offs = 0x0010,
1138 .syss_offs = 0x0014,
1139 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
1140 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1141 SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1142 SYSS_HAS_RESET_STATUS),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1144 .sysc_fields = &omap_hwmod_sysc_type1,
1148 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1152 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1153 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1154 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1155 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1156 .sysc_fields = &omap_hwmod_sysc_type1,
1159 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
1161 .sysc = &omap3xxx_wd_timer_sysc,
1162 .pre_shutdown = &omap2_wd_timer_disable
1166 static struct omap_hwmod_ocp_if *omap3xxx_wd_timer2_slaves[] = {
1167 &omap3xxx_l4_wkup__wd_timer2,
1170 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
1171 .name = "wd_timer2",
1172 .class = &omap3xxx_wd_timer_hwmod_class,
1173 .main_clk = "wdt2_fck",
1177 .module_bit = OMAP3430_EN_WDT2_SHIFT,
1178 .module_offs = WKUP_MOD,
1180 .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
1183 .slaves = omap3xxx_wd_timer2_slaves,
1184 .slaves_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
1185 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1187 * XXX: Use software supervised mode, HW supervised smartidle seems to
1188 * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
1190 .flags = HWMOD_SWSUP_SIDLE,
1195 static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
1196 &omap3_l4_core__uart1,
1199 static struct omap_hwmod omap3xxx_uart1_hwmod = {
1201 .mpu_irqs = omap2_uart1_mpu_irqs,
1202 .sdma_reqs = omap2_uart1_sdma_reqs,
1203 .main_clk = "uart1_fck",
1206 .module_offs = CORE_MOD,
1208 .module_bit = OMAP3430_EN_UART1_SHIFT,
1210 .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
1213 .slaves = omap3xxx_uart1_slaves,
1214 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
1215 .class = &omap2_uart_class,
1216 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1221 static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
1222 &omap3_l4_core__uart2,
1225 static struct omap_hwmod omap3xxx_uart2_hwmod = {
1227 .mpu_irqs = omap2_uart2_mpu_irqs,
1228 .sdma_reqs = omap2_uart2_sdma_reqs,
1229 .main_clk = "uart2_fck",
1232 .module_offs = CORE_MOD,
1234 .module_bit = OMAP3430_EN_UART2_SHIFT,
1236 .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
1239 .slaves = omap3xxx_uart2_slaves,
1240 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
1241 .class = &omap2_uart_class,
1242 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1247 static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
1248 &omap3_l4_per__uart3,
1251 static struct omap_hwmod omap3xxx_uart3_hwmod = {
1253 .mpu_irqs = omap2_uart3_mpu_irqs,
1254 .sdma_reqs = omap2_uart3_sdma_reqs,
1255 .main_clk = "uart3_fck",
1258 .module_offs = OMAP3430_PER_MOD,
1260 .module_bit = OMAP3430_EN_UART3_SHIFT,
1262 .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
1265 .slaves = omap3xxx_uart3_slaves,
1266 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
1267 .class = &omap2_uart_class,
1268 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1273 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
1274 { .irq = INT_36XX_UART4_IRQ, },
1278 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
1279 { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
1280 { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
1284 static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
1285 &omap3_l4_per__uart4,
1288 static struct omap_hwmod omap3xxx_uart4_hwmod = {
1290 .mpu_irqs = uart4_mpu_irqs,
1291 .sdma_reqs = uart4_sdma_reqs,
1292 .main_clk = "uart4_fck",
1295 .module_offs = OMAP3430_PER_MOD,
1297 .module_bit = OMAP3630_EN_UART4_SHIFT,
1299 .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
1302 .slaves = omap3xxx_uart4_slaves,
1303 .slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
1304 .class = &omap2_uart_class,
1305 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
1308 static struct omap_hwmod_class i2c_class = {
1313 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
1314 { .name = "dispc", .dma_req = 5 },
1315 { .name = "dsi1", .dma_req = 74 },
1320 /* dss master ports */
1321 static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
1325 /* l4_core -> dss */
1326 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
1327 .master = &omap3xxx_l4_core_hwmod,
1328 .slave = &omap3430es1_dss_core_hwmod,
1330 .addr = omap2_dss_addrs,
1333 .l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
1334 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1335 .flags = OMAP_FIREWALL_L4,
1338 .user = OCP_USER_MPU | OCP_USER_SDMA,
1341 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
1342 .master = &omap3xxx_l4_core_hwmod,
1343 .slave = &omap3xxx_dss_core_hwmod,
1345 .addr = omap2_dss_addrs,
1348 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
1349 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1350 .flags = OMAP_FIREWALL_L4,
1353 .user = OCP_USER_MPU | OCP_USER_SDMA,
1356 /* dss slave ports */
1357 static struct omap_hwmod_ocp_if *omap3430es1_dss_slaves[] = {
1358 &omap3430es1_l4_core__dss,
1361 static struct omap_hwmod_ocp_if *omap3xxx_dss_slaves[] = {
1362 &omap3xxx_l4_core__dss,
1365 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1366 { .role = "tv_clk", .clk = "dss_tv_fck" },
1367 { .role = "video_clk", .clk = "dss_96m_fck" },
1368 { .role = "sys_clk", .clk = "dss2_alwon_fck" },
1371 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
1373 .class = &omap2_dss_hwmod_class,
1374 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1375 .sdma_reqs = omap3xxx_dss_sdma_chs,
1379 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1380 .module_offs = OMAP3430_DSS_MOD,
1382 .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
1385 .opt_clks = dss_opt_clks,
1386 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1387 .slaves = omap3430es1_dss_slaves,
1388 .slaves_cnt = ARRAY_SIZE(omap3430es1_dss_slaves),
1389 .masters = omap3xxx_dss_masters,
1390 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1391 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
1392 .flags = HWMOD_NO_IDLEST,
1395 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
1397 .class = &omap2_dss_hwmod_class,
1398 .main_clk = "dss1_alwon_fck", /* instead of dss_fck */
1399 .sdma_reqs = omap3xxx_dss_sdma_chs,
1403 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1404 .module_offs = OMAP3430_DSS_MOD,
1406 .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
1407 .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
1410 .opt_clks = dss_opt_clks,
1411 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1412 .slaves = omap3xxx_dss_slaves,
1413 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_slaves),
1414 .masters = omap3xxx_dss_masters,
1415 .masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
1416 .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2 |
1417 CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
1420 /* l4_core -> dss_dispc */
1421 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
1422 .master = &omap3xxx_l4_core_hwmod,
1423 .slave = &omap3xxx_dss_dispc_hwmod,
1425 .addr = omap2_dss_dispc_addrs,
1428 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
1429 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1430 .flags = OMAP_FIREWALL_L4,
1433 .user = OCP_USER_MPU | OCP_USER_SDMA,
1436 /* dss_dispc slave ports */
1437 static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
1438 &omap3xxx_l4_core__dss_dispc,
1441 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
1442 .name = "dss_dispc",
1443 .class = &omap2_dispc_hwmod_class,
1444 .mpu_irqs = omap2_dispc_irqs,
1445 .main_clk = "dss1_alwon_fck",
1449 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1450 .module_offs = OMAP3430_DSS_MOD,
1453 .slaves = omap3xxx_dss_dispc_slaves,
1454 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_slaves),
1455 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1456 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1457 CHIP_GE_OMAP3630ES1_1),
1458 .flags = HWMOD_NO_IDLEST,
1463 * display serial interface controller
1466 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
1470 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
1476 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
1478 .pa_start = 0x4804FC00,
1479 .pa_end = 0x4804FFFF,
1480 .flags = ADDR_TYPE_RT
1485 /* l4_core -> dss_dsi1 */
1486 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
1487 .master = &omap3xxx_l4_core_hwmod,
1488 .slave = &omap3xxx_dss_dsi1_hwmod,
1489 .addr = omap3xxx_dss_dsi1_addrs,
1492 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
1493 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1494 .flags = OMAP_FIREWALL_L4,
1497 .user = OCP_USER_MPU | OCP_USER_SDMA,
1500 /* dss_dsi1 slave ports */
1501 static struct omap_hwmod_ocp_if *omap3xxx_dss_dsi1_slaves[] = {
1502 &omap3xxx_l4_core__dss_dsi1,
1505 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
1507 .class = &omap3xxx_dsi_hwmod_class,
1508 .mpu_irqs = omap3xxx_dsi1_irqs,
1509 .main_clk = "dss1_alwon_fck",
1513 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1514 .module_offs = OMAP3430_DSS_MOD,
1517 .slaves = omap3xxx_dss_dsi1_slaves,
1518 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_slaves),
1519 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1520 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1521 CHIP_GE_OMAP3630ES1_1),
1522 .flags = HWMOD_NO_IDLEST,
1525 /* l4_core -> dss_rfbi */
1526 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
1527 .master = &omap3xxx_l4_core_hwmod,
1528 .slave = &omap3xxx_dss_rfbi_hwmod,
1530 .addr = omap2_dss_rfbi_addrs,
1533 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
1534 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
1535 .flags = OMAP_FIREWALL_L4,
1538 .user = OCP_USER_MPU | OCP_USER_SDMA,
1541 /* dss_rfbi slave ports */
1542 static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
1543 &omap3xxx_l4_core__dss_rfbi,
1546 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
1548 .class = &omap2_rfbi_hwmod_class,
1549 .main_clk = "dss1_alwon_fck",
1553 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1554 .module_offs = OMAP3430_DSS_MOD,
1557 .slaves = omap3xxx_dss_rfbi_slaves,
1558 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_slaves),
1559 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1560 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1561 CHIP_GE_OMAP3630ES1_1),
1562 .flags = HWMOD_NO_IDLEST,
1565 /* l4_core -> dss_venc */
1566 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
1567 .master = &omap3xxx_l4_core_hwmod,
1568 .slave = &omap3xxx_dss_venc_hwmod,
1569 .clk = "dss_tv_fck",
1570 .addr = omap2_dss_venc_addrs,
1573 .l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
1574 .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
1575 .flags = OMAP_FIREWALL_L4,
1578 .flags = OCPIF_SWSUP_IDLE,
1579 .user = OCP_USER_MPU | OCP_USER_SDMA,
1582 /* dss_venc slave ports */
1583 static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
1584 &omap3xxx_l4_core__dss_venc,
1587 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
1589 .class = &omap2_venc_hwmod_class,
1590 .main_clk = "dss1_alwon_fck",
1594 .module_bit = OMAP3430_EN_DSS1_SHIFT,
1595 .module_offs = OMAP3430_DSS_MOD,
1598 .slaves = omap3xxx_dss_venc_slaves,
1599 .slaves_cnt = ARRAY_SIZE(omap3xxx_dss_venc_slaves),
1600 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
1601 CHIP_GE_OMAP3430ES2 | CHIP_IS_OMAP3630ES1 |
1602 CHIP_GE_OMAP3630ES1_1),
1603 .flags = HWMOD_NO_IDLEST,
1608 static struct omap_i2c_dev_attr i2c1_dev_attr = {
1609 .fifo_depth = 8, /* bytes */
1612 static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
1613 &omap3_l4_core__i2c1,
1616 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
1618 .mpu_irqs = omap2_i2c1_mpu_irqs,
1619 .sdma_reqs = omap2_i2c1_sdma_reqs,
1620 .main_clk = "i2c1_fck",
1623 .module_offs = CORE_MOD,
1625 .module_bit = OMAP3430_EN_I2C1_SHIFT,
1627 .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
1630 .slaves = omap3xxx_i2c1_slaves,
1631 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves),
1632 .class = &i2c_class,
1633 .dev_attr = &i2c1_dev_attr,
1634 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1639 static struct omap_i2c_dev_attr i2c2_dev_attr = {
1640 .fifo_depth = 8, /* bytes */
1643 static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
1644 &omap3_l4_core__i2c2,
1647 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
1649 .mpu_irqs = omap2_i2c2_mpu_irqs,
1650 .sdma_reqs = omap2_i2c2_sdma_reqs,
1651 .main_clk = "i2c2_fck",
1654 .module_offs = CORE_MOD,
1656 .module_bit = OMAP3430_EN_I2C2_SHIFT,
1658 .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
1661 .slaves = omap3xxx_i2c2_slaves,
1662 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves),
1663 .class = &i2c_class,
1664 .dev_attr = &i2c2_dev_attr,
1665 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1670 static struct omap_i2c_dev_attr i2c3_dev_attr = {
1671 .fifo_depth = 64, /* bytes */
1674 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1675 { .irq = INT_34XX_I2C3_IRQ, },
1679 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
1680 { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
1681 { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
1685 static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
1686 &omap3_l4_core__i2c3,
1689 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
1691 .mpu_irqs = i2c3_mpu_irqs,
1692 .sdma_reqs = i2c3_sdma_reqs,
1693 .main_clk = "i2c3_fck",
1696 .module_offs = CORE_MOD,
1698 .module_bit = OMAP3430_EN_I2C3_SHIFT,
1700 .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
1703 .slaves = omap3xxx_i2c3_slaves,
1704 .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves),
1705 .class = &i2c_class,
1706 .dev_attr = &i2c3_dev_attr,
1707 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1710 /* l4_wkup -> gpio1 */
1711 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
1713 .pa_start = 0x48310000,
1714 .pa_end = 0x483101ff,
1715 .flags = ADDR_TYPE_RT
1720 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
1721 .master = &omap3xxx_l4_wkup_hwmod,
1722 .slave = &omap3xxx_gpio1_hwmod,
1723 .addr = omap3xxx_gpio1_addrs,
1724 .user = OCP_USER_MPU | OCP_USER_SDMA,
1727 /* l4_per -> gpio2 */
1728 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
1730 .pa_start = 0x49050000,
1731 .pa_end = 0x490501ff,
1732 .flags = ADDR_TYPE_RT
1737 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
1738 .master = &omap3xxx_l4_per_hwmod,
1739 .slave = &omap3xxx_gpio2_hwmod,
1740 .addr = omap3xxx_gpio2_addrs,
1741 .user = OCP_USER_MPU | OCP_USER_SDMA,
1744 /* l4_per -> gpio3 */
1745 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
1747 .pa_start = 0x49052000,
1748 .pa_end = 0x490521ff,
1749 .flags = ADDR_TYPE_RT
1754 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
1755 .master = &omap3xxx_l4_per_hwmod,
1756 .slave = &omap3xxx_gpio3_hwmod,
1757 .addr = omap3xxx_gpio3_addrs,
1758 .user = OCP_USER_MPU | OCP_USER_SDMA,
1761 /* l4_per -> gpio4 */
1762 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
1764 .pa_start = 0x49054000,
1765 .pa_end = 0x490541ff,
1766 .flags = ADDR_TYPE_RT
1771 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
1772 .master = &omap3xxx_l4_per_hwmod,
1773 .slave = &omap3xxx_gpio4_hwmod,
1774 .addr = omap3xxx_gpio4_addrs,
1775 .user = OCP_USER_MPU | OCP_USER_SDMA,
1778 /* l4_per -> gpio5 */
1779 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
1781 .pa_start = 0x49056000,
1782 .pa_end = 0x490561ff,
1783 .flags = ADDR_TYPE_RT
1788 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
1789 .master = &omap3xxx_l4_per_hwmod,
1790 .slave = &omap3xxx_gpio5_hwmod,
1791 .addr = omap3xxx_gpio5_addrs,
1792 .user = OCP_USER_MPU | OCP_USER_SDMA,
1795 /* l4_per -> gpio6 */
1796 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
1798 .pa_start = 0x49058000,
1799 .pa_end = 0x490581ff,
1800 .flags = ADDR_TYPE_RT
1805 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
1806 .master = &omap3xxx_l4_per_hwmod,
1807 .slave = &omap3xxx_gpio6_hwmod,
1808 .addr = omap3xxx_gpio6_addrs,
1809 .user = OCP_USER_MPU | OCP_USER_SDMA,
1814 * general purpose io module
1817 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
1819 .sysc_offs = 0x0010,
1820 .syss_offs = 0x0014,
1821 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1822 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1823 SYSS_HAS_RESET_STATUS),
1824 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1825 .sysc_fields = &omap_hwmod_sysc_type1,
1828 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
1830 .sysc = &omap3xxx_gpio_sysc,
1835 static struct omap_gpio_dev_attr gpio_dev_attr = {
1841 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1842 { .role = "dbclk", .clk = "gpio1_dbck", },
1845 static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
1846 &omap3xxx_l4_wkup__gpio1,
1849 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
1851 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1852 .mpu_irqs = omap2_gpio1_irqs,
1853 .main_clk = "gpio1_ick",
1854 .opt_clks = gpio1_opt_clks,
1855 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1859 .module_bit = OMAP3430_EN_GPIO1_SHIFT,
1860 .module_offs = WKUP_MOD,
1862 .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
1865 .slaves = omap3xxx_gpio1_slaves,
1866 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio1_slaves),
1867 .class = &omap3xxx_gpio_hwmod_class,
1868 .dev_attr = &gpio_dev_attr,
1869 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1873 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1874 { .role = "dbclk", .clk = "gpio2_dbck", },
1877 static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
1878 &omap3xxx_l4_per__gpio2,
1881 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
1883 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1884 .mpu_irqs = omap2_gpio2_irqs,
1885 .main_clk = "gpio2_ick",
1886 .opt_clks = gpio2_opt_clks,
1887 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1891 .module_bit = OMAP3430_EN_GPIO2_SHIFT,
1892 .module_offs = OMAP3430_PER_MOD,
1894 .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
1897 .slaves = omap3xxx_gpio2_slaves,
1898 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio2_slaves),
1899 .class = &omap3xxx_gpio_hwmod_class,
1900 .dev_attr = &gpio_dev_attr,
1901 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1905 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1906 { .role = "dbclk", .clk = "gpio3_dbck", },
1909 static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
1910 &omap3xxx_l4_per__gpio3,
1913 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
1915 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1916 .mpu_irqs = omap2_gpio3_irqs,
1917 .main_clk = "gpio3_ick",
1918 .opt_clks = gpio3_opt_clks,
1919 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1923 .module_bit = OMAP3430_EN_GPIO3_SHIFT,
1924 .module_offs = OMAP3430_PER_MOD,
1926 .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
1929 .slaves = omap3xxx_gpio3_slaves,
1930 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio3_slaves),
1931 .class = &omap3xxx_gpio_hwmod_class,
1932 .dev_attr = &gpio_dev_attr,
1933 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1937 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1938 { .role = "dbclk", .clk = "gpio4_dbck", },
1941 static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
1942 &omap3xxx_l4_per__gpio4,
1945 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
1947 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1948 .mpu_irqs = omap2_gpio4_irqs,
1949 .main_clk = "gpio4_ick",
1950 .opt_clks = gpio4_opt_clks,
1951 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1955 .module_bit = OMAP3430_EN_GPIO4_SHIFT,
1956 .module_offs = OMAP3430_PER_MOD,
1958 .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
1961 .slaves = omap3xxx_gpio4_slaves,
1962 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio4_slaves),
1963 .class = &omap3xxx_gpio_hwmod_class,
1964 .dev_attr = &gpio_dev_attr,
1965 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
1969 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
1970 { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
1974 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1975 { .role = "dbclk", .clk = "gpio5_dbck", },
1978 static struct omap_hwmod_ocp_if *omap3xxx_gpio5_slaves[] = {
1979 &omap3xxx_l4_per__gpio5,
1982 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
1984 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1985 .mpu_irqs = omap3xxx_gpio5_irqs,
1986 .main_clk = "gpio5_ick",
1987 .opt_clks = gpio5_opt_clks,
1988 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1992 .module_bit = OMAP3430_EN_GPIO5_SHIFT,
1993 .module_offs = OMAP3430_PER_MOD,
1995 .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
1998 .slaves = omap3xxx_gpio5_slaves,
1999 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio5_slaves),
2000 .class = &omap3xxx_gpio_hwmod_class,
2001 .dev_attr = &gpio_dev_attr,
2002 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2006 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
2007 { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
2011 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2012 { .role = "dbclk", .clk = "gpio6_dbck", },
2015 static struct omap_hwmod_ocp_if *omap3xxx_gpio6_slaves[] = {
2016 &omap3xxx_l4_per__gpio6,
2019 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
2021 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2022 .mpu_irqs = omap3xxx_gpio6_irqs,
2023 .main_clk = "gpio6_ick",
2024 .opt_clks = gpio6_opt_clks,
2025 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2029 .module_bit = OMAP3430_EN_GPIO6_SHIFT,
2030 .module_offs = OMAP3430_PER_MOD,
2032 .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
2035 .slaves = omap3xxx_gpio6_slaves,
2036 .slaves_cnt = ARRAY_SIZE(omap3xxx_gpio6_slaves),
2037 .class = &omap3xxx_gpio_hwmod_class,
2038 .dev_attr = &gpio_dev_attr,
2039 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2042 /* dma_system -> L3 */
2043 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2044 .master = &omap3xxx_dma_system_hwmod,
2045 .slave = &omap3xxx_l3_main_hwmod,
2046 .clk = "core_l3_ick",
2047 .user = OCP_USER_MPU | OCP_USER_SDMA,
2050 /* dma attributes */
2051 static struct omap_dma_dev_attr dma_dev_attr = {
2052 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
2053 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
2057 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
2059 .sysc_offs = 0x002c,
2060 .syss_offs = 0x0028,
2061 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2062 SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
2063 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
2064 SYSS_HAS_RESET_STATUS),
2065 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2066 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2067 .sysc_fields = &omap_hwmod_sysc_type1,
2070 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
2072 .sysc = &omap3xxx_dma_sysc,
2076 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2078 .pa_start = 0x48056000,
2079 .pa_end = 0x48056fff,
2080 .flags = ADDR_TYPE_RT
2085 /* dma_system master ports */
2086 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
2087 &omap3xxx_dma_system__l3,
2090 /* l4_cfg -> dma_system */
2091 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2092 .master = &omap3xxx_l4_core_hwmod,
2093 .slave = &omap3xxx_dma_system_hwmod,
2094 .clk = "core_l4_ick",
2095 .addr = omap3xxx_dma_system_addrs,
2096 .user = OCP_USER_MPU | OCP_USER_SDMA,
2099 /* dma_system slave ports */
2100 static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
2101 &omap3xxx_l4_core__dma_system,
2104 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2106 .class = &omap3xxx_dma_hwmod_class,
2107 .mpu_irqs = omap2_dma_system_irqs,
2108 .main_clk = "core_l3_ick",
2111 .module_offs = CORE_MOD,
2113 .module_bit = OMAP3430_ST_SDMA_SHIFT,
2115 .idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
2118 .slaves = omap3xxx_dma_system_slaves,
2119 .slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
2120 .masters = omap3xxx_dma_system_masters,
2121 .masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
2122 .dev_attr = &dma_dev_attr,
2123 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2124 .flags = HWMOD_NO_IDLEST,
2129 * multi channel buffered serial port controller
2132 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2133 .sysc_offs = 0x008c,
2134 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2135 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2136 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2137 .sysc_fields = &omap_hwmod_sysc_type1,
2141 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2143 .sysc = &omap3xxx_mcbsp_sysc,
2144 .rev = MCBSP_CONFIG_TYPE3,
2148 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2149 { .name = "irq", .irq = 16 },
2150 { .name = "tx", .irq = 59 },
2151 { .name = "rx", .irq = 60 },
2155 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2158 .pa_start = 0x48074000,
2159 .pa_end = 0x480740ff,
2160 .flags = ADDR_TYPE_RT
2165 /* l4_core -> mcbsp1 */
2166 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2167 .master = &omap3xxx_l4_core_hwmod,
2168 .slave = &omap3xxx_mcbsp1_hwmod,
2169 .clk = "mcbsp1_ick",
2170 .addr = omap3xxx_mcbsp1_addrs,
2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2174 /* mcbsp1 slave ports */
2175 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2176 &omap3xxx_l4_core__mcbsp1,
2179 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2181 .class = &omap3xxx_mcbsp_hwmod_class,
2182 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2183 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
2184 .main_clk = "mcbsp1_fck",
2188 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2189 .module_offs = CORE_MOD,
2191 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2194 .slaves = omap3xxx_mcbsp1_slaves,
2195 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2196 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2200 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2201 { .name = "irq", .irq = 17 },
2202 { .name = "tx", .irq = 62 },
2203 { .name = "rx", .irq = 63 },
2207 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2210 .pa_start = 0x49022000,
2211 .pa_end = 0x490220ff,
2212 .flags = ADDR_TYPE_RT
2217 /* l4_per -> mcbsp2 */
2218 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2219 .master = &omap3xxx_l4_per_hwmod,
2220 .slave = &omap3xxx_mcbsp2_hwmod,
2221 .clk = "mcbsp2_ick",
2222 .addr = omap3xxx_mcbsp2_addrs,
2223 .user = OCP_USER_MPU | OCP_USER_SDMA,
2226 /* mcbsp2 slave ports */
2227 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2228 &omap3xxx_l4_per__mcbsp2,
2231 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2232 .sidetone = "mcbsp2_sidetone",
2235 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2237 .class = &omap3xxx_mcbsp_hwmod_class,
2238 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2239 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
2240 .main_clk = "mcbsp2_fck",
2244 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2245 .module_offs = OMAP3430_PER_MOD,
2247 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2250 .slaves = omap3xxx_mcbsp2_slaves,
2251 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2252 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2253 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2257 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2258 { .name = "irq", .irq = 22 },
2259 { .name = "tx", .irq = 89 },
2260 { .name = "rx", .irq = 90 },
2264 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2267 .pa_start = 0x49024000,
2268 .pa_end = 0x490240ff,
2269 .flags = ADDR_TYPE_RT
2274 /* l4_per -> mcbsp3 */
2275 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2276 .master = &omap3xxx_l4_per_hwmod,
2277 .slave = &omap3xxx_mcbsp3_hwmod,
2278 .clk = "mcbsp3_ick",
2279 .addr = omap3xxx_mcbsp3_addrs,
2280 .user = OCP_USER_MPU | OCP_USER_SDMA,
2283 /* mcbsp3 slave ports */
2284 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2285 &omap3xxx_l4_per__mcbsp3,
2288 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2289 .sidetone = "mcbsp3_sidetone",
2292 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2294 .class = &omap3xxx_mcbsp_hwmod_class,
2295 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2296 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
2297 .main_clk = "mcbsp3_fck",
2301 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2302 .module_offs = OMAP3430_PER_MOD,
2304 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2307 .slaves = omap3xxx_mcbsp3_slaves,
2308 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2309 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2314 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2315 { .name = "irq", .irq = 23 },
2316 { .name = "tx", .irq = 54 },
2317 { .name = "rx", .irq = 55 },
2321 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2322 { .name = "rx", .dma_req = 20 },
2323 { .name = "tx", .dma_req = 19 },
2327 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2330 .pa_start = 0x49026000,
2331 .pa_end = 0x490260ff,
2332 .flags = ADDR_TYPE_RT
2337 /* l4_per -> mcbsp4 */
2338 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2339 .master = &omap3xxx_l4_per_hwmod,
2340 .slave = &omap3xxx_mcbsp4_hwmod,
2341 .clk = "mcbsp4_ick",
2342 .addr = omap3xxx_mcbsp4_addrs,
2343 .user = OCP_USER_MPU | OCP_USER_SDMA,
2346 /* mcbsp4 slave ports */
2347 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2348 &omap3xxx_l4_per__mcbsp4,
2351 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2353 .class = &omap3xxx_mcbsp_hwmod_class,
2354 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2355 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2356 .main_clk = "mcbsp4_fck",
2360 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2361 .module_offs = OMAP3430_PER_MOD,
2363 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2366 .slaves = omap3xxx_mcbsp4_slaves,
2367 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2368 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2372 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2373 { .name = "irq", .irq = 27 },
2374 { .name = "tx", .irq = 81 },
2375 { .name = "rx", .irq = 82 },
2379 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2380 { .name = "rx", .dma_req = 22 },
2381 { .name = "tx", .dma_req = 21 },
2385 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2388 .pa_start = 0x48096000,
2389 .pa_end = 0x480960ff,
2390 .flags = ADDR_TYPE_RT
2395 /* l4_core -> mcbsp5 */
2396 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2397 .master = &omap3xxx_l4_core_hwmod,
2398 .slave = &omap3xxx_mcbsp5_hwmod,
2399 .clk = "mcbsp5_ick",
2400 .addr = omap3xxx_mcbsp5_addrs,
2401 .user = OCP_USER_MPU | OCP_USER_SDMA,
2404 /* mcbsp5 slave ports */
2405 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2406 &omap3xxx_l4_core__mcbsp5,
2409 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2411 .class = &omap3xxx_mcbsp_hwmod_class,
2412 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2413 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2414 .main_clk = "mcbsp5_fck",
2418 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2419 .module_offs = CORE_MOD,
2421 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2424 .slaves = omap3xxx_mcbsp5_slaves,
2425 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2426 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2428 /* 'mcbsp sidetone' class */
2430 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2431 .sysc_offs = 0x0010,
2432 .sysc_flags = SYSC_HAS_AUTOIDLE,
2433 .sysc_fields = &omap_hwmod_sysc_type1,
2436 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2437 .name = "mcbsp_sidetone",
2438 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2441 /* mcbsp2_sidetone */
2442 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2443 { .name = "irq", .irq = 4 },
2447 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2450 .pa_start = 0x49028000,
2451 .pa_end = 0x490280ff,
2452 .flags = ADDR_TYPE_RT
2457 /* l4_per -> mcbsp2_sidetone */
2458 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2459 .master = &omap3xxx_l4_per_hwmod,
2460 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2461 .clk = "mcbsp2_ick",
2462 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2463 .user = OCP_USER_MPU,
2466 /* mcbsp2_sidetone slave ports */
2467 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2468 &omap3xxx_l4_per__mcbsp2_sidetone,
2471 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2472 .name = "mcbsp2_sidetone",
2473 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2474 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2475 .main_clk = "mcbsp2_fck",
2479 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2480 .module_offs = OMAP3430_PER_MOD,
2482 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2485 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2486 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2487 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2490 /* mcbsp3_sidetone */
2491 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2492 { .name = "irq", .irq = 5 },
2496 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2499 .pa_start = 0x4902A000,
2500 .pa_end = 0x4902A0ff,
2501 .flags = ADDR_TYPE_RT
2506 /* l4_per -> mcbsp3_sidetone */
2507 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2508 .master = &omap3xxx_l4_per_hwmod,
2509 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2510 .clk = "mcbsp3_ick",
2511 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2512 .user = OCP_USER_MPU,
2515 /* mcbsp3_sidetone slave ports */
2516 static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2517 &omap3xxx_l4_per__mcbsp3_sidetone,
2520 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2521 .name = "mcbsp3_sidetone",
2522 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2523 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2524 .main_clk = "mcbsp3_fck",
2528 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2529 .module_offs = OMAP3430_PER_MOD,
2531 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2534 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2535 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2536 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2541 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2545 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
2547 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
2548 .clockact = CLOCKACT_TEST_ICLK,
2549 .sysc_fields = &omap34xx_sr_sysc_fields,
2552 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
2553 .name = "smartreflex",
2554 .sysc = &omap34xx_sr_sysc,
2558 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
2563 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
2565 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2566 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
2568 .sysc_fields = &omap36xx_sr_sysc_fields,
2571 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
2572 .name = "smartreflex",
2573 .sysc = &omap36xx_sr_sysc,
2578 static struct omap_hwmod_ocp_if *omap3_sr1_slaves[] = {
2579 &omap3_l4_core__sr1,
2582 static struct omap_hwmod omap34xx_sr1_hwmod = {
2583 .name = "sr1_hwmod",
2584 .class = &omap34xx_smartreflex_hwmod_class,
2585 .main_clk = "sr1_fck",
2590 .module_bit = OMAP3430_EN_SR1_SHIFT,
2591 .module_offs = WKUP_MOD,
2593 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2596 .slaves = omap3_sr1_slaves,
2597 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2598 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2599 CHIP_IS_OMAP3430ES3_0 |
2600 CHIP_IS_OMAP3430ES3_1),
2601 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2604 static struct omap_hwmod omap36xx_sr1_hwmod = {
2605 .name = "sr1_hwmod",
2606 .class = &omap36xx_smartreflex_hwmod_class,
2607 .main_clk = "sr1_fck",
2612 .module_bit = OMAP3430_EN_SR1_SHIFT,
2613 .module_offs = WKUP_MOD,
2615 .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
2618 .slaves = omap3_sr1_slaves,
2619 .slaves_cnt = ARRAY_SIZE(omap3_sr1_slaves),
2620 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2624 static struct omap_hwmod_ocp_if *omap3_sr2_slaves[] = {
2625 &omap3_l4_core__sr2,
2628 static struct omap_hwmod omap34xx_sr2_hwmod = {
2629 .name = "sr2_hwmod",
2630 .class = &omap34xx_smartreflex_hwmod_class,
2631 .main_clk = "sr2_fck",
2636 .module_bit = OMAP3430_EN_SR2_SHIFT,
2637 .module_offs = WKUP_MOD,
2639 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2642 .slaves = omap3_sr2_slaves,
2643 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2644 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2 |
2645 CHIP_IS_OMAP3430ES3_0 |
2646 CHIP_IS_OMAP3430ES3_1),
2647 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2650 static struct omap_hwmod omap36xx_sr2_hwmod = {
2651 .name = "sr2_hwmod",
2652 .class = &omap36xx_smartreflex_hwmod_class,
2653 .main_clk = "sr2_fck",
2658 .module_bit = OMAP3430_EN_SR2_SHIFT,
2659 .module_offs = WKUP_MOD,
2661 .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
2664 .slaves = omap3_sr2_slaves,
2665 .slaves_cnt = ARRAY_SIZE(omap3_sr2_slaves),
2666 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2671 * mailbox module allowing communication between the on-chip processors
2672 * using a queued mailbox-interrupt mechanism.
2675 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
2679 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2680 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2681 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2682 .sysc_fields = &omap_hwmod_sysc_type1,
2685 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
2687 .sysc = &omap3xxx_mailbox_sysc,
2690 static struct omap_hwmod omap3xxx_mailbox_hwmod;
2691 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
2696 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2698 .pa_start = 0x48094000,
2699 .pa_end = 0x480941ff,
2700 .flags = ADDR_TYPE_RT,
2705 /* l4_core -> mailbox */
2706 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
2707 .master = &omap3xxx_l4_core_hwmod,
2708 .slave = &omap3xxx_mailbox_hwmod,
2709 .addr = omap3xxx_mailbox_addrs,
2710 .user = OCP_USER_MPU | OCP_USER_SDMA,
2713 /* mailbox slave ports */
2714 static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
2715 &omap3xxx_l4_core__mailbox,
2718 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
2720 .class = &omap3xxx_mailbox_hwmod_class,
2721 .mpu_irqs = omap3xxx_mailbox_irqs,
2722 .main_clk = "mailboxes_ick",
2726 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
2727 .module_offs = CORE_MOD,
2729 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
2732 .slaves = omap3xxx_mailbox_slaves,
2733 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
2734 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2737 /* l4 core -> mcspi1 interface */
2738 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
2739 .master = &omap3xxx_l4_core_hwmod,
2740 .slave = &omap34xx_mcspi1,
2741 .clk = "mcspi1_ick",
2742 .addr = omap2_mcspi1_addr_space,
2743 .user = OCP_USER_MPU | OCP_USER_SDMA,
2746 /* l4 core -> mcspi2 interface */
2747 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
2748 .master = &omap3xxx_l4_core_hwmod,
2749 .slave = &omap34xx_mcspi2,
2750 .clk = "mcspi2_ick",
2751 .addr = omap2_mcspi2_addr_space,
2752 .user = OCP_USER_MPU | OCP_USER_SDMA,
2755 /* l4 core -> mcspi3 interface */
2756 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
2757 .master = &omap3xxx_l4_core_hwmod,
2758 .slave = &omap34xx_mcspi3,
2759 .clk = "mcspi3_ick",
2760 .addr = omap2430_mcspi3_addr_space,
2761 .user = OCP_USER_MPU | OCP_USER_SDMA,
2764 /* l4 core -> mcspi4 interface */
2765 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
2767 .pa_start = 0x480ba000,
2768 .pa_end = 0x480ba0ff,
2769 .flags = ADDR_TYPE_RT,
2774 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
2775 .master = &omap3xxx_l4_core_hwmod,
2776 .slave = &omap34xx_mcspi4,
2777 .clk = "mcspi4_ick",
2778 .addr = omap34xx_mcspi4_addr_space,
2779 .user = OCP_USER_MPU | OCP_USER_SDMA,
2784 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2788 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
2790 .sysc_offs = 0x0010,
2791 .syss_offs = 0x0014,
2792 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2793 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2794 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2795 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2796 .sysc_fields = &omap_hwmod_sysc_type1,
2799 static struct omap_hwmod_class omap34xx_mcspi_class = {
2801 .sysc = &omap34xx_mcspi_sysc,
2802 .rev = OMAP3_MCSPI_REV,
2806 static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
2807 &omap34xx_l4_core__mcspi1,
2810 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
2811 .num_chipselect = 4,
2814 static struct omap_hwmod omap34xx_mcspi1 = {
2816 .mpu_irqs = omap2_mcspi1_mpu_irqs,
2817 .sdma_reqs = omap2_mcspi1_sdma_reqs,
2818 .main_clk = "mcspi1_fck",
2821 .module_offs = CORE_MOD,
2823 .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
2825 .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
2828 .slaves = omap34xx_mcspi1_slaves,
2829 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi1_slaves),
2830 .class = &omap34xx_mcspi_class,
2831 .dev_attr = &omap_mcspi1_dev_attr,
2832 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2836 static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
2837 &omap34xx_l4_core__mcspi2,
2840 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
2841 .num_chipselect = 2,
2844 static struct omap_hwmod omap34xx_mcspi2 = {
2846 .mpu_irqs = omap2_mcspi2_mpu_irqs,
2847 .sdma_reqs = omap2_mcspi2_sdma_reqs,
2848 .main_clk = "mcspi2_fck",
2851 .module_offs = CORE_MOD,
2853 .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
2855 .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
2858 .slaves = omap34xx_mcspi2_slaves,
2859 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi2_slaves),
2860 .class = &omap34xx_mcspi_class,
2861 .dev_attr = &omap_mcspi2_dev_attr,
2862 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2866 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
2867 { .name = "irq", .irq = 91 }, /* 91 */
2871 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
2872 { .name = "tx0", .dma_req = 15 },
2873 { .name = "rx0", .dma_req = 16 },
2874 { .name = "tx1", .dma_req = 23 },
2875 { .name = "rx1", .dma_req = 24 },
2879 static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
2880 &omap34xx_l4_core__mcspi3,
2883 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
2884 .num_chipselect = 2,
2887 static struct omap_hwmod omap34xx_mcspi3 = {
2889 .mpu_irqs = omap34xx_mcspi3_mpu_irqs,
2890 .sdma_reqs = omap34xx_mcspi3_sdma_reqs,
2891 .main_clk = "mcspi3_fck",
2894 .module_offs = CORE_MOD,
2896 .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
2898 .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
2901 .slaves = omap34xx_mcspi3_slaves,
2902 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi3_slaves),
2903 .class = &omap34xx_mcspi_class,
2904 .dev_attr = &omap_mcspi3_dev_attr,
2905 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2909 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
2910 { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
2914 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
2915 { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
2916 { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
2920 static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
2921 &omap34xx_l4_core__mcspi4,
2924 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
2925 .num_chipselect = 1,
2928 static struct omap_hwmod omap34xx_mcspi4 = {
2930 .mpu_irqs = omap34xx_mcspi4_mpu_irqs,
2931 .sdma_reqs = omap34xx_mcspi4_sdma_reqs,
2932 .main_clk = "mcspi4_fck",
2935 .module_offs = CORE_MOD,
2937 .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
2939 .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
2942 .slaves = omap34xx_mcspi4_slaves,
2943 .slaves_cnt = ARRAY_SIZE(omap34xx_mcspi4_slaves),
2944 .class = &omap34xx_mcspi_class,
2945 .dev_attr = &omap_mcspi4_dev_attr,
2946 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2952 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
2954 .sysc_offs = 0x0404,
2955 .syss_offs = 0x0408,
2956 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
2957 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2959 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2960 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2961 .sysc_fields = &omap_hwmod_sysc_type1,
2964 static struct omap_hwmod_class usbotg_class = {
2966 .sysc = &omap3xxx_usbhsotg_sysc,
2969 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
2971 { .name = "mc", .irq = 92 },
2972 { .name = "dma", .irq = 93 },
2976 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
2977 .name = "usb_otg_hs",
2978 .mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
2979 .main_clk = "hsotgusb_ick",
2983 .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
2984 .module_offs = CORE_MOD,
2986 .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
2987 .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
2990 .masters = omap3xxx_usbhsotg_masters,
2991 .masters_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_masters),
2992 .slaves = omap3xxx_usbhsotg_slaves,
2993 .slaves_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_slaves),
2994 .class = &usbotg_class,
2997 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
2998 * broken when autoidle is enabled
2999 * workaround is to disable the autoidle bit at module level.
3001 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
3002 | HWMOD_SWSUP_MSTANDBY,
3003 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
3007 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
3009 { .name = "mc", .irq = 71 },
3013 static struct omap_hwmod_class am35xx_usbotg_class = {
3014 .name = "am35xx_usbotg",
3018 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
3019 .name = "am35x_otg_hs",
3020 .mpu_irqs = am35xx_usbhsotg_mpu_irqs,
3026 .masters = am35xx_usbhsotg_masters,
3027 .masters_cnt = ARRAY_SIZE(am35xx_usbhsotg_masters),
3028 .slaves = am35xx_usbhsotg_slaves,
3029 .slaves_cnt = ARRAY_SIZE(am35xx_usbhsotg_slaves),
3030 .class = &am35xx_usbotg_class,
3031 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
3034 /* MMC/SD/SDIO common */
3036 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3040 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3041 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3042 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3043 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3044 .sysc_fields = &omap_hwmod_sysc_type1,
3047 static struct omap_hwmod_class omap34xx_mmc_class = {
3049 .sysc = &omap34xx_mmc_sysc,
3054 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3059 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3060 { .name = "tx", .dma_req = 61, },
3061 { .name = "rx", .dma_req = 62, },
3065 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3066 { .role = "dbck", .clk = "omap_32k_fck", },
3069 static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3070 &omap3xxx_l4_core__mmc1,
3073 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3074 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3077 static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3079 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3080 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3081 .opt_clks = omap34xx_mmc1_opt_clks,
3082 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3083 .main_clk = "mmchs1_fck",
3086 .module_offs = CORE_MOD,
3088 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3090 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3093 .dev_attr = &mmc1_dev_attr,
3094 .slaves = omap3xxx_mmc1_slaves,
3095 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3096 .class = &omap34xx_mmc_class,
3097 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3102 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3103 { .irq = INT_24XX_MMC2_IRQ, },
3107 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3108 { .name = "tx", .dma_req = 47, },
3109 { .name = "rx", .dma_req = 48, },
3113 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3114 { .role = "dbck", .clk = "omap_32k_fck", },
3117 static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3118 &omap3xxx_l4_core__mmc2,
3121 static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3123 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3124 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3125 .opt_clks = omap34xx_mmc2_opt_clks,
3126 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3127 .main_clk = "mmchs2_fck",
3130 .module_offs = CORE_MOD,
3132 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3134 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3137 .slaves = omap3xxx_mmc2_slaves,
3138 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3139 .class = &omap34xx_mmc_class,
3140 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3145 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3150 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3151 { .name = "tx", .dma_req = 77, },
3152 { .name = "rx", .dma_req = 78, },
3156 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3157 { .role = "dbck", .clk = "omap_32k_fck", },
3160 static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3161 &omap3xxx_l4_core__mmc3,
3164 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3166 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3167 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3168 .opt_clks = omap34xx_mmc3_opt_clks,
3169 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3170 .main_clk = "mmchs3_fck",
3174 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3176 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3179 .slaves = omap3xxx_mmc3_slaves,
3180 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3181 .class = &omap34xx_mmc_class,
3182 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3185 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
3186 &omap3xxx_l3_main_hwmod,
3187 &omap3xxx_l4_core_hwmod,
3188 &omap3xxx_l4_per_hwmod,
3189 &omap3xxx_l4_wkup_hwmod,
3190 &omap3xxx_mmc1_hwmod,
3191 &omap3xxx_mmc2_hwmod,
3192 &omap3xxx_mmc3_hwmod,
3193 &omap3xxx_mpu_hwmod,
3194 &omap3xxx_iva_hwmod,
3196 &omap3xxx_timer1_hwmod,
3197 &omap3xxx_timer2_hwmod,
3198 &omap3xxx_timer3_hwmod,
3199 &omap3xxx_timer4_hwmod,
3200 &omap3xxx_timer5_hwmod,
3201 &omap3xxx_timer6_hwmod,
3202 &omap3xxx_timer7_hwmod,
3203 &omap3xxx_timer8_hwmod,
3204 &omap3xxx_timer9_hwmod,
3205 &omap3xxx_timer10_hwmod,
3206 &omap3xxx_timer11_hwmod,
3207 &omap3xxx_timer12_hwmod,
3209 &omap3xxx_wd_timer2_hwmod,
3210 &omap3xxx_uart1_hwmod,
3211 &omap3xxx_uart2_hwmod,
3212 &omap3xxx_uart3_hwmod,
3213 &omap3xxx_uart4_hwmod,
3215 &omap3430es1_dss_core_hwmod,
3216 &omap3xxx_dss_core_hwmod,
3217 &omap3xxx_dss_dispc_hwmod,
3218 &omap3xxx_dss_dsi1_hwmod,
3219 &omap3xxx_dss_rfbi_hwmod,
3220 &omap3xxx_dss_venc_hwmod,
3223 &omap3xxx_i2c1_hwmod,
3224 &omap3xxx_i2c2_hwmod,
3225 &omap3xxx_i2c3_hwmod,
3226 &omap34xx_sr1_hwmod,
3227 &omap34xx_sr2_hwmod,
3228 &omap36xx_sr1_hwmod,
3229 &omap36xx_sr2_hwmod,
3233 &omap3xxx_gpio1_hwmod,
3234 &omap3xxx_gpio2_hwmod,
3235 &omap3xxx_gpio3_hwmod,
3236 &omap3xxx_gpio4_hwmod,
3237 &omap3xxx_gpio5_hwmod,
3238 &omap3xxx_gpio6_hwmod,
3240 /* dma_system class*/
3241 &omap3xxx_dma_system_hwmod,
3244 &omap3xxx_mcbsp1_hwmod,
3245 &omap3xxx_mcbsp2_hwmod,
3246 &omap3xxx_mcbsp3_hwmod,
3247 &omap3xxx_mcbsp4_hwmod,
3248 &omap3xxx_mcbsp5_hwmod,
3249 &omap3xxx_mcbsp2_sidetone_hwmod,
3250 &omap3xxx_mcbsp3_sidetone_hwmod,
3253 &omap3xxx_mailbox_hwmod,
3262 &omap3xxx_usbhsotg_hwmod,
3264 /* usbotg for am35x */
3265 &am35xx_usbhsotg_hwmod,
3270 int __init omap3xxx_hwmod_init(void)
3272 return omap_hwmod_register(omap3xxx_hwmods);