2 * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
4 * Copyright (C) 2011 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <plat/omap_hwmod.h>
12 #include <plat/serial.h>
14 #include <plat/dmtimer.h>
15 #include <plat/mcspi.h>
17 #include <mach/irqs.h>
19 #include "omap_hwmod_common_data.h"
22 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
27 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
28 { .name = "dispc", .dma_req = 5 },
31 /* OMAP2xxx Timer Common */
32 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
36 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
37 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
39 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
40 .sysc_fields = &omap_hwmod_sysc_type1,
43 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
45 .sysc = &omap2xxx_timer_sysc,
46 .rev = OMAP_TIMER_IP_VERSION_1,
51 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
55 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
59 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
60 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
61 .sysc_fields = &omap_hwmod_sysc_type1,
64 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
66 .sysc = &omap2xxx_wd_timer_sysc,
67 .pre_shutdown = &omap2_wd_timer_disable
72 * general purpose io module
74 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
78 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
79 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
80 SYSS_HAS_RESET_STATUS),
81 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
82 .sysc_fields = &omap_hwmod_sysc_type1,
85 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
87 .sysc = &omap2xxx_gpio_sysc,
92 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
96 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
97 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
98 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
99 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
100 .sysc_fields = &omap_hwmod_sysc_type1,
103 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
105 .sysc = &omap2xxx_dma_sysc,
110 * mailbox module allowing communication between the on-chip processors
111 * using a queued mailbox-interrupt mechanism.
114 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
118 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
119 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
120 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
121 .sysc_fields = &omap_hwmod_sysc_type1,
124 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
126 .sysc = &omap2xxx_mailbox_sysc,
131 * multichannel serial port interface (mcspi) / master/slave synchronous serial
135 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
139 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
140 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
141 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
142 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
143 .sysc_fields = &omap_hwmod_sysc_type1,
146 struct omap_hwmod_class omap2xxx_mcspi_class = {
148 .sysc = &omap2xxx_mcspi_sysc,
149 .rev = OMAP2_MCSPI_REV,