arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <plat/omap_hwmod.h>
  12 #include <plat/serial.h>
  13 #include <plat/dma.h>
  14
  15 #include <mach/irqs.h>
  16
  17 #include "omap_hwmod_common_data.h"
  18
  19 /* UART */
  20
  21 static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
  22         .rev_offs       = 0x50,
  23         .sysc_offs      = 0x54,
  24         .syss_offs      = 0x58,
  25         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
  26                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  27                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  28         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  29         .sysc_fields    = &omap_hwmod_sysc_type1,
  30 };
  31
  32 struct omap_hwmod_class omap2_uart_class = {
  33         .name   = "uart",
  34         .sysc   = &omap2_uart_sysc,
  35 };
  36
  37 /*
  38  * 'dss' class
  39  * display sub-system
  40  */
  41
  42 static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
  43         .rev_offs       = 0x0000,
  44         .sysc_offs      = 0x0010,
  45         .syss_offs      = 0x0014,
  46         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  47                            SYSS_HAS_RESET_STATUS),
  48         .sysc_fields    = &omap_hwmod_sysc_type1,
  49 };
  50
  51 struct omap_hwmod_class omap2_dss_hwmod_class = {
  52         .name   = "dss",
  53         .sysc   = &omap2_dss_sysc,
  54 };
  55
  56 /*
  57  * 'dispc' class
  58  * display controller
  59  */
  60
  61 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  62         .rev_offs       = 0x0000,
  63         .sysc_offs      = 0x0010,
  64         .syss_offs      = 0x0014,
  65         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  66                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  67         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  68                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  69         .sysc_fields    = &omap_hwmod_sysc_type1,
  70 };
  71
  72 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  73         .name   = "dispc",
  74         .sysc   = &omap2_dispc_sysc,
  75 };
  76
  77 /*
  78  * 'rfbi' class
  79  * remote frame buffer interface
  80  */
  81
  82 static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
  83         .rev_offs       = 0x0000,
  84         .sysc_offs      = 0x0010,
  85         .syss_offs      = 0x0014,
  86         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  87                            SYSC_HAS_AUTOIDLE),
  88         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  89         .sysc_fields    = &omap_hwmod_sysc_type1,
  90 };
  91
  92 struct omap_hwmod_class omap2_rfbi_hwmod_class = {
  93         .name   = "rfbi",
  94         .sysc   = &omap2_rfbi_sysc,
  95 };
  96
  97 /*
  98  * 'venc' class
  99  * video encoder
 100  */
 101
 102 struct omap_hwmod_class omap2_venc_hwmod_class = {
 103         .name = "venc",
 104 };
 105
 106
 107 /* Common DMA request line data */
 108 struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
 109         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 110         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 111         { .dma_req = -1 }
 112 };
 113
 114 struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
 115         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 116         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 117         { .dma_req = -1 }
 118 };
 119
 120 struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
 121         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 122         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 123         { .dma_req = -1 }
 124 };
 125
 126 struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
 127         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
 128         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
 129         { .dma_req = -1 }
 130 };
 131
 132 struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
 133         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
 134         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
 135         { .dma_req = -1 }
 136 };
 137
 138 struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
 139         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
 140         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
 141         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
 142         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
 143         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
 144         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
 145         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
 146         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
 147         { .dma_req = -1 }
 148 };
 149
 150 struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
 151         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
 152         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
 153         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
 154         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
 155         { .dma_req = -1 }
 156 };
 157
 158 struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
 159         { .name = "rx", .dma_req = 32 },
 160         { .name = "tx", .dma_req = 31 },
 161         { .dma_req = -1 }
 162 };
 163
 164 struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
 165         { .name = "rx", .dma_req = 34 },
 166         { .name = "tx", .dma_req = 33 },
 167         { .dma_req = -1 }
 168 };
 169
 170 struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
 171         { .name = "rx", .dma_req = 18 },
 172         { .name = "tx", .dma_req = 17 },
 173         { .dma_req = -1 }
 174 };
 175
 176 /* Other IP block data */
 177
 178
 179 /*
 180  * omap_hwmod class data
 181  */
 182
 183 struct omap_hwmod_class l3_hwmod_class = {
 184         .name = "l3"
 185 };
 186
 187 struct omap_hwmod_class l4_hwmod_class = {
 188         .name = "l4"
 189 };
 190
 191 struct omap_hwmod_class mpu_hwmod_class = {
 192         .name = "mpu"
 193 };
 194
 195 struct omap_hwmod_class iva_hwmod_class = {
 196         .name = "iva"
 197 };
 198
 199 /* Common MPU IRQ line data */
 200
 201 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
 202         { .irq = 37, },
 203         { .irq = -1 }
 204 };
 205
 206 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
 207         { .irq = 38, },
 208         { .irq = -1 }
 209 };
 210
 211 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
 212         { .irq = 39, },
 213         { .irq = -1 }
 214 };
 215
 216 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
 217         { .irq = 40, },
 218         { .irq = -1 }
 219 };
 220
 221 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
 222         { .irq = 41, },
 223         { .irq = -1 }
 224 };
 225
 226 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
 227         { .irq = 42, },
 228         { .irq = -1 }
 229 };
 230
 231 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
 232         { .irq = 43, },
 233         { .irq = -1 }
 234 };
 235
 236 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
 237         { .irq = 44, },
 238         { .irq = -1 }
 239 };
 240
 241 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
 242         { .irq = 45, },
 243         { .irq = -1 }
 244 };
 245
 246 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
 247         { .irq = 46, },
 248         { .irq = -1 }
 249 };
 250
 251 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
 252         { .irq = 47, },
 253         { .irq = -1 }
 254 };
 255
 256 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
 257         { .irq = INT_24XX_UART1_IRQ, },
 258         { .irq = -1 }
 259 };
 260
 261 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
 262         { .irq = INT_24XX_UART2_IRQ, },
 263         { .irq = -1 }
 264 };
 265
 266 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
 267         { .irq = INT_24XX_UART3_IRQ, },
 268         { .irq = -1 }
 269 };
 270
 271 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
 272         { .irq = 25 },
 273         { .irq = -1 }
 274 };
 275
 276 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
 277         { .irq = INT_24XX_I2C1_IRQ, },
 278         { .irq = -1 }
 279 };
 280
 281 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
 282         { .irq = INT_24XX_I2C2_IRQ, },
 283         { .irq = -1 }
 284 };
 285
 286 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
 287         { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
 288         { .irq = -1 }
 289 };
 290
 291 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
 292         { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
 293         { .irq = -1 }
 294 };
 295
 296 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
 297         { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
 298         { .irq = -1 }
 299 };
 300
 301 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
 302         { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
 303         { .irq = -1 }
 304 };
 305
 306 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
 307         { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
 308         { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
 309         { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
 310         { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
 311         { .irq = -1 }
 312 };
 313
 314 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
 315         { .irq = 65 },
 316         { .irq = -1 }
 317 };
 318
 319 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
 320         { .irq = 66 },
 321         { .irq = -1 }
 322 };
 323