arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/l3_2xxx.h>
  24 #include <plat/l4_2xxx.h>
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "wd_timer.h"
  31
  32 /*
  33  * OMAP2420 hardware module integration data
  34  *
  35  * ALl of the data in this section should be autogeneratable from the
  36  * TI hardware database or other technical documentation.  Data that
  37  * is driver-specific or driver-kernel integration-specific belongs
  38  * elsewhere.
  39  */
  40
  41 static struct omap_hwmod omap2420_mpu_hwmod;
  42 static struct omap_hwmod omap2420_iva_hwmod;
  43 static struct omap_hwmod omap2420_l3_main_hwmod;
  44 static struct omap_hwmod omap2420_l4_core_hwmod;
  45 static struct omap_hwmod omap2420_dss_core_hwmod;
  46 static struct omap_hwmod omap2420_dss_dispc_hwmod;
  47 static struct omap_hwmod omap2420_dss_rfbi_hwmod;
  48 static struct omap_hwmod omap2420_dss_venc_hwmod;
  49 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  50 static struct omap_hwmod omap2420_gpio1_hwmod;
  51 static struct omap_hwmod omap2420_gpio2_hwmod;
  52 static struct omap_hwmod omap2420_gpio3_hwmod;
  53 static struct omap_hwmod omap2420_gpio4_hwmod;
  54 static struct omap_hwmod omap2420_dma_system_hwmod;
  55 static struct omap_hwmod omap2420_mcspi1_hwmod;
  56 static struct omap_hwmod omap2420_mcspi2_hwmod;
  57
  58 /* L3 -> L4_CORE interface */
  59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  60         .master = &omap2420_l3_main_hwmod,
  61         .slave  = &omap2420_l4_core_hwmod,
  62         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  63 };
  64
  65 /* MPU -> L3 interface */
  66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  67         .master = &omap2420_mpu_hwmod,
  68         .slave  = &omap2420_l3_main_hwmod,
  69         .user   = OCP_USER_MPU,
  70 };
  71
  72 /* Slave interfaces on the L3 interconnect */
  73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  74         &omap2420_mpu__l3_main,
  75 };
  76
  77 /* DSS -> l3 */
  78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
  79         .master         = &omap2420_dss_core_hwmod,
  80         .slave          = &omap2420_l3_main_hwmod,
  81         .fw = {
  82                 .omap2 = {
  83                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  84                         .flags  = OMAP_FIREWALL_L3,
  85                 }
  86         },
  87         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  88 };
  89
  90 /* Master interfaces on the L3 interconnect */
  91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  92         &omap2420_l3_main__l4_core,
  93 };
  94
  95 /* L3 */
  96 static struct omap_hwmod omap2420_l3_main_hwmod = {
  97         .name           = "l3_main",
  98         .class          = &l3_hwmod_class,
  99         .masters        = omap2420_l3_main_masters,
 100         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
 101         .slaves         = omap2420_l3_main_slaves,
 102         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
 103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 104         .flags          = HWMOD_NO_IDLEST,
 105 };
 106
 107 static struct omap_hwmod omap2420_l4_wkup_hwmod;
 108 static struct omap_hwmod omap2420_uart1_hwmod;
 109 static struct omap_hwmod omap2420_uart2_hwmod;
 110 static struct omap_hwmod omap2420_uart3_hwmod;
 111 static struct omap_hwmod omap2420_i2c1_hwmod;
 112 static struct omap_hwmod omap2420_i2c2_hwmod;
 113 static struct omap_hwmod omap2420_mcbsp1_hwmod;
 114 static struct omap_hwmod omap2420_mcbsp2_hwmod;
 115
 116 /* l4 core -> mcspi1 interface */
 117 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
 118         .master         = &omap2420_l4_core_hwmod,
 119         .slave          = &omap2420_mcspi1_hwmod,
 120         .clk            = "mcspi1_ick",
 121         .addr           = omap2_mcspi1_addr_space,
 122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 123 };
 124
 125 /* l4 core -> mcspi2 interface */
 126 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
 127         .master         = &omap2420_l4_core_hwmod,
 128         .slave          = &omap2420_mcspi2_hwmod,
 129         .clk            = "mcspi2_ick",
 130         .addr           = omap2_mcspi2_addr_space,
 131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 132 };
 133
 134 /* L4_CORE -> L4_WKUP interface */
 135 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 136         .master = &omap2420_l4_core_hwmod,
 137         .slave  = &omap2420_l4_wkup_hwmod,
 138         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 139 };
 140
 141 /* L4 CORE -> UART1 interface */
 142 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 143         .master         = &omap2420_l4_core_hwmod,
 144         .slave          = &omap2420_uart1_hwmod,
 145         .clk            = "uart1_ick",
 146         .addr           = omap2xxx_uart1_addr_space,
 147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 148 };
 149
 150 /* L4 CORE -> UART2 interface */
 151 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 152         .master         = &omap2420_l4_core_hwmod,
 153         .slave          = &omap2420_uart2_hwmod,
 154         .clk            = "uart2_ick",
 155         .addr           = omap2xxx_uart2_addr_space,
 156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 /* L4 PER -> UART3 interface */
 160 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 161         .master         = &omap2420_l4_core_hwmod,
 162         .slave          = &omap2420_uart3_hwmod,
 163         .clk            = "uart3_ick",
 164         .addr           = omap2xxx_uart3_addr_space,
 165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 166 };
 167
 168 /* L4 CORE -> I2C1 interface */
 169 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 170         .master         = &omap2420_l4_core_hwmod,
 171         .slave          = &omap2420_i2c1_hwmod,
 172         .clk            = "i2c1_ick",
 173         .addr           = omap2_i2c1_addr_space,
 174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 175 };
 176
 177 /* L4 CORE -> I2C2 interface */
 178 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 179         .master         = &omap2420_l4_core_hwmod,
 180         .slave          = &omap2420_i2c2_hwmod,
 181         .clk            = "i2c2_ick",
 182         .addr           = omap2_i2c2_addr_space,
 183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 184 };
 185
 186 /* Slave interfaces on the L4_CORE interconnect */
 187 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 188         &omap2420_l3_main__l4_core,
 189 };
 190
 191 /* Master interfaces on the L4_CORE interconnect */
 192 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 193         &omap2420_l4_core__l4_wkup,
 194         &omap2_l4_core__uart1,
 195         &omap2_l4_core__uart2,
 196         &omap2_l4_core__uart3,
 197         &omap2420_l4_core__i2c1,
 198         &omap2420_l4_core__i2c2
 199 };
 200
 201 /* L4 CORE */
 202 static struct omap_hwmod omap2420_l4_core_hwmod = {
 203         .name           = "l4_core",
 204         .class          = &l4_hwmod_class,
 205         .masters        = omap2420_l4_core_masters,
 206         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 207         .slaves         = omap2420_l4_core_slaves,
 208         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 209         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 210         .flags          = HWMOD_NO_IDLEST,
 211 };
 212
 213 /* Slave interfaces on the L4_WKUP interconnect */
 214 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 215         &omap2420_l4_core__l4_wkup,
 216 };
 217
 218 /* Master interfaces on the L4_WKUP interconnect */
 219 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 220 };
 221
 222 /* L4 WKUP */
 223 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 224         .name           = "l4_wkup",
 225         .class          = &l4_hwmod_class,
 226         .masters        = omap2420_l4_wkup_masters,
 227         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 228         .slaves         = omap2420_l4_wkup_slaves,
 229         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 230         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 231         .flags          = HWMOD_NO_IDLEST,
 232 };
 233
 234 /* Master interfaces on the MPU device */
 235 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 236         &omap2420_mpu__l3_main,
 237 };
 238
 239 /* MPU */
 240 static struct omap_hwmod omap2420_mpu_hwmod = {
 241         .name           = "mpu",
 242         .class          = &mpu_hwmod_class,
 243         .main_clk       = "mpu_ck",
 244         .masters        = omap2420_mpu_masters,
 245         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 246         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 247 };
 248
 249 /*
 250  * IVA1 interface data
 251  */
 252
 253 /* IVA <- L3 interface */
 254 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 255         .master         = &omap2420_l3_main_hwmod,
 256         .slave          = &omap2420_iva_hwmod,
 257         .clk            = "iva1_ifck",
 258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 259 };
 260
 261 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 262         &omap2420_l3__iva,
 263 };
 264
 265 /*
 266  * IVA2 (IVA2)
 267  */
 268
 269 static struct omap_hwmod omap2420_iva_hwmod = {
 270         .name           = "iva",
 271         .class          = &iva_hwmod_class,
 272         .masters        = omap2420_iva_masters,
 273         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 274         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 275 };
 276
 277 /* Timer Common */
 278 static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
 279         .rev_offs       = 0x0000,
 280         .sysc_offs      = 0x0010,
 281         .syss_offs      = 0x0014,
 282         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 283                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 284                            SYSC_HAS_AUTOIDLE),
 285         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 286         .sysc_fields    = &omap_hwmod_sysc_type1,
 287 };
 288
 289 static struct omap_hwmod_class omap2420_timer_hwmod_class = {
 290         .name = "timer",
 291         .sysc = &omap2420_timer_sysc,
 292         .rev = OMAP_TIMER_IP_VERSION_1,
 293 };
 294
 295 /* timer1 */
 296 static struct omap_hwmod omap2420_timer1_hwmod;
 297
 298 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 299         {
 300                 .pa_start       = 0x48028000,
 301                 .pa_end         = 0x48028000 + SZ_1K - 1,
 302                 .flags          = ADDR_TYPE_RT
 303         },
 304         { }
 305 };
 306
 307 /* l4_wkup -> timer1 */
 308 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 309         .master         = &omap2420_l4_wkup_hwmod,
 310         .slave          = &omap2420_timer1_hwmod,
 311         .clk            = "gpt1_ick",
 312         .addr           = omap2420_timer1_addrs,
 313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 314 };
 315
 316 /* timer1 slave port */
 317 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
 318         &omap2420_l4_wkup__timer1,
 319 };
 320
 321 /* timer1 hwmod */
 322 static struct omap_hwmod omap2420_timer1_hwmod = {
 323         .name           = "timer1",
 324         .mpu_irqs       = omap2_timer1_mpu_irqs,
 325         .main_clk       = "gpt1_fck",
 326         .prcm           = {
 327                 .omap2 = {
 328                         .prcm_reg_id = 1,
 329                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 330                         .module_offs = WKUP_MOD,
 331                         .idlest_reg_id = 1,
 332                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 333                 },
 334         },
 335         .slaves         = omap2420_timer1_slaves,
 336         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
 337         .class          = &omap2420_timer_hwmod_class,
 338         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 339 };
 340
 341 /* timer2 */
 342 static struct omap_hwmod omap2420_timer2_hwmod;
 343
 344 /* l4_core -> timer2 */
 345 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
 346         .master         = &omap2420_l4_core_hwmod,
 347         .slave          = &omap2420_timer2_hwmod,
 348         .clk            = "gpt2_ick",
 349         .addr           = omap2xxx_timer2_addrs,
 350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 351 };
 352
 353 /* timer2 slave port */
 354 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
 355         &omap2420_l4_core__timer2,
 356 };
 357
 358 /* timer2 hwmod */
 359 static struct omap_hwmod omap2420_timer2_hwmod = {
 360         .name           = "timer2",
 361         .mpu_irqs       = omap2_timer2_mpu_irqs,
 362         .main_clk       = "gpt2_fck",
 363         .prcm           = {
 364                 .omap2 = {
 365                         .prcm_reg_id = 1,
 366                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 367                         .module_offs = CORE_MOD,
 368                         .idlest_reg_id = 1,
 369                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 370                 },
 371         },
 372         .slaves         = omap2420_timer2_slaves,
 373         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
 374         .class          = &omap2420_timer_hwmod_class,
 375         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 376 };
 377
 378 /* timer3 */
 379 static struct omap_hwmod omap2420_timer3_hwmod;
 380
 381 /* l4_core -> timer3 */
 382 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
 383         .master         = &omap2420_l4_core_hwmod,
 384         .slave          = &omap2420_timer3_hwmod,
 385         .clk            = "gpt3_ick",
 386         .addr           = omap2xxx_timer3_addrs,
 387         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 388 };
 389
 390 /* timer3 slave port */
 391 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
 392         &omap2420_l4_core__timer3,
 393 };
 394
 395 /* timer3 hwmod */
 396 static struct omap_hwmod omap2420_timer3_hwmod = {
 397         .name           = "timer3",
 398         .mpu_irqs       = omap2_timer3_mpu_irqs,
 399         .main_clk       = "gpt3_fck",
 400         .prcm           = {
 401                 .omap2 = {
 402                         .prcm_reg_id = 1,
 403                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 404                         .module_offs = CORE_MOD,
 405                         .idlest_reg_id = 1,
 406                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 407                 },
 408         },
 409         .slaves         = omap2420_timer3_slaves,
 410         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
 411         .class          = &omap2420_timer_hwmod_class,
 412         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 413 };
 414
 415 /* timer4 */
 416 static struct omap_hwmod omap2420_timer4_hwmod;
 417
 418 /* l4_core -> timer4 */
 419 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
 420         .master         = &omap2420_l4_core_hwmod,
 421         .slave          = &omap2420_timer4_hwmod,
 422         .clk            = "gpt4_ick",
 423         .addr           = omap2xxx_timer4_addrs,
 424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 425 };
 426
 427 /* timer4 slave port */
 428 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
 429         &omap2420_l4_core__timer4,
 430 };
 431
 432 /* timer4 hwmod */
 433 static struct omap_hwmod omap2420_timer4_hwmod = {
 434         .name           = "timer4",
 435         .mpu_irqs       = omap2_timer4_mpu_irqs,
 436         .main_clk       = "gpt4_fck",
 437         .prcm           = {
 438                 .omap2 = {
 439                         .prcm_reg_id = 1,
 440                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 441                         .module_offs = CORE_MOD,
 442                         .idlest_reg_id = 1,
 443                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 444                 },
 445         },
 446         .slaves         = omap2420_timer4_slaves,
 447         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
 448         .class          = &omap2420_timer_hwmod_class,
 449         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 450 };
 451
 452 /* timer5 */
 453 static struct omap_hwmod omap2420_timer5_hwmod;
 454
 455 /* l4_core -> timer5 */
 456 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
 457         .master         = &omap2420_l4_core_hwmod,
 458         .slave          = &omap2420_timer5_hwmod,
 459         .clk            = "gpt5_ick",
 460         .addr           = omap2xxx_timer5_addrs,
 461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 462 };
 463
 464 /* timer5 slave port */
 465 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
 466         &omap2420_l4_core__timer5,
 467 };
 468
 469 /* timer5 hwmod */
 470 static struct omap_hwmod omap2420_timer5_hwmod = {
 471         .name           = "timer5",
 472         .mpu_irqs       = omap2_timer5_mpu_irqs,
 473         .main_clk       = "gpt5_fck",
 474         .prcm           = {
 475                 .omap2 = {
 476                         .prcm_reg_id = 1,
 477                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 478                         .module_offs = CORE_MOD,
 479                         .idlest_reg_id = 1,
 480                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 481                 },
 482         },
 483         .slaves         = omap2420_timer5_slaves,
 484         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
 485         .class          = &omap2420_timer_hwmod_class,
 486         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 487 };
 488
 489
 490 /* timer6 */
 491 static struct omap_hwmod omap2420_timer6_hwmod;
 492
 493 /* l4_core -> timer6 */
 494 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
 495         .master         = &omap2420_l4_core_hwmod,
 496         .slave          = &omap2420_timer6_hwmod,
 497         .clk            = "gpt6_ick",
 498         .addr           = omap2xxx_timer6_addrs,
 499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 500 };
 501
 502 /* timer6 slave port */
 503 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
 504         &omap2420_l4_core__timer6,
 505 };
 506
 507 /* timer6 hwmod */
 508 static struct omap_hwmod omap2420_timer6_hwmod = {
 509         .name           = "timer6",
 510         .mpu_irqs       = omap2_timer6_mpu_irqs,
 511         .main_clk       = "gpt6_fck",
 512         .prcm           = {
 513                 .omap2 = {
 514                         .prcm_reg_id = 1,
 515                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 516                         .module_offs = CORE_MOD,
 517                         .idlest_reg_id = 1,
 518                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 519                 },
 520         },
 521         .slaves         = omap2420_timer6_slaves,
 522         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
 523         .class          = &omap2420_timer_hwmod_class,
 524         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 525 };
 526
 527 /* timer7 */
 528 static struct omap_hwmod omap2420_timer7_hwmod;
 529
 530 /* l4_core -> timer7 */
 531 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
 532         .master         = &omap2420_l4_core_hwmod,
 533         .slave          = &omap2420_timer7_hwmod,
 534         .clk            = "gpt7_ick",
 535         .addr           = omap2xxx_timer7_addrs,
 536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 537 };
 538
 539 /* timer7 slave port */
 540 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
 541         &omap2420_l4_core__timer7,
 542 };
 543
 544 /* timer7 hwmod */
 545 static struct omap_hwmod omap2420_timer7_hwmod = {
 546         .name           = "timer7",
 547         .mpu_irqs       = omap2_timer7_mpu_irqs,
 548         .main_clk       = "gpt7_fck",
 549         .prcm           = {
 550                 .omap2 = {
 551                         .prcm_reg_id = 1,
 552                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 553                         .module_offs = CORE_MOD,
 554                         .idlest_reg_id = 1,
 555                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 556                 },
 557         },
 558         .slaves         = omap2420_timer7_slaves,
 559         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
 560         .class          = &omap2420_timer_hwmod_class,
 561         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 562 };
 563
 564 /* timer8 */
 565 static struct omap_hwmod omap2420_timer8_hwmod;
 566
 567 /* l4_core -> timer8 */
 568 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
 569         .master         = &omap2420_l4_core_hwmod,
 570         .slave          = &omap2420_timer8_hwmod,
 571         .clk            = "gpt8_ick",
 572         .addr           = omap2xxx_timer8_addrs,
 573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 574 };
 575
 576 /* timer8 slave port */
 577 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
 578         &omap2420_l4_core__timer8,
 579 };
 580
 581 /* timer8 hwmod */
 582 static struct omap_hwmod omap2420_timer8_hwmod = {
 583         .name           = "timer8",
 584         .mpu_irqs       = omap2_timer8_mpu_irqs,
 585         .main_clk       = "gpt8_fck",
 586         .prcm           = {
 587                 .omap2 = {
 588                         .prcm_reg_id = 1,
 589                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 590                         .module_offs = CORE_MOD,
 591                         .idlest_reg_id = 1,
 592                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 593                 },
 594         },
 595         .slaves         = omap2420_timer8_slaves,
 596         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
 597         .class          = &omap2420_timer_hwmod_class,
 598         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 599 };
 600
 601 /* timer9 */
 602 static struct omap_hwmod omap2420_timer9_hwmod;
 603
 604 /* l4_core -> timer9 */
 605 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
 606         .master         = &omap2420_l4_core_hwmod,
 607         .slave          = &omap2420_timer9_hwmod,
 608         .clk            = "gpt9_ick",
 609         .addr           = omap2xxx_timer9_addrs,
 610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 611 };
 612
 613 /* timer9 slave port */
 614 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
 615         &omap2420_l4_core__timer9,
 616 };
 617
 618 /* timer9 hwmod */
 619 static struct omap_hwmod omap2420_timer9_hwmod = {
 620         .name           = "timer9",
 621         .mpu_irqs       = omap2_timer9_mpu_irqs,
 622         .main_clk       = "gpt9_fck",
 623         .prcm           = {
 624                 .omap2 = {
 625                         .prcm_reg_id = 1,
 626                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 627                         .module_offs = CORE_MOD,
 628                         .idlest_reg_id = 1,
 629                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 630                 },
 631         },
 632         .slaves         = omap2420_timer9_slaves,
 633         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
 634         .class          = &omap2420_timer_hwmod_class,
 635         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 636 };
 637
 638 /* timer10 */
 639 static struct omap_hwmod omap2420_timer10_hwmod;
 640
 641 /* l4_core -> timer10 */
 642 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
 643         .master         = &omap2420_l4_core_hwmod,
 644         .slave          = &omap2420_timer10_hwmod,
 645         .clk            = "gpt10_ick",
 646         .addr           = omap2_timer10_addrs,
 647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 648 };
 649
 650 /* timer10 slave port */
 651 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
 652         &omap2420_l4_core__timer10,
 653 };
 654
 655 /* timer10 hwmod */
 656 static struct omap_hwmod omap2420_timer10_hwmod = {
 657         .name           = "timer10",
 658         .mpu_irqs       = omap2_timer10_mpu_irqs,
 659         .main_clk       = "gpt10_fck",
 660         .prcm           = {
 661                 .omap2 = {
 662                         .prcm_reg_id = 1,
 663                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 664                         .module_offs = CORE_MOD,
 665                         .idlest_reg_id = 1,
 666                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 667                 },
 668         },
 669         .slaves         = omap2420_timer10_slaves,
 670         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
 671         .class          = &omap2420_timer_hwmod_class,
 672         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 673 };
 674
 675 /* timer11 */
 676 static struct omap_hwmod omap2420_timer11_hwmod;
 677
 678 /* l4_core -> timer11 */
 679 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
 680         .master         = &omap2420_l4_core_hwmod,
 681         .slave          = &omap2420_timer11_hwmod,
 682         .clk            = "gpt11_ick",
 683         .addr           = omap2_timer11_addrs,
 684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 685 };
 686
 687 /* timer11 slave port */
 688 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
 689         &omap2420_l4_core__timer11,
 690 };
 691
 692 /* timer11 hwmod */
 693 static struct omap_hwmod omap2420_timer11_hwmod = {
 694         .name           = "timer11",
 695         .mpu_irqs       = omap2_timer11_mpu_irqs,
 696         .main_clk       = "gpt11_fck",
 697         .prcm           = {
 698                 .omap2 = {
 699                         .prcm_reg_id = 1,
 700                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 701                         .module_offs = CORE_MOD,
 702                         .idlest_reg_id = 1,
 703                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 704                 },
 705         },
 706         .slaves         = omap2420_timer11_slaves,
 707         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
 708         .class          = &omap2420_timer_hwmod_class,
 709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 710 };
 711
 712 /* timer12 */
 713 static struct omap_hwmod omap2420_timer12_hwmod;
 714
 715 /* l4_core -> timer12 */
 716 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
 717         .master         = &omap2420_l4_core_hwmod,
 718         .slave          = &omap2420_timer12_hwmod,
 719         .clk            = "gpt12_ick",
 720         .addr           = omap2xxx_timer12_addrs,
 721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 722 };
 723
 724 /* timer12 slave port */
 725 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
 726         &omap2420_l4_core__timer12,
 727 };
 728
 729 /* timer12 hwmod */
 730 static struct omap_hwmod omap2420_timer12_hwmod = {
 731         .name           = "timer12",
 732         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 733         .main_clk       = "gpt12_fck",
 734         .prcm           = {
 735                 .omap2 = {
 736                         .prcm_reg_id = 1,
 737                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 738                         .module_offs = CORE_MOD,
 739                         .idlest_reg_id = 1,
 740                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 741                 },
 742         },
 743         .slaves         = omap2420_timer12_slaves,
 744         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
 745         .class          = &omap2420_timer_hwmod_class,
 746         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 747 };
 748
 749 /* l4_wkup -> wd_timer2 */
 750 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 751         {
 752                 .pa_start       = 0x48022000,
 753                 .pa_end         = 0x4802207f,
 754                 .flags          = ADDR_TYPE_RT
 755         },
 756         { }
 757 };
 758
 759 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 760         .master         = &omap2420_l4_wkup_hwmod,
 761         .slave          = &omap2420_wd_timer2_hwmod,
 762         .clk            = "mpu_wdt_ick",
 763         .addr           = omap2420_wd_timer2_addrs,
 764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 765 };
 766
 767 /*
 768  * 'wd_timer' class
 769  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 770  * overflow condition
 771  */
 772
 773 static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 774         .rev_offs       = 0x0000,
 775         .sysc_offs      = 0x0010,
 776         .syss_offs      = 0x0014,
 777         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 778                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 779         .sysc_fields    = &omap_hwmod_sysc_type1,
 780 };
 781
 782 static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
 783         .name           = "wd_timer",
 784         .sysc           = &omap2420_wd_timer_sysc,
 785         .pre_shutdown   = &omap2_wd_timer_disable
 786 };
 787
 788 /* wd_timer2 */
 789 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 790         &omap2420_l4_wkup__wd_timer2,
 791 };
 792
 793 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
 794         .name           = "wd_timer2",
 795         .class          = &omap2420_wd_timer_hwmod_class,
 796         .main_clk       = "mpu_wdt_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 801                         .module_offs = WKUP_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 804                 },
 805         },
 806         .slaves         = omap2420_wd_timer2_slaves,
 807         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
 808         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 809 };
 810
 811 /* UART */
 812
 813 static struct omap_hwmod_class_sysconfig uart_sysc = {
 814         .rev_offs       = 0x50,
 815         .sysc_offs      = 0x54,
 816         .syss_offs      = 0x58,
 817         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 818                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 819                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 820         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 821         .sysc_fields    = &omap_hwmod_sysc_type1,
 822 };
 823
 824 static struct omap_hwmod_class uart_class = {
 825         .name = "uart",
 826         .sysc = &uart_sysc,
 827 };
 828
 829 /* UART1 */
 830
 831 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
 832         &omap2_l4_core__uart1,
 833 };
 834
 835 static struct omap_hwmod omap2420_uart1_hwmod = {
 836         .name           = "uart1",
 837         .mpu_irqs       = omap2_uart1_mpu_irqs,
 838         .sdma_reqs      = omap2_uart1_sdma_reqs,
 839         .main_clk       = "uart1_fck",
 840         .prcm           = {
 841                 .omap2 = {
 842                         .module_offs = CORE_MOD,
 843                         .prcm_reg_id = 1,
 844                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 845                         .idlest_reg_id = 1,
 846                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 847                 },
 848         },
 849         .slaves         = omap2420_uart1_slaves,
 850         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
 851         .class          = &uart_class,
 852         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 853 };
 854
 855 /* UART2 */
 856
 857 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
 858         &omap2_l4_core__uart2,
 859 };
 860
 861 static struct omap_hwmod omap2420_uart2_hwmod = {
 862         .name           = "uart2",
 863         .mpu_irqs       = omap2_uart2_mpu_irqs,
 864         .sdma_reqs      = omap2_uart2_sdma_reqs,
 865         .main_clk       = "uart2_fck",
 866         .prcm           = {
 867                 .omap2 = {
 868                         .module_offs = CORE_MOD,
 869                         .prcm_reg_id = 1,
 870                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 871                         .idlest_reg_id = 1,
 872                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 873                 },
 874         },
 875         .slaves         = omap2420_uart2_slaves,
 876         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
 877         .class          = &uart_class,
 878         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 879 };
 880
 881 /* UART3 */
 882
 883 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
 884         &omap2_l4_core__uart3,
 885 };
 886
 887 static struct omap_hwmod omap2420_uart3_hwmod = {
 888         .name           = "uart3",
 889         .mpu_irqs       = omap2_uart3_mpu_irqs,
 890         .sdma_reqs      = omap2_uart3_sdma_reqs,
 891         .main_clk       = "uart3_fck",
 892         .prcm           = {
 893                 .omap2 = {
 894                         .module_offs = CORE_MOD,
 895                         .prcm_reg_id = 2,
 896                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 897                         .idlest_reg_id = 2,
 898                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 899                 },
 900         },
 901         .slaves         = omap2420_uart3_slaves,
 902         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
 903         .class          = &uart_class,
 904         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 905 };
 906
 907 /*
 908  * 'dss' class
 909  * display sub-system
 910  */
 911
 912 static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
 913         .rev_offs       = 0x0000,
 914         .sysc_offs      = 0x0010,
 915         .syss_offs      = 0x0014,
 916         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 917         .sysc_fields    = &omap_hwmod_sysc_type1,
 918 };
 919
 920 static struct omap_hwmod_class omap2420_dss_hwmod_class = {
 921         .name = "dss",
 922         .sysc = &omap2420_dss_sysc,
 923 };
 924
 925 /* dss */
 926 /* dss master ports */
 927 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
 928         &omap2420_dss__l3,
 929 };
 930
 931 /* l4_core -> dss */
 932 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
 933         .master         = &omap2420_l4_core_hwmod,
 934         .slave          = &omap2420_dss_core_hwmod,
 935         .clk            = "dss_ick",
 936         .addr           = omap2_dss_addrs,
 937         .fw = {
 938                 .omap2 = {
 939                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
 940                         .flags  = OMAP_FIREWALL_L4,
 941                 }
 942         },
 943         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 944 };
 945
 946 /* dss slave ports */
 947 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
 948         &omap2420_l4_core__dss,
 949 };
 950
 951 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 952         { .role = "tv_clk", .clk = "dss_54m_fck" },
 953         { .role = "sys_clk", .clk = "dss2_fck" },
 954 };
 955
 956 static struct omap_hwmod omap2420_dss_core_hwmod = {
 957         .name           = "dss_core",
 958         .class          = &omap2420_dss_hwmod_class,
 959         .main_clk       = "dss1_fck", /* instead of dss_fck */
 960         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 961         .prcm           = {
 962                 .omap2 = {
 963                         .prcm_reg_id = 1,
 964                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 965                         .module_offs = CORE_MOD,
 966                         .idlest_reg_id = 1,
 967                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 968                 },
 969         },
 970         .opt_clks       = dss_opt_clks,
 971         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 972         .slaves         = omap2420_dss_slaves,
 973         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
 974         .masters        = omap2420_dss_masters,
 975         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
 976         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 977         .flags          = HWMOD_NO_IDLEST,
 978 };
 979
 980 /*
 981  * 'dispc' class
 982  * display controller
 983  */
 984
 985 static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
 986         .rev_offs       = 0x0000,
 987         .sysc_offs      = 0x0010,
 988         .syss_offs      = 0x0014,
 989         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 990                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 991         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 992                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 993         .sysc_fields    = &omap_hwmod_sysc_type1,
 994 };
 995
 996 static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
 997         .name = "dispc",
 998         .sysc = &omap2420_dispc_sysc,
 999 };
1000
1001 /* l4_core -> dss_dispc */
1002 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
1003         .master         = &omap2420_l4_core_hwmod,
1004         .slave          = &omap2420_dss_dispc_hwmod,
1005         .clk            = "dss_ick",
1006         .addr           = omap2_dss_dispc_addrs,
1007         .fw = {
1008                 .omap2 = {
1009                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
1010                         .flags  = OMAP_FIREWALL_L4,
1011                 }
1012         },
1013         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1014 };
1015
1016 /* dss_dispc slave ports */
1017 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
1018         &omap2420_l4_core__dss_dispc,
1019 };
1020
1021 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1022         .name           = "dss_dispc",
1023         .class          = &omap2420_dispc_hwmod_class,
1024         .mpu_irqs       = omap2_dispc_irqs,
1025         .main_clk       = "dss1_fck",
1026         .prcm           = {
1027                 .omap2 = {
1028                         .prcm_reg_id = 1,
1029                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1030                         .module_offs = CORE_MOD,
1031                         .idlest_reg_id = 1,
1032                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1033                 },
1034         },
1035         .slaves         = omap2420_dss_dispc_slaves,
1036         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
1037         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1038         .flags          = HWMOD_NO_IDLEST,
1039 };
1040
1041 /*
1042  * 'rfbi' class
1043  * remote frame buffer interface
1044  */
1045
1046 static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
1047         .rev_offs       = 0x0000,
1048         .sysc_offs      = 0x0010,
1049         .syss_offs      = 0x0014,
1050         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1051                            SYSC_HAS_AUTOIDLE),
1052         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1053         .sysc_fields    = &omap_hwmod_sysc_type1,
1054 };
1055
1056 static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
1057         .name = "rfbi",
1058         .sysc = &omap2420_rfbi_sysc,
1059 };
1060
1061 /* l4_core -> dss_rfbi */
1062 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
1063         .master         = &omap2420_l4_core_hwmod,
1064         .slave          = &omap2420_dss_rfbi_hwmod,
1065         .clk            = "dss_ick",
1066         .addr           = omap2_dss_rfbi_addrs,
1067         .fw = {
1068                 .omap2 = {
1069                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
1070                         .flags  = OMAP_FIREWALL_L4,
1071                 }
1072         },
1073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1074 };
1075
1076 /* dss_rfbi slave ports */
1077 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
1078         &omap2420_l4_core__dss_rfbi,
1079 };
1080
1081 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1082         .name           = "dss_rfbi",
1083         .class          = &omap2420_rfbi_hwmod_class,
1084         .main_clk       = "dss1_fck",
1085         .prcm           = {
1086                 .omap2 = {
1087                         .prcm_reg_id = 1,
1088                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1089                         .module_offs = CORE_MOD,
1090                 },
1091         },
1092         .slaves         = omap2420_dss_rfbi_slaves,
1093         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
1094         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1095         .flags          = HWMOD_NO_IDLEST,
1096 };
1097
1098 /*
1099  * 'venc' class
1100  * video encoder
1101  */
1102
1103 static struct omap_hwmod_class omap2420_venc_hwmod_class = {
1104         .name = "venc",
1105 };
1106
1107 /* l4_core -> dss_venc */
1108 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1109         .master         = &omap2420_l4_core_hwmod,
1110         .slave          = &omap2420_dss_venc_hwmod,
1111         .clk            = "dss_54m_fck",
1112         .addr           = omap2_dss_venc_addrs,
1113         .fw = {
1114                 .omap2 = {
1115                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
1116                         .flags  = OMAP_FIREWALL_L4,
1117                 }
1118         },
1119         .flags          = OCPIF_SWSUP_IDLE,
1120         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1121 };
1122
1123 /* dss_venc slave ports */
1124 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1125         &omap2420_l4_core__dss_venc,
1126 };
1127
1128 static struct omap_hwmod omap2420_dss_venc_hwmod = {
1129         .name           = "dss_venc",
1130         .class          = &omap2420_venc_hwmod_class,
1131         .main_clk       = "dss1_fck",
1132         .prcm           = {
1133                 .omap2 = {
1134                         .prcm_reg_id = 1,
1135                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1136                         .module_offs = CORE_MOD,
1137                 },
1138         },
1139         .slaves         = omap2420_dss_venc_slaves,
1140         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
1141         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1142         .flags          = HWMOD_NO_IDLEST,
1143 };
1144
1145 /* I2C common */
1146 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1147         .rev_offs       = 0x00,
1148         .sysc_offs      = 0x20,
1149         .syss_offs      = 0x10,
1150         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1151         .sysc_fields    = &omap_hwmod_sysc_type1,
1152 };
1153
1154 static struct omap_hwmod_class i2c_class = {
1155         .name           = "i2c",
1156         .sysc           = &i2c_sysc,
1157 };
1158
1159 static struct omap_i2c_dev_attr i2c_dev_attr;
1160
1161 /* I2C1 */
1162
1163 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1164         &omap2420_l4_core__i2c1,
1165 };
1166
1167 static struct omap_hwmod omap2420_i2c1_hwmod = {
1168         .name           = "i2c1",
1169         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1170         .sdma_reqs      = omap2_i2c1_sdma_reqs,
1171         .main_clk       = "i2c1_fck",
1172         .prcm           = {
1173                 .omap2 = {
1174                         .module_offs = CORE_MOD,
1175                         .prcm_reg_id = 1,
1176                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
1177                         .idlest_reg_id = 1,
1178                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1179                 },
1180         },
1181         .slaves         = omap2420_i2c1_slaves,
1182         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
1183         .class          = &i2c_class,
1184         .dev_attr       = &i2c_dev_attr,
1185         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1186         .flags          = HWMOD_16BIT_REG,
1187 };
1188
1189 /* I2C2 */
1190
1191 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1192         &omap2420_l4_core__i2c2,
1193 };
1194
1195 static struct omap_hwmod omap2420_i2c2_hwmod = {
1196         .name           = "i2c2",
1197         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1198         .sdma_reqs      = omap2_i2c2_sdma_reqs,
1199         .main_clk       = "i2c2_fck",
1200         .prcm           = {
1201                 .omap2 = {
1202                         .module_offs = CORE_MOD,
1203                         .prcm_reg_id = 1,
1204                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
1205                         .idlest_reg_id = 1,
1206                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1207                 },
1208         },
1209         .slaves         = omap2420_i2c2_slaves,
1210         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
1211         .class          = &i2c_class,
1212         .dev_attr       = &i2c_dev_attr,
1213         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1214         .flags          = HWMOD_16BIT_REG,
1215 };
1216
1217 /* l4_wkup -> gpio1 */
1218 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1219         {
1220                 .pa_start       = 0x48018000,
1221                 .pa_end         = 0x480181ff,
1222                 .flags          = ADDR_TYPE_RT
1223         },
1224         { }
1225 };
1226
1227 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1228         .master         = &omap2420_l4_wkup_hwmod,
1229         .slave          = &omap2420_gpio1_hwmod,
1230         .clk            = "gpios_ick",
1231         .addr           = omap2420_gpio1_addr_space,
1232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1233 };
1234
1235 /* l4_wkup -> gpio2 */
1236 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1237         {
1238                 .pa_start       = 0x4801a000,
1239                 .pa_end         = 0x4801a1ff,
1240                 .flags          = ADDR_TYPE_RT
1241         },
1242         { }
1243 };
1244
1245 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1246         .master         = &omap2420_l4_wkup_hwmod,
1247         .slave          = &omap2420_gpio2_hwmod,
1248         .clk            = "gpios_ick",
1249         .addr           = omap2420_gpio2_addr_space,
1250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1251 };
1252
1253 /* l4_wkup -> gpio3 */
1254 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1255         {
1256                 .pa_start       = 0x4801c000,
1257                 .pa_end         = 0x4801c1ff,
1258                 .flags          = ADDR_TYPE_RT
1259         },
1260         { }
1261 };
1262
1263 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1264         .master         = &omap2420_l4_wkup_hwmod,
1265         .slave          = &omap2420_gpio3_hwmod,
1266         .clk            = "gpios_ick",
1267         .addr           = omap2420_gpio3_addr_space,
1268         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1269 };
1270
1271 /* l4_wkup -> gpio4 */
1272 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1273         {
1274                 .pa_start       = 0x4801e000,
1275                 .pa_end         = 0x4801e1ff,
1276                 .flags          = ADDR_TYPE_RT
1277         },
1278         { }
1279 };
1280
1281 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1282         .master         = &omap2420_l4_wkup_hwmod,
1283         .slave          = &omap2420_gpio4_hwmod,
1284         .clk            = "gpios_ick",
1285         .addr           = omap2420_gpio4_addr_space,
1286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1287 };
1288
1289 /* gpio dev_attr */
1290 static struct omap_gpio_dev_attr gpio_dev_attr = {
1291         .bank_width = 32,
1292         .dbck_flag = false,
1293 };
1294
1295 static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
1296         .rev_offs       = 0x0000,
1297         .sysc_offs      = 0x0010,
1298         .syss_offs      = 0x0014,
1299         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1300                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1301                            SYSS_HAS_RESET_STATUS),
1302         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1303         .sysc_fields    = &omap_hwmod_sysc_type1,
1304 };
1305
1306 /*
1307  * 'gpio' class
1308  * general purpose io module
1309  */
1310 static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
1311         .name = "gpio",
1312         .sysc = &omap242x_gpio_sysc,
1313         .rev = 0,
1314 };
1315
1316 /* gpio1 */
1317 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1318         &omap2420_l4_wkup__gpio1,
1319 };
1320
1321 static struct omap_hwmod omap2420_gpio1_hwmod = {
1322         .name           = "gpio1",
1323         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1324         .mpu_irqs       = omap2_gpio1_irqs,
1325         .main_clk       = "gpios_fck",
1326         .prcm           = {
1327                 .omap2 = {
1328                         .prcm_reg_id = 1,
1329                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1330                         .module_offs = WKUP_MOD,
1331                         .idlest_reg_id = 1,
1332                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1333                 },
1334         },
1335         .slaves         = omap2420_gpio1_slaves,
1336         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
1337         .class          = &omap242x_gpio_hwmod_class,
1338         .dev_attr       = &gpio_dev_attr,
1339         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1340 };
1341
1342 /* gpio2 */
1343 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1344         &omap2420_l4_wkup__gpio2,
1345 };
1346
1347 static struct omap_hwmod omap2420_gpio2_hwmod = {
1348         .name           = "gpio2",
1349         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1350         .mpu_irqs       = omap2_gpio2_irqs,
1351         .main_clk       = "gpios_fck",
1352         .prcm           = {
1353                 .omap2 = {
1354                         .prcm_reg_id = 1,
1355                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1356                         .module_offs = WKUP_MOD,
1357                         .idlest_reg_id = 1,
1358                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1359                 },
1360         },
1361         .slaves         = omap2420_gpio2_slaves,
1362         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
1363         .class          = &omap242x_gpio_hwmod_class,
1364         .dev_attr       = &gpio_dev_attr,
1365         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1366 };
1367
1368 /* gpio3 */
1369 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1370         &omap2420_l4_wkup__gpio3,
1371 };
1372
1373 static struct omap_hwmod omap2420_gpio3_hwmod = {
1374         .name           = "gpio3",
1375         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1376         .mpu_irqs       = omap2_gpio3_irqs,
1377         .main_clk       = "gpios_fck",
1378         .prcm           = {
1379                 .omap2 = {
1380                         .prcm_reg_id = 1,
1381                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1382                         .module_offs = WKUP_MOD,
1383                         .idlest_reg_id = 1,
1384                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1385                 },
1386         },
1387         .slaves         = omap2420_gpio3_slaves,
1388         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
1389         .class          = &omap242x_gpio_hwmod_class,
1390         .dev_attr       = &gpio_dev_attr,
1391         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1392 };
1393
1394 /* gpio4 */
1395 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1396         &omap2420_l4_wkup__gpio4,
1397 };
1398
1399 static struct omap_hwmod omap2420_gpio4_hwmod = {
1400         .name           = "gpio4",
1401         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1402         .mpu_irqs       = omap2_gpio4_irqs,
1403         .main_clk       = "gpios_fck",
1404         .prcm           = {
1405                 .omap2 = {
1406                         .prcm_reg_id = 1,
1407                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1408                         .module_offs = WKUP_MOD,
1409                         .idlest_reg_id = 1,
1410                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1411                 },
1412         },
1413         .slaves         = omap2420_gpio4_slaves,
1414         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
1415         .class          = &omap242x_gpio_hwmod_class,
1416         .dev_attr       = &gpio_dev_attr,
1417         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1418 };
1419
1420 /* system dma */
1421 static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
1422         .rev_offs       = 0x0000,
1423         .sysc_offs      = 0x002c,
1424         .syss_offs      = 0x0028,
1425         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1426                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1427                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1428         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1429         .sysc_fields    = &omap_hwmod_sysc_type1,
1430 };
1431
1432 static struct omap_hwmod_class omap2420_dma_hwmod_class = {
1433         .name = "dma",
1434         .sysc = &omap2420_dma_sysc,
1435 };
1436
1437 /* dma attributes */
1438 static struct omap_dma_dev_attr dma_dev_attr = {
1439         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1440                                                 IS_CSSA_32 | IS_CDSA_32,
1441         .lch_count = 32,
1442 };
1443
1444 /* dma_system -> L3 */
1445 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1446         .master         = &omap2420_dma_system_hwmod,
1447         .slave          = &omap2420_l3_main_hwmod,
1448         .clk            = "core_l3_ck",
1449         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1450 };
1451
1452 /* dma_system master ports */
1453 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1454         &omap2420_dma_system__l3,
1455 };
1456
1457 /* l4_core -> dma_system */
1458 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1459         .master         = &omap2420_l4_core_hwmod,
1460         .slave          = &omap2420_dma_system_hwmod,
1461         .clk            = "sdma_ick",
1462         .addr           = omap2_dma_system_addrs,
1463         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1464 };
1465
1466 /* dma_system slave ports */
1467 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1468         &omap2420_l4_core__dma_system,
1469 };
1470
1471 static struct omap_hwmod omap2420_dma_system_hwmod = {
1472         .name           = "dma",
1473         .class          = &omap2420_dma_hwmod_class,
1474         .mpu_irqs       = omap2_dma_system_irqs,
1475         .main_clk       = "core_l3_ck",
1476         .slaves         = omap2420_dma_system_slaves,
1477         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
1478         .masters        = omap2420_dma_system_masters,
1479         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
1480         .dev_attr       = &dma_dev_attr,
1481         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1482         .flags          = HWMOD_NO_IDLEST,
1483 };
1484
1485 /*
1486  * 'mailbox' class
1487  * mailbox module allowing communication between the on-chip processors
1488  * using a queued mailbox-interrupt mechanism.
1489  */
1490
1491 static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1492         .rev_offs       = 0x000,
1493         .sysc_offs      = 0x010,
1494         .syss_offs      = 0x014,
1495         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1496                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1497         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1498         .sysc_fields    = &omap_hwmod_sysc_type1,
1499 };
1500
1501 static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1502         .name = "mailbox",
1503         .sysc = &omap2420_mailbox_sysc,
1504 };
1505
1506 /* mailbox */
1507 static struct omap_hwmod omap2420_mailbox_hwmod;
1508 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1509         { .name = "dsp", .irq = 26 },
1510         { .name = "iva", .irq = 34 },
1511         { .irq = -1 }
1512 };
1513
1514 /* l4_core -> mailbox */
1515 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1516         .master         = &omap2420_l4_core_hwmod,
1517         .slave          = &omap2420_mailbox_hwmod,
1518         .addr           = omap2_mailbox_addrs,
1519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1520 };
1521
1522 /* mailbox slave ports */
1523 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1524         &omap2420_l4_core__mailbox,
1525 };
1526
1527 static struct omap_hwmod omap2420_mailbox_hwmod = {
1528         .name           = "mailbox",
1529         .class          = &omap2420_mailbox_hwmod_class,
1530         .mpu_irqs       = omap2420_mailbox_irqs,
1531         .main_clk       = "mailboxes_ick",
1532         .prcm           = {
1533                 .omap2 = {
1534                         .prcm_reg_id = 1,
1535                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1536                         .module_offs = CORE_MOD,
1537                         .idlest_reg_id = 1,
1538                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1539                 },
1540         },
1541         .slaves         = omap2420_mailbox_slaves,
1542         .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
1543         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1544 };
1545
1546 /*
1547  * 'mcspi' class
1548  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1549  * bus
1550  */
1551
1552 static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
1553         .rev_offs       = 0x0000,
1554         .sysc_offs      = 0x0010,
1555         .syss_offs      = 0x0014,
1556         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1557                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1558                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1559         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1560         .sysc_fields    = &omap_hwmod_sysc_type1,
1561 };
1562
1563 static struct omap_hwmod_class omap2420_mcspi_class = {
1564         .name = "mcspi",
1565         .sysc = &omap2420_mcspi_sysc,
1566         .rev = OMAP2_MCSPI_REV,
1567 };
1568
1569 /* mcspi1 */
1570 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1571         &omap2420_l4_core__mcspi1,
1572 };
1573
1574 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1575         .num_chipselect = 4,
1576 };
1577
1578 static struct omap_hwmod omap2420_mcspi1_hwmod = {
1579         .name           = "mcspi1_hwmod",
1580         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1581         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1582         .main_clk       = "mcspi1_fck",
1583         .prcm           = {
1584                 .omap2 = {
1585                         .module_offs = CORE_MOD,
1586                         .prcm_reg_id = 1,
1587                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1588                         .idlest_reg_id = 1,
1589                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1590                 },
1591         },
1592         .slaves         = omap2420_mcspi1_slaves,
1593         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
1594         .class          = &omap2420_mcspi_class,
1595         .dev_attr       = &omap_mcspi1_dev_attr,
1596         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1597 };
1598
1599 /* mcspi2 */
1600 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1601         &omap2420_l4_core__mcspi2,
1602 };
1603
1604 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1605         .num_chipselect = 2,
1606 };
1607
1608 static struct omap_hwmod omap2420_mcspi2_hwmod = {
1609         .name           = "mcspi2_hwmod",
1610         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1611         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1612         .main_clk       = "mcspi2_fck",
1613         .prcm           = {
1614                 .omap2 = {
1615                         .module_offs = CORE_MOD,
1616                         .prcm_reg_id = 1,
1617                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1618                         .idlest_reg_id = 1,
1619                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1620                 },
1621         },
1622         .slaves         = omap2420_mcspi2_slaves,
1623         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
1624         .class          = &omap2420_mcspi_class,
1625         .dev_attr       = &omap_mcspi2_dev_attr,
1626         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1627 };
1628
1629 /*
1630  * 'mcbsp' class
1631  * multi channel buffered serial port controller
1632  */
1633
1634 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1635         .name = "mcbsp",
1636 };
1637
1638 /* mcbsp1 */
1639 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1640         { .name = "tx", .irq = 59 },
1641         { .name = "rx", .irq = 60 },
1642         { .irq = -1 }
1643 };
1644
1645 /* l4_core -> mcbsp1 */
1646 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1647         .master         = &omap2420_l4_core_hwmod,
1648         .slave          = &omap2420_mcbsp1_hwmod,
1649         .clk            = "mcbsp1_ick",
1650         .addr           = omap2_mcbsp1_addrs,
1651         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1652 };
1653
1654 /* mcbsp1 slave ports */
1655 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1656         &omap2420_l4_core__mcbsp1,
1657 };
1658
1659 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1660         .name           = "mcbsp1",
1661         .class          = &omap2420_mcbsp_hwmod_class,
1662         .mpu_irqs       = omap2420_mcbsp1_irqs,
1663         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1664         .main_clk       = "mcbsp1_fck",
1665         .prcm           = {
1666                 .omap2 = {
1667                         .prcm_reg_id = 1,
1668                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1669                         .module_offs = CORE_MOD,
1670                         .idlest_reg_id = 1,
1671                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1672                 },
1673         },
1674         .slaves         = omap2420_mcbsp1_slaves,
1675         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1676         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1677 };
1678
1679 /* mcbsp2 */
1680 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1681         { .name = "tx", .irq = 62 },
1682         { .name = "rx", .irq = 63 },
1683         { .irq = -1 }
1684 };
1685
1686 /* l4_core -> mcbsp2 */
1687 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1688         .master         = &omap2420_l4_core_hwmod,
1689         .slave          = &omap2420_mcbsp2_hwmod,
1690         .clk            = "mcbsp2_ick",
1691         .addr           = omap2xxx_mcbsp2_addrs,
1692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1693 };
1694
1695 /* mcbsp2 slave ports */
1696 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
1697         &omap2420_l4_core__mcbsp2,
1698 };
1699
1700 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1701         .name           = "mcbsp2",
1702         .class          = &omap2420_mcbsp_hwmod_class,
1703         .mpu_irqs       = omap2420_mcbsp2_irqs,
1704         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1705         .main_clk       = "mcbsp2_fck",
1706         .prcm           = {
1707                 .omap2 = {
1708                         .prcm_reg_id = 1,
1709                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1710                         .module_offs = CORE_MOD,
1711                         .idlest_reg_id = 1,
1712                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1713                 },
1714         },
1715         .slaves         = omap2420_mcbsp2_slaves,
1716         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1717         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1718 };
1719
1720 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1721         &omap2420_l3_main_hwmod,
1722         &omap2420_l4_core_hwmod,
1723         &omap2420_l4_wkup_hwmod,
1724         &omap2420_mpu_hwmod,
1725         &omap2420_iva_hwmod,
1726
1727         &omap2420_timer1_hwmod,
1728         &omap2420_timer2_hwmod,
1729         &omap2420_timer3_hwmod,
1730         &omap2420_timer4_hwmod,
1731         &omap2420_timer5_hwmod,
1732         &omap2420_timer6_hwmod,
1733         &omap2420_timer7_hwmod,
1734         &omap2420_timer8_hwmod,
1735         &omap2420_timer9_hwmod,
1736         &omap2420_timer10_hwmod,
1737         &omap2420_timer11_hwmod,
1738         &omap2420_timer12_hwmod,
1739
1740         &omap2420_wd_timer2_hwmod,
1741         &omap2420_uart1_hwmod,
1742         &omap2420_uart2_hwmod,
1743         &omap2420_uart3_hwmod,
1744         /* dss class */
1745         &omap2420_dss_core_hwmod,
1746         &omap2420_dss_dispc_hwmod,
1747         &omap2420_dss_rfbi_hwmod,
1748         &omap2420_dss_venc_hwmod,
1749         /* i2c class */
1750         &omap2420_i2c1_hwmod,
1751         &omap2420_i2c2_hwmod,
1752
1753         /* gpio class */
1754         &omap2420_gpio1_hwmod,
1755         &omap2420_gpio2_hwmod,
1756         &omap2420_gpio3_hwmod,
1757         &omap2420_gpio4_hwmod,
1758
1759         /* dma_system class*/
1760         &omap2420_dma_system_hwmod,
1761
1762         /* mailbox class */
1763         &omap2420_mailbox_hwmod,
1764
1765         /* mcbsp class */
1766         &omap2420_mcbsp1_hwmod,
1767         &omap2420_mcbsp2_hwmod,
1768
1769         /* mcspi class */
1770         &omap2420_mcspi1_hwmod,
1771         &omap2420_mcspi2_hwmod,
1772         NULL,
1773 };
1774
1775 int __init omap2420_hwmod_init(void)
1776 {
1777         return omap_hwmod_register(omap2420_hwmods);
1778 }