2 * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
4 * Copyright (C) 2009-2010 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * XXX handle crossbar/shared link difference for L3?
12 * XXX these should be marked initdata for multi-OMAP kernels
14 #include <plat/omap_hwmod.h>
15 #include <mach/irqs.h>
18 #include <plat/serial.h>
20 #include <plat/gpio.h>
22 #include "omap_hwmod_common_data.h"
24 #include "cm-regbits-24xx.h"
25 #include "prm-regbits-24xx.h"
29 * OMAP2420 hardware module integration data
31 * ALl of the data in this section should be autogeneratable from the
32 * TI hardware database or other technical documentation. Data that
33 * is driver-specific or driver-kernel integration-specific belongs
37 static struct omap_hwmod omap2420_mpu_hwmod;
38 static struct omap_hwmod omap2420_iva_hwmod;
39 static struct omap_hwmod omap2420_l3_main_hwmod;
40 static struct omap_hwmod omap2420_l4_core_hwmod;
41 static struct omap_hwmod omap2420_wd_timer2_hwmod;
42 static struct omap_hwmod omap2420_gpio1_hwmod;
43 static struct omap_hwmod omap2420_gpio2_hwmod;
44 static struct omap_hwmod omap2420_gpio3_hwmod;
45 static struct omap_hwmod omap2420_gpio4_hwmod;
46 static struct omap_hwmod omap2420_dma_system_hwmod;
48 /* L3 -> L4_CORE interface */
49 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
50 .master = &omap2420_l3_main_hwmod,
51 .slave = &omap2420_l4_core_hwmod,
52 .user = OCP_USER_MPU | OCP_USER_SDMA,
55 /* MPU -> L3 interface */
56 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
57 .master = &omap2420_mpu_hwmod,
58 .slave = &omap2420_l3_main_hwmod,
62 /* Slave interfaces on the L3 interconnect */
63 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
64 &omap2420_mpu__l3_main,
67 /* Master interfaces on the L3 interconnect */
68 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
69 &omap2420_l3_main__l4_core,
73 static struct omap_hwmod omap2420_l3_main_hwmod = {
75 .class = &l3_hwmod_class,
76 .masters = omap2420_l3_main_masters,
77 .masters_cnt = ARRAY_SIZE(omap2420_l3_main_masters),
78 .slaves = omap2420_l3_main_slaves,
79 .slaves_cnt = ARRAY_SIZE(omap2420_l3_main_slaves),
80 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
81 .flags = HWMOD_NO_IDLEST,
84 static struct omap_hwmod omap2420_l4_wkup_hwmod;
85 static struct omap_hwmod omap2420_uart1_hwmod;
86 static struct omap_hwmod omap2420_uart2_hwmod;
87 static struct omap_hwmod omap2420_uart3_hwmod;
88 static struct omap_hwmod omap2420_i2c1_hwmod;
89 static struct omap_hwmod omap2420_i2c2_hwmod;
91 /* L4_CORE -> L4_WKUP interface */
92 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
93 .master = &omap2420_l4_core_hwmod,
94 .slave = &omap2420_l4_wkup_hwmod,
95 .user = OCP_USER_MPU | OCP_USER_SDMA,
98 /* L4 CORE -> UART1 interface */
99 static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
101 .pa_start = OMAP2_UART1_BASE,
102 .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
103 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
107 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
108 .master = &omap2420_l4_core_hwmod,
109 .slave = &omap2420_uart1_hwmod,
111 .addr = omap2420_uart1_addr_space,
112 .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
113 .user = OCP_USER_MPU | OCP_USER_SDMA,
116 /* L4 CORE -> UART2 interface */
117 static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
119 .pa_start = OMAP2_UART2_BASE,
120 .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
121 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
125 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
126 .master = &omap2420_l4_core_hwmod,
127 .slave = &omap2420_uart2_hwmod,
129 .addr = omap2420_uart2_addr_space,
130 .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
131 .user = OCP_USER_MPU | OCP_USER_SDMA,
134 /* L4 PER -> UART3 interface */
135 static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
137 .pa_start = OMAP2_UART3_BASE,
138 .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
139 .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
143 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
144 .master = &omap2420_l4_core_hwmod,
145 .slave = &omap2420_uart3_hwmod,
147 .addr = omap2420_uart3_addr_space,
148 .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
149 .user = OCP_USER_MPU | OCP_USER_SDMA,
152 /* I2C IP block address space length (in bytes) */
153 #define OMAP2_I2C_AS_LEN 128
155 /* L4 CORE -> I2C1 interface */
156 static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
158 .pa_start = 0x48070000,
159 .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
160 .flags = ADDR_TYPE_RT,
164 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
165 .master = &omap2420_l4_core_hwmod,
166 .slave = &omap2420_i2c1_hwmod,
168 .addr = omap2420_i2c1_addr_space,
169 .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
170 .user = OCP_USER_MPU | OCP_USER_SDMA,
173 /* L4 CORE -> I2C2 interface */
174 static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
176 .pa_start = 0x48072000,
177 .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
178 .flags = ADDR_TYPE_RT,
182 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
183 .master = &omap2420_l4_core_hwmod,
184 .slave = &omap2420_i2c2_hwmod,
186 .addr = omap2420_i2c2_addr_space,
187 .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
188 .user = OCP_USER_MPU | OCP_USER_SDMA,
191 /* Slave interfaces on the L4_CORE interconnect */
192 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
193 &omap2420_l3_main__l4_core,
196 /* Master interfaces on the L4_CORE interconnect */
197 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
198 &omap2420_l4_core__l4_wkup,
199 &omap2_l4_core__uart1,
200 &omap2_l4_core__uart2,
201 &omap2_l4_core__uart3,
202 &omap2420_l4_core__i2c1,
203 &omap2420_l4_core__i2c2
207 static struct omap_hwmod omap2420_l4_core_hwmod = {
209 .class = &l4_hwmod_class,
210 .masters = omap2420_l4_core_masters,
211 .masters_cnt = ARRAY_SIZE(omap2420_l4_core_masters),
212 .slaves = omap2420_l4_core_slaves,
213 .slaves_cnt = ARRAY_SIZE(omap2420_l4_core_slaves),
214 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
215 .flags = HWMOD_NO_IDLEST,
218 /* Slave interfaces on the L4_WKUP interconnect */
219 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
220 &omap2420_l4_core__l4_wkup,
223 /* Master interfaces on the L4_WKUP interconnect */
224 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
228 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
230 .class = &l4_hwmod_class,
231 .masters = omap2420_l4_wkup_masters,
232 .masters_cnt = ARRAY_SIZE(omap2420_l4_wkup_masters),
233 .slaves = omap2420_l4_wkup_slaves,
234 .slaves_cnt = ARRAY_SIZE(omap2420_l4_wkup_slaves),
235 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
236 .flags = HWMOD_NO_IDLEST,
239 /* Master interfaces on the MPU device */
240 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
241 &omap2420_mpu__l3_main,
245 static struct omap_hwmod omap2420_mpu_hwmod = {
247 .class = &mpu_hwmod_class,
248 .main_clk = "mpu_ck",
249 .masters = omap2420_mpu_masters,
250 .masters_cnt = ARRAY_SIZE(omap2420_mpu_masters),
251 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
255 * IVA1 interface data
258 /* IVA <- L3 interface */
259 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
260 .master = &omap2420_l3_main_hwmod,
261 .slave = &omap2420_iva_hwmod,
263 .user = OCP_USER_MPU | OCP_USER_SDMA,
266 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
274 static struct omap_hwmod omap2420_iva_hwmod = {
276 .class = &iva_hwmod_class,
277 .masters = omap2420_iva_masters,
278 .masters_cnt = ARRAY_SIZE(omap2420_iva_masters),
279 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
282 /* l4_wkup -> wd_timer2 */
283 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
285 .pa_start = 0x48022000,
286 .pa_end = 0x4802207f,
287 .flags = ADDR_TYPE_RT
291 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
292 .master = &omap2420_l4_wkup_hwmod,
293 .slave = &omap2420_wd_timer2_hwmod,
294 .clk = "mpu_wdt_ick",
295 .addr = omap2420_wd_timer2_addrs,
296 .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
297 .user = OCP_USER_MPU | OCP_USER_SDMA,
302 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
306 static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
310 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
311 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
312 .sysc_fields = &omap_hwmod_sysc_type1,
315 static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
317 .sysc = &omap2420_wd_timer_sysc,
318 .pre_shutdown = &omap2_wd_timer_disable
322 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
323 &omap2420_l4_wkup__wd_timer2,
326 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
328 .class = &omap2420_wd_timer_hwmod_class,
329 .main_clk = "mpu_wdt_fck",
333 .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
334 .module_offs = WKUP_MOD,
336 .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
339 .slaves = omap2420_wd_timer2_slaves,
340 .slaves_cnt = ARRAY_SIZE(omap2420_wd_timer2_slaves),
341 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
346 static struct omap_hwmod_class_sysconfig uart_sysc = {
350 .sysc_flags = (SYSC_HAS_SIDLEMODE |
351 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
352 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
353 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
354 .sysc_fields = &omap_hwmod_sysc_type1,
357 static struct omap_hwmod_class uart_class = {
364 static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
365 { .irq = INT_24XX_UART1_IRQ, },
368 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
369 { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
370 { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
373 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
374 &omap2_l4_core__uart1,
377 static struct omap_hwmod omap2420_uart1_hwmod = {
379 .mpu_irqs = uart1_mpu_irqs,
380 .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
381 .sdma_reqs = uart1_sdma_reqs,
382 .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
383 .main_clk = "uart1_fck",
386 .module_offs = CORE_MOD,
388 .module_bit = OMAP24XX_EN_UART1_SHIFT,
390 .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
393 .slaves = omap2420_uart1_slaves,
394 .slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
395 .class = &uart_class,
396 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
401 static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
402 { .irq = INT_24XX_UART2_IRQ, },
405 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
406 { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
407 { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
410 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
411 &omap2_l4_core__uart2,
414 static struct omap_hwmod omap2420_uart2_hwmod = {
416 .mpu_irqs = uart2_mpu_irqs,
417 .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
418 .sdma_reqs = uart2_sdma_reqs,
419 .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
420 .main_clk = "uart2_fck",
423 .module_offs = CORE_MOD,
425 .module_bit = OMAP24XX_EN_UART2_SHIFT,
427 .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
430 .slaves = omap2420_uart2_slaves,
431 .slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
432 .class = &uart_class,
433 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
438 static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
439 { .irq = INT_24XX_UART3_IRQ, },
442 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
443 { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
444 { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
447 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
448 &omap2_l4_core__uart3,
451 static struct omap_hwmod omap2420_uart3_hwmod = {
453 .mpu_irqs = uart3_mpu_irqs,
454 .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
455 .sdma_reqs = uart3_sdma_reqs,
456 .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
457 .main_clk = "uart3_fck",
460 .module_offs = CORE_MOD,
462 .module_bit = OMAP24XX_EN_UART3_SHIFT,
464 .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
467 .slaves = omap2420_uart3_slaves,
468 .slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
469 .class = &uart_class,
470 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
474 static struct omap_hwmod_class_sysconfig i2c_sysc = {
478 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
479 .sysc_fields = &omap_hwmod_sysc_type1,
482 static struct omap_hwmod_class i2c_class = {
487 static struct omap_i2c_dev_attr i2c_dev_attr;
491 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
492 { .irq = INT_24XX_I2C1_IRQ, },
495 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
496 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
497 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
500 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
501 &omap2420_l4_core__i2c1,
504 static struct omap_hwmod omap2420_i2c1_hwmod = {
506 .mpu_irqs = i2c1_mpu_irqs,
507 .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
508 .sdma_reqs = i2c1_sdma_reqs,
509 .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
510 .main_clk = "i2c1_fck",
513 .module_offs = CORE_MOD,
515 .module_bit = OMAP2420_EN_I2C1_SHIFT,
517 .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
520 .slaves = omap2420_i2c1_slaves,
521 .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves),
523 .dev_attr = &i2c_dev_attr,
524 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
525 .flags = HWMOD_16BIT_REG,
530 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
531 { .irq = INT_24XX_I2C2_IRQ, },
534 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
535 { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
536 { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
539 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
540 &omap2420_l4_core__i2c2,
543 static struct omap_hwmod omap2420_i2c2_hwmod = {
545 .mpu_irqs = i2c2_mpu_irqs,
546 .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
547 .sdma_reqs = i2c2_sdma_reqs,
548 .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
549 .main_clk = "i2c2_fck",
552 .module_offs = CORE_MOD,
554 .module_bit = OMAP2420_EN_I2C2_SHIFT,
556 .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
559 .slaves = omap2420_i2c2_slaves,
560 .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves),
562 .dev_attr = &i2c_dev_attr,
563 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
564 .flags = HWMOD_16BIT_REG,
567 /* l4_wkup -> gpio1 */
568 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
570 .pa_start = 0x48018000,
571 .pa_end = 0x480181ff,
572 .flags = ADDR_TYPE_RT
576 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
577 .master = &omap2420_l4_wkup_hwmod,
578 .slave = &omap2420_gpio1_hwmod,
580 .addr = omap2420_gpio1_addr_space,
581 .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
582 .user = OCP_USER_MPU | OCP_USER_SDMA,
585 /* l4_wkup -> gpio2 */
586 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
588 .pa_start = 0x4801a000,
589 .pa_end = 0x4801a1ff,
590 .flags = ADDR_TYPE_RT
594 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
595 .master = &omap2420_l4_wkup_hwmod,
596 .slave = &omap2420_gpio2_hwmod,
598 .addr = omap2420_gpio2_addr_space,
599 .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
600 .user = OCP_USER_MPU | OCP_USER_SDMA,
603 /* l4_wkup -> gpio3 */
604 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
606 .pa_start = 0x4801c000,
607 .pa_end = 0x4801c1ff,
608 .flags = ADDR_TYPE_RT
612 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
613 .master = &omap2420_l4_wkup_hwmod,
614 .slave = &omap2420_gpio3_hwmod,
616 .addr = omap2420_gpio3_addr_space,
617 .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
618 .user = OCP_USER_MPU | OCP_USER_SDMA,
621 /* l4_wkup -> gpio4 */
622 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
624 .pa_start = 0x4801e000,
625 .pa_end = 0x4801e1ff,
626 .flags = ADDR_TYPE_RT
630 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
631 .master = &omap2420_l4_wkup_hwmod,
632 .slave = &omap2420_gpio4_hwmod,
634 .addr = omap2420_gpio4_addr_space,
635 .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
636 .user = OCP_USER_MPU | OCP_USER_SDMA,
640 static struct omap_gpio_dev_attr gpio_dev_attr = {
645 static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
649 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
650 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
651 SYSS_HAS_RESET_STATUS),
652 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
653 .sysc_fields = &omap_hwmod_sysc_type1,
658 * general purpose io module
660 static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
662 .sysc = &omap242x_gpio_sysc,
667 static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
668 { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
671 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
672 &omap2420_l4_wkup__gpio1,
675 static struct omap_hwmod omap2420_gpio1_hwmod = {
677 .mpu_irqs = omap242x_gpio1_irqs,
678 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
679 .main_clk = "gpios_fck",
683 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
684 .module_offs = WKUP_MOD,
686 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
689 .slaves = omap2420_gpio1_slaves,
690 .slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
691 .class = &omap242x_gpio_hwmod_class,
692 .dev_attr = &gpio_dev_attr,
693 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
697 static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
698 { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
701 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
702 &omap2420_l4_wkup__gpio2,
705 static struct omap_hwmod omap2420_gpio2_hwmod = {
707 .mpu_irqs = omap242x_gpio2_irqs,
708 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
709 .main_clk = "gpios_fck",
713 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
714 .module_offs = WKUP_MOD,
716 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
719 .slaves = omap2420_gpio2_slaves,
720 .slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
721 .class = &omap242x_gpio_hwmod_class,
722 .dev_attr = &gpio_dev_attr,
723 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
727 static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
728 { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
731 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
732 &omap2420_l4_wkup__gpio3,
735 static struct omap_hwmod omap2420_gpio3_hwmod = {
737 .mpu_irqs = omap242x_gpio3_irqs,
738 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
739 .main_clk = "gpios_fck",
743 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
744 .module_offs = WKUP_MOD,
746 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
749 .slaves = omap2420_gpio3_slaves,
750 .slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
751 .class = &omap242x_gpio_hwmod_class,
752 .dev_attr = &gpio_dev_attr,
753 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
757 static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
758 { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
761 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
762 &omap2420_l4_wkup__gpio4,
765 static struct omap_hwmod omap2420_gpio4_hwmod = {
767 .mpu_irqs = omap242x_gpio4_irqs,
768 .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
769 .main_clk = "gpios_fck",
773 .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
774 .module_offs = WKUP_MOD,
776 .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
779 .slaves = omap2420_gpio4_slaves,
780 .slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
781 .class = &omap242x_gpio_hwmod_class,
782 .dev_attr = &gpio_dev_attr,
783 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
787 static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
791 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
792 SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
793 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
794 .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
795 .sysc_fields = &omap_hwmod_sysc_type1,
798 static struct omap_hwmod_class omap2420_dma_hwmod_class = {
800 .sysc = &omap2420_dma_sysc,
804 static struct omap_dma_dev_attr dma_dev_attr = {
805 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
806 IS_CSSA_32 | IS_CDSA_32,
810 static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
811 { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
812 { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
813 { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
814 { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
817 static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
819 .pa_start = 0x48056000,
820 .pa_end = 0x4a0560ff,
821 .flags = ADDR_TYPE_RT
825 /* dma_system -> L3 */
826 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
827 .master = &omap2420_dma_system_hwmod,
828 .slave = &omap2420_l3_main_hwmod,
830 .user = OCP_USER_MPU | OCP_USER_SDMA,
833 /* dma_system master ports */
834 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
835 &omap2420_dma_system__l3,
838 /* l4_core -> dma_system */
839 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
840 .master = &omap2420_l4_core_hwmod,
841 .slave = &omap2420_dma_system_hwmod,
843 .addr = omap2420_dma_system_addrs,
844 .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
845 .user = OCP_USER_MPU | OCP_USER_SDMA,
848 /* dma_system slave ports */
849 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
850 &omap2420_l4_core__dma_system,
853 static struct omap_hwmod omap2420_dma_system_hwmod = {
855 .class = &omap2420_dma_hwmod_class,
856 .mpu_irqs = omap2420_dma_system_irqs,
857 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
858 .main_clk = "core_l3_ck",
859 .slaves = omap2420_dma_system_slaves,
860 .slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
861 .masters = omap2420_dma_system_masters,
862 .masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
863 .dev_attr = &dma_dev_attr,
864 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
865 .flags = HWMOD_NO_IDLEST,
868 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
869 &omap2420_l3_main_hwmod,
870 &omap2420_l4_core_hwmod,
871 &omap2420_l4_wkup_hwmod,
874 &omap2420_wd_timer2_hwmod,
875 &omap2420_uart1_hwmod,
876 &omap2420_uart2_hwmod,
877 &omap2420_uart3_hwmod,
878 &omap2420_i2c1_hwmod,
879 &omap2420_i2c2_hwmod,
882 &omap2420_gpio1_hwmod,
883 &omap2420_gpio2_hwmod,
884 &omap2420_gpio3_hwmod,
885 &omap2420_gpio4_hwmod,
887 /* dma_system class*/
888 &omap2420_dma_system_hwmod,
892 int __init omap2420_hwmod_init(void)
894 return omap_hwmod_init(omap2420_hwmods);