arch/arm/mach-omap2/omap_hwmod_2420_data.c

   1 /*
   2  * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * XXX handle crossbar/shared link difference for L3?
  12  * XXX these should be marked initdata for multi-OMAP kernels
  13  */
  14 #include <plat/omap_hwmod.h>
  15 #include <mach/irqs.h>
  16 #include <plat/cpu.h>
  17 #include <plat/dma.h>
  18 #include <plat/serial.h>
  19 #include <plat/i2c.h>
  20 #include <plat/gpio.h>
  21 #include <plat/mcspi.h>
  22 #include <plat/dmtimer.h>
  23 #include <plat/l3_2xxx.h>
  24 #include <plat/l4_2xxx.h>
  25
  26 #include "omap_hwmod_common_data.h"
  27
  28 #include "cm-regbits-24xx.h"
  29 #include "prm-regbits-24xx.h"
  30 #include "wd_timer.h"
  31
  32 /*
  33  * OMAP2420 hardware module integration data
  34  *
  35  * ALl of the data in this section should be autogeneratable from the
  36  * TI hardware database or other technical documentation.  Data that
  37  * is driver-specific or driver-kernel integration-specific belongs
  38  * elsewhere.
  39  */
  40
  41 static struct omap_hwmod omap2420_mpu_hwmod;
  42 static struct omap_hwmod omap2420_iva_hwmod;
  43 static struct omap_hwmod omap2420_l3_main_hwmod;
  44 static struct omap_hwmod omap2420_l4_core_hwmod;
  45 static struct omap_hwmod omap2420_dss_core_hwmod;
  46 static struct omap_hwmod omap2420_dss_dispc_hwmod;
  47 static struct omap_hwmod omap2420_dss_rfbi_hwmod;
  48 static struct omap_hwmod omap2420_dss_venc_hwmod;
  49 static struct omap_hwmod omap2420_wd_timer2_hwmod;
  50 static struct omap_hwmod omap2420_gpio1_hwmod;
  51 static struct omap_hwmod omap2420_gpio2_hwmod;
  52 static struct omap_hwmod omap2420_gpio3_hwmod;
  53 static struct omap_hwmod omap2420_gpio4_hwmod;
  54 static struct omap_hwmod omap2420_dma_system_hwmod;
  55 static struct omap_hwmod omap2420_mcspi1_hwmod;
  56 static struct omap_hwmod omap2420_mcspi2_hwmod;
  57
  58 /* L3 -> L4_CORE interface */
  59 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
  60         .master = &omap2420_l3_main_hwmod,
  61         .slave  = &omap2420_l4_core_hwmod,
  62         .user   = OCP_USER_MPU | OCP_USER_SDMA,
  63 };
  64
  65 /* MPU -> L3 interface */
  66 static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = {
  67         .master = &omap2420_mpu_hwmod,
  68         .slave  = &omap2420_l3_main_hwmod,
  69         .user   = OCP_USER_MPU,
  70 };
  71
  72 /* Slave interfaces on the L3 interconnect */
  73 static struct omap_hwmod_ocp_if *omap2420_l3_main_slaves[] = {
  74         &omap2420_mpu__l3_main,
  75 };
  76
  77 /* DSS -> l3 */
  78 static struct omap_hwmod_ocp_if omap2420_dss__l3 = {
  79         .master         = &omap2420_dss_core_hwmod,
  80         .slave          = &omap2420_l3_main_hwmod,
  81         .fw = {
  82                 .omap2 = {
  83                         .l3_perm_bit  = OMAP2_L3_CORE_FW_CONNID_DSS,
  84                         .flags  = OMAP_FIREWALL_L3,
  85                 }
  86         },
  87         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  88 };
  89
  90 /* Master interfaces on the L3 interconnect */
  91 static struct omap_hwmod_ocp_if *omap2420_l3_main_masters[] = {
  92         &omap2420_l3_main__l4_core,
  93 };
  94
  95 /* L3 */
  96 static struct omap_hwmod omap2420_l3_main_hwmod = {
  97         .name           = "l3_main",
  98         .class          = &l3_hwmod_class,
  99         .masters        = omap2420_l3_main_masters,
 100         .masters_cnt    = ARRAY_SIZE(omap2420_l3_main_masters),
 101         .slaves         = omap2420_l3_main_slaves,
 102         .slaves_cnt     = ARRAY_SIZE(omap2420_l3_main_slaves),
 103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 104         .flags          = HWMOD_NO_IDLEST,
 105 };
 106
 107 static struct omap_hwmod omap2420_l4_wkup_hwmod;
 108 static struct omap_hwmod omap2420_uart1_hwmod;
 109 static struct omap_hwmod omap2420_uart2_hwmod;
 110 static struct omap_hwmod omap2420_uart3_hwmod;
 111 static struct omap_hwmod omap2420_i2c1_hwmod;
 112 static struct omap_hwmod omap2420_i2c2_hwmod;
 113 static struct omap_hwmod omap2420_mcbsp1_hwmod;
 114 static struct omap_hwmod omap2420_mcbsp2_hwmod;
 115
 116 /* l4 core -> mcspi1 interface */
 117 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
 118         .master         = &omap2420_l4_core_hwmod,
 119         .slave          = &omap2420_mcspi1_hwmod,
 120         .clk            = "mcspi1_ick",
 121         .addr           = omap2_mcspi1_addr_space,
 122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 123 };
 124
 125 /* l4 core -> mcspi2 interface */
 126 static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
 127         .master         = &omap2420_l4_core_hwmod,
 128         .slave          = &omap2420_mcspi2_hwmod,
 129         .clk            = "mcspi2_ick",
 130         .addr           = omap2_mcspi2_addr_space,
 131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 132 };
 133
 134 /* L4_CORE -> L4_WKUP interface */
 135 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 136         .master = &omap2420_l4_core_hwmod,
 137         .slave  = &omap2420_l4_wkup_hwmod,
 138         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 139 };
 140
 141 /* L4 CORE -> UART1 interface */
 142 static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
 143         .master         = &omap2420_l4_core_hwmod,
 144         .slave          = &omap2420_uart1_hwmod,
 145         .clk            = "uart1_ick",
 146         .addr           = omap2xxx_uart1_addr_space,
 147         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 148 };
 149
 150 /* L4 CORE -> UART2 interface */
 151 static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
 152         .master         = &omap2420_l4_core_hwmod,
 153         .slave          = &omap2420_uart2_hwmod,
 154         .clk            = "uart2_ick",
 155         .addr           = omap2xxx_uart2_addr_space,
 156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 /* L4 PER -> UART3 interface */
 160 static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
 161         .master         = &omap2420_l4_core_hwmod,
 162         .slave          = &omap2420_uart3_hwmod,
 163         .clk            = "uart3_ick",
 164         .addr           = omap2xxx_uart3_addr_space,
 165         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 166 };
 167
 168 /* L4 CORE -> I2C1 interface */
 169 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
 170         .master         = &omap2420_l4_core_hwmod,
 171         .slave          = &omap2420_i2c1_hwmod,
 172         .clk            = "i2c1_ick",
 173         .addr           = omap2_i2c1_addr_space,
 174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 175 };
 176
 177 /* L4 CORE -> I2C2 interface */
 178 static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
 179         .master         = &omap2420_l4_core_hwmod,
 180         .slave          = &omap2420_i2c2_hwmod,
 181         .clk            = "i2c2_ick",
 182         .addr           = omap2_i2c2_addr_space,
 183         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 184 };
 185
 186 /* Slave interfaces on the L4_CORE interconnect */
 187 static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = {
 188         &omap2420_l3_main__l4_core,
 189 };
 190
 191 /* Master interfaces on the L4_CORE interconnect */
 192 static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = {
 193         &omap2420_l4_core__l4_wkup,
 194         &omap2_l4_core__uart1,
 195         &omap2_l4_core__uart2,
 196         &omap2_l4_core__uart3,
 197         &omap2420_l4_core__i2c1,
 198         &omap2420_l4_core__i2c2
 199 };
 200
 201 /* L4 CORE */
 202 static struct omap_hwmod omap2420_l4_core_hwmod = {
 203         .name           = "l4_core",
 204         .class          = &l4_hwmod_class,
 205         .masters        = omap2420_l4_core_masters,
 206         .masters_cnt    = ARRAY_SIZE(omap2420_l4_core_masters),
 207         .slaves         = omap2420_l4_core_slaves,
 208         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_core_slaves),
 209         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 210         .flags          = HWMOD_NO_IDLEST,
 211 };
 212
 213 /* Slave interfaces on the L4_WKUP interconnect */
 214 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_slaves[] = {
 215         &omap2420_l4_core__l4_wkup,
 216 };
 217
 218 /* Master interfaces on the L4_WKUP interconnect */
 219 static struct omap_hwmod_ocp_if *omap2420_l4_wkup_masters[] = {
 220 };
 221
 222 /* L4 WKUP */
 223 static struct omap_hwmod omap2420_l4_wkup_hwmod = {
 224         .name           = "l4_wkup",
 225         .class          = &l4_hwmod_class,
 226         .masters        = omap2420_l4_wkup_masters,
 227         .masters_cnt    = ARRAY_SIZE(omap2420_l4_wkup_masters),
 228         .slaves         = omap2420_l4_wkup_slaves,
 229         .slaves_cnt     = ARRAY_SIZE(omap2420_l4_wkup_slaves),
 230         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 231         .flags          = HWMOD_NO_IDLEST,
 232 };
 233
 234 /* Master interfaces on the MPU device */
 235 static struct omap_hwmod_ocp_if *omap2420_mpu_masters[] = {
 236         &omap2420_mpu__l3_main,
 237 };
 238
 239 /* MPU */
 240 static struct omap_hwmod omap2420_mpu_hwmod = {
 241         .name           = "mpu",
 242         .class          = &mpu_hwmod_class,
 243         .main_clk       = "mpu_ck",
 244         .masters        = omap2420_mpu_masters,
 245         .masters_cnt    = ARRAY_SIZE(omap2420_mpu_masters),
 246         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 247 };
 248
 249 /*
 250  * IVA1 interface data
 251  */
 252
 253 /* IVA <- L3 interface */
 254 static struct omap_hwmod_ocp_if omap2420_l3__iva = {
 255         .master         = &omap2420_l3_main_hwmod,
 256         .slave          = &omap2420_iva_hwmod,
 257         .clk            = "iva1_ifck",
 258         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 259 };
 260
 261 static struct omap_hwmod_ocp_if *omap2420_iva_masters[] = {
 262         &omap2420_l3__iva,
 263 };
 264
 265 /*
 266  * IVA2 (IVA2)
 267  */
 268
 269 static struct omap_hwmod omap2420_iva_hwmod = {
 270         .name           = "iva",
 271         .class          = &iva_hwmod_class,
 272         .masters        = omap2420_iva_masters,
 273         .masters_cnt    = ARRAY_SIZE(omap2420_iva_masters),
 274         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 275 };
 276
 277 /* Timer Common */
 278 static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
 279         .rev_offs       = 0x0000,
 280         .sysc_offs      = 0x0010,
 281         .syss_offs      = 0x0014,
 282         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 283                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 284                            SYSC_HAS_AUTOIDLE),
 285         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 286         .sysc_fields    = &omap_hwmod_sysc_type1,
 287 };
 288
 289 static struct omap_hwmod_class omap2420_timer_hwmod_class = {
 290         .name = "timer",
 291         .sysc = &omap2420_timer_sysc,
 292         .rev = OMAP_TIMER_IP_VERSION_1,
 293 };
 294
 295 /* timer1 */
 296 static struct omap_hwmod omap2420_timer1_hwmod;
 297
 298 static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
 299         {
 300                 .pa_start       = 0x48028000,
 301                 .pa_end         = 0x48028000 + SZ_1K - 1,
 302                 .flags          = ADDR_TYPE_RT
 303         },
 304         { }
 305 };
 306
 307 /* l4_wkup -> timer1 */
 308 static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
 309         .master         = &omap2420_l4_wkup_hwmod,
 310         .slave          = &omap2420_timer1_hwmod,
 311         .clk            = "gpt1_ick",
 312         .addr           = omap2420_timer1_addrs,
 313         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 314 };
 315
 316 /* timer1 slave port */
 317 static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
 318         &omap2420_l4_wkup__timer1,
 319 };
 320
 321 /* timer1 hwmod */
 322 static struct omap_hwmod omap2420_timer1_hwmod = {
 323         .name           = "timer1",
 324         .mpu_irqs       = omap2_timer1_mpu_irqs,
 325         .main_clk       = "gpt1_fck",
 326         .prcm           = {
 327                 .omap2 = {
 328                         .prcm_reg_id = 1,
 329                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 330                         .module_offs = WKUP_MOD,
 331                         .idlest_reg_id = 1,
 332                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 333                 },
 334         },
 335         .slaves         = omap2420_timer1_slaves,
 336         .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
 337         .class          = &omap2420_timer_hwmod_class,
 338         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 339 };
 340
 341 /* timer2 */
 342 static struct omap_hwmod omap2420_timer2_hwmod;
 343
 344 /* l4_core -> timer2 */
 345 static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
 346         .master         = &omap2420_l4_core_hwmod,
 347         .slave          = &omap2420_timer2_hwmod,
 348         .clk            = "gpt2_ick",
 349         .addr           = omap2xxx_timer2_addrs,
 350         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 351 };
 352
 353 /* timer2 slave port */
 354 static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
 355         &omap2420_l4_core__timer2,
 356 };
 357
 358 /* timer2 hwmod */
 359 static struct omap_hwmod omap2420_timer2_hwmod = {
 360         .name           = "timer2",
 361         .mpu_irqs       = omap2_timer2_mpu_irqs,
 362         .main_clk       = "gpt2_fck",
 363         .prcm           = {
 364                 .omap2 = {
 365                         .prcm_reg_id = 1,
 366                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 367                         .module_offs = CORE_MOD,
 368                         .idlest_reg_id = 1,
 369                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 370                 },
 371         },
 372         .slaves         = omap2420_timer2_slaves,
 373         .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
 374         .class          = &omap2420_timer_hwmod_class,
 375         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 376 };
 377
 378 /* timer3 */
 379 static struct omap_hwmod omap2420_timer3_hwmod;
 380
 381 /* l4_core -> timer3 */
 382 static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
 383         .master         = &omap2420_l4_core_hwmod,
 384         .slave          = &omap2420_timer3_hwmod,
 385         .clk            = "gpt3_ick",
 386         .addr           = omap2xxx_timer3_addrs,
 387         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 388 };
 389
 390 /* timer3 slave port */
 391 static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
 392         &omap2420_l4_core__timer3,
 393 };
 394
 395 /* timer3 hwmod */
 396 static struct omap_hwmod omap2420_timer3_hwmod = {
 397         .name           = "timer3",
 398         .mpu_irqs       = omap2_timer3_mpu_irqs,
 399         .main_clk       = "gpt3_fck",
 400         .prcm           = {
 401                 .omap2 = {
 402                         .prcm_reg_id = 1,
 403                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 404                         .module_offs = CORE_MOD,
 405                         .idlest_reg_id = 1,
 406                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 407                 },
 408         },
 409         .slaves         = omap2420_timer3_slaves,
 410         .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
 411         .class          = &omap2420_timer_hwmod_class,
 412         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 413 };
 414
 415 /* timer4 */
 416 static struct omap_hwmod omap2420_timer4_hwmod;
 417
 418 /* l4_core -> timer4 */
 419 static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
 420         .master         = &omap2420_l4_core_hwmod,
 421         .slave          = &omap2420_timer4_hwmod,
 422         .clk            = "gpt4_ick",
 423         .addr           = omap2xxx_timer4_addrs,
 424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 425 };
 426
 427 /* timer4 slave port */
 428 static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
 429         &omap2420_l4_core__timer4,
 430 };
 431
 432 /* timer4 hwmod */
 433 static struct omap_hwmod omap2420_timer4_hwmod = {
 434         .name           = "timer4",
 435         .mpu_irqs       = omap2_timer4_mpu_irqs,
 436         .main_clk       = "gpt4_fck",
 437         .prcm           = {
 438                 .omap2 = {
 439                         .prcm_reg_id = 1,
 440                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 441                         .module_offs = CORE_MOD,
 442                         .idlest_reg_id = 1,
 443                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 444                 },
 445         },
 446         .slaves         = omap2420_timer4_slaves,
 447         .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
 448         .class          = &omap2420_timer_hwmod_class,
 449         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 450 };
 451
 452 /* timer5 */
 453 static struct omap_hwmod omap2420_timer5_hwmod;
 454
 455 /* l4_core -> timer5 */
 456 static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
 457         .master         = &omap2420_l4_core_hwmod,
 458         .slave          = &omap2420_timer5_hwmod,
 459         .clk            = "gpt5_ick",
 460         .addr           = omap2xxx_timer5_addrs,
 461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 462 };
 463
 464 /* timer5 slave port */
 465 static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
 466         &omap2420_l4_core__timer5,
 467 };
 468
 469 /* timer5 hwmod */
 470 static struct omap_hwmod omap2420_timer5_hwmod = {
 471         .name           = "timer5",
 472         .mpu_irqs       = omap2_timer5_mpu_irqs,
 473         .main_clk       = "gpt5_fck",
 474         .prcm           = {
 475                 .omap2 = {
 476                         .prcm_reg_id = 1,
 477                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 478                         .module_offs = CORE_MOD,
 479                         .idlest_reg_id = 1,
 480                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 481                 },
 482         },
 483         .slaves         = omap2420_timer5_slaves,
 484         .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
 485         .class          = &omap2420_timer_hwmod_class,
 486         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 487 };
 488
 489
 490 /* timer6 */
 491 static struct omap_hwmod omap2420_timer6_hwmod;
 492
 493 /* l4_core -> timer6 */
 494 static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
 495         .master         = &omap2420_l4_core_hwmod,
 496         .slave          = &omap2420_timer6_hwmod,
 497         .clk            = "gpt6_ick",
 498         .addr           = omap2xxx_timer6_addrs,
 499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 500 };
 501
 502 /* timer6 slave port */
 503 static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
 504         &omap2420_l4_core__timer6,
 505 };
 506
 507 /* timer6 hwmod */
 508 static struct omap_hwmod omap2420_timer6_hwmod = {
 509         .name           = "timer6",
 510         .mpu_irqs       = omap2_timer6_mpu_irqs,
 511         .main_clk       = "gpt6_fck",
 512         .prcm           = {
 513                 .omap2 = {
 514                         .prcm_reg_id = 1,
 515                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 516                         .module_offs = CORE_MOD,
 517                         .idlest_reg_id = 1,
 518                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 519                 },
 520         },
 521         .slaves         = omap2420_timer6_slaves,
 522         .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
 523         .class          = &omap2420_timer_hwmod_class,
 524         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 525 };
 526
 527 /* timer7 */
 528 static struct omap_hwmod omap2420_timer7_hwmod;
 529
 530 /* l4_core -> timer7 */
 531 static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
 532         .master         = &omap2420_l4_core_hwmod,
 533         .slave          = &omap2420_timer7_hwmod,
 534         .clk            = "gpt7_ick",
 535         .addr           = omap2xxx_timer7_addrs,
 536         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 537 };
 538
 539 /* timer7 slave port */
 540 static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
 541         &omap2420_l4_core__timer7,
 542 };
 543
 544 /* timer7 hwmod */
 545 static struct omap_hwmod omap2420_timer7_hwmod = {
 546         .name           = "timer7",
 547         .mpu_irqs       = omap2_timer7_mpu_irqs,
 548         .main_clk       = "gpt7_fck",
 549         .prcm           = {
 550                 .omap2 = {
 551                         .prcm_reg_id = 1,
 552                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 553                         .module_offs = CORE_MOD,
 554                         .idlest_reg_id = 1,
 555                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 556                 },
 557         },
 558         .slaves         = omap2420_timer7_slaves,
 559         .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
 560         .class          = &omap2420_timer_hwmod_class,
 561         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 562 };
 563
 564 /* timer8 */
 565 static struct omap_hwmod omap2420_timer8_hwmod;
 566
 567 /* l4_core -> timer8 */
 568 static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
 569         .master         = &omap2420_l4_core_hwmod,
 570         .slave          = &omap2420_timer8_hwmod,
 571         .clk            = "gpt8_ick",
 572         .addr           = omap2xxx_timer8_addrs,
 573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 574 };
 575
 576 /* timer8 slave port */
 577 static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
 578         &omap2420_l4_core__timer8,
 579 };
 580
 581 /* timer8 hwmod */
 582 static struct omap_hwmod omap2420_timer8_hwmod = {
 583         .name           = "timer8",
 584         .mpu_irqs       = omap2_timer8_mpu_irqs,
 585         .main_clk       = "gpt8_fck",
 586         .prcm           = {
 587                 .omap2 = {
 588                         .prcm_reg_id = 1,
 589                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 590                         .module_offs = CORE_MOD,
 591                         .idlest_reg_id = 1,
 592                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 593                 },
 594         },
 595         .slaves         = omap2420_timer8_slaves,
 596         .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
 597         .class          = &omap2420_timer_hwmod_class,
 598         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 599 };
 600
 601 /* timer9 */
 602 static struct omap_hwmod omap2420_timer9_hwmod;
 603
 604 /* l4_core -> timer9 */
 605 static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
 606         .master         = &omap2420_l4_core_hwmod,
 607         .slave          = &omap2420_timer9_hwmod,
 608         .clk            = "gpt9_ick",
 609         .addr           = omap2xxx_timer9_addrs,
 610         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 611 };
 612
 613 /* timer9 slave port */
 614 static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
 615         &omap2420_l4_core__timer9,
 616 };
 617
 618 /* timer9 hwmod */
 619 static struct omap_hwmod omap2420_timer9_hwmod = {
 620         .name           = "timer9",
 621         .mpu_irqs       = omap2_timer9_mpu_irqs,
 622         .main_clk       = "gpt9_fck",
 623         .prcm           = {
 624                 .omap2 = {
 625                         .prcm_reg_id = 1,
 626                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 627                         .module_offs = CORE_MOD,
 628                         .idlest_reg_id = 1,
 629                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 630                 },
 631         },
 632         .slaves         = omap2420_timer9_slaves,
 633         .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
 634         .class          = &omap2420_timer_hwmod_class,
 635         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 636 };
 637
 638 /* timer10 */
 639 static struct omap_hwmod omap2420_timer10_hwmod;
 640
 641 /* l4_core -> timer10 */
 642 static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
 643         .master         = &omap2420_l4_core_hwmod,
 644         .slave          = &omap2420_timer10_hwmod,
 645         .clk            = "gpt10_ick",
 646         .addr           = omap2_timer10_addrs,
 647         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 648 };
 649
 650 /* timer10 slave port */
 651 static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
 652         &omap2420_l4_core__timer10,
 653 };
 654
 655 /* timer10 hwmod */
 656 static struct omap_hwmod omap2420_timer10_hwmod = {
 657         .name           = "timer10",
 658         .mpu_irqs       = omap2_timer10_mpu_irqs,
 659         .main_clk       = "gpt10_fck",
 660         .prcm           = {
 661                 .omap2 = {
 662                         .prcm_reg_id = 1,
 663                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 664                         .module_offs = CORE_MOD,
 665                         .idlest_reg_id = 1,
 666                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 667                 },
 668         },
 669         .slaves         = omap2420_timer10_slaves,
 670         .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
 671         .class          = &omap2420_timer_hwmod_class,
 672         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 673 };
 674
 675 /* timer11 */
 676 static struct omap_hwmod omap2420_timer11_hwmod;
 677
 678 /* l4_core -> timer11 */
 679 static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
 680         .master         = &omap2420_l4_core_hwmod,
 681         .slave          = &omap2420_timer11_hwmod,
 682         .clk            = "gpt11_ick",
 683         .addr           = omap2_timer11_addrs,
 684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 685 };
 686
 687 /* timer11 slave port */
 688 static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
 689         &omap2420_l4_core__timer11,
 690 };
 691
 692 /* timer11 hwmod */
 693 static struct omap_hwmod omap2420_timer11_hwmod = {
 694         .name           = "timer11",
 695         .mpu_irqs       = omap2_timer11_mpu_irqs,
 696         .main_clk       = "gpt11_fck",
 697         .prcm           = {
 698                 .omap2 = {
 699                         .prcm_reg_id = 1,
 700                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 701                         .module_offs = CORE_MOD,
 702                         .idlest_reg_id = 1,
 703                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 704                 },
 705         },
 706         .slaves         = omap2420_timer11_slaves,
 707         .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
 708         .class          = &omap2420_timer_hwmod_class,
 709         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 710 };
 711
 712 /* timer12 */
 713 static struct omap_hwmod omap2420_timer12_hwmod;
 714
 715 /* l4_core -> timer12 */
 716 static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
 717         .master         = &omap2420_l4_core_hwmod,
 718         .slave          = &omap2420_timer12_hwmod,
 719         .clk            = "gpt12_ick",
 720         .addr           = omap2xxx_timer12_addrs,
 721         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 722 };
 723
 724 /* timer12 slave port */
 725 static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
 726         &omap2420_l4_core__timer12,
 727 };
 728
 729 /* timer12 hwmod */
 730 static struct omap_hwmod omap2420_timer12_hwmod = {
 731         .name           = "timer12",
 732         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 733         .main_clk       = "gpt12_fck",
 734         .prcm           = {
 735                 .omap2 = {
 736                         .prcm_reg_id = 1,
 737                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 738                         .module_offs = CORE_MOD,
 739                         .idlest_reg_id = 1,
 740                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 741                 },
 742         },
 743         .slaves         = omap2420_timer12_slaves,
 744         .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
 745         .class          = &omap2420_timer_hwmod_class,
 746         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 747 };
 748
 749 /* l4_wkup -> wd_timer2 */
 750 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
 751         {
 752                 .pa_start       = 0x48022000,
 753                 .pa_end         = 0x4802207f,
 754                 .flags          = ADDR_TYPE_RT
 755         },
 756         { }
 757 };
 758
 759 static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
 760         .master         = &omap2420_l4_wkup_hwmod,
 761         .slave          = &omap2420_wd_timer2_hwmod,
 762         .clk            = "mpu_wdt_ick",
 763         .addr           = omap2420_wd_timer2_addrs,
 764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 765 };
 766
 767 /*
 768  * 'wd_timer' class
 769  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 770  * overflow condition
 771  */
 772
 773 static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
 774         .rev_offs       = 0x0000,
 775         .sysc_offs      = 0x0010,
 776         .syss_offs      = 0x0014,
 777         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
 778                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 779         .sysc_fields    = &omap_hwmod_sysc_type1,
 780 };
 781
 782 static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
 783         .name           = "wd_timer",
 784         .sysc           = &omap2420_wd_timer_sysc,
 785         .pre_shutdown   = &omap2_wd_timer_disable
 786 };
 787
 788 /* wd_timer2 */
 789 static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
 790         &omap2420_l4_wkup__wd_timer2,
 791 };
 792
 793 static struct omap_hwmod omap2420_wd_timer2_hwmod = {
 794         .name           = "wd_timer2",
 795         .class          = &omap2420_wd_timer_hwmod_class,
 796         .main_clk       = "mpu_wdt_fck",
 797         .prcm           = {
 798                 .omap2 = {
 799                         .prcm_reg_id = 1,
 800                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 801                         .module_offs = WKUP_MOD,
 802                         .idlest_reg_id = 1,
 803                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 804                 },
 805         },
 806         .slaves         = omap2420_wd_timer2_slaves,
 807         .slaves_cnt     = ARRAY_SIZE(omap2420_wd_timer2_slaves),
 808         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 809 };
 810
 811 /* UART */
 812
 813 static struct omap_hwmod_class_sysconfig uart_sysc = {
 814         .rev_offs       = 0x50,
 815         .sysc_offs      = 0x54,
 816         .syss_offs      = 0x58,
 817         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
 818                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 819                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 820         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 821         .sysc_fields    = &omap_hwmod_sysc_type1,
 822 };
 823
 824 static struct omap_hwmod_class uart_class = {
 825         .name = "uart",
 826         .sysc = &uart_sysc,
 827 };
 828
 829 /* UART1 */
 830
 831 static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
 832         { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
 833         { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
 834 };
 835
 836 static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
 837         &omap2_l4_core__uart1,
 838 };
 839
 840 static struct omap_hwmod omap2420_uart1_hwmod = {
 841         .name           = "uart1",
 842         .mpu_irqs       = omap2_uart1_mpu_irqs,
 843         .sdma_reqs      = uart1_sdma_reqs,
 844         .sdma_reqs_cnt  = ARRAY_SIZE(uart1_sdma_reqs),
 845         .main_clk       = "uart1_fck",
 846         .prcm           = {
 847                 .omap2 = {
 848                         .module_offs = CORE_MOD,
 849                         .prcm_reg_id = 1,
 850                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 851                         .idlest_reg_id = 1,
 852                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 853                 },
 854         },
 855         .slaves         = omap2420_uart1_slaves,
 856         .slaves_cnt     = ARRAY_SIZE(omap2420_uart1_slaves),
 857         .class          = &uart_class,
 858         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 859 };
 860
 861 /* UART2 */
 862
 863 static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
 864         { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
 865         { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
 866 };
 867
 868 static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
 869         &omap2_l4_core__uart2,
 870 };
 871
 872 static struct omap_hwmod omap2420_uart2_hwmod = {
 873         .name           = "uart2",
 874         .mpu_irqs       = omap2_uart2_mpu_irqs,
 875         .sdma_reqs      = uart2_sdma_reqs,
 876         .sdma_reqs_cnt  = ARRAY_SIZE(uart2_sdma_reqs),
 877         .main_clk       = "uart2_fck",
 878         .prcm           = {
 879                 .omap2 = {
 880                         .module_offs = CORE_MOD,
 881                         .prcm_reg_id = 1,
 882                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 883                         .idlest_reg_id = 1,
 884                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 885                 },
 886         },
 887         .slaves         = omap2420_uart2_slaves,
 888         .slaves_cnt     = ARRAY_SIZE(omap2420_uart2_slaves),
 889         .class          = &uart_class,
 890         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 891 };
 892
 893 /* UART3 */
 894
 895 static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
 896         { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
 897         { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
 898 };
 899
 900 static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
 901         &omap2_l4_core__uart3,
 902 };
 903
 904 static struct omap_hwmod omap2420_uart3_hwmod = {
 905         .name           = "uart3",
 906         .mpu_irqs       = omap2_uart3_mpu_irqs,
 907         .sdma_reqs      = uart3_sdma_reqs,
 908         .sdma_reqs_cnt  = ARRAY_SIZE(uart3_sdma_reqs),
 909         .main_clk       = "uart3_fck",
 910         .prcm           = {
 911                 .omap2 = {
 912                         .module_offs = CORE_MOD,
 913                         .prcm_reg_id = 2,
 914                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 915                         .idlest_reg_id = 2,
 916                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 917                 },
 918         },
 919         .slaves         = omap2420_uart3_slaves,
 920         .slaves_cnt     = ARRAY_SIZE(omap2420_uart3_slaves),
 921         .class          = &uart_class,
 922         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 923 };
 924
 925 /*
 926  * 'dss' class
 927  * display sub-system
 928  */
 929
 930 static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
 931         .rev_offs       = 0x0000,
 932         .sysc_offs      = 0x0010,
 933         .syss_offs      = 0x0014,
 934         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 935         .sysc_fields    = &omap_hwmod_sysc_type1,
 936 };
 937
 938 static struct omap_hwmod_class omap2420_dss_hwmod_class = {
 939         .name = "dss",
 940         .sysc = &omap2420_dss_sysc,
 941 };
 942
 943 static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
 944         { .name = "dispc", .dma_req = 5 },
 945 };
 946
 947 /* dss */
 948 /* dss master ports */
 949 static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
 950         &omap2420_dss__l3,
 951 };
 952
 953 /* l4_core -> dss */
 954 static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
 955         .master         = &omap2420_l4_core_hwmod,
 956         .slave          = &omap2420_dss_core_hwmod,
 957         .clk            = "dss_ick",
 958         .addr           = omap2_dss_addrs,
 959         .fw = {
 960                 .omap2 = {
 961                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
 962                         .flags  = OMAP_FIREWALL_L4,
 963                 }
 964         },
 965         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 966 };
 967
 968 /* dss slave ports */
 969 static struct omap_hwmod_ocp_if *omap2420_dss_slaves[] = {
 970         &omap2420_l4_core__dss,
 971 };
 972
 973 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 974         { .role = "tv_clk", .clk = "dss_54m_fck" },
 975         { .role = "sys_clk", .clk = "dss2_fck" },
 976 };
 977
 978 static struct omap_hwmod omap2420_dss_core_hwmod = {
 979         .name           = "dss_core",
 980         .class          = &omap2420_dss_hwmod_class,
 981         .main_clk       = "dss1_fck", /* instead of dss_fck */
 982         .sdma_reqs      = omap2420_dss_sdma_chs,
 983         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_dss_sdma_chs),
 984         .prcm           = {
 985                 .omap2 = {
 986                         .prcm_reg_id = 1,
 987                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 988                         .module_offs = CORE_MOD,
 989                         .idlest_reg_id = 1,
 990                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 991                 },
 992         },
 993         .opt_clks       = dss_opt_clks,
 994         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 995         .slaves         = omap2420_dss_slaves,
 996         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_slaves),
 997         .masters        = omap2420_dss_masters,
 998         .masters_cnt    = ARRAY_SIZE(omap2420_dss_masters),
 999         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1000         .flags          = HWMOD_NO_IDLEST,
1001 };
1002
1003 /*
1004  * 'dispc' class
1005  * display controller
1006  */
1007
1008 static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
1009         .rev_offs       = 0x0000,
1010         .sysc_offs      = 0x0010,
1011         .syss_offs      = 0x0014,
1012         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
1013                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1014         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1015                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1016         .sysc_fields    = &omap_hwmod_sysc_type1,
1017 };
1018
1019 static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
1020         .name = "dispc",
1021         .sysc = &omap2420_dispc_sysc,
1022 };
1023
1024 /* l4_core -> dss_dispc */
1025 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
1026         .master         = &omap2420_l4_core_hwmod,
1027         .slave          = &omap2420_dss_dispc_hwmod,
1028         .clk            = "dss_ick",
1029         .addr           = omap2_dss_dispc_addrs,
1030         .fw = {
1031                 .omap2 = {
1032                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
1033                         .flags  = OMAP_FIREWALL_L4,
1034                 }
1035         },
1036         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1037 };
1038
1039 /* dss_dispc slave ports */
1040 static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
1041         &omap2420_l4_core__dss_dispc,
1042 };
1043
1044 static struct omap_hwmod omap2420_dss_dispc_hwmod = {
1045         .name           = "dss_dispc",
1046         .class          = &omap2420_dispc_hwmod_class,
1047         .mpu_irqs       = omap2_dispc_irqs,
1048         .main_clk       = "dss1_fck",
1049         .prcm           = {
1050                 .omap2 = {
1051                         .prcm_reg_id = 1,
1052                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1053                         .module_offs = CORE_MOD,
1054                         .idlest_reg_id = 1,
1055                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
1056                 },
1057         },
1058         .slaves         = omap2420_dss_dispc_slaves,
1059         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_dispc_slaves),
1060         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1061         .flags          = HWMOD_NO_IDLEST,
1062 };
1063
1064 /*
1065  * 'rfbi' class
1066  * remote frame buffer interface
1067  */
1068
1069 static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
1070         .rev_offs       = 0x0000,
1071         .sysc_offs      = 0x0010,
1072         .syss_offs      = 0x0014,
1073         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1074                            SYSC_HAS_AUTOIDLE),
1075         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1076         .sysc_fields    = &omap_hwmod_sysc_type1,
1077 };
1078
1079 static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
1080         .name = "rfbi",
1081         .sysc = &omap2420_rfbi_sysc,
1082 };
1083
1084 /* l4_core -> dss_rfbi */
1085 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
1086         .master         = &omap2420_l4_core_hwmod,
1087         .slave          = &omap2420_dss_rfbi_hwmod,
1088         .clk            = "dss_ick",
1089         .addr           = omap2_dss_rfbi_addrs,
1090         .fw = {
1091                 .omap2 = {
1092                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
1093                         .flags  = OMAP_FIREWALL_L4,
1094                 }
1095         },
1096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1097 };
1098
1099 /* dss_rfbi slave ports */
1100 static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
1101         &omap2420_l4_core__dss_rfbi,
1102 };
1103
1104 static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
1105         .name           = "dss_rfbi",
1106         .class          = &omap2420_rfbi_hwmod_class,
1107         .main_clk       = "dss1_fck",
1108         .prcm           = {
1109                 .omap2 = {
1110                         .prcm_reg_id = 1,
1111                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1112                         .module_offs = CORE_MOD,
1113                 },
1114         },
1115         .slaves         = omap2420_dss_rfbi_slaves,
1116         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_rfbi_slaves),
1117         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1118         .flags          = HWMOD_NO_IDLEST,
1119 };
1120
1121 /*
1122  * 'venc' class
1123  * video encoder
1124  */
1125
1126 static struct omap_hwmod_class omap2420_venc_hwmod_class = {
1127         .name = "venc",
1128 };
1129
1130 /* l4_core -> dss_venc */
1131 static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
1132         .master         = &omap2420_l4_core_hwmod,
1133         .slave          = &omap2420_dss_venc_hwmod,
1134         .clk            = "dss_54m_fck",
1135         .addr           = omap2_dss_venc_addrs,
1136         .fw = {
1137                 .omap2 = {
1138                         .l4_fw_region  = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
1139                         .flags  = OMAP_FIREWALL_L4,
1140                 }
1141         },
1142         .flags          = OCPIF_SWSUP_IDLE,
1143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1144 };
1145
1146 /* dss_venc slave ports */
1147 static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
1148         &omap2420_l4_core__dss_venc,
1149 };
1150
1151 static struct omap_hwmod omap2420_dss_venc_hwmod = {
1152         .name           = "dss_venc",
1153         .class          = &omap2420_venc_hwmod_class,
1154         .main_clk       = "dss1_fck",
1155         .prcm           = {
1156                 .omap2 = {
1157                         .prcm_reg_id = 1,
1158                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
1159                         .module_offs = CORE_MOD,
1160                 },
1161         },
1162         .slaves         = omap2420_dss_venc_slaves,
1163         .slaves_cnt     = ARRAY_SIZE(omap2420_dss_venc_slaves),
1164         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1165         .flags          = HWMOD_NO_IDLEST,
1166 };
1167
1168 /* I2C common */
1169 static struct omap_hwmod_class_sysconfig i2c_sysc = {
1170         .rev_offs       = 0x00,
1171         .sysc_offs      = 0x20,
1172         .syss_offs      = 0x10,
1173         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1174         .sysc_fields    = &omap_hwmod_sysc_type1,
1175 };
1176
1177 static struct omap_hwmod_class i2c_class = {
1178         .name           = "i2c",
1179         .sysc           = &i2c_sysc,
1180 };
1181
1182 static struct omap_i2c_dev_attr i2c_dev_attr;
1183
1184 /* I2C1 */
1185
1186 static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
1187         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
1188         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
1189 };
1190
1191 static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
1192         &omap2420_l4_core__i2c1,
1193 };
1194
1195 static struct omap_hwmod omap2420_i2c1_hwmod = {
1196         .name           = "i2c1",
1197         .mpu_irqs       = omap2_i2c1_mpu_irqs,
1198         .sdma_reqs      = i2c1_sdma_reqs,
1199         .sdma_reqs_cnt  = ARRAY_SIZE(i2c1_sdma_reqs),
1200         .main_clk       = "i2c1_fck",
1201         .prcm           = {
1202                 .omap2 = {
1203                         .module_offs = CORE_MOD,
1204                         .prcm_reg_id = 1,
1205                         .module_bit = OMAP2420_EN_I2C1_SHIFT,
1206                         .idlest_reg_id = 1,
1207                         .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
1208                 },
1209         },
1210         .slaves         = omap2420_i2c1_slaves,
1211         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c1_slaves),
1212         .class          = &i2c_class,
1213         .dev_attr       = &i2c_dev_attr,
1214         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1215         .flags          = HWMOD_16BIT_REG,
1216 };
1217
1218 /* I2C2 */
1219
1220 static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
1221         { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
1222         { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
1223 };
1224
1225 static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
1226         &omap2420_l4_core__i2c2,
1227 };
1228
1229 static struct omap_hwmod omap2420_i2c2_hwmod = {
1230         .name           = "i2c2",
1231         .mpu_irqs       = omap2_i2c2_mpu_irqs,
1232         .sdma_reqs      = i2c2_sdma_reqs,
1233         .sdma_reqs_cnt  = ARRAY_SIZE(i2c2_sdma_reqs),
1234         .main_clk       = "i2c2_fck",
1235         .prcm           = {
1236                 .omap2 = {
1237                         .module_offs = CORE_MOD,
1238                         .prcm_reg_id = 1,
1239                         .module_bit = OMAP2420_EN_I2C2_SHIFT,
1240                         .idlest_reg_id = 1,
1241                         .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
1242                 },
1243         },
1244         .slaves         = omap2420_i2c2_slaves,
1245         .slaves_cnt     = ARRAY_SIZE(omap2420_i2c2_slaves),
1246         .class          = &i2c_class,
1247         .dev_attr       = &i2c_dev_attr,
1248         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1249         .flags          = HWMOD_16BIT_REG,
1250 };
1251
1252 /* l4_wkup -> gpio1 */
1253 static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
1254         {
1255                 .pa_start       = 0x48018000,
1256                 .pa_end         = 0x480181ff,
1257                 .flags          = ADDR_TYPE_RT
1258         },
1259         { }
1260 };
1261
1262 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
1263         .master         = &omap2420_l4_wkup_hwmod,
1264         .slave          = &omap2420_gpio1_hwmod,
1265         .clk            = "gpios_ick",
1266         .addr           = omap2420_gpio1_addr_space,
1267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1268 };
1269
1270 /* l4_wkup -> gpio2 */
1271 static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
1272         {
1273                 .pa_start       = 0x4801a000,
1274                 .pa_end         = 0x4801a1ff,
1275                 .flags          = ADDR_TYPE_RT
1276         },
1277         { }
1278 };
1279
1280 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
1281         .master         = &omap2420_l4_wkup_hwmod,
1282         .slave          = &omap2420_gpio2_hwmod,
1283         .clk            = "gpios_ick",
1284         .addr           = omap2420_gpio2_addr_space,
1285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1286 };
1287
1288 /* l4_wkup -> gpio3 */
1289 static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
1290         {
1291                 .pa_start       = 0x4801c000,
1292                 .pa_end         = 0x4801c1ff,
1293                 .flags          = ADDR_TYPE_RT
1294         },
1295         { }
1296 };
1297
1298 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
1299         .master         = &omap2420_l4_wkup_hwmod,
1300         .slave          = &omap2420_gpio3_hwmod,
1301         .clk            = "gpios_ick",
1302         .addr           = omap2420_gpio3_addr_space,
1303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1304 };
1305
1306 /* l4_wkup -> gpio4 */
1307 static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
1308         {
1309                 .pa_start       = 0x4801e000,
1310                 .pa_end         = 0x4801e1ff,
1311                 .flags          = ADDR_TYPE_RT
1312         },
1313         { }
1314 };
1315
1316 static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
1317         .master         = &omap2420_l4_wkup_hwmod,
1318         .slave          = &omap2420_gpio4_hwmod,
1319         .clk            = "gpios_ick",
1320         .addr           = omap2420_gpio4_addr_space,
1321         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1322 };
1323
1324 /* gpio dev_attr */
1325 static struct omap_gpio_dev_attr gpio_dev_attr = {
1326         .bank_width = 32,
1327         .dbck_flag = false,
1328 };
1329
1330 static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
1331         .rev_offs       = 0x0000,
1332         .sysc_offs      = 0x0010,
1333         .syss_offs      = 0x0014,
1334         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1335                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1336                            SYSS_HAS_RESET_STATUS),
1337         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1338         .sysc_fields    = &omap_hwmod_sysc_type1,
1339 };
1340
1341 /*
1342  * 'gpio' class
1343  * general purpose io module
1344  */
1345 static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
1346         .name = "gpio",
1347         .sysc = &omap242x_gpio_sysc,
1348         .rev = 0,
1349 };
1350
1351 /* gpio1 */
1352 static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
1353         &omap2420_l4_wkup__gpio1,
1354 };
1355
1356 static struct omap_hwmod omap2420_gpio1_hwmod = {
1357         .name           = "gpio1",
1358         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1359         .mpu_irqs       = omap2_gpio1_irqs,
1360         .main_clk       = "gpios_fck",
1361         .prcm           = {
1362                 .omap2 = {
1363                         .prcm_reg_id = 1,
1364                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1365                         .module_offs = WKUP_MOD,
1366                         .idlest_reg_id = 1,
1367                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1368                 },
1369         },
1370         .slaves         = omap2420_gpio1_slaves,
1371         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio1_slaves),
1372         .class          = &omap242x_gpio_hwmod_class,
1373         .dev_attr       = &gpio_dev_attr,
1374         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1375 };
1376
1377 /* gpio2 */
1378 static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
1379         &omap2420_l4_wkup__gpio2,
1380 };
1381
1382 static struct omap_hwmod omap2420_gpio2_hwmod = {
1383         .name           = "gpio2",
1384         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1385         .mpu_irqs       = omap2_gpio2_irqs,
1386         .main_clk       = "gpios_fck",
1387         .prcm           = {
1388                 .omap2 = {
1389                         .prcm_reg_id = 1,
1390                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1391                         .module_offs = WKUP_MOD,
1392                         .idlest_reg_id = 1,
1393                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1394                 },
1395         },
1396         .slaves         = omap2420_gpio2_slaves,
1397         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio2_slaves),
1398         .class          = &omap242x_gpio_hwmod_class,
1399         .dev_attr       = &gpio_dev_attr,
1400         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1401 };
1402
1403 /* gpio3 */
1404 static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
1405         &omap2420_l4_wkup__gpio3,
1406 };
1407
1408 static struct omap_hwmod omap2420_gpio3_hwmod = {
1409         .name           = "gpio3",
1410         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1411         .mpu_irqs       = omap2_gpio3_irqs,
1412         .main_clk       = "gpios_fck",
1413         .prcm           = {
1414                 .omap2 = {
1415                         .prcm_reg_id = 1,
1416                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1417                         .module_offs = WKUP_MOD,
1418                         .idlest_reg_id = 1,
1419                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1420                 },
1421         },
1422         .slaves         = omap2420_gpio3_slaves,
1423         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio3_slaves),
1424         .class          = &omap242x_gpio_hwmod_class,
1425         .dev_attr       = &gpio_dev_attr,
1426         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1427 };
1428
1429 /* gpio4 */
1430 static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
1431         &omap2420_l4_wkup__gpio4,
1432 };
1433
1434 static struct omap_hwmod omap2420_gpio4_hwmod = {
1435         .name           = "gpio4",
1436         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1437         .mpu_irqs       = omap2_gpio4_irqs,
1438         .main_clk       = "gpios_fck",
1439         .prcm           = {
1440                 .omap2 = {
1441                         .prcm_reg_id = 1,
1442                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
1443                         .module_offs = WKUP_MOD,
1444                         .idlest_reg_id = 1,
1445                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
1446                 },
1447         },
1448         .slaves         = omap2420_gpio4_slaves,
1449         .slaves_cnt     = ARRAY_SIZE(omap2420_gpio4_slaves),
1450         .class          = &omap242x_gpio_hwmod_class,
1451         .dev_attr       = &gpio_dev_attr,
1452         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1453 };
1454
1455 /* system dma */
1456 static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
1457         .rev_offs       = 0x0000,
1458         .sysc_offs      = 0x002c,
1459         .syss_offs      = 0x0028,
1460         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
1461                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
1462                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1463         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1464         .sysc_fields    = &omap_hwmod_sysc_type1,
1465 };
1466
1467 static struct omap_hwmod_class omap2420_dma_hwmod_class = {
1468         .name = "dma",
1469         .sysc = &omap2420_dma_sysc,
1470 };
1471
1472 /* dma attributes */
1473 static struct omap_dma_dev_attr dma_dev_attr = {
1474         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1475                                                 IS_CSSA_32 | IS_CDSA_32,
1476         .lch_count = 32,
1477 };
1478
1479 /* dma_system -> L3 */
1480 static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
1481         .master         = &omap2420_dma_system_hwmod,
1482         .slave          = &omap2420_l3_main_hwmod,
1483         .clk            = "core_l3_ck",
1484         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1485 };
1486
1487 /* dma_system master ports */
1488 static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
1489         &omap2420_dma_system__l3,
1490 };
1491
1492 /* l4_core -> dma_system */
1493 static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
1494         .master         = &omap2420_l4_core_hwmod,
1495         .slave          = &omap2420_dma_system_hwmod,
1496         .clk            = "sdma_ick",
1497         .addr           = omap2_dma_system_addrs,
1498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1499 };
1500
1501 /* dma_system slave ports */
1502 static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
1503         &omap2420_l4_core__dma_system,
1504 };
1505
1506 static struct omap_hwmod omap2420_dma_system_hwmod = {
1507         .name           = "dma",
1508         .class          = &omap2420_dma_hwmod_class,
1509         .mpu_irqs       = omap2_dma_system_irqs,
1510         .main_clk       = "core_l3_ck",
1511         .slaves         = omap2420_dma_system_slaves,
1512         .slaves_cnt     = ARRAY_SIZE(omap2420_dma_system_slaves),
1513         .masters        = omap2420_dma_system_masters,
1514         .masters_cnt    = ARRAY_SIZE(omap2420_dma_system_masters),
1515         .dev_attr       = &dma_dev_attr,
1516         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1517         .flags          = HWMOD_NO_IDLEST,
1518 };
1519
1520 /*
1521  * 'mailbox' class
1522  * mailbox module allowing communication between the on-chip processors
1523  * using a queued mailbox-interrupt mechanism.
1524  */
1525
1526 static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1527         .rev_offs       = 0x000,
1528         .sysc_offs      = 0x010,
1529         .syss_offs      = 0x014,
1530         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1531                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1532         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1533         .sysc_fields    = &omap_hwmod_sysc_type1,
1534 };
1535
1536 static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1537         .name = "mailbox",
1538         .sysc = &omap2420_mailbox_sysc,
1539 };
1540
1541 /* mailbox */
1542 static struct omap_hwmod omap2420_mailbox_hwmod;
1543 static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1544         { .name = "dsp", .irq = 26 },
1545         { .name = "iva", .irq = 34 },
1546         { .irq = -1 }
1547 };
1548
1549 /* l4_core -> mailbox */
1550 static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1551         .master         = &omap2420_l4_core_hwmod,
1552         .slave          = &omap2420_mailbox_hwmod,
1553         .addr           = omap2_mailbox_addrs,
1554         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1555 };
1556
1557 /* mailbox slave ports */
1558 static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1559         &omap2420_l4_core__mailbox,
1560 };
1561
1562 static struct omap_hwmod omap2420_mailbox_hwmod = {
1563         .name           = "mailbox",
1564         .class          = &omap2420_mailbox_hwmod_class,
1565         .mpu_irqs       = omap2420_mailbox_irqs,
1566         .main_clk       = "mailboxes_ick",
1567         .prcm           = {
1568                 .omap2 = {
1569                         .prcm_reg_id = 1,
1570                         .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1571                         .module_offs = CORE_MOD,
1572                         .idlest_reg_id = 1,
1573                         .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1574                 },
1575         },
1576         .slaves         = omap2420_mailbox_slaves,
1577         .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
1578         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1579 };
1580
1581 /*
1582  * 'mcspi' class
1583  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1584  * bus
1585  */
1586
1587 static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
1588         .rev_offs       = 0x0000,
1589         .sysc_offs      = 0x0010,
1590         .syss_offs      = 0x0014,
1591         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1592                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1593                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1594         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1595         .sysc_fields    = &omap_hwmod_sysc_type1,
1596 };
1597
1598 static struct omap_hwmod_class omap2420_mcspi_class = {
1599         .name = "mcspi",
1600         .sysc = &omap2420_mcspi_sysc,
1601         .rev = OMAP2_MCSPI_REV,
1602 };
1603
1604 /* mcspi1 */
1605 static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
1606         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
1607         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
1608         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
1609         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
1610         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
1611         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
1612         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
1613         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
1614 };
1615
1616 static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
1617         &omap2420_l4_core__mcspi1,
1618 };
1619
1620 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1621         .num_chipselect = 4,
1622 };
1623
1624 static struct omap_hwmod omap2420_mcspi1_hwmod = {
1625         .name           = "mcspi1_hwmod",
1626         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1627         .sdma_reqs      = omap2420_mcspi1_sdma_reqs,
1628         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
1629         .main_clk       = "mcspi1_fck",
1630         .prcm           = {
1631                 .omap2 = {
1632                         .module_offs = CORE_MOD,
1633                         .prcm_reg_id = 1,
1634                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1635                         .idlest_reg_id = 1,
1636                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
1637                 },
1638         },
1639         .slaves         = omap2420_mcspi1_slaves,
1640         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi1_slaves),
1641         .class          = &omap2420_mcspi_class,
1642         .dev_attr       = &omap_mcspi1_dev_attr,
1643         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1644 };
1645
1646 /* mcspi2 */
1647 static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
1648         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
1649         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
1650         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
1651         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
1652 };
1653
1654 static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
1655         &omap2420_l4_core__mcspi2,
1656 };
1657
1658 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1659         .num_chipselect = 2,
1660 };
1661
1662 static struct omap_hwmod omap2420_mcspi2_hwmod = {
1663         .name           = "mcspi2_hwmod",
1664         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1665         .sdma_reqs      = omap2420_mcspi2_sdma_reqs,
1666         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
1667         .main_clk       = "mcspi2_fck",
1668         .prcm           = {
1669                 .omap2 = {
1670                         .module_offs = CORE_MOD,
1671                         .prcm_reg_id = 1,
1672                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1673                         .idlest_reg_id = 1,
1674                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
1675                 },
1676         },
1677         .slaves         = omap2420_mcspi2_slaves,
1678         .slaves_cnt     = ARRAY_SIZE(omap2420_mcspi2_slaves),
1679         .class          = &omap2420_mcspi_class,
1680         .dev_attr       = &omap_mcspi2_dev_attr,
1681         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1682 };
1683
1684 /*
1685  * 'mcbsp' class
1686  * multi channel buffered serial port controller
1687  */
1688
1689 static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
1690         .name = "mcbsp",
1691 };
1692
1693 /* mcbsp1 */
1694 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
1695         { .name = "tx", .irq = 59 },
1696         { .name = "rx", .irq = 60 },
1697         { .irq = -1 }
1698 };
1699
1700 static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
1701         { .name = "rx", .dma_req = 32 },
1702         { .name = "tx", .dma_req = 31 },
1703 };
1704
1705 /* l4_core -> mcbsp1 */
1706 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
1707         .master         = &omap2420_l4_core_hwmod,
1708         .slave          = &omap2420_mcbsp1_hwmod,
1709         .clk            = "mcbsp1_ick",
1710         .addr           = omap2_mcbsp1_addrs,
1711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1712 };
1713
1714 /* mcbsp1 slave ports */
1715 static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
1716         &omap2420_l4_core__mcbsp1,
1717 };
1718
1719 static struct omap_hwmod omap2420_mcbsp1_hwmod = {
1720         .name           = "mcbsp1",
1721         .class          = &omap2420_mcbsp_hwmod_class,
1722         .mpu_irqs       = omap2420_mcbsp1_irqs,
1723         .sdma_reqs      = omap2420_mcbsp1_sdma_chs,
1724         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
1725         .main_clk       = "mcbsp1_fck",
1726         .prcm           = {
1727                 .omap2 = {
1728                         .prcm_reg_id = 1,
1729                         .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1730                         .module_offs = CORE_MOD,
1731                         .idlest_reg_id = 1,
1732                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
1733                 },
1734         },
1735         .slaves         = omap2420_mcbsp1_slaves,
1736         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
1737         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1738 };
1739
1740 /* mcbsp2 */
1741 static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
1742         { .name = "tx", .irq = 62 },
1743         { .name = "rx", .irq = 63 },
1744         { .irq = -1 }
1745 };
1746
1747 static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
1748         { .name = "rx", .dma_req = 34 },
1749         { .name = "tx", .dma_req = 33 },
1750 };
1751
1752 /* l4_core -> mcbsp2 */
1753 static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
1754         .master         = &omap2420_l4_core_hwmod,
1755         .slave          = &omap2420_mcbsp2_hwmod,
1756         .clk            = "mcbsp2_ick",
1757         .addr           = omap2xxx_mcbsp2_addrs,
1758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1759 };
1760
1761 /* mcbsp2 slave ports */
1762 static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
1763         &omap2420_l4_core__mcbsp2,
1764 };
1765
1766 static struct omap_hwmod omap2420_mcbsp2_hwmod = {
1767         .name           = "mcbsp2",
1768         .class          = &omap2420_mcbsp_hwmod_class,
1769         .mpu_irqs       = omap2420_mcbsp2_irqs,
1770         .sdma_reqs      = omap2420_mcbsp2_sdma_chs,
1771         .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
1772         .main_clk       = "mcbsp2_fck",
1773         .prcm           = {
1774                 .omap2 = {
1775                         .prcm_reg_id = 1,
1776                         .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1777                         .module_offs = CORE_MOD,
1778                         .idlest_reg_id = 1,
1779                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
1780                 },
1781         },
1782         .slaves         = omap2420_mcbsp2_slaves,
1783         .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
1784         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1785 };
1786
1787 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1788         &omap2420_l3_main_hwmod,
1789         &omap2420_l4_core_hwmod,
1790         &omap2420_l4_wkup_hwmod,
1791         &omap2420_mpu_hwmod,
1792         &omap2420_iva_hwmod,
1793
1794         &omap2420_timer1_hwmod,
1795         &omap2420_timer2_hwmod,
1796         &omap2420_timer3_hwmod,
1797         &omap2420_timer4_hwmod,
1798         &omap2420_timer5_hwmod,
1799         &omap2420_timer6_hwmod,
1800         &omap2420_timer7_hwmod,
1801         &omap2420_timer8_hwmod,
1802         &omap2420_timer9_hwmod,
1803         &omap2420_timer10_hwmod,
1804         &omap2420_timer11_hwmod,
1805         &omap2420_timer12_hwmod,
1806
1807         &omap2420_wd_timer2_hwmod,
1808         &omap2420_uart1_hwmod,
1809         &omap2420_uart2_hwmod,
1810         &omap2420_uart3_hwmod,
1811         /* dss class */
1812         &omap2420_dss_core_hwmod,
1813         &omap2420_dss_dispc_hwmod,
1814         &omap2420_dss_rfbi_hwmod,
1815         &omap2420_dss_venc_hwmod,
1816         /* i2c class */
1817         &omap2420_i2c1_hwmod,
1818         &omap2420_i2c2_hwmod,
1819
1820         /* gpio class */
1821         &omap2420_gpio1_hwmod,
1822         &omap2420_gpio2_hwmod,
1823         &omap2420_gpio3_hwmod,
1824         &omap2420_gpio4_hwmod,
1825
1826         /* dma_system class*/
1827         &omap2420_dma_system_hwmod,
1828
1829         /* mailbox class */
1830         &omap2420_mailbox_hwmod,
1831
1832         /* mcbsp class */
1833         &omap2420_mcbsp1_hwmod,
1834         &omap2420_mcbsp2_hwmod,
1835
1836         /* mcspi class */
1837         &omap2420_mcspi1_hwmod,
1838         &omap2420_mcspi2_hwmod,
1839         NULL,
1840 };
1841
1842 int __init omap2420_hwmod_init(void)
1843 {
1844         return omap_hwmod_register(omap2420_hwmods);
1845 }