2 * OMAP4 SMP source file. It contains platform specific fucntions
3 * needed for the linux smp kernel.
5 * Copyright (C) 2009 Texas Instruments, Inc.
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/smp.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/gic.h>
25 #include <asm/smp_scu.h>
26 #include <mach/hardware.h>
27 #include <mach/omap4-common.h>
29 /* SCU base address */
30 static void __iomem *scu_base;
32 static DEFINE_SPINLOCK(boot_lock);
34 void __cpuinit platform_secondary_init(unsigned int cpu)
37 * If any interrupts are already enabled for the primary
38 * core (e.g. timer irq), then they will not have been enabled
41 gic_secondary_init(0);
44 * Synchronise with the boot thread.
46 spin_lock(&boot_lock);
47 spin_unlock(&boot_lock);
50 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
53 * Set synchronisation state between this boot processor
54 * and the secondary one
56 spin_lock(&boot_lock);
59 * Update the AuxCoreBoot0 with boot state for secondary core.
60 * omap_secondary_startup() routine will hold the secondary core till
61 * the AuxCoreBoot1 register is updated with cpu state
62 * A barrier is added to ensure that write buffer is drained
64 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
67 gic_raise_softirq(cpumask_of(cpu), 1);
70 * Now the secondary core is starting up let it run its
71 * calibrations, then wait for it to finish
73 spin_unlock(&boot_lock);
78 static void __init wakeup_secondary(void)
81 * Write the address of secondary startup routine into the
82 * AuxCoreBoot1 where ROM code will jump and start executing
83 * on secondary core once out of WFE
84 * A barrier is added to ensure that write buffer is drained
86 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
90 * Send a 'sev' to wake the secondary core from WFE.
91 * Drain the outstanding writes to memory
98 * Initialise the CPU possible map early - this describes the CPUs
99 * which may be present or become present in the system.
101 void __init smp_init_cpus(void)
103 unsigned int i, ncores;
106 * Currently we can't call ioremap here because
107 * SoC detection won't work until after init_early.
109 scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
112 ncores = scu_get_core_count(scu_base);
115 if (ncores > nr_cpu_ids) {
116 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
121 for (i = 0; i < ncores; i++)
122 set_cpu_possible(i, true);
124 set_smp_cross_call(gic_raise_softirq);
127 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
131 * Initialise the SCU and wake up the secondary core using
132 * wakeup_secondary().
134 scu_enable(scu_base);