2 * linux/arch/arm/mach-omap2/mux.c
4 * OMAP2 and OMAP3 pin multiplexing configurations
6 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation
9 * Written by Tony Lindgren
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/ctype.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/uaccess.h>
37 #include <asm/system.h>
39 #include <plat/control.h>
44 #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */
45 #define OMAP_MUX_BASE_SZ 0x5ca
46 #define MUXABLE_GPIO_MODE3 BIT(0)
48 struct omap_mux_entry {
50 struct list_head node;
53 static unsigned long mux_phys;
54 static void __iomem *mux_base;
55 static u8 omap_mux_flags;
57 u16 omap_mux_read(u16 reg)
59 if (cpu_is_omap24xx())
60 return __raw_readb(mux_base + reg);
62 return __raw_readw(mux_base + reg);
65 void omap_mux_write(u16 val, u16 reg)
67 if (cpu_is_omap24xx())
68 __raw_writeb(val, mux_base + reg);
70 __raw_writew(val, mux_base + reg);
73 void omap_mux_write_array(struct omap_board_mux *board_mux)
75 while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) {
76 omap_mux_write(board_mux->value, board_mux->reg_offset);
81 #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX)
83 static struct omap_mux_cfg arch_mux_cfg;
85 /* NOTE: See mux.h for the enumeration */
87 static struct pin_config __initdata_or_module omap24xx_pins[] = {
89 * description mux mux pull pull debug
90 * offset mode ena type
94 MUX_CFG_24XX("M19_24XX_I2C1_SCL", 0x111, 0, 0, 0, 1)
95 MUX_CFG_24XX("L15_24XX_I2C1_SDA", 0x112, 0, 0, 0, 1)
96 MUX_CFG_24XX("J15_24XX_I2C2_SCL", 0x113, 0, 0, 1, 1)
97 MUX_CFG_24XX("H19_24XX_I2C2_SDA", 0x114, 0, 0, 0, 1)
99 /* Menelaus interrupt */
100 MUX_CFG_24XX("W19_24XX_SYS_NIRQ", 0x12c, 0, 1, 1, 1)
103 MUX_CFG_24XX("W14_24XX_SYS_CLKOUT", 0x137, 0, 1, 1, 1)
105 /* 24xx GPMC chipselects, wait pin monitoring */
106 MUX_CFG_24XX("E2_GPMC_NCS2", 0x08e, 0, 1, 1, 1)
107 MUX_CFG_24XX("L2_GPMC_NCS7", 0x093, 0, 1, 1, 1)
108 MUX_CFG_24XX("L3_GPMC_WAIT0", 0x09a, 0, 1, 1, 1)
109 MUX_CFG_24XX("N7_GPMC_WAIT1", 0x09b, 0, 1, 1, 1)
110 MUX_CFG_24XX("M1_GPMC_WAIT2", 0x09c, 0, 1, 1, 1)
111 MUX_CFG_24XX("P1_GPMC_WAIT3", 0x09d, 0, 1, 1, 1)
114 MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX", 0x124, 1, 1, 0, 1)
115 MUX_CFG_24XX("R14_24XX_MCBSP2_FSX", 0x125, 1, 1, 0, 1)
116 MUX_CFG_24XX("W15_24XX_MCBSP2_DR", 0x126, 1, 1, 0, 1)
117 MUX_CFG_24XX("V15_24XX_MCBSP2_DX", 0x127, 1, 1, 0, 1)
120 MUX_CFG_24XX("M21_242X_GPIO11", 0x0c9, 3, 1, 1, 1)
121 MUX_CFG_24XX("P21_242X_GPIO12", 0x0ca, 3, 0, 0, 1)
122 MUX_CFG_24XX("AA10_242X_GPIO13", 0x0e5, 3, 0, 0, 1)
123 MUX_CFG_24XX("AA6_242X_GPIO14", 0x0e6, 3, 0, 0, 1)
124 MUX_CFG_24XX("AA4_242X_GPIO15", 0x0e7, 3, 0, 0, 1)
125 MUX_CFG_24XX("Y11_242X_GPIO16", 0x0e8, 3, 0, 0, 1)
126 MUX_CFG_24XX("AA12_242X_GPIO17", 0x0e9, 3, 0, 0, 1)
127 MUX_CFG_24XX("AA8_242X_GPIO58", 0x0ea, 3, 0, 0, 1)
128 MUX_CFG_24XX("Y20_24XX_GPIO60", 0x12c, 3, 0, 0, 1)
129 MUX_CFG_24XX("W4__24XX_GPIO74", 0x0f2, 3, 0, 0, 1)
130 MUX_CFG_24XX("N15_24XX_GPIO85", 0x103, 3, 0, 0, 1)
131 MUX_CFG_24XX("M15_24XX_GPIO92", 0x10a, 3, 0, 0, 1)
132 MUX_CFG_24XX("P20_24XX_GPIO93", 0x10b, 3, 0, 0, 1)
133 MUX_CFG_24XX("P18_24XX_GPIO95", 0x10d, 3, 0, 0, 1)
134 MUX_CFG_24XX("M18_24XX_GPIO96", 0x10e, 3, 0, 0, 1)
135 MUX_CFG_24XX("L14_24XX_GPIO97", 0x10f, 3, 0, 0, 1)
136 MUX_CFG_24XX("J15_24XX_GPIO99", 0x113, 3, 1, 1, 1)
137 MUX_CFG_24XX("V14_24XX_GPIO117", 0x128, 3, 1, 0, 1)
138 MUX_CFG_24XX("P14_24XX_GPIO125", 0x140, 3, 1, 1, 1)
141 MUX_CFG_24XX("V4_242X_GPIO49", 0xd3, 3, 0, 0, 1)
142 MUX_CFG_24XX("W2_242X_GPIO50", 0xd4, 3, 0, 0, 1)
143 MUX_CFG_24XX("U4_242X_GPIO51", 0xd5, 3, 0, 0, 1)
144 MUX_CFG_24XX("V3_242X_GPIO52", 0xd6, 3, 0, 0, 1)
145 MUX_CFG_24XX("V2_242X_GPIO53", 0xd7, 3, 0, 0, 1)
146 MUX_CFG_24XX("V6_242X_GPIO53", 0xcf, 3, 0, 0, 1)
147 MUX_CFG_24XX("T4_242X_GPIO54", 0xd8, 3, 0, 0, 1)
148 MUX_CFG_24XX("Y4_242X_GPIO54", 0xd0, 3, 0, 0, 1)
149 MUX_CFG_24XX("T3_242X_GPIO55", 0xd9, 3, 0, 0, 1)
150 MUX_CFG_24XX("U2_242X_GPIO56", 0xda, 3, 0, 0, 1)
152 /* 24xx external DMA requests */
153 MUX_CFG_24XX("AA10_242X_DMAREQ0", 0x0e5, 2, 0, 0, 1)
154 MUX_CFG_24XX("AA6_242X_DMAREQ1", 0x0e6, 2, 0, 0, 1)
155 MUX_CFG_24XX("E4_242X_DMAREQ2", 0x074, 2, 0, 0, 1)
156 MUX_CFG_24XX("G4_242X_DMAREQ3", 0x073, 2, 0, 0, 1)
157 MUX_CFG_24XX("D3_242X_DMAREQ4", 0x072, 2, 0, 0, 1)
158 MUX_CFG_24XX("E3_242X_DMAREQ5", 0x071, 2, 0, 0, 1)
161 MUX_CFG_24XX("K15_24XX_UART3_TX", 0x118, 0, 0, 0, 1)
162 MUX_CFG_24XX("K14_24XX_UART3_RX", 0x119, 0, 0, 0, 1)
165 MUX_CFG_24XX("G19_24XX_MMC_CLKO", 0x0f3, 0, 0, 0, 1)
166 MUX_CFG_24XX("H18_24XX_MMC_CMD", 0x0f4, 0, 0, 0, 1)
167 MUX_CFG_24XX("F20_24XX_MMC_DAT0", 0x0f5, 0, 0, 0, 1)
168 MUX_CFG_24XX("H14_24XX_MMC_DAT1", 0x0f6, 0, 0, 0, 1)
169 MUX_CFG_24XX("E19_24XX_MMC_DAT2", 0x0f7, 0, 0, 0, 1)
170 MUX_CFG_24XX("D19_24XX_MMC_DAT3", 0x0f8, 0, 0, 0, 1)
171 MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0", 0x0f9, 0, 0, 0, 1)
172 MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1", 0x0fa, 0, 0, 0, 1)
173 MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2", 0x0fb, 0, 0, 0, 1)
174 MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3", 0x0fc, 0, 0, 0, 1)
175 MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR", 0x0fd, 0, 0, 0, 1)
176 MUX_CFG_24XX("H15_24XX_MMC_CLKI", 0x0fe, 0, 0, 0, 1)
179 MUX_CFG_24XX("J20_24XX_USB0_PUEN", 0x11d, 0, 0, 0, 1)
180 MUX_CFG_24XX("J19_24XX_USB0_VP", 0x11e, 0, 0, 0, 1)
181 MUX_CFG_24XX("K20_24XX_USB0_VM", 0x11f, 0, 0, 0, 1)
182 MUX_CFG_24XX("J18_24XX_USB0_RCV", 0x120, 0, 0, 0, 1)
183 MUX_CFG_24XX("K19_24XX_USB0_TXEN", 0x121, 0, 0, 0, 1)
184 MUX_CFG_24XX("J14_24XX_USB0_SE0", 0x122, 0, 0, 0, 1)
185 MUX_CFG_24XX("K18_24XX_USB0_DAT", 0x123, 0, 0, 0, 1)
187 MUX_CFG_24XX("N14_24XX_USB1_SE0", 0x0ed, 2, 0, 0, 1)
188 MUX_CFG_24XX("W12_24XX_USB1_SE0", 0x0dd, 3, 0, 0, 1)
189 MUX_CFG_24XX("P15_24XX_USB1_DAT", 0x0ee, 2, 0, 0, 1)
190 MUX_CFG_24XX("R13_24XX_USB1_DAT", 0x0e0, 3, 0, 0, 1)
191 MUX_CFG_24XX("W20_24XX_USB1_TXEN", 0x0ec, 2, 0, 0, 1)
192 MUX_CFG_24XX("P13_24XX_USB1_TXEN", 0x0df, 3, 0, 0, 1)
193 MUX_CFG_24XX("V19_24XX_USB1_RCV", 0x0eb, 2, 0, 0, 1)
194 MUX_CFG_24XX("V12_24XX_USB1_RCV", 0x0de, 3, 0, 0, 1)
196 MUX_CFG_24XX("AA10_24XX_USB2_SE0", 0x0e5, 2, 0, 0, 1)
197 MUX_CFG_24XX("Y11_24XX_USB2_DAT", 0x0e8, 2, 0, 0, 1)
198 MUX_CFG_24XX("AA12_24XX_USB2_TXEN", 0x0e9, 2, 0, 0, 1)
199 MUX_CFG_24XX("AA6_24XX_USB2_RCV", 0x0e6, 2, 0, 0, 1)
200 MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0", 0x0e7, 2, 0, 0, 1)
203 MUX_CFG_24XX("T19_24XX_KBR0", 0x106, 3, 1, 1, 1)
204 MUX_CFG_24XX("R19_24XX_KBR1", 0x107, 3, 1, 1, 1)
205 MUX_CFG_24XX("V18_24XX_KBR2", 0x139, 3, 1, 1, 1)
206 MUX_CFG_24XX("M21_24XX_KBR3", 0xc9, 3, 1, 1, 1)
207 MUX_CFG_24XX("E5__24XX_KBR4", 0x138, 3, 1, 1, 1)
208 MUX_CFG_24XX("M18_24XX_KBR5", 0x10e, 3, 1, 1, 1)
209 MUX_CFG_24XX("R20_24XX_KBC0", 0x108, 3, 0, 0, 1)
210 MUX_CFG_24XX("M14_24XX_KBC1", 0x109, 3, 0, 0, 1)
211 MUX_CFG_24XX("H19_24XX_KBC2", 0x114, 3, 0, 0, 1)
212 MUX_CFG_24XX("V17_24XX_KBC3", 0x135, 3, 0, 0, 1)
213 MUX_CFG_24XX("P21_24XX_KBC4", 0xca, 3, 0, 0, 1)
214 MUX_CFG_24XX("L14_24XX_KBC5", 0x10f, 3, 0, 0, 1)
215 MUX_CFG_24XX("N19_24XX_KBC6", 0x110, 3, 0, 0, 1)
217 /* 24xx Menelaus Keypad GPIO */
218 MUX_CFG_24XX("B3__24XX_KBR5", 0x30, 3, 1, 1, 1)
219 MUX_CFG_24XX("AA4_24XX_KBC2", 0xe7, 3, 0, 0, 1)
220 MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
223 MUX_CFG_24XX("AD9_2430_USB0_PUEN", 0x133, 4, 0, 0, 1)
224 MUX_CFG_24XX("Y11_2430_USB0_VP", 0x134, 4, 0, 0, 1)
225 MUX_CFG_24XX("AD7_2430_USB0_VM", 0x135, 4, 0, 0, 1)
226 MUX_CFG_24XX("AE7_2430_USB0_RCV", 0x136, 4, 0, 0, 1)
227 MUX_CFG_24XX("AD4_2430_USB0_TXEN", 0x137, 4, 0, 0, 1)
228 MUX_CFG_24XX("AF9_2430_USB0_SE0", 0x138, 4, 0, 0, 1)
229 MUX_CFG_24XX("AE6_2430_USB0_DAT", 0x139, 4, 0, 0, 1)
230 MUX_CFG_24XX("AD24_2430_USB1_SE0", 0x107, 2, 0, 0, 1)
231 MUX_CFG_24XX("AB24_2430_USB1_RCV", 0x108, 2, 0, 0, 1)
232 MUX_CFG_24XX("Y25_2430_USB1_TXEN", 0x109, 2, 0, 0, 1)
233 MUX_CFG_24XX("AA26_2430_USB1_DAT", 0x10A, 2, 0, 0, 1)
236 MUX_CFG_24XX("AD9_2430_USB0HS_DATA3", 0x133, 0, 0, 0, 1)
237 MUX_CFG_24XX("Y11_2430_USB0HS_DATA4", 0x134, 0, 0, 0, 1)
238 MUX_CFG_24XX("AD7_2430_USB0HS_DATA5", 0x135, 0, 0, 0, 1)
239 MUX_CFG_24XX("AE7_2430_USB0HS_DATA6", 0x136, 0, 0, 0, 1)
240 MUX_CFG_24XX("AD4_2430_USB0HS_DATA2", 0x137, 0, 0, 0, 1)
241 MUX_CFG_24XX("AF9_2430_USB0HS_DATA0", 0x138, 0, 0, 0, 1)
242 MUX_CFG_24XX("AE6_2430_USB0HS_DATA1", 0x139, 0, 0, 0, 1)
243 MUX_CFG_24XX("AE8_2430_USB0HS_CLK", 0x13A, 0, 0, 0, 1)
244 MUX_CFG_24XX("AD8_2430_USB0HS_DIR", 0x13B, 0, 0, 0, 1)
245 MUX_CFG_24XX("AE5_2430_USB0HS_STP", 0x13c, 0, 1, 1, 1)
246 MUX_CFG_24XX("AE9_2430_USB0HS_NXT", 0x13D, 0, 0, 0, 1)
247 MUX_CFG_24XX("AC7_2430_USB0HS_DATA7", 0x13E, 0, 0, 0, 1)
250 MUX_CFG_24XX("AD6_2430_MCBSP_CLKS", 0x011E, 0, 0, 0, 1)
252 MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR", 0x011A, 0, 0, 0, 1)
253 MUX_CFG_24XX("AD5_2430_MCBSP1_FSR", 0x011B, 0, 0, 0, 1)
254 MUX_CFG_24XX("AA1_2430_MCBSP1_DX", 0x011C, 0, 0, 0, 1)
255 MUX_CFG_24XX("AF3_2430_MCBSP1_DR", 0x011D, 0, 0, 0, 1)
256 MUX_CFG_24XX("AB3_2430_MCBSP1_FSX", 0x011F, 0, 0, 0, 1)
257 MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX", 0x0120, 0, 0, 0, 1)
259 MUX_CFG_24XX("AC10_2430_MCBSP2_FSX", 0x012E, 1, 0, 0, 1)
260 MUX_CFG_24XX("AD16_2430_MCBSP2_CLX", 0x012F, 1, 0, 0, 1)
261 MUX_CFG_24XX("AE13_2430_MCBSP2_DX", 0x0130, 1, 0, 0, 1)
262 MUX_CFG_24XX("AD13_2430_MCBSP2_DR", 0x0131, 1, 0, 0, 1)
263 MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E, 0, 0, 0, 1)
264 MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F, 0, 0, 0, 1)
265 MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF", 0x0130, 0, 0, 0, 1)
266 MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
268 MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX", 0x0103, 0, 0, 0, 1)
269 MUX_CFG_24XX("AE4_2430_MCBSP3_FSX", 0x0104, 0, 0, 0, 1)
270 MUX_CFG_24XX("AE2_2430_MCBSP3_DR", 0x0105, 0, 0, 0, 1)
271 MUX_CFG_24XX("AF4_2430_MCBSP3_DX", 0x0106, 0, 0, 0, 1)
273 MUX_CFG_24XX("N3_2430_MCBSP4_CLKX", 0x010B, 1, 0, 0, 1)
274 MUX_CFG_24XX("AD23_2430_MCBSP4_DR", 0x010C, 1, 0, 0, 1)
275 MUX_CFG_24XX("AB25_2430_MCBSP4_DX", 0x010D, 1, 0, 0, 1)
276 MUX_CFG_24XX("AC25_2430_MCBSP4_FSX", 0x010E, 1, 0, 0, 1)
278 MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX", 0x00ED, 1, 0, 0, 1)
279 MUX_CFG_24XX("AF12_2430_MCBSP5_FSX", 0x00ED, 1, 0, 0, 1)
280 MUX_CFG_24XX("K7_2430_MCBSP5_DX", 0x00EF, 1, 0, 0, 1)
281 MUX_CFG_24XX("M1_2430_MCBSP5_DR", 0x00F0, 1, 0, 0, 1)
284 MUX_CFG_24XX("Y18_2430_MCSPI1_CLK", 0x010F, 0, 0, 0, 1)
285 MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO", 0x0110, 0, 0, 0, 1)
286 MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI", 0x0111, 0, 0, 0, 1)
287 MUX_CFG_24XX("U1_2430_MCSPI1_CS0", 0x0112, 0, 0, 0, 1)
289 /* Touchscreen GPIO */
290 MUX_CFG_24XX("AF19_2430_GPIO_85", 0x0113, 3, 0, 0, 1)
294 #define OMAP24XX_PINS_SZ ARRAY_SIZE(omap24xx_pins)
296 #if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
298 static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
301 u8 warn = 0, debug = 0;
303 orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
305 #ifdef CONFIG_OMAP_MUX_DEBUG
308 warn = (orig != reg);
311 "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
312 cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
316 #define omap2_cfg_debug(x, y) do {} while (0)
319 static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
321 static DEFINE_SPINLOCK(mux_spin_lock);
325 spin_lock_irqsave(&mux_spin_lock, flags);
326 reg |= cfg->mask & 0x7;
328 reg |= OMAP2_PULL_ENA;
330 reg |= OMAP2_PULL_UP;
331 omap2_cfg_debug(cfg, reg);
332 omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
333 spin_unlock_irqrestore(&mux_spin_lock, flags);
338 int __init omap2_mux_init(void)
342 if (cpu_is_omap2420())
343 mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
344 else if (cpu_is_omap2430())
345 mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
349 mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
351 printk(KERN_ERR "mux: Could not ioremap\n");
355 if (cpu_is_omap24xx()) {
356 arch_mux_cfg.pins = omap24xx_pins;
357 arch_mux_cfg.size = OMAP24XX_PINS_SZ;
358 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
360 return omap_mux_register(&arch_mux_cfg);
367 int __init omap2_mux_init(void)
371 #endif /* CONFIG_OMAP_MUX */
373 /*----------------------------------------------------------------------------*/
375 #ifdef CONFIG_ARCH_OMAP2PLUS
376 static LIST_HEAD(muxmodes);
377 static DEFINE_MUTEX(muxmode_mutex);
379 #ifdef CONFIG_OMAP_MUX
381 static char *omap_mux_options;
383 int __init omap_mux_init_gpio(int gpio, int val)
385 struct omap_mux_entry *e;
391 list_for_each_entry(e, &muxmodes, node) {
392 struct omap_mux *m = &e->mux;
393 if (gpio == m->gpio) {
397 old_mode = omap_mux_read(m->reg_offset);
398 mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
399 if (omap_mux_flags & MUXABLE_GPIO_MODE3)
400 mux_mode |= OMAP_MUX_MODE3;
402 mux_mode |= OMAP_MUX_MODE4;
403 printk(KERN_DEBUG "mux: Setting signal "
404 "%s.gpio%i 0x%04x -> 0x%04x\n",
405 m->muxnames[0], gpio, old_mode, mux_mode);
406 omap_mux_write(mux_mode, m->reg_offset);
415 printk(KERN_ERR "mux: Multiple gpio paths for gpio%i\n", gpio);
419 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
424 int __init omap_mux_init_signal(char *muxname, int val)
426 struct omap_mux_entry *e;
427 char *m0_name = NULL, *mode_name = NULL;
430 mode_name = strchr(muxname, '.');
439 list_for_each_entry(e, &muxmodes, node) {
440 struct omap_mux *m = &e->mux;
441 char *m0_entry = m->muxnames[0];
444 if (m0_name && strcmp(m0_name, m0_entry))
447 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
448 char *mode_cur = m->muxnames[i];
453 if (!strcmp(mode_name, mode_cur)) {
457 old_mode = omap_mux_read(m->reg_offset);
459 printk(KERN_DEBUG "mux: Setting signal "
460 "%s.%s 0x%04x -> 0x%04x\n",
461 m0_entry, muxname, old_mode, mux_mode);
462 omap_mux_write(mux_mode, m->reg_offset);
472 printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n",
477 printk(KERN_ERR "mux: Could not set signal %s\n", muxname);
482 #ifdef CONFIG_DEBUG_FS
484 #define OMAP_MUX_MAX_NR_FLAGS 10
485 #define OMAP_MUX_TEST_FLAG(val, mask) \
486 if (((val) & (mask)) == (mask)) { \
491 /* REVISIT: Add checking for non-optimal mux settings */
492 static inline void omap_mux_decode(struct seq_file *s, u16 val)
494 char *flags[OMAP_MUX_MAX_NR_FLAGS];
495 char mode[sizeof("OMAP_MUX_MODE") + 1];
498 sprintf(mode, "OMAP_MUX_MODE%d", val & 0x7);
502 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_OFF_WAKEUPENABLE);
503 if (val & OMAP_OFF_EN) {
504 if (!(val & OMAP_OFFOUT_EN)) {
505 if (!(val & OMAP_OFF_PULL_UP)) {
506 OMAP_MUX_TEST_FLAG(val,
507 OMAP_PIN_OFF_INPUT_PULLDOWN);
509 OMAP_MUX_TEST_FLAG(val,
510 OMAP_PIN_OFF_INPUT_PULLUP);
513 if (!(val & OMAP_OFFOUT_VAL)) {
514 OMAP_MUX_TEST_FLAG(val,
515 OMAP_PIN_OFF_OUTPUT_LOW);
517 OMAP_MUX_TEST_FLAG(val,
518 OMAP_PIN_OFF_OUTPUT_HIGH);
523 if (val & OMAP_INPUT_EN) {
524 if (val & OMAP_PULL_ENA) {
525 if (!(val & OMAP_PULL_UP)) {
526 OMAP_MUX_TEST_FLAG(val,
527 OMAP_PIN_INPUT_PULLDOWN);
529 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT_PULLUP);
532 OMAP_MUX_TEST_FLAG(val, OMAP_PIN_INPUT);
536 flags[i] = "OMAP_PIN_OUTPUT";
540 seq_printf(s, "%s", flags[i]);
542 seq_printf(s, " | ");
546 #define OMAP_MUX_DEFNAME_LEN 16
548 static int omap_mux_dbg_board_show(struct seq_file *s, void *unused)
550 struct omap_mux_entry *e;
552 list_for_each_entry(e, &muxmodes, node) {
553 struct omap_mux *m = &e->mux;
554 char m0_def[OMAP_MUX_DEFNAME_LEN];
555 char *m0_name = m->muxnames[0];
562 /* REVISIT: Needs to be updated if mode0 names get longer */
563 for (i = 0; i < OMAP_MUX_DEFNAME_LEN; i++) {
564 if (m0_name[i] == '\0') {
565 m0_def[i] = m0_name[i];
568 m0_def[i] = toupper(m0_name[i]);
570 val = omap_mux_read(m->reg_offset);
571 mode = val & OMAP_MUX_MODE7;
573 seq_printf(s, "OMAP%i_MUX(%s, ",
574 cpu_is_omap34xx() ? 3 : 0, m0_def);
575 omap_mux_decode(s, val);
576 seq_printf(s, "),\n");
582 static int omap_mux_dbg_board_open(struct inode *inode, struct file *file)
584 return single_open(file, omap_mux_dbg_board_show, &inode->i_private);
587 static const struct file_operations omap_mux_dbg_board_fops = {
588 .open = omap_mux_dbg_board_open,
591 .release = single_release,
594 static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused)
596 struct omap_mux *m = s->private;
597 const char *none = "NA";
601 val = omap_mux_read(m->reg_offset);
602 mode = val & OMAP_MUX_MODE7;
604 seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n",
605 m->muxnames[0], m->muxnames[mode],
606 mux_phys + m->reg_offset, m->reg_offset, val,
607 m->balls[0] ? m->balls[0] : none,
608 m->balls[1] ? m->balls[1] : none);
609 seq_printf(s, "mode: ");
610 omap_mux_decode(s, val);
612 seq_printf(s, "signals: %s | %s | %s | %s | %s | %s | %s | %s\n",
613 m->muxnames[0] ? m->muxnames[0] : none,
614 m->muxnames[1] ? m->muxnames[1] : none,
615 m->muxnames[2] ? m->muxnames[2] : none,
616 m->muxnames[3] ? m->muxnames[3] : none,
617 m->muxnames[4] ? m->muxnames[4] : none,
618 m->muxnames[5] ? m->muxnames[5] : none,
619 m->muxnames[6] ? m->muxnames[6] : none,
620 m->muxnames[7] ? m->muxnames[7] : none);
625 #define OMAP_MUX_MAX_ARG_CHAR 7
627 static ssize_t omap_mux_dbg_signal_write(struct file *file,
628 const char __user *user_buf,
629 size_t count, loff_t *ppos)
631 char buf[OMAP_MUX_MAX_ARG_CHAR];
632 struct seq_file *seqf;
637 if (count > OMAP_MUX_MAX_ARG_CHAR)
640 memset(buf, 0, sizeof(buf));
641 buf_size = min(count, sizeof(buf) - 1);
643 if (copy_from_user(buf, user_buf, buf_size))
646 ret = strict_strtoul(buf, 0x10, &val);
653 seqf = file->private_data;
656 omap_mux_write((u16)val, m->reg_offset);
662 static int omap_mux_dbg_signal_open(struct inode *inode, struct file *file)
664 return single_open(file, omap_mux_dbg_signal_show, inode->i_private);
667 static const struct file_operations omap_mux_dbg_signal_fops = {
668 .open = omap_mux_dbg_signal_open,
670 .write = omap_mux_dbg_signal_write,
672 .release = single_release,
675 static struct dentry *mux_dbg_dir;
677 static void __init omap_mux_dbg_init(void)
679 struct omap_mux_entry *e;
681 mux_dbg_dir = debugfs_create_dir("omap_mux", NULL);
685 (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir,
686 NULL, &omap_mux_dbg_board_fops);
688 list_for_each_entry(e, &muxmodes, node) {
689 struct omap_mux *m = &e->mux;
691 (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
692 m, &omap_mux_dbg_signal_fops);
697 static inline void omap_mux_dbg_init(void)
700 #endif /* CONFIG_DEBUG_FS */
702 static void __init omap_mux_free_names(struct omap_mux *m)
706 for (i = 0; i < OMAP_MUX_NR_MODES; i++)
707 kfree(m->muxnames[i]);
709 #ifdef CONFIG_DEBUG_FS
710 for (i = 0; i < OMAP_MUX_NR_SIDES; i++)
716 /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */
717 static int __init omap_mux_late_init(void)
719 struct omap_mux_entry *e, *tmp;
721 list_for_each_entry_safe(e, tmp, &muxmodes, node) {
722 struct omap_mux *m = &e->mux;
723 u16 mode = omap_mux_read(m->reg_offset);
725 if (OMAP_MODE_GPIO(mode))
728 #ifndef CONFIG_DEBUG_FS
729 mutex_lock(&muxmode_mutex);
731 mutex_unlock(&muxmode_mutex);
732 omap_mux_free_names(m);
742 late_initcall(omap_mux_late_init);
744 static void __init omap_mux_package_fixup(struct omap_mux *p,
745 struct omap_mux *superset)
747 while (p->reg_offset != OMAP_MUX_TERMINATOR) {
748 struct omap_mux *s = superset;
751 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
752 if (s->reg_offset == p->reg_offset) {
760 printk(KERN_ERR "mux: Unknown entry offset 0x%x\n",
766 #ifdef CONFIG_DEBUG_FS
768 static void __init omap_mux_package_init_balls(struct omap_ball *b,
769 struct omap_mux *superset)
771 while (b->reg_offset != OMAP_MUX_TERMINATOR) {
772 struct omap_mux *s = superset;
775 while (s->reg_offset != OMAP_MUX_TERMINATOR) {
776 if (s->reg_offset == b->reg_offset) {
777 s->balls[0] = b->balls[0];
778 s->balls[1] = b->balls[1];
785 printk(KERN_ERR "mux: Unknown ball offset 0x%x\n",
791 #else /* CONFIG_DEBUG_FS */
793 static inline void omap_mux_package_init_balls(struct omap_ball *b,
794 struct omap_mux *superset)
798 #endif /* CONFIG_DEBUG_FS */
800 static int __init omap_mux_setup(char *options)
805 omap_mux_options = options;
809 __setup("omap_mux=", omap_mux_setup);
812 * Note that the omap_mux=some.signal1=0x1234,some.signal2=0x1234
813 * cmdline options only override the bootloader values.
814 * During development, please enable CONFIG_DEBUG_FS, and use the
815 * signal specific entries under debugfs.
817 static void __init omap_mux_set_cmdline_signals(void)
819 char *options, *next_opt, *token;
821 if (!omap_mux_options)
824 options = kmalloc(strlen(omap_mux_options) + 1, GFP_KERNEL);
828 strcpy(options, omap_mux_options);
831 while ((token = strsep(&next_opt, ",")) != NULL) {
836 name = strsep(&keyval, "=");
840 res = strict_strtoul(keyval, 0x10, &val);
844 omap_mux_init_signal(name, (u16)val);
851 static int __init omap_mux_copy_names(struct omap_mux *src,
852 struct omap_mux *dst)
856 for (i = 0; i < OMAP_MUX_NR_MODES; i++) {
857 if (src->muxnames[i]) {
859 kmalloc(strlen(src->muxnames[i]) + 1,
861 if (!dst->muxnames[i])
863 strcpy(dst->muxnames[i], src->muxnames[i]);
867 #ifdef CONFIG_DEBUG_FS
868 for (i = 0; i < OMAP_MUX_NR_SIDES; i++) {
871 kmalloc(strlen(src->balls[i]) + 1,
875 strcpy(dst->balls[i], src->balls[i]);
883 omap_mux_free_names(dst);
888 #endif /* CONFIG_OMAP_MUX */
890 static u16 omap_mux_get_by_gpio(int gpio)
892 struct omap_mux_entry *e;
893 u16 offset = OMAP_MUX_TERMINATOR;
895 list_for_each_entry(e, &muxmodes, node) {
896 struct omap_mux *m = &e->mux;
897 if (m->gpio == gpio) {
898 offset = m->reg_offset;
906 /* Needed for dynamic muxing of GPIO pins for off-idle */
907 u16 omap_mux_get_gpio(int gpio)
911 offset = omap_mux_get_by_gpio(gpio);
912 if (offset == OMAP_MUX_TERMINATOR) {
913 printk(KERN_ERR "mux: Could not get gpio%i\n", gpio);
917 return omap_mux_read(offset);
920 /* Needed for dynamic muxing of GPIO pins for off-idle */
921 void omap_mux_set_gpio(u16 val, int gpio)
925 offset = omap_mux_get_by_gpio(gpio);
926 if (offset == OMAP_MUX_TERMINATOR) {
927 printk(KERN_ERR "mux: Could not set gpio%i\n", gpio);
931 omap_mux_write(val, offset);
934 static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src)
936 struct omap_mux_entry *entry;
939 entry = kzalloc(sizeof(struct omap_mux_entry), GFP_KERNEL);
944 memcpy(m, src, sizeof(struct omap_mux_entry));
946 #ifdef CONFIG_OMAP_MUX
947 if (omap_mux_copy_names(src, m)) {
953 mutex_lock(&muxmode_mutex);
954 list_add_tail(&entry->node, &muxmodes);
955 mutex_unlock(&muxmode_mutex);
961 * Note if CONFIG_OMAP_MUX is not selected, we will only initialize
962 * the GPIO to mux offset mapping that is needed for dynamic muxing
963 * of GPIO pins for off-idle.
965 static void __init omap_mux_init_list(struct omap_mux *superset)
967 while (superset->reg_offset != OMAP_MUX_TERMINATOR) {
968 struct omap_mux *entry;
970 #ifdef CONFIG_OMAP_MUX
971 if (!superset->muxnames || !superset->muxnames[0]) {
976 /* Skip pins that are not muxed as GPIO by bootloader */
977 if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) {
983 entry = omap_mux_list_add(superset);
985 printk(KERN_ERR "mux: Could not add entry\n");
992 #ifdef CONFIG_OMAP_MUX
994 static void omap_mux_init_package(struct omap_mux *superset,
995 struct omap_mux *package_subset,
996 struct omap_ball *package_balls)
999 omap_mux_package_fixup(package_subset, superset);
1001 omap_mux_package_init_balls(package_balls, superset);
1004 static void omap_mux_init_signals(struct omap_board_mux *board_mux)
1006 omap_mux_set_cmdline_signals();
1007 omap_mux_write_array(board_mux);
1012 static void omap_mux_init_package(struct omap_mux *superset,
1013 struct omap_mux *package_subset,
1014 struct omap_ball *package_balls)
1018 static void omap_mux_init_signals(struct omap_board_mux *board_mux)
1024 int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
1025 struct omap_mux *superset,
1026 struct omap_mux *package_subset,
1027 struct omap_board_mux *board_mux,
1028 struct omap_ball *package_balls)
1033 mux_phys = mux_pbase;
1034 mux_base = ioremap(mux_pbase, mux_size);
1036 printk(KERN_ERR "mux: Could not ioremap\n");
1040 if (cpu_is_omap24xx())
1041 omap_mux_flags = MUXABLE_GPIO_MODE3;
1043 omap_mux_init_package(superset, package_subset, package_balls);
1044 omap_mux_init_list(superset);
1045 omap_mux_init_signals(board_mux);
1050 #endif /* CONFIG_ARCH_OMAP3 */