2 * linux/arch/arm/mach-omap2/mcbsp.c
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Multichannel mode not supported.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
18 #include <linux/platform_device.h>
20 #include <mach/irqs.h>
24 #include <plat/mcbsp.h>
26 static void omap2_mcbsp2_mux_setup(void)
28 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
29 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
30 omap_cfg_reg(W15_24XX_MCBSP2_DR);
31 omap_cfg_reg(V15_24XX_MCBSP2_DX);
32 omap_cfg_reg(V14_24XX_GPIO117);
34 * TODO: Need to add MUX settings for OMAP 2430 SDP
38 static void omap2_mcbsp_request(unsigned int id)
40 if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
41 omap2_mcbsp2_mux_setup();
44 static struct omap_mcbsp_ops omap2_mcbsp_ops = {
45 .request = omap2_mcbsp_request,
48 #ifdef CONFIG_ARCH_OMAP2420
49 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
51 .phys_base = OMAP24XX_MCBSP1_BASE,
52 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
53 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
54 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
55 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
56 .ops = &omap2_mcbsp_ops,
59 .phys_base = OMAP24XX_MCBSP2_BASE,
60 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
61 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
62 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
63 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
64 .ops = &omap2_mcbsp_ops,
67 #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
68 #define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
70 #define omap2420_mcbsp_pdata NULL
71 #define OMAP2420_MCBSP_PDATA_SZ 0
72 #define OMAP2420_MCBSP_REG_NUM 0
75 #ifdef CONFIG_ARCH_OMAP2430
76 static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
78 .phys_base = OMAP24XX_MCBSP1_BASE,
79 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
80 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
81 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
82 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
83 .ops = &omap2_mcbsp_ops,
86 .phys_base = OMAP24XX_MCBSP2_BASE,
87 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
88 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
89 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
90 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
91 .ops = &omap2_mcbsp_ops,
94 .phys_base = OMAP2430_MCBSP3_BASE,
95 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
96 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
97 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
98 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
99 .ops = &omap2_mcbsp_ops,
102 .phys_base = OMAP2430_MCBSP4_BASE,
103 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
104 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
105 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
106 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
107 .ops = &omap2_mcbsp_ops,
110 .phys_base = OMAP2430_MCBSP5_BASE,
111 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
112 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
113 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
114 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
115 .ops = &omap2_mcbsp_ops,
118 #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
119 #define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
121 #define omap2430_mcbsp_pdata NULL
122 #define OMAP2430_MCBSP_PDATA_SZ 0
123 #define OMAP2430_MCBSP_REG_NUM 0
126 #ifdef CONFIG_ARCH_OMAP3
127 static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
129 .phys_base = OMAP34XX_MCBSP1_BASE,
130 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
131 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
132 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
133 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
134 .ops = &omap2_mcbsp_ops,
138 .phys_base = OMAP34XX_MCBSP2_BASE,
139 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
140 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
141 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
142 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
143 .ops = &omap2_mcbsp_ops,
144 .buffer_size = 0x3FF,
147 .phys_base = OMAP34XX_MCBSP3_BASE,
148 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
149 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
150 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
151 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
152 .ops = &omap2_mcbsp_ops,
156 .phys_base = OMAP34XX_MCBSP4_BASE,
157 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
158 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
159 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
160 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
161 .ops = &omap2_mcbsp_ops,
165 .phys_base = OMAP34XX_MCBSP5_BASE,
166 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
167 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
168 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
169 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
170 .ops = &omap2_mcbsp_ops,
174 #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
175 #define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
177 #define omap34xx_mcbsp_pdata NULL
178 #define OMAP34XX_MCBSP_PDATA_SZ 0
179 #define OMAP34XX_MCBSP_REG_NUM 0
182 static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
184 .phys_base = OMAP44XX_MCBSP1_BASE,
185 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX,
186 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX,
187 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
188 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
189 .ops = &omap2_mcbsp_ops,
192 .phys_base = OMAP44XX_MCBSP2_BASE,
193 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX,
194 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX,
195 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
196 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
197 .ops = &omap2_mcbsp_ops,
200 .phys_base = OMAP44XX_MCBSP3_BASE,
201 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX,
202 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX,
203 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
204 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
205 .ops = &omap2_mcbsp_ops,
208 .phys_base = OMAP44XX_MCBSP4_BASE,
209 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX,
210 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX,
211 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
212 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
213 .ops = &omap2_mcbsp_ops,
216 #define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata)
217 #define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
219 static int __init omap2_mcbsp_init(void)
221 if (cpu_is_omap2420()) {
222 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
223 omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
224 } else if (cpu_is_omap2430()) {
225 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
226 omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
227 } else if (cpu_is_omap34xx()) {
228 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
229 omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
230 } else if (cpu_is_omap44xx()) {
231 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
232 omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
235 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
240 if (cpu_is_omap2420())
241 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
242 OMAP2420_MCBSP_PDATA_SZ);
243 if (cpu_is_omap2430())
244 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
245 OMAP2430_MCBSP_PDATA_SZ);
246 if (cpu_is_omap34xx())
247 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
248 OMAP34XX_MCBSP_PDATA_SZ);
249 if (cpu_is_omap44xx())
250 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
251 OMAP44XX_MCBSP_PDATA_SZ);
253 return omap_mcbsp_init();
255 arch_initcall(omap2_mcbsp_init);