2 * arch/arm/plat-omap/include/mach/entry-macro.S
4 * Low-level IRQ helper macros for OMAP-based platforms
6 * Copyright (C) 2009 Texas Instruments
7 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
13 #include <mach/hardware.h>
15 #include <mach/irqs.h>
16 #include <asm/hardware/gic.h>
18 #include <plat/omap24xx.h>
19 #include <plat/omap34xx.h>
20 #include <plat/omap44xx.h>
22 #include <plat/multi.h>
24 #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
25 #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
26 #define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
27 #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
28 #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
33 .macro arch_ret_to_user, tmp1, tmp2
37 * Unoptimized irq functions for multi-omap2, 3 and 4
43 * We use __glue to avoid errors with multiple definitions of
44 * .globl omap_irq_base as it's included from entry-armv.S but not
45 * from entry-common.S.
56 * Configure the interrupt base on the first interrupt.
57 * See also omap_irq_base_init for setting omap_irq_base.
59 .macro get_irqnr_preamble, base, tmp
60 ldr \base, =omap_irq_base @ irq base address
61 ldr \base, [\base, #0] @ irq base value
64 /* Check the pending interrupts. Note that base already set */
65 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
66 tst \base, #0x100 @ gic address?
69 /* Handle omap2 and omap3 */
70 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
73 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
76 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
79 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
80 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
84 4401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
86 bic \irqnr, \irqstat, #0x1c00
95 /* We assume that irqstat (the raw value of the IRQ acknowledge
96 * register) is preserved from the macro above.
97 * If there is an IPI, we immediately signal end of interrupt
98 * on the controller, since this requires the original irqstat
99 * value which we won't easily be able to recreate later.
102 .macro test_for_ipi, irqnr, irqstat, base, tmp
103 bic \irqnr, \irqstat, #0x1c00
106 strcc \irqstat, [\base, #GIC_CPU_EOI]
111 /* As above, this assumes that irqstat and base are preserved */
113 .macro test_for_ltirq, irqnr, irqstat, base, tmp
114 bic \irqnr, \irqstat, #0x1c00
119 streq \irqstat, [\base, #GIC_CPU_EOI]
122 #endif /* CONFIG_SMP */
124 #else /* MULTI_OMAP2 */
128 * Optimized irq functions for omap2, 3 and 4
131 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
132 .macro get_irqnr_preamble, base, tmp
133 #ifdef CONFIG_ARCH_OMAP2
134 ldr \base, =OMAP2_IRQ_BASE
136 ldr \base, =OMAP3_IRQ_BASE
140 /* Check the pending interrupts. Note that base already set */
141 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
142 ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
145 ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
148 ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
151 ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
152 and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
158 #ifdef CONFIG_ARCH_OMAP4
159 #define HAVE_GET_IRQNR_PREAMBLE
160 #include <asm/hardware/entry-macro-gic.S>
162 .macro get_irqnr_preamble, base, tmp
163 ldr \base, =OMAP4_IRQ_BASE
168 #endif /* MULTI_OMAP2 */
170 .macro irq_prio_table