2 * OMAP3/4 - specific DPLL control functions
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
10 * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth
13 * Parts of this code are based on code written by
14 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/kernel.h>
22 #include <linux/device.h>
23 #include <linux/list.h>
24 #include <linux/errno.h>
25 #include <linux/delay.h>
26 #include <linux/clk.h>
28 #include <linux/bitops.h>
29 #include <linux/clkdev.h>
32 #include <plat/clock.h>
35 #include "cm2xxx_3xxx.h"
36 #include "cm-regbits-34xx.h"
38 /* CM_AUTOIDLE_PLL*.AUTO_* bit values */
39 #define DPLL_AUTOIDLE_DISABLE 0x0
40 #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
42 #define MAX_DPLL_WAIT_TRIES 1000000
44 /* Private functions */
46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
47 static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
49 const struct dpll_data *dd;
54 v = __raw_readl(dd->control_reg);
55 v &= ~dd->enable_mask;
56 v |= clken_bits << __ffs(dd->enable_mask);
57 __raw_writel(v, dd->control_reg);
60 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
61 static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
63 const struct dpll_data *dd;
69 state <<= __ffs(dd->idlest_mask);
71 while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
72 i < MAX_DPLL_WAIT_TRIES) {
77 if (i == MAX_DPLL_WAIT_TRIES) {
78 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
79 clk->name, (state) ? "locked" : "bypassed");
81 pr_debug("clock: %s transition to '%s' in %d loops\n",
82 clk->name, (state) ? "locked" : "bypassed", i);
90 /* From 3430 TRM ES2 4.7.6.2 */
91 static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
96 fint = clk->dpll_data->clk_ref->rate / n;
98 pr_debug("clock: fint is %lu\n", fint);
100 if (fint >= 750000 && fint <= 1000000)
102 else if (fint > 1000000 && fint <= 1250000)
104 else if (fint > 1250000 && fint <= 1500000)
106 else if (fint > 1500000 && fint <= 1750000)
108 else if (fint > 1750000 && fint <= 2100000)
110 else if (fint > 7500000 && fint <= 10000000)
112 else if (fint > 10000000 && fint <= 12500000)
114 else if (fint > 12500000 && fint <= 15000000)
116 else if (fint > 15000000 && fint <= 17500000)
118 else if (fint > 17500000 && fint <= 21000000)
121 pr_debug("clock: unknown freqsel setting for %d\n", n);
127 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
128 * @clk: pointer to a DPLL struct clk
130 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
131 * readiness before returning. Will save and restore the DPLL's
132 * autoidle state across the enable, per the CDP code. If the DPLL
133 * locked successfully, return 0; if the DPLL did not lock in the time
134 * allotted, or DPLL3 was passed in, return -EINVAL.
136 static int _omap3_noncore_dpll_lock(struct clk *clk)
141 pr_debug("clock: locking DPLL %s\n", clk->name);
143 ai = omap3_dpll_autoidle_read(clk);
145 omap3_dpll_deny_idle(clk);
147 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
149 r = _omap3_wait_dpll_status(clk, 1);
152 omap3_dpll_allow_idle(clk);
158 * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
159 * @clk: pointer to a DPLL struct clk
161 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
162 * bypass mode, the DPLL's rate is set equal to its parent clock's
163 * rate. Waits for the DPLL to report readiness before returning.
164 * Will save and restore the DPLL's autoidle state across the enable,
165 * per the CDP code. If the DPLL entered bypass mode successfully,
166 * return 0; if the DPLL did not enter bypass in the time allotted, or
167 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
170 static int _omap3_noncore_dpll_bypass(struct clk *clk)
175 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
178 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
181 ai = omap3_dpll_autoidle_read(clk);
183 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
185 r = _omap3_wait_dpll_status(clk, 0);
188 omap3_dpll_allow_idle(clk);
190 omap3_dpll_deny_idle(clk);
196 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
197 * @clk: pointer to a DPLL struct clk
199 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
200 * restore the DPLL's autoidle state across the stop, per the CDP
201 * code. If DPLL3 was passed in, or the DPLL does not support
202 * low-power stop, return -EINVAL; otherwise, return 0.
204 static int _omap3_noncore_dpll_stop(struct clk *clk)
208 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
211 pr_debug("clock: stopping DPLL %s\n", clk->name);
213 ai = omap3_dpll_autoidle_read(clk);
215 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
218 omap3_dpll_allow_idle(clk);
220 omap3_dpll_deny_idle(clk);
226 * _lookup_dco - Lookup DCO used by j-type DPLL
227 * @clk: pointer to a DPLL struct clk
228 * @dco: digital control oscillator selector
229 * @m: DPLL multiplier to set
230 * @n: DPLL divider to set
232 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
234 * XXX This code is not needed for 3430/AM35xx; can it be optimized
235 * out in non-multi-OMAP builds for those chips?
237 static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
239 unsigned long fint, clkinp; /* watch out for overflow */
241 clkinp = clk->parent->rate;
242 fint = (clkinp / n) * m;
244 if (fint < 1000000000)
251 * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL
252 * @clk: pointer to a DPLL struct clk
253 * @sd_div: target sigma-delta divider
254 * @m: DPLL multiplier to set
255 * @n: DPLL divider to set
257 * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)"
259 * XXX This code is not needed for 3430/AM35xx; can it be optimized
260 * out in non-multi-OMAP builds for those chips?
262 static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
264 unsigned long clkinp, sd; /* watch out for overflow */
267 clkinp = clk->parent->rate;
270 * target sigma-delta to near 250MHz
271 * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)]
273 clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */
274 mod1 = (clkinp * m) % (250 * n);
275 sd = (clkinp * m) / (250 * n);
285 * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly
286 * @clk: struct clk * of DPLL to set
287 * @m: DPLL multiplier to set
288 * @n: DPLL divider to set
289 * @freqsel: FREQSEL value to set
291 * Program the DPLL with the supplied M, N values, and wait for the DPLL to
292 * lock.. Returns -EINVAL upon error, or 0 upon success.
294 static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel)
296 struct dpll_data *dd = clk->dpll_data;
300 /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */
301 _omap3_noncore_dpll_bypass(clk);
304 * Set jitter correction. No jitter correction for OMAP4 and 3630
305 * since freqsel field is no longer present
307 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
308 v = __raw_readl(dd->control_reg);
309 v &= ~dd->freqsel_mask;
310 v |= freqsel << __ffs(dd->freqsel_mask);
311 __raw_writel(v, dd->control_reg);
314 /* Set DPLL multiplier, divider */
315 v = __raw_readl(dd->mult_div1_reg);
316 v &= ~(dd->mult_mask | dd->div1_mask);
317 v |= m << __ffs(dd->mult_mask);
318 v |= (n - 1) << __ffs(dd->div1_mask);
320 /* Configure dco and sd_div for dplls that have these fields */
322 _lookup_dco(clk, &dco, m, n);
323 v &= ~(dd->dco_mask);
324 v |= dco << __ffs(dd->dco_mask);
326 if (dd->sddiv_mask) {
327 _lookup_sddiv(clk, &sd_div, m, n);
328 v &= ~(dd->sddiv_mask);
329 v |= sd_div << __ffs(dd->sddiv_mask);
332 __raw_writel(v, dd->mult_div1_reg);
334 /* We let the clock framework set the other output dividers later */
336 /* REVISIT: Set ramp-up delay? */
338 _omap3_noncore_dpll_lock(clk);
343 /* Public functions */
346 * omap3_dpll_recalc - recalculate DPLL rate
347 * @clk: DPLL struct clk
349 * Recalculate and propagate the DPLL rate.
351 unsigned long omap3_dpll_recalc(struct clk *clk)
353 return omap2_get_dpll_rate(clk);
356 /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
359 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
360 * @clk: pointer to a DPLL struct clk
362 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
363 * The choice of modes depends on the DPLL's programmed rate: if it is
364 * the same as the DPLL's parent clock, it will enter bypass;
365 * otherwise, it will enter lock. This code will wait for the DPLL to
366 * indicate readiness before returning, unless the DPLL takes too long
367 * to enter the target state. Intended to be used as the struct clk's
368 * enable function. If DPLL3 was passed in, or the DPLL does not
369 * support low-power stop, or if the DPLL took too long to enter
370 * bypass or lock, return -EINVAL; otherwise, return 0.
372 int omap3_noncore_dpll_enable(struct clk *clk)
375 struct dpll_data *dd;
381 if (clk->rate == dd->clk_bypass->rate) {
382 WARN_ON(clk->parent != dd->clk_bypass);
383 r = _omap3_noncore_dpll_bypass(clk);
385 WARN_ON(clk->parent != dd->clk_ref);
386 r = _omap3_noncore_dpll_lock(clk);
389 *FIXME: this is dubious - if clk->rate has changed, what about
393 clk->rate = (clk->recalc) ? clk->recalc(clk) :
394 omap2_get_dpll_rate(clk);
400 * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop
401 * @clk: pointer to a DPLL struct clk
403 * Instructs a non-CORE DPLL to enter low-power stop. This function is
404 * intended for use in struct clkops. No return value.
406 void omap3_noncore_dpll_disable(struct clk *clk)
408 _omap3_noncore_dpll_stop(clk);
412 /* Non-CORE DPLL rate set code */
415 * omap3_noncore_dpll_set_rate - set non-core DPLL rate
416 * @clk: struct clk * of DPLL to set
417 * @rate: rounded target rate
419 * Set the DPLL CLKOUT to the target rate. If the DPLL can enter
420 * low-power bypass, and the target rate is the bypass source clock
421 * rate, then configure the DPLL for bypass. Otherwise, round the
422 * target rate if it hasn't been done already, then program and lock
423 * the DPLL. Returns -EINVAL upon error, or 0 upon success.
425 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
427 struct clk *new_parent = NULL;
428 unsigned long hw_rate;
430 struct dpll_data *dd;
440 hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk);
445 * Ensure both the bypass and ref clocks are enabled prior to
446 * doing anything; we need the bypass clock running to reprogram
449 omap2_clk_enable(dd->clk_bypass);
450 omap2_clk_enable(dd->clk_ref);
452 if (dd->clk_bypass->rate == rate &&
453 (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
454 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
456 ret = _omap3_noncore_dpll_bypass(clk);
458 new_parent = dd->clk_bypass;
460 if (dd->last_rounded_rate != rate)
461 rate = clk->round_rate(clk, rate);
463 if (dd->last_rounded_rate == 0)
466 /* No freqsel on OMAP4 and OMAP3630 */
467 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) {
468 freqsel = _omap3_dpll_compute_freqsel(clk,
474 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
477 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
478 dd->last_rounded_n, freqsel);
480 new_parent = dd->clk_ref;
484 * Switch the parent clock in the hierarchy, and make sure
485 * that the new parent's usecount is correct. Note: we
486 * enable the new parent before disabling the old to avoid
487 * any unnecessary hardware disable->enable transitions.
490 omap2_clk_enable(new_parent);
491 omap2_clk_disable(clk->parent);
493 clk_reparent(clk, new_parent);
496 omap2_clk_disable(dd->clk_ref);
497 omap2_clk_disable(dd->clk_bypass);
502 /* DPLL autoidle read/set code */
505 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
506 * @clk: struct clk * of the DPLL to read
508 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
509 * -EINVAL if passed a null pointer or if the struct clk does not
510 * appear to refer to a DPLL.
512 u32 omap3_dpll_autoidle_read(struct clk *clk)
514 const struct dpll_data *dd;
517 if (!clk || !clk->dpll_data)
522 v = __raw_readl(dd->autoidle_reg);
523 v &= dd->autoidle_mask;
524 v >>= __ffs(dd->autoidle_mask);
530 * omap3_dpll_allow_idle - enable DPLL autoidle bits
531 * @clk: struct clk * of the DPLL to operate on
533 * Enable DPLL automatic idle control. This automatic idle mode
534 * switching takes effect only when the DPLL is locked, at least on
535 * OMAP3430. The DPLL will enter low-power stop when its downstream
536 * clocks are gated. No return value.
538 void omap3_dpll_allow_idle(struct clk *clk)
540 const struct dpll_data *dd;
543 if (!clk || !clk->dpll_data)
549 * REVISIT: CORE DPLL can optionally enter low-power bypass
550 * by writing 0x5 instead of 0x1. Add some mechanism to
551 * optionally enter this mode.
553 v = __raw_readl(dd->autoidle_reg);
554 v &= ~dd->autoidle_mask;
555 v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
556 __raw_writel(v, dd->autoidle_reg);
560 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
561 * @clk: struct clk * of the DPLL to operate on
563 * Disable DPLL automatic idle control. No return value.
565 void omap3_dpll_deny_idle(struct clk *clk)
567 const struct dpll_data *dd;
570 if (!clk || !clk->dpll_data)
575 v = __raw_readl(dd->autoidle_reg);
576 v &= ~dd->autoidle_mask;
577 v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
578 __raw_writel(v, dd->autoidle_reg);
582 /* Clock control for DPLL outputs */
585 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
586 * @clk: DPLL output struct clk
588 * Using parent clock DPLL data, look up DPLL state. If locked, set our
589 * rate to the dpll_clk * 2; otherwise, just use dpll_clk.
591 unsigned long omap3_clkoutx2_recalc(struct clk *clk)
593 const struct dpll_data *dd;
598 /* Walk up the parents of clk, looking for a DPLL */
600 while (pclk && !pclk->dpll_data)
603 /* clk does not have a DPLL as a parent? */
606 dd = pclk->dpll_data;
608 WARN_ON(!dd->enable_mask);
610 v = __raw_readl(dd->control_reg) & dd->enable_mask;
611 v >>= __ffs(dd->enable_mask);
612 if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
613 rate = clk->parent->rate;
615 rate = clk->parent->rate * 2;