arch/arm/mach-omap2/control.c

   1 /*
   2  * OMAP2/3 System Control Module register access
   3  *
   4  * Copyright (C) 2007, 2012 Texas Instruments, Inc.
   5  * Copyright (C) 2007 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #undef DEBUG
  14
  15 #include <linux/kernel.h>
  16 #include <linux/io.h>
  17
  18 #include "soc.h"
  19 #include "iomap.h"
  20 #include "common.h"
  21 #include "cm-regbits-34xx.h"
  22 #include "prm-regbits-34xx.h"
  23 #include "prm3xxx.h"
  24 #include "cm3xxx.h"
  25 #include "sdrc.h"
  26 #include "pm.h"
  27 #include "control.h"
  28
  29 /* Used by omap3_ctrl_save_padconf() */
  30 #define START_PADCONF_SAVE              0x2
  31 #define PADCONF_SAVE_DONE               0x1
  32
  33 static void __iomem *omap2_ctrl_base;
  34 static void __iomem *omap4_ctrl_pad_base;
  35
  36 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  37 struct omap3_scratchpad {
  38         u32 boot_config_ptr;
  39         u32 public_restore_ptr;
  40         u32 secure_ram_restore_ptr;
  41         u32 sdrc_module_semaphore;
  42         u32 prcm_block_offset;
  43         u32 sdrc_block_offset;
  44 };
  45
  46 struct omap3_scratchpad_prcm_block {
  47         u32 prm_contents[2];
  48         u32 cm_contents[11];
  49         u32 prcm_block_size;
  50 };
  51
  52 struct omap3_scratchpad_sdrc_block {
  53         u16 sysconfig;
  54         u16 cs_cfg;
  55         u16 sharing;
  56         u16 err_type;
  57         u32 dll_a_ctrl;
  58         u32 dll_b_ctrl;
  59         u32 power;
  60         u32 cs_0;
  61         u32 mcfg_0;
  62         u16 mr_0;
  63         u16 emr_1_0;
  64         u16 emr_2_0;
  65         u16 emr_3_0;
  66         u32 actim_ctrla_0;
  67         u32 actim_ctrlb_0;
  68         u32 rfr_ctrl_0;
  69         u32 cs_1;
  70         u32 mcfg_1;
  71         u16 mr_1;
  72         u16 emr_1_1;
  73         u16 emr_2_1;
  74         u16 emr_3_1;
  75         u32 actim_ctrla_1;
  76         u32 actim_ctrlb_1;
  77         u32 rfr_ctrl_1;
  78         u16 dcdl_1_ctrl;
  79         u16 dcdl_2_ctrl;
  80         u32 flags;
  81         u32 block_size;
  82 };
  83
  84 void *omap3_secure_ram_storage;
  85
  86 /*
  87  * This is used to store ARM registers in SDRAM before attempting
  88  * an MPU OFF. The save and restore happens from the SRAM sleep code.
  89  * The address is stored in scratchpad, so that it can be used
  90  * during the restore path.
  91  */
  92 u32 omap3_arm_context[128];
  93
  94 struct omap3_control_regs {
  95         u32 sysconfig;
  96         u32 devconf0;
  97         u32 mem_dftrw0;
  98         u32 mem_dftrw1;
  99         u32 msuspendmux_0;
 100         u32 msuspendmux_1;
 101         u32 msuspendmux_2;
 102         u32 msuspendmux_3;
 103         u32 msuspendmux_4;
 104         u32 msuspendmux_5;
 105         u32 sec_ctrl;
 106         u32 devconf1;
 107         u32 csirxfe;
 108         u32 iva2_bootaddr;
 109         u32 iva2_bootmod;
 110         u32 debobs_0;
 111         u32 debobs_1;
 112         u32 debobs_2;
 113         u32 debobs_3;
 114         u32 debobs_4;
 115         u32 debobs_5;
 116         u32 debobs_6;
 117         u32 debobs_7;
 118         u32 debobs_8;
 119         u32 prog_io0;
 120         u32 prog_io1;
 121         u32 dss_dpll_spreading;
 122         u32 core_dpll_spreading;
 123         u32 per_dpll_spreading;
 124         u32 usbhost_dpll_spreading;
 125         u32 pbias_lite;
 126         u32 temp_sensor;
 127         u32 sramldo4;
 128         u32 sramldo5;
 129         u32 csi;
 130         u32 padconf_sys_nirq;
 131 };
 132
 133 static struct omap3_control_regs control_context;
 134 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
 135
 136 #define OMAP_CTRL_REGADDR(reg)          (omap2_ctrl_base + (reg))
 137 #define OMAP4_CTRL_PAD_REGADDR(reg)     (omap4_ctrl_pad_base + (reg))
 138
 139 void __init omap2_set_globals_control(void __iomem *ctrl,
 140                                       void __iomem *ctrl_pad)
 141 {
 142         omap2_ctrl_base = ctrl;
 143         omap4_ctrl_pad_base = ctrl_pad;
 144 }
 145
 146 void __iomem *omap_ctrl_base_get(void)
 147 {
 148         return omap2_ctrl_base;
 149 }
 150
 151 u8 omap_ctrl_readb(u16 offset)
 152 {
 153         return readb_relaxed(OMAP_CTRL_REGADDR(offset));
 154 }
 155
 156 u16 omap_ctrl_readw(u16 offset)
 157 {
 158         return readw_relaxed(OMAP_CTRL_REGADDR(offset));
 159 }
 160
 161 u32 omap_ctrl_readl(u16 offset)
 162 {
 163         return readl_relaxed(OMAP_CTRL_REGADDR(offset));
 164 }
 165
 166 void omap_ctrl_writeb(u8 val, u16 offset)
 167 {
 168         writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
 169 }
 170
 171 void omap_ctrl_writew(u16 val, u16 offset)
 172 {
 173         writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
 174 }
 175
 176 void omap_ctrl_writel(u32 val, u16 offset)
 177 {
 178         writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
 179 }
 180
 181 /*
 182  * On OMAP4 control pad are not addressable from control
 183  * core base. So the common omap_ctrl_read/write APIs breaks
 184  * Hence export separate APIs to manage the omap4 pad control
 185  * registers. This APIs will work only for OMAP4
 186  */
 187
 188 u32 omap4_ctrl_pad_readl(u16 offset)
 189 {
 190         return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
 191 }
 192
 193 void omap4_ctrl_pad_writel(u32 val, u16 offset)
 194 {
 195         writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
 196 }
 197
 198 #ifdef CONFIG_ARCH_OMAP3
 199
 200 /**
 201  * omap3_ctrl_write_boot_mode - set scratchpad boot mode for the next boot
 202  * @bootmode: 8-bit value to pass to some boot code
 203  *
 204  * Set the bootmode in the scratchpad RAM.  This is used after the
 205  * system restarts.  Not sure what actually uses this - it may be the
 206  * bootloader, rather than the boot ROM - contrary to the preserved
 207  * comment below.  No return value.
 208  */
 209 void omap3_ctrl_write_boot_mode(u8 bootmode)
 210 {
 211         u32 l;
 212
 213         l = ('B' << 24) | ('M' << 16) | bootmode;
 214
 215         /*
 216          * Reserve the first word in scratchpad for communicating
 217          * with the boot ROM. A pointer to a data structure
 218          * describing the boot process can be stored there,
 219          * cf. OMAP34xx TRM, Initialization / Software Booting
 220          * Configuration.
 221          *
 222          * XXX This should use some omap_ctrl_writel()-type function
 223          */
 224         writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
 225 }
 226
 227 #endif
 228
 229 /**
 230  * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
 231  * @bootaddr: physical address of the boot loader
 232  *
 233  * Set boot address for the boot loader of a supported processor
 234  * when a power ON sequence occurs.
 235  */
 236 void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
 237 {
 238         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
 239                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
 240                      cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 241                      soc_is_omap54xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
 242                      0;
 243
 244         if (!offset) {
 245                 pr_err("%s: unsupported omap type\n", __func__);
 246                 return;
 247         }
 248
 249         omap_ctrl_writel(bootaddr, offset);
 250 }
 251
 252 /**
 253  * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
 254  * @bootmode: 8-bit value to pass to some boot code
 255  *
 256  * Sets boot mode for the boot loader of a supported processor
 257  * when a power ON sequence occurs.
 258  */
 259 void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
 260 {
 261         u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
 262                      cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
 263                      0;
 264
 265         if (!offset) {
 266                 pr_err("%s: unsupported omap type\n", __func__);
 267                 return;
 268         }
 269
 270         omap_ctrl_writel(bootmode, offset);
 271 }
 272
 273 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 274 /*
 275  * Clears the scratchpad contents in case of cold boot-
 276  * called during bootup
 277  */
 278 void omap3_clear_scratchpad_contents(void)
 279 {
 280         u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
 281         void __iomem *v_addr;
 282         u32 offset = 0;
 283         v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
 284         if (omap3xxx_prm_clear_global_cold_reset()) {
 285                 for ( ; offset <= max_offset; offset += 0x4)
 286                         writel_relaxed(0x0, (v_addr + offset));
 287         }
 288 }
 289
 290 /* Populate the scratchpad structure with restore structure */
 291 void omap3_save_scratchpad_contents(void)
 292 {
 293         void  __iomem *scratchpad_address;
 294         u32 arm_context_addr;
 295         struct omap3_scratchpad scratchpad_contents;
 296         struct omap3_scratchpad_prcm_block prcm_block_contents;
 297         struct omap3_scratchpad_sdrc_block sdrc_block_contents;
 298
 299         /*
 300          * Populate the Scratchpad contents
 301          *
 302          * The "get_*restore_pointer" functions are used to provide a
 303          * physical restore address where the ROM code jumps while waking
 304          * up from MPU OFF/OSWR state.
 305          * The restore pointer is stored into the scratchpad.
 306          */
 307         scratchpad_contents.boot_config_ptr = 0x0;
 308         if (cpu_is_omap3630())
 309                 scratchpad_contents.public_restore_ptr =
 310                         virt_to_phys(omap3_restore_3630);
 311         else if (omap_rev() != OMAP3430_REV_ES3_0 &&
 312                                         omap_rev() != OMAP3430_REV_ES3_1 &&
 313                                         omap_rev() != OMAP3430_REV_ES3_1_2)
 314                 scratchpad_contents.public_restore_ptr =
 315                         virt_to_phys(omap3_restore);
 316         else
 317                 scratchpad_contents.public_restore_ptr =
 318                         virt_to_phys(omap3_restore_es3);
 319
 320         if (omap_type() == OMAP2_DEVICE_TYPE_GP)
 321                 scratchpad_contents.secure_ram_restore_ptr = 0x0;
 322         else
 323                 scratchpad_contents.secure_ram_restore_ptr =
 324                         (u32) __pa(omap3_secure_ram_storage);
 325         scratchpad_contents.sdrc_module_semaphore = 0x0;
 326         scratchpad_contents.prcm_block_offset = 0x2C;
 327         scratchpad_contents.sdrc_block_offset = 0x64;
 328
 329         /* Populate the PRCM block contents */
 330         omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents);
 331         omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents);
 332
 333         prcm_block_contents.prcm_block_size = 0x0;
 334
 335         /* Populate the SDRC block contents */
 336         sdrc_block_contents.sysconfig =
 337                         (sdrc_read_reg(SDRC_SYSCONFIG) & 0xFFFF);
 338         sdrc_block_contents.cs_cfg =
 339                         (sdrc_read_reg(SDRC_CS_CFG) & 0xFFFF);
 340         sdrc_block_contents.sharing =
 341                         (sdrc_read_reg(SDRC_SHARING) & 0xFFFF);
 342         sdrc_block_contents.err_type =
 343                         (sdrc_read_reg(SDRC_ERR_TYPE) & 0xFFFF);
 344         sdrc_block_contents.dll_a_ctrl = sdrc_read_reg(SDRC_DLLA_CTRL);
 345         sdrc_block_contents.dll_b_ctrl = 0x0;
 346         /*
 347          * Due to a OMAP3 errata (1.142), on EMU/HS devices SRDC should
 348          * be programed to issue automatic self refresh on timeout
 349          * of AUTO_CNT = 1 prior to any transition to OFF mode.
 350          */
 351         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)
 352                         && (omap_rev() >= OMAP3430_REV_ES3_0))
 353                 sdrc_block_contents.power = (sdrc_read_reg(SDRC_POWER) &
 354                                 ~(SDRC_POWER_AUTOCOUNT_MASK|
 355                                 SDRC_POWER_CLKCTRL_MASK)) |
 356                                 (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 357                                 SDRC_SELF_REFRESH_ON_AUTOCOUNT;
 358         else
 359                 sdrc_block_contents.power = sdrc_read_reg(SDRC_POWER);
 360
 361         sdrc_block_contents.cs_0 = 0x0;
 362         sdrc_block_contents.mcfg_0 = sdrc_read_reg(SDRC_MCFG_0);
 363         sdrc_block_contents.mr_0 = (sdrc_read_reg(SDRC_MR_0) & 0xFFFF);
 364         sdrc_block_contents.emr_1_0 = 0x0;
 365         sdrc_block_contents.emr_2_0 = 0x0;
 366         sdrc_block_contents.emr_3_0 = 0x0;
 367         sdrc_block_contents.actim_ctrla_0 =
 368                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_0);
 369         sdrc_block_contents.actim_ctrlb_0 =
 370                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_0);
 371         sdrc_block_contents.rfr_ctrl_0 =
 372                         sdrc_read_reg(SDRC_RFR_CTRL_0);
 373         sdrc_block_contents.cs_1 = 0x0;
 374         sdrc_block_contents.mcfg_1 = sdrc_read_reg(SDRC_MCFG_1);
 375         sdrc_block_contents.mr_1 = sdrc_read_reg(SDRC_MR_1) & 0xFFFF;
 376         sdrc_block_contents.emr_1_1 = 0x0;
 377         sdrc_block_contents.emr_2_1 = 0x0;
 378         sdrc_block_contents.emr_3_1 = 0x0;
 379         sdrc_block_contents.actim_ctrla_1 =
 380                         sdrc_read_reg(SDRC_ACTIM_CTRL_A_1);
 381         sdrc_block_contents.actim_ctrlb_1 =
 382                         sdrc_read_reg(SDRC_ACTIM_CTRL_B_1);
 383         sdrc_block_contents.rfr_ctrl_1 =
 384                         sdrc_read_reg(SDRC_RFR_CTRL_1);
 385         sdrc_block_contents.dcdl_1_ctrl = 0x0;
 386         sdrc_block_contents.dcdl_2_ctrl = 0x0;
 387         sdrc_block_contents.flags = 0x0;
 388         sdrc_block_contents.block_size = 0x0;
 389
 390         arm_context_addr = virt_to_phys(omap3_arm_context);
 391
 392         /* Copy all the contents to the scratchpad location */
 393         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 394         memcpy_toio(scratchpad_address, &scratchpad_contents,
 395                  sizeof(scratchpad_contents));
 396         /* Scratchpad contents being 32 bits, a divide by 4 done here */
 397         memcpy_toio(scratchpad_address +
 398                 scratchpad_contents.prcm_block_offset,
 399                 &prcm_block_contents, sizeof(prcm_block_contents));
 400         memcpy_toio(scratchpad_address +
 401                 scratchpad_contents.sdrc_block_offset,
 402                 &sdrc_block_contents, sizeof(sdrc_block_contents));
 403         /*
 404          * Copies the address of the location in SDRAM where ARM
 405          * registers get saved during a MPU OFF transition.
 406          */
 407         memcpy_toio(scratchpad_address +
 408                 scratchpad_contents.sdrc_block_offset +
 409                 sizeof(sdrc_block_contents), &arm_context_addr, 4);
 410 }
 411
 412 void omap3_control_save_context(void)
 413 {
 414         control_context.sysconfig = omap_ctrl_readl(OMAP2_CONTROL_SYSCONFIG);
 415         control_context.devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 416         control_context.mem_dftrw0 =
 417                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW0);
 418         control_context.mem_dftrw1 =
 419                         omap_ctrl_readl(OMAP343X_CONTROL_MEM_DFTRW1);
 420         control_context.msuspendmux_0 =
 421                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_0);
 422         control_context.msuspendmux_1 =
 423                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_1);
 424         control_context.msuspendmux_2 =
 425                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_2);
 426         control_context.msuspendmux_3 =
 427                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_3);
 428         control_context.msuspendmux_4 =
 429                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_4);
 430         control_context.msuspendmux_5 =
 431                         omap_ctrl_readl(OMAP2_CONTROL_MSUSPENDMUX_5);
 432         control_context.sec_ctrl = omap_ctrl_readl(OMAP2_CONTROL_SEC_CTRL);
 433         control_context.devconf1 = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
 434         control_context.csirxfe = omap_ctrl_readl(OMAP343X_CONTROL_CSIRXFE);
 435         control_context.iva2_bootaddr =
 436                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTADDR);
 437         control_context.iva2_bootmod =
 438                         omap_ctrl_readl(OMAP343X_CONTROL_IVA2_BOOTMOD);
 439         control_context.debobs_0 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(0));
 440         control_context.debobs_1 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(1));
 441         control_context.debobs_2 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(2));
 442         control_context.debobs_3 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(3));
 443         control_context.debobs_4 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(4));
 444         control_context.debobs_5 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(5));
 445         control_context.debobs_6 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(6));
 446         control_context.debobs_7 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(7));
 447         control_context.debobs_8 = omap_ctrl_readl(OMAP343X_CONTROL_DEBOBS(8));
 448         control_context.prog_io0 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO0);
 449         control_context.prog_io1 = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
 450         control_context.dss_dpll_spreading =
 451                         omap_ctrl_readl(OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 452         control_context.core_dpll_spreading =
 453                         omap_ctrl_readl(OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 454         control_context.per_dpll_spreading =
 455                         omap_ctrl_readl(OMAP343X_CONTROL_PER_DPLL_SPREADING);
 456         control_context.usbhost_dpll_spreading =
 457                 omap_ctrl_readl(OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 458         control_context.pbias_lite =
 459                         omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
 460         control_context.temp_sensor =
 461                         omap_ctrl_readl(OMAP343X_CONTROL_TEMP_SENSOR);
 462         control_context.sramldo4 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO4);
 463         control_context.sramldo5 = omap_ctrl_readl(OMAP343X_CONTROL_SRAMLDO5);
 464         control_context.csi = omap_ctrl_readl(OMAP343X_CONTROL_CSI);
 465         control_context.padconf_sys_nirq =
 466                 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 467         return;
 468 }
 469
 470 void omap3_control_restore_context(void)
 471 {
 472         omap_ctrl_writel(control_context.sysconfig, OMAP2_CONTROL_SYSCONFIG);
 473         omap_ctrl_writel(control_context.devconf0, OMAP2_CONTROL_DEVCONF0);
 474         omap_ctrl_writel(control_context.mem_dftrw0,
 475                                         OMAP343X_CONTROL_MEM_DFTRW0);
 476         omap_ctrl_writel(control_context.mem_dftrw1,
 477                                         OMAP343X_CONTROL_MEM_DFTRW1);
 478         omap_ctrl_writel(control_context.msuspendmux_0,
 479                                         OMAP2_CONTROL_MSUSPENDMUX_0);
 480         omap_ctrl_writel(control_context.msuspendmux_1,
 481                                         OMAP2_CONTROL_MSUSPENDMUX_1);
 482         omap_ctrl_writel(control_context.msuspendmux_2,
 483                                         OMAP2_CONTROL_MSUSPENDMUX_2);
 484         omap_ctrl_writel(control_context.msuspendmux_3,
 485                                         OMAP2_CONTROL_MSUSPENDMUX_3);
 486         omap_ctrl_writel(control_context.msuspendmux_4,
 487                                         OMAP2_CONTROL_MSUSPENDMUX_4);
 488         omap_ctrl_writel(control_context.msuspendmux_5,
 489                                         OMAP2_CONTROL_MSUSPENDMUX_5);
 490         omap_ctrl_writel(control_context.sec_ctrl, OMAP2_CONTROL_SEC_CTRL);
 491         omap_ctrl_writel(control_context.devconf1, OMAP343X_CONTROL_DEVCONF1);
 492         omap_ctrl_writel(control_context.csirxfe, OMAP343X_CONTROL_CSIRXFE);
 493         omap_ctrl_writel(control_context.iva2_bootaddr,
 494                                         OMAP343X_CONTROL_IVA2_BOOTADDR);
 495         omap_ctrl_writel(control_context.iva2_bootmod,
 496                                         OMAP343X_CONTROL_IVA2_BOOTMOD);
 497         omap_ctrl_writel(control_context.debobs_0, OMAP343X_CONTROL_DEBOBS(0));
 498         omap_ctrl_writel(control_context.debobs_1, OMAP343X_CONTROL_DEBOBS(1));
 499         omap_ctrl_writel(control_context.debobs_2, OMAP343X_CONTROL_DEBOBS(2));
 500         omap_ctrl_writel(control_context.debobs_3, OMAP343X_CONTROL_DEBOBS(3));
 501         omap_ctrl_writel(control_context.debobs_4, OMAP343X_CONTROL_DEBOBS(4));
 502         omap_ctrl_writel(control_context.debobs_5, OMAP343X_CONTROL_DEBOBS(5));
 503         omap_ctrl_writel(control_context.debobs_6, OMAP343X_CONTROL_DEBOBS(6));
 504         omap_ctrl_writel(control_context.debobs_7, OMAP343X_CONTROL_DEBOBS(7));
 505         omap_ctrl_writel(control_context.debobs_8, OMAP343X_CONTROL_DEBOBS(8));
 506         omap_ctrl_writel(control_context.prog_io0, OMAP343X_CONTROL_PROG_IO0);
 507         omap_ctrl_writel(control_context.prog_io1, OMAP343X_CONTROL_PROG_IO1);
 508         omap_ctrl_writel(control_context.dss_dpll_spreading,
 509                                         OMAP343X_CONTROL_DSS_DPLL_SPREADING);
 510         omap_ctrl_writel(control_context.core_dpll_spreading,
 511                                         OMAP343X_CONTROL_CORE_DPLL_SPREADING);
 512         omap_ctrl_writel(control_context.per_dpll_spreading,
 513                                         OMAP343X_CONTROL_PER_DPLL_SPREADING);
 514         omap_ctrl_writel(control_context.usbhost_dpll_spreading,
 515                                 OMAP343X_CONTROL_USBHOST_DPLL_SPREADING);
 516         omap_ctrl_writel(control_context.pbias_lite,
 517                                         OMAP343X_CONTROL_PBIAS_LITE);
 518         omap_ctrl_writel(control_context.temp_sensor,
 519                                         OMAP343X_CONTROL_TEMP_SENSOR);
 520         omap_ctrl_writel(control_context.sramldo4, OMAP343X_CONTROL_SRAMLDO4);
 521         omap_ctrl_writel(control_context.sramldo5, OMAP343X_CONTROL_SRAMLDO5);
 522         omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
 523         omap_ctrl_writel(control_context.padconf_sys_nirq,
 524                          OMAP343X_CONTROL_PADCONF_SYSNIRQ);
 525         return;
 526 }
 527
 528 void omap3630_ctrl_disable_rta(void)
 529 {
 530         if (!cpu_is_omap3630())
 531                 return;
 532         omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
 533 }
 534
 535 /**
 536  * omap3_ctrl_save_padconf - save padconf registers to scratchpad RAM
 537  *
 538  * Tell the SCM to start saving the padconf registers, then wait for
 539  * the process to complete.  Returns 0 unconditionally, although it
 540  * should also eventually be able to return -ETIMEDOUT, if the save
 541  * does not complete.
 542  *
 543  * XXX This function is missing a timeout.  What should it be?
 544  */
 545 int omap3_ctrl_save_padconf(void)
 546 {
 547         u32 cpo;
 548
 549         /* Save the padconf registers */
 550         cpo = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 551         cpo |= START_PADCONF_SAVE;
 552         omap_ctrl_writel(cpo, OMAP343X_CONTROL_PADCONF_OFF);
 553
 554         /* wait for the save to complete */
 555         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 556                  & PADCONF_SAVE_DONE))
 557                 udelay(1);
 558
 559         return 0;
 560 }
 561
 562 /**
 563  * omap3_ctrl_set_iva_bootmode_idle - sets the IVA2 bootmode to idle
 564  *
 565  * Sets the bootmode for IVA2 to idle. This is needed by the PM code to
 566  * force disable IVA2 so that it does not prevent any low-power states.
 567  */
 568 static void __init omap3_ctrl_set_iva_bootmode_idle(void)
 569 {
 570         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 571                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 572 }
 573
 574 /**
 575  * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle
 576  *
 577  * Sets up the pads controlling the stacked modem in such way that the
 578  * device can enter idle.
 579  */
 580 static void __init omap3_ctrl_setup_d2d_padconf(void)
 581 {
 582         u16 mask, padconf;
 583
 584         /*
 585          * In a stand alone OMAP3430 where there is not a stacked
 586          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 587          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 588          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up.
 589          */
 590         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 591         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 592         padconf |= mask;
 593         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 594
 595         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 596         padconf |= mask;
 597         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 598 }
 599
 600 /**
 601  * omap3_ctrl_init - does static initializations for control module
 602  *
 603  * Initializes system control module. This sets up the sysconfig autoidle,
 604  * and sets up modem and iva2 so that they can be idled properly.
 605  */
 606 void __init omap3_ctrl_init(void)
 607 {
 608         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 609
 610         omap3_ctrl_set_iva_bootmode_idle();
 611
 612         omap3_ctrl_setup_d2d_padconf();
 613 }
 614 #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */