arch/arm/mach-omap2/cm1_44xx.h

   1 /*
   2  * OMAP44xx CM1 instance offset macros
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley (paul@pwsan.com)
   8  * Rajendra Nayak (rnayak@ti.com)
   9  * Benoit Cousson (b-cousson@ti.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  *
  21  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
  22  *     or "OMAP4430".
  23  */
  24
  25 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
  26 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
  27
  28 /* CM1 base address */
  29 #define OMAP4430_CM1_BASE               0x4a004000
  30
  31 #define OMAP44XX_CM1_REGADDR(inst, reg)                         \
  32         OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
  33
  34 /* CM1 instances */
  35 #define OMAP4430_CM1_OCP_SOCKET_INST    0x0000
  36 #define OMAP4430_CM1_CKGEN_INST         0x0100
  37 #define OMAP4430_CM1_MPU_INST           0x0300
  38 #define OMAP4430_CM1_TESLA_INST         0x0400
  39 #define OMAP4430_CM1_ABE_INST           0x0500
  40 #define OMAP4430_CM1_RESTORE_INST       0x0e00
  41 #define OMAP4430_CM1_INSTR_INST         0x0f00
  42
  43 /* CM1 */
  44
  45 /* CM1.OCP_SOCKET_CM1 register offsets */
  46 #define OMAP4_REVISION_CM1_OFFSET                       0x0000
  47 #define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
  48 #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET           0x0040
  49 #define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
  50
  51 /* CM1.CKGEN_CM1 register offsets */
  52 #define OMAP4_CM_CLKSEL_CORE_OFFSET                     0x0000
  53 #define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
  54 #define OMAP4_CM_CLKSEL_ABE_OFFSET                      0x0008
  55 #define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
  56 #define OMAP4_CM_DLL_CTRL_OFFSET                        0x0010
  57 #define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
  58 #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET               0x0020
  59 #define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
  60 #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET                0x0024
  61 #define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
  62 #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET              0x0028
  63 #define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
  64 #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET                0x002c
  65 #define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
  66 #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET                0x0030
  67 #define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
  68 #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET                0x0034
  69 #define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
  70 #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET                0x0038
  71 #define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
  72 #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET                0x003c
  73 #define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
  74 #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET                0x0040
  75 #define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
  76 #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET                0x0044
  77 #define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
  78 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
  79 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
  80 #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET       0x004c
  81 #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
  82 #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
  83 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
  84 #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
  85 #define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
  86 #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET                 0x0064
  87 #define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
  88 #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET               0x0068
  89 #define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
  90 #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET                 0x006c
  91 #define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
  92 #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET                 0x0070
  93 #define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
  94 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
  95 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
  96 #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET                0x008c
  97 #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
  98 #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
  99 #define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
 100 #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
 101 #define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
 102 #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET                 0x00a4
 103 #define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
 104 #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET               0x00a8
 105 #define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
 106 #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET                 0x00ac
 107 #define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
 108 #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET                 0x00b8
 109 #define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
 110 #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET                 0x00bc
 111 #define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
 112 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
 113 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
 114 #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET                0x00cc
 115 #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
 116 #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
 117 #define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
 118 #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
 119 #define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
 120 #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET                 0x00e4
 121 #define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
 122 #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET               0x00e8
 123 #define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
 124 #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET                 0x00ec
 125 #define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
 126 #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET                 0x00f0
 127 #define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
 128 #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET                 0x00f4
 129 #define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
 130 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
 131 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
 132 #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET                0x010c
 133 #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
 134 #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
 135 #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
 136 #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
 137 #define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
 138 #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET            0x0128
 139 #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
 140 #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET              0x012c
 141 #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
 142 #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET              0x0130
 143 #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
 144 #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET              0x0138
 145 #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
 146 #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET              0x013c
 147 #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
 148 #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET              0x0140
 149 #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
 150 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
 151 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
 152 #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET     0x014c
 153 #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
 154 #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
 155 #define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
 156 #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
 157 #define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
 158 #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET                 0x0170
 159 #define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
 160 #define OMAP4_CM_RESTORE_ST_OFFSET                      0x0180
 161 #define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
 162
 163 /* CM1.MPU_CM1 register offsets */
 164 #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET                   0x0000
 165 #define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
 166 #define OMAP4_CM_MPU_STATICDEP_OFFSET                   0x0004
 167 #define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
 168 #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET                  0x0008
 169 #define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
 170 #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET                 0x0020
 171 #define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
 172
 173 /* CM1.TESLA_CM1 register offsets */
 174 #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET                 0x0000
 175 #define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
 176 #define OMAP4_CM_TESLA_STATICDEP_OFFSET                 0x0004
 177 #define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
 178 #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET                0x0008
 179 #define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
 180 #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET             0x0020
 181 #define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
 182
 183 /* CM1.ABE_CM1 register offsets */
 184 #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET                  0x0000
 185 #define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
 186 #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET              0x0020
 187 #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
 188 #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET               0x0028
 189 #define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
 190 #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET                0x0030
 191 #define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
 192 #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET               0x0038
 193 #define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
 194 #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET              0x0040
 195 #define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
 196 #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET             0x0048
 197 #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
 198 #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET             0x0050
 199 #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
 200 #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET             0x0058
 201 #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
 202 #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET            0x0060
 203 #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
 204 #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET             0x0068
 205 #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
 206 #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET             0x0070
 207 #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
 208 #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET             0x0078
 209 #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
 210 #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET             0x0080
 211 #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
 212 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
 213 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
 214
 215 /* CM1.RESTORE_CM1 register offsets */
 216 #define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET             0x0000
 217 #define OMAP4430_CM_CLKSEL_CORE_RESTORE                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
 218 #define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET        0x0004
 219 #define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
 220 #define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET        0x0008
 221 #define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
 222 #define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET        0x000c
 223 #define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
 224 #define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET        0x0010
 225 #define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
 226 #define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET        0x0014
 227 #define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
 228 #define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET        0x0018
 229 #define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
 230 #define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET        0x001c
 231 #define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
 232 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET        0x0020
 233 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
 234 #define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET       0x0024
 235 #define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
 236 #define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET       0x0028
 237 #define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
 238 #define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET     0x002c
 239 #define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
 240 #define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET     0x0030
 241 #define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
 242 #define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET      0x0034
 243 #define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
 244 #define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET           0x0038
 245 #define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
 246 #define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET   0x003c
 247 #define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
 248 #define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET         0x0040
 249 #define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
 250
 251 #endif