2 * OMAP3-specific clock framework functions
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/clk.h>
24 #include <plat/clock.h>
27 #include "clock3xxx.h"
28 #include "prm2xxx_3xxx.h"
29 #include "prm-regbits-34xx.h"
30 #include "cm2xxx_3xxx.h"
31 #include "cm-regbits-34xx.h"
34 * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
35 * that are sourced by DPLL5, and both of these require this clock
36 * to be at 120 MHz for proper operation.
38 #define DPLL5_FREQ_FOR_USBHOST 120000000
40 /* needed by omap3_core_dpll_m2_set_rate() */
41 struct clk *sdrc_ick_p, *arm_fck_p;
43 struct dpll_settings {
48 static int omap3_dpll5_apply_erratum21(struct clk *clk, struct clk *dpll5_m2)
52 static const struct dpll_settings precomputed[] = {
53 /* From DM3730 errata (sprz319e), table 36
54 * N+1 is because the values in the table are register values;
55 * dpll_program() will subtract one from the N we give it,
58 { 13000000, 443, 5+1, 8 },
59 { 26000000, 443, 11+1, 8 }
62 sys_clk = clk_get(NULL, "sys_ck");
64 for (i = 0 ; i < (sizeof(precomputed)/sizeof(struct dpll_settings)) ;
66 const struct dpll_settings *d = &precomputed[i];
67 if (sys_clk->rate == d->rate) {
68 rv = omap3_noncore_dpll_program(clk, d->m , d->n, 0);
71 rv = omap2_clksel_force_divisor(dpll5_m2 , d->f);
78 int omap3_dpll5_set_rate(struct clk *clk, unsigned long rate)
82 dpll5_m2 = clk_get(NULL, "dpll5_m2_ck");
84 if (cpu_is_omap3630() && rate == DPLL5_FREQ_FOR_USBHOST &&
85 omap3_dpll5_apply_erratum21(clk, dpll5_m2)) {
88 rv = omap3_noncore_dpll_set_rate(clk, rate);
91 rv = clk_set_rate(dpll5_m2, rate);
97 int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
100 * According to the 12-5 CDP code from TI, "Limitation 2.5"
101 * on 3430ES1 prevents us from changing DPLL multipliers or dividers
104 if (omap_rev() == OMAP3430_REV_ES1_0) {
105 pr_err("clock: DPLL4 cannot change rate due to "
106 "silicon 'Limitation 2.5' on 3430ES1.\n");
110 return omap3_noncore_dpll_set_rate(clk, rate);
113 void __init omap3_clk_lock_dpll5(void)
115 struct clk *dpll5_clk;
117 dpll5_clk = clk_get(NULL, "dpll5_ck");
118 clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
120 /* dpll5_m2_ck is now (grottily!) handled by dpll5_clk's set routine,
121 * to cope with an erratum on DM3730
127 /* Common clock code */
130 * Switch the MPU rate if specified on cmdline. We cannot do this
131 * early until cmdline is parsed. XXX This should be removed from the
132 * clock code and handled by the OPP layer code in the near future.
134 static int __init omap3xxx_clk_arch_init(void)
138 if (!cpu_is_omap34xx())
141 ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
143 omap2_clk_print_new_rates("osc_sys_ck", "core_ck", "arm_fck");
148 arch_initcall(omap3xxx_clk_arch_init);