arch/arm/mach-omap2/clock34xx.h

   1 /*
   2  * OMAP3 clock framework
   3  *
   4  * Virtual clocks are introduced as a convenient tools.
   5  * They are sources for other clocks and not supposed
   6  * to be requested from drivers directly.
   7  *
   8  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   9  * Copyright (C) 2007-2008 Nokia Corporation
  10  *
  11  * Written by Paul Walmsley
  12  */
  13
  14 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  15 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
  16
  17 #include <asm/arch/control.h>
  18
  19 #include "clock.h"
  20 #include "cm.h"
  21 #include "cm-regbits-34xx.h"
  22 #include "prm.h"
  23 #include "prm-regbits-34xx.h"
  24
  25 static void omap3_dpll_recalc(struct clk *clk);
  26 static void omap3_clkoutx2_recalc(struct clk *clk);
  27
  28 /*
  29  * DPLL1 supplies clock to the MPU.
  30  * DPLL2 supplies clock to the IVA2.
  31  * DPLL3 supplies CORE domain clocks.
  32  * DPLL4 supplies peripheral clocks.
  33  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
  34  */
  35
  36 /* PRM CLOCKS */
  37
  38 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
  39 static struct clk omap_32k_fck = {
  40         .name           = "omap_32k_fck",
  41         .rate           = 32768,
  42         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  43                                 ALWAYS_ENABLED,
  44         .recalc         = &propagate_rate,
  45 };
  46
  47 static struct clk secure_32k_fck = {
  48         .name           = "secure_32k_fck",
  49         .rate           = 32768,
  50         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  51                                 ALWAYS_ENABLED,
  52         .recalc         = &propagate_rate,
  53 };
  54
  55 /* Virtual source clocks for osc_sys_ck */
  56 static struct clk virt_12m_ck = {
  57         .name           = "virt_12m_ck",
  58         .rate           = 12000000,
  59         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  60                                 ALWAYS_ENABLED,
  61         .recalc         = &propagate_rate,
  62 };
  63
  64 static struct clk virt_13m_ck = {
  65         .name           = "virt_13m_ck",
  66         .rate           = 13000000,
  67         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  68                                 ALWAYS_ENABLED,
  69         .recalc         = &propagate_rate,
  70 };
  71
  72 static struct clk virt_16_8m_ck = {
  73         .name           = "virt_16_8m_ck",
  74         .rate           = 16800000,
  75         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
  76                                 ALWAYS_ENABLED,
  77         .recalc         = &propagate_rate,
  78 };
  79
  80 static struct clk virt_19_2m_ck = {
  81         .name           = "virt_19_2m_ck",
  82         .rate           = 19200000,
  83         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  84                                 ALWAYS_ENABLED,
  85         .recalc         = &propagate_rate,
  86 };
  87
  88 static struct clk virt_26m_ck = {
  89         .name           = "virt_26m_ck",
  90         .rate           = 26000000,
  91         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
  92                                 ALWAYS_ENABLED,
  93         .recalc         = &propagate_rate,
  94 };
  95
  96 static struct clk virt_38_4m_ck = {
  97         .name           = "virt_38_4m_ck",
  98         .rate           = 38400000,
  99         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 100                                 ALWAYS_ENABLED,
 101         .recalc         = &propagate_rate,
 102 };
 103
 104 static const struct clksel_rate osc_sys_12m_rates[] = {
 105         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 106         { .div = 0 }
 107 };
 108
 109 static const struct clksel_rate osc_sys_13m_rates[] = {
 110         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 111         { .div = 0 }
 112 };
 113
 114 static const struct clksel_rate osc_sys_16_8m_rates[] = {
 115         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
 116         { .div = 0 }
 117 };
 118
 119 static const struct clksel_rate osc_sys_19_2m_rates[] = {
 120         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 121         { .div = 0 }
 122 };
 123
 124 static const struct clksel_rate osc_sys_26m_rates[] = {
 125         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 126         { .div = 0 }
 127 };
 128
 129 static const struct clksel_rate osc_sys_38_4m_rates[] = {
 130         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
 131         { .div = 0 }
 132 };
 133
 134 static const struct clksel osc_sys_clksel[] = {
 135         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
 136         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
 137         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
 138         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
 139         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
 140         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
 141         { .parent = NULL },
 142 };
 143
 144 /* Oscillator clock */
 145 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
 146 static struct clk osc_sys_ck = {
 147         .name           = "osc_sys_ck",
 148         .init           = &omap2_init_clksel_parent,
 149         .clksel_reg     = OMAP3430_PRM_CLKSEL,
 150         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
 151         .clksel         = osc_sys_clksel,
 152         /* REVISIT: deal with autoextclkmode? */
 153         .flags          = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
 154                                 ALWAYS_ENABLED,
 155         .recalc         = &omap2_clksel_recalc,
 156 };
 157
 158 static const struct clksel_rate div2_rates[] = {
 159         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 160         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 161         { .div = 0 }
 162 };
 163
 164 static const struct clksel sys_clksel[] = {
 165         { .parent = &osc_sys_ck, .rates = div2_rates },
 166         { .parent = NULL }
 167 };
 168
 169 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
 170 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
 171 static struct clk sys_ck = {
 172         .name           = "sys_ck",
 173         .parent         = &osc_sys_ck,
 174         .init           = &omap2_init_clksel_parent,
 175         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
 176         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
 177         .clksel         = sys_clksel,
 178         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 179         .recalc         = &omap2_clksel_recalc,
 180 };
 181
 182 static struct clk sys_altclk = {
 183         .name           = "sys_altclk",
 184         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 185         .recalc         = &propagate_rate,
 186 };
 187
 188 /* Optional external clock input for some McBSPs */
 189 static struct clk mcbsp_clks = {
 190         .name           = "mcbsp_clks",
 191         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 192         .recalc         = &propagate_rate,
 193 };
 194
 195 /* PRM EXTERNAL CLOCK OUTPUT */
 196
 197 static struct clk sys_clkout1 = {
 198         .name           = "sys_clkout1",
 199         .parent         = &osc_sys_ck,
 200         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
 201         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
 202         .flags          = CLOCK_IN_OMAP343X,
 203         .recalc         = &followparent_recalc,
 204 };
 205
 206 /* DPLLS */
 207
 208 /* CM CLOCKS */
 209
 210 static const struct clksel_rate dpll_bypass_rates[] = {
 211         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 212         { .div = 0 }
 213 };
 214
 215 static const struct clksel_rate dpll_locked_rates[] = {
 216         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 217         { .div = 0 }
 218 };
 219
 220 static const struct clksel_rate div16_dpll_rates[] = {
 221         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 222         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 223         { .div = 3, .val = 3, .flags = RATE_IN_343X },
 224         { .div = 4, .val = 4, .flags = RATE_IN_343X },
 225         { .div = 5, .val = 5, .flags = RATE_IN_343X },
 226         { .div = 6, .val = 6, .flags = RATE_IN_343X },
 227         { .div = 7, .val = 7, .flags = RATE_IN_343X },
 228         { .div = 8, .val = 8, .flags = RATE_IN_343X },
 229         { .div = 9, .val = 9, .flags = RATE_IN_343X },
 230         { .div = 10, .val = 10, .flags = RATE_IN_343X },
 231         { .div = 11, .val = 11, .flags = RATE_IN_343X },
 232         { .div = 12, .val = 12, .flags = RATE_IN_343X },
 233         { .div = 13, .val = 13, .flags = RATE_IN_343X },
 234         { .div = 14, .val = 14, .flags = RATE_IN_343X },
 235         { .div = 15, .val = 15, .flags = RATE_IN_343X },
 236         { .div = 16, .val = 16, .flags = RATE_IN_343X },
 237         { .div = 0 }
 238 };
 239
 240 /* DPLL1 */
 241 /* MPU clock source */
 242 /* Type: DPLL */
 243 static const struct dpll_data dpll1_dd = {
 244         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 245         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
 246         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
 247         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
 248         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
 249         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
 250         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
 251         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
 252 };
 253
 254 static struct clk dpll1_ck = {
 255         .name           = "dpll1_ck",
 256         .parent         = &sys_ck,
 257         .dpll_data      = &dpll1_dd,
 258         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 259         .recalc         = &omap3_dpll_recalc,
 260 };
 261
 262 /*
 263  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 264  * DPLL isn't bypassed.
 265  */
 266 static struct clk dpll1_x2_ck = {
 267         .name           = "dpll1_x2_ck",
 268         .parent         = &dpll1_ck,
 269         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 270                                 PARENT_CONTROLS_CLOCK,
 271         .recalc         = &omap3_clkoutx2_recalc,
 272 };
 273
 274 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
 275 static const struct clksel div16_dpll1_x2m2_clksel[] = {
 276         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
 277         { .parent = NULL }
 278 };
 279
 280 /*
 281  * Does not exist in the TRM - needed to separate the M2 divider from
 282  * bypass selection in mpu_ck
 283  */
 284 static struct clk dpll1_x2m2_ck = {
 285         .name           = "dpll1_x2m2_ck",
 286         .parent         = &dpll1_x2_ck,
 287         .init           = &omap2_init_clksel_parent,
 288         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
 289         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
 290         .clksel         = div16_dpll1_x2m2_clksel,
 291         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 292                                 PARENT_CONTROLS_CLOCK,
 293         .recalc         = &omap2_clksel_recalc,
 294 };
 295
 296 /* DPLL2 */
 297 /* IVA2 clock source */
 298 /* Type: DPLL */
 299
 300 static const struct dpll_data dpll2_dd = {
 301         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
 302         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
 303         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
 304         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
 305         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
 306         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
 307         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
 308         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
 309 };
 310
 311 static struct clk dpll2_ck = {
 312         .name           = "dpll2_ck",
 313         .parent         = &sys_ck,
 314         .dpll_data      = &dpll2_dd,
 315         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 316         .recalc         = &omap3_dpll_recalc,
 317 };
 318
 319 static const struct clksel div16_dpll2_m2x2_clksel[] = {
 320         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
 321         { .parent = NULL }
 322 };
 323
 324 /*
 325  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
 326  * or CLKOUTX2. CLKOUT seems most plausible.
 327  */
 328 static struct clk dpll2_m2_ck = {
 329         .name           = "dpll2_m2_ck",
 330         .parent         = &dpll2_ck,
 331         .init           = &omap2_init_clksel_parent,
 332         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
 333                                           OMAP3430_CM_CLKSEL2_PLL),
 334         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
 335         .clksel         = div16_dpll2_m2x2_clksel,
 336         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 337                                 PARENT_CONTROLS_CLOCK,
 338         .recalc         = &omap2_clksel_recalc,
 339 };
 340
 341 /* DPLL3 */
 342 /* Source clock for all interfaces and for some device fclks */
 343 /* Type: DPLL */
 344 static const struct dpll_data dpll3_dd = {
 345         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 346         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
 347         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
 348         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 349         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
 350         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
 351         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
 352         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
 353 };
 354
 355 static struct clk dpll3_ck = {
 356         .name           = "dpll3_ck",
 357         .parent         = &sys_ck,
 358         .dpll_data      = &dpll3_dd,
 359         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 360         .recalc         = &omap3_dpll_recalc,
 361 };
 362
 363 /*
 364  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 365  * DPLL isn't bypassed
 366  */
 367 static struct clk dpll3_x2_ck = {
 368         .name           = "dpll3_x2_ck",
 369         .parent         = &dpll3_ck,
 370         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 371                                 PARENT_CONTROLS_CLOCK,
 372         .recalc         = &omap3_clkoutx2_recalc,
 373 };
 374
 375 static const struct clksel_rate div31_dpll3_rates[] = {
 376         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 377         { .div = 2, .val = 2, .flags = RATE_IN_343X },
 378         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
 379         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
 380         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
 381         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
 382         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
 383         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
 384         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
 385         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
 386         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
 387         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
 388         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
 389         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
 390         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
 391         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
 392         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
 393         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
 394         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
 395         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
 396         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
 397         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
 398         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
 399         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
 400         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
 401         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
 402         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
 403         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
 404         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
 405         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
 406         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
 407         { .div = 0 },
 408 };
 409
 410 static const struct clksel div31_dpll3m2_clksel[] = {
 411         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
 412         { .parent = NULL }
 413 };
 414
 415 /*
 416  * DPLL3 output M2
 417  * REVISIT: This DPLL output divider must be changed in SRAM, so until
 418  * that code is ready, this should remain a 'read-only' clksel clock.
 419  */
 420 static struct clk dpll3_m2_ck = {
 421         .name           = "dpll3_m2_ck",
 422         .parent         = &dpll3_ck,
 423         .init           = &omap2_init_clksel_parent,
 424         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 425         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
 426         .clksel         = div31_dpll3m2_clksel,
 427         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 428                                 PARENT_CONTROLS_CLOCK,
 429         .recalc         = &omap2_clksel_recalc,
 430 };
 431
 432 static const struct clksel core_ck_clksel[] = {
 433         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 434         { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
 435         { .parent = NULL }
 436 };
 437
 438 static struct clk core_ck = {
 439         .name           = "core_ck",
 440         .init           = &omap2_init_clksel_parent,
 441         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 442         .clksel_mask    = OMAP3430_ST_CORE_CLK,
 443         .clksel         = core_ck_clksel,
 444         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 445                                 PARENT_CONTROLS_CLOCK,
 446         .recalc         = &omap2_clksel_recalc,
 447 };
 448
 449 static const struct clksel dpll3_m2x2_ck_clksel[] = {
 450         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 451         { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
 452         { .parent = NULL }
 453 };
 454
 455 static struct clk dpll3_m2x2_ck = {
 456         .name           = "dpll3_m2x2_ck",
 457         .init           = &omap2_init_clksel_parent,
 458         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 459         .clksel_mask    = OMAP3430_ST_CORE_CLK,
 460         .clksel         = dpll3_m2x2_ck_clksel,
 461         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 462                                 PARENT_CONTROLS_CLOCK,
 463         .recalc         = &omap2_clksel_recalc,
 464 };
 465
 466 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 467 static const struct clksel div16_dpll3_clksel[] = {
 468         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
 469         { .parent = NULL }
 470 };
 471
 472 /* This virtual clock is the source for dpll3_m3x2_ck */
 473 static struct clk dpll3_m3_ck = {
 474         .name           = "dpll3_m3_ck",
 475         .parent         = &dpll3_ck,
 476         .init           = &omap2_init_clksel_parent,
 477         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 478         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
 479         .clksel         = div16_dpll3_clksel,
 480         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 481                                 PARENT_CONTROLS_CLOCK,
 482         .recalc         = &omap2_clksel_recalc,
 483 };
 484
 485 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 486 static struct clk dpll3_m3x2_ck = {
 487         .name           = "dpll3_m3x2_ck",
 488         .parent         = &dpll3_m3_ck,
 489         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 490         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
 491         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 492         .recalc         = &omap3_clkoutx2_recalc,
 493 };
 494
 495 static const struct clksel emu_core_alwon_ck_clksel[] = {
 496         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 497         { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
 498         { .parent = NULL }
 499 };
 500
 501 static struct clk emu_core_alwon_ck = {
 502         .name           = "emu_core_alwon_ck",
 503         .parent         = &dpll3_m3x2_ck,
 504         .init           = &omap2_init_clksel_parent,
 505         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 506         .clksel_mask    = OMAP3430_ST_CORE_CLK,
 507         .clksel         = emu_core_alwon_ck_clksel,
 508         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 509                                 PARENT_CONTROLS_CLOCK,
 510         .recalc         = &omap2_clksel_recalc,
 511 };
 512
 513 /* DPLL4 */
 514 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
 515 /* Type: DPLL */
 516 static const struct dpll_data dpll4_dd = {
 517         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
 518         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
 519         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
 520         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 521         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
 522         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
 523         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
 524         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
 525 };
 526
 527 static struct clk dpll4_ck = {
 528         .name           = "dpll4_ck",
 529         .parent         = &sys_ck,
 530         .dpll_data      = &dpll4_dd,
 531         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
 532         .recalc         = &omap3_dpll_recalc,
 533 };
 534
 535 /*
 536  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
 537  * DPLL isn't bypassed --
 538  * XXX does this serve any downstream clocks?
 539  */
 540 static struct clk dpll4_x2_ck = {
 541         .name           = "dpll4_x2_ck",
 542         .parent         = &dpll4_ck,
 543         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 544                                 PARENT_CONTROLS_CLOCK,
 545         .recalc         = &omap3_clkoutx2_recalc,
 546 };
 547
 548 static const struct clksel div16_dpll4_clksel[] = {
 549         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
 550         { .parent = NULL }
 551 };
 552
 553 /* This virtual clock is the source for dpll4_m2x2_ck */
 554 static struct clk dpll4_m2_ck = {
 555         .name           = "dpll4_m2_ck",
 556         .parent         = &dpll4_ck,
 557         .init           = &omap2_init_clksel_parent,
 558         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
 559         .clksel_mask    = OMAP3430_DIV_96M_MASK,
 560         .clksel         = div16_dpll4_clksel,
 561         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 562                                 PARENT_CONTROLS_CLOCK,
 563         .recalc         = &omap2_clksel_recalc,
 564 };
 565
 566 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 567 static struct clk dpll4_m2x2_ck = {
 568         .name           = "dpll4_m2x2_ck",
 569         .parent         = &dpll4_m2_ck,
 570         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 571         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
 572         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 573         .recalc         = &omap3_clkoutx2_recalc,
 574 };
 575
 576 static const struct clksel omap_96m_alwon_fck_clksel[] = {
 577         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 578         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 579         { .parent = NULL }
 580 };
 581
 582 static struct clk omap_96m_alwon_fck = {
 583         .name           = "omap_96m_alwon_fck",
 584         .parent         = &dpll4_m2x2_ck,
 585         .init           = &omap2_init_clksel_parent,
 586         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 587         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
 588         .clksel         = omap_96m_alwon_fck_clksel,
 589         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 590                                  PARENT_CONTROLS_CLOCK,
 591         .recalc         = &omap2_clksel_recalc,
 592 };
 593
 594 static struct clk omap_96m_fck = {
 595         .name           = "omap_96m_fck",
 596         .parent         = &omap_96m_alwon_fck,
 597         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 598                                 PARENT_CONTROLS_CLOCK,
 599         .recalc         = &followparent_recalc,
 600 };
 601
 602 static const struct clksel cm_96m_fck_clksel[] = {
 603         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 604         { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
 605         { .parent = NULL }
 606 };
 607
 608 static struct clk cm_96m_fck = {
 609         .name           = "cm_96m_fck",
 610         .parent         = &dpll4_m2x2_ck,
 611         .init           = &omap2_init_clksel_parent,
 612         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 613         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
 614         .clksel         = cm_96m_fck_clksel,
 615         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 616                                 PARENT_CONTROLS_CLOCK,
 617         .recalc         = &omap2_clksel_recalc,
 618 };
 619
 620 /* This virtual clock is the source for dpll4_m3x2_ck */
 621 static struct clk dpll4_m3_ck = {
 622         .name           = "dpll4_m3_ck",
 623         .parent         = &dpll4_ck,
 624         .init           = &omap2_init_clksel_parent,
 625         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 626         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
 627         .clksel         = div16_dpll4_clksel,
 628         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 629                                 PARENT_CONTROLS_CLOCK,
 630         .recalc         = &omap2_clksel_recalc,
 631 };
 632
 633 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 634 static struct clk dpll4_m3x2_ck = {
 635         .name           = "dpll4_m3x2_ck",
 636         .parent         = &dpll4_m3_ck,
 637         .init           = &omap2_init_clksel_parent,
 638         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 639         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
 640         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 641         .recalc         = &omap3_clkoutx2_recalc,
 642 };
 643
 644 static const struct clksel virt_omap_54m_fck_clksel[] = {
 645         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
 646         { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
 647         { .parent = NULL }
 648 };
 649
 650 static struct clk virt_omap_54m_fck = {
 651         .name           = "virt_omap_54m_fck",
 652         .parent         = &dpll4_m3x2_ck,
 653         .init           = &omap2_init_clksel_parent,
 654         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
 655         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
 656         .clksel         = virt_omap_54m_fck_clksel,
 657         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 658                                 PARENT_CONTROLS_CLOCK,
 659         .recalc         = &omap2_clksel_recalc,
 660 };
 661
 662 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
 663         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 664         { .div = 0 }
 665 };
 666
 667 static const struct clksel_rate omap_54m_alt_rates[] = {
 668         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 669         { .div = 0 }
 670 };
 671
 672 static const struct clksel omap_54m_clksel[] = {
 673         { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
 674         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
 675         { .parent = NULL }
 676 };
 677
 678 static struct clk omap_54m_fck = {
 679         .name           = "omap_54m_fck",
 680         .init           = &omap2_init_clksel_parent,
 681         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 682         .clksel_mask    = OMAP3430_SOURCE_54M,
 683         .clksel         = omap_54m_clksel,
 684         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 685                                 PARENT_CONTROLS_CLOCK,
 686         .recalc         = &omap2_clksel_recalc,
 687 };
 688
 689 static const struct clksel_rate omap_48m_96md2_rates[] = {
 690         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 691         { .div = 0 }
 692 };
 693
 694 static const struct clksel_rate omap_48m_alt_rates[] = {
 695         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 696         { .div = 0 }
 697 };
 698
 699 static const struct clksel omap_48m_clksel[] = {
 700         { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
 701         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
 702         { .parent = NULL }
 703 };
 704
 705 static struct clk omap_48m_fck = {
 706         .name           = "omap_48m_fck",
 707         .init           = &omap2_init_clksel_parent,
 708         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 709         .clksel_mask    = OMAP3430_SOURCE_48M,
 710         .clksel         = omap_48m_clksel,
 711         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 712                                 PARENT_CONTROLS_CLOCK,
 713         .recalc         = &omap2_clksel_recalc,
 714 };
 715
 716 static struct clk omap_12m_fck = {
 717         .name           = "omap_12m_fck",
 718         .parent         = &omap_48m_fck,
 719         .fixed_div      = 4,
 720         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 721                                 PARENT_CONTROLS_CLOCK,
 722         .recalc         = &omap2_fixed_divisor_recalc,
 723 };
 724
 725 /* This virstual clock is the source for dpll4_m4x2_ck */
 726 static struct clk dpll4_m4_ck = {
 727         .name           = "dpll4_m4_ck",
 728         .parent         = &dpll4_ck,
 729         .init           = &omap2_init_clksel_parent,
 730         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
 731         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
 732         .clksel         = div16_dpll4_clksel,
 733         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 734                                 PARENT_CONTROLS_CLOCK,
 735         .recalc         = &omap2_clksel_recalc,
 736 };
 737
 738 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 739 static struct clk dpll4_m4x2_ck = {
 740         .name           = "dpll4_m4x2_ck",
 741         .parent         = &dpll4_m4_ck,
 742         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 743         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 744         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 745         .recalc         = &omap3_clkoutx2_recalc,
 746 };
 747
 748 /* This virtual clock is the source for dpll4_m5x2_ck */
 749 static struct clk dpll4_m5_ck = {
 750         .name           = "dpll4_m5_ck",
 751         .parent         = &dpll4_ck,
 752         .init           = &omap2_init_clksel_parent,
 753         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
 754         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
 755         .clksel         = div16_dpll4_clksel,
 756         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 757                                 PARENT_CONTROLS_CLOCK,
 758         .recalc         = &omap2_clksel_recalc,
 759 };
 760
 761 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 762 static struct clk dpll4_m5x2_ck = {
 763         .name           = "dpll4_m5x2_ck",
 764         .parent         = &dpll4_m5_ck,
 765         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 766         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
 767         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 768         .recalc         = &omap3_clkoutx2_recalc,
 769 };
 770
 771 /* This virtual clock is the source for dpll4_m6x2_ck */
 772 static struct clk dpll4_m6_ck = {
 773         .name           = "dpll4_m6_ck",
 774         .parent         = &dpll4_ck,
 775         .init           = &omap2_init_clksel_parent,
 776         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
 777         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
 778         .clksel         = div16_dpll4_clksel,
 779         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 780                                 PARENT_CONTROLS_CLOCK,
 781         .recalc         = &omap2_clksel_recalc,
 782 };
 783
 784 /* The PWRDN bit is apparently only available on 3430ES2 and above */
 785 static struct clk dpll4_m6x2_ck = {
 786         .name           = "dpll4_m6x2_ck",
 787         .parent         = &dpll4_m6_ck,
 788         .init           = &omap2_init_clksel_parent,
 789         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 790         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
 791         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
 792         .recalc         = &omap3_clkoutx2_recalc,
 793 };
 794
 795 static struct clk emu_per_alwon_ck = {
 796         .name           = "emu_per_alwon_ck",
 797         .parent         = &dpll4_m6x2_ck,
 798         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 799                                 PARENT_CONTROLS_CLOCK,
 800         .recalc         = &followparent_recalc,
 801 };
 802
 803 /* DPLL5 */
 804 /* Supplies 120MHz clock, USIM source clock */
 805 /* Type: DPLL */
 806 /* 3430ES2 only */
 807 static const struct dpll_data dpll5_dd = {
 808         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
 809         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
 810         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
 811         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
 812         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
 813         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
 814         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
 815         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
 816 };
 817
 818 static struct clk dpll5_ck = {
 819         .name           = "dpll5_ck",
 820         .parent         = &sys_ck,
 821         .dpll_data      = &dpll5_dd,
 822         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 823                                 ALWAYS_ENABLED,
 824         .recalc         = &omap3_dpll_recalc,
 825 };
 826
 827 static const struct clksel div16_dpll5_clksel[] = {
 828         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
 829         { .parent = NULL }
 830 };
 831
 832 static struct clk dpll5_m2_ck = {
 833         .name           = "dpll5_m2_ck",
 834         .parent         = &dpll5_ck,
 835         .init           = &omap2_init_clksel_parent,
 836         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
 837         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
 838         .clksel         = div16_dpll5_clksel,
 839         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
 840         .recalc         = &omap2_clksel_recalc,
 841 };
 842
 843 static const struct clksel omap_120m_fck_clksel[] = {
 844         { .parent = &sys_ck,      .rates = dpll_bypass_rates },
 845         { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
 846         { .parent = NULL }
 847 };
 848
 849 static struct clk omap_120m_fck = {
 850         .name           = "omap_120m_fck",
 851         .parent         = &dpll5_m2_ck,
 852         .init           = &omap2_init_clksel_parent,
 853         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
 854         .clksel_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
 855         .clksel         = omap_120m_fck_clksel,
 856         .flags          = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
 857                                 PARENT_CONTROLS_CLOCK,
 858         .recalc         = &omap2_clksel_recalc,
 859 };
 860
 861 /* CM EXTERNAL CLOCK OUTPUTS */
 862
 863 static const struct clksel_rate clkout2_src_core_rates[] = {
 864         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 865         { .div = 0 }
 866 };
 867
 868 static const struct clksel_rate clkout2_src_sys_rates[] = {
 869         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
 870         { .div = 0 }
 871 };
 872
 873 static const struct clksel_rate clkout2_src_96m_rates[] = {
 874         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
 875         { .div = 0 }
 876 };
 877
 878 static const struct clksel_rate clkout2_src_54m_rates[] = {
 879         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
 880         { .div = 0 }
 881 };
 882
 883 static const struct clksel clkout2_src_clksel[] = {
 884         { .parent = &core_ck,             .rates = clkout2_src_core_rates },
 885         { .parent = &sys_ck,              .rates = clkout2_src_sys_rates },
 886         { .parent = &omap_96m_alwon_fck,  .rates = clkout2_src_96m_rates },
 887         { .parent = &omap_54m_fck,        .rates = clkout2_src_54m_rates },
 888         { .parent = NULL }
 889 };
 890
 891 static struct clk clkout2_src_ck = {
 892         .name           = "clkout2_src_ck",
 893         .init           = &omap2_init_clksel_parent,
 894         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
 895         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
 896         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 897         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
 898         .clksel         = clkout2_src_clksel,
 899         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
 900         .recalc         = &omap2_clksel_recalc,
 901 };
 902
 903 static const struct clksel_rate sys_clkout2_rates[] = {
 904         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 905         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 906         { .div = 4, .val = 2, .flags = RATE_IN_343X },
 907         { .div = 8, .val = 3, .flags = RATE_IN_343X },
 908         { .div = 16, .val = 4, .flags = RATE_IN_343X },
 909         { .div = 0 },
 910 };
 911
 912 static const struct clksel sys_clkout2_clksel[] = {
 913         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
 914         { .parent = NULL },
 915 };
 916
 917 static struct clk sys_clkout2 = {
 918         .name           = "sys_clkout2",
 919         .init           = &omap2_init_clksel_parent,
 920         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
 921         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
 922         .clksel         = sys_clkout2_clksel,
 923         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
 924         .recalc         = &omap2_clksel_recalc,
 925 };
 926
 927 /* CM OUTPUT CLOCKS */
 928
 929 static struct clk corex2_fck = {
 930         .name           = "corex2_fck",
 931         .parent         = &dpll3_m2x2_ck,
 932         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 933                                 PARENT_CONTROLS_CLOCK,
 934         .recalc         = &followparent_recalc,
 935 };
 936
 937 /* DPLL power domain clock controls */
 938
 939 static const struct clksel div2_core_clksel[] = {
 940         { .parent = &core_ck, .rates = div2_rates },
 941         { .parent = NULL }
 942 };
 943
 944 /*
 945  * REVISIT: Are these in DPLL power domain or CM power domain? docs
 946  * may be inconsistent here?
 947  */
 948 static struct clk dpll1_fck = {
 949         .name           = "dpll1_fck",
 950         .parent         = &core_ck,
 951         .init           = &omap2_init_clksel_parent,
 952         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
 953         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
 954         .clksel         = div2_core_clksel,
 955         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 956                                 PARENT_CONTROLS_CLOCK,
 957         .recalc         = &omap2_clksel_recalc,
 958 };
 959
 960 /*
 961  * MPU clksel:
 962  * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
 963  * derives from the high-frequency bypass clock originating from DPLL3,
 964  * called 'dpll1_fck'
 965  */
 966 static const struct clksel mpu_clksel[] = {
 967         { .parent = &dpll1_fck,     .rates = dpll_bypass_rates },
 968         { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
 969         { .parent = NULL }
 970 };
 971
 972 static struct clk mpu_ck = {
 973         .name           = "mpu_ck",
 974         .parent         = &dpll1_x2m2_ck,
 975         .init           = &omap2_init_clksel_parent,
 976         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
 977         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
 978         .clksel         = mpu_clksel,
 979         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
 980                                 PARENT_CONTROLS_CLOCK,
 981         .recalc         = &omap2_clksel_recalc,
 982 };
 983
 984 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
 985 static const struct clksel_rate arm_fck_rates[] = {
 986         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
 987         { .div = 2, .val = 1, .flags = RATE_IN_343X },
 988         { .div = 0 },
 989 };
 990
 991 static const struct clksel arm_fck_clksel[] = {
 992         { .parent = &mpu_ck, .rates = arm_fck_rates },
 993         { .parent = NULL }
 994 };
 995
 996 static struct clk arm_fck = {
 997         .name           = "arm_fck",
 998         .parent         = &mpu_ck,
 999         .init           = &omap2_init_clksel_parent,
1000         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1001         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1002         .clksel         = arm_fck_clksel,
1003         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1004                                 PARENT_CONTROLS_CLOCK,
1005         .recalc         = &omap2_clksel_recalc,
1006 };
1007
1008 /*
1009  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1010  * although it is referenced - so this is a guess
1011  */
1012 static struct clk emu_mpu_alwon_ck = {
1013         .name           = "emu_mpu_alwon_ck",
1014         .parent         = &mpu_ck,
1015         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1016                                 PARENT_CONTROLS_CLOCK,
1017         .recalc         = &followparent_recalc,
1018 };
1019
1020 static struct clk dpll2_fck = {
1021         .name           = "dpll2_fck",
1022         .parent         = &core_ck,
1023         .init           = &omap2_init_clksel_parent,
1024         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1025         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1026         .clksel         = div2_core_clksel,
1027         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1028                                 PARENT_CONTROLS_CLOCK,
1029         .recalc         = &omap2_clksel_recalc,
1030 };
1031
1032 /*
1033  * IVA2 clksel:
1034  * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1035  * derives from the high-frequency bypass clock originating from DPLL3,
1036  * called 'dpll2_fck'
1037  */
1038
1039 static const struct clksel iva2_clksel[] = {
1040         { .parent = &dpll2_fck,   .rates = dpll_bypass_rates },
1041         { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1042         { .parent = NULL }
1043 };
1044
1045 static struct clk iva2_ck = {
1046         .name           = "iva2_ck",
1047         .parent         = &dpll2_m2_ck,
1048         .init           = &omap2_init_clksel_parent,
1049         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1050                                           OMAP3430_CM_IDLEST_PLL),
1051         .clksel_mask    = OMAP3430_ST_IVA2_CLK_MASK,
1052         .clksel         = iva2_clksel,
1053         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1054                                 PARENT_CONTROLS_CLOCK,
1055         .recalc         = &omap2_clksel_recalc,
1056 };
1057
1058 /* Common interface clocks */
1059
1060 static struct clk l3_ick = {
1061         .name           = "l3_ick",
1062         .parent         = &core_ck,
1063         .init           = &omap2_init_clksel_parent,
1064         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1065         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1066         .clksel         = div2_core_clksel,
1067         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1068                                 PARENT_CONTROLS_CLOCK,
1069         .recalc         = &omap2_clksel_recalc,
1070 };
1071
1072 static const struct clksel div2_l3_clksel[] = {
1073         { .parent = &l3_ick, .rates = div2_rates },
1074         { .parent = NULL }
1075 };
1076
1077 static struct clk l4_ick = {
1078         .name           = "l4_ick",
1079         .parent         = &l3_ick,
1080         .init           = &omap2_init_clksel_parent,
1081         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1082         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1083         .clksel         = div2_l3_clksel,
1084         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1085                                 PARENT_CONTROLS_CLOCK,
1086         .recalc         = &omap2_clksel_recalc,
1087
1088 };
1089
1090 static const struct clksel div2_l4_clksel[] = {
1091         { .parent = &l4_ick, .rates = div2_rates },
1092         { .parent = NULL }
1093 };
1094
1095 static struct clk rm_ick = {
1096         .name           = "rm_ick",
1097         .parent         = &l4_ick,
1098         .init           = &omap2_init_clksel_parent,
1099         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1100         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1101         .clksel         = div2_l4_clksel,
1102         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1103         .recalc         = &omap2_clksel_recalc,
1104 };
1105
1106 /* GFX power domain */
1107
1108 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1109
1110 static const struct clksel gfx_l3_clksel[] = {
1111         { .parent = &l3_ick, .rates = gfx_l3_rates },
1112         { .parent = NULL }
1113 };
1114
1115 static struct clk gfx_l3_fck = {
1116         .name           = "gfx_l3_fck",
1117         .parent         = &l3_ick,
1118         .init           = &omap2_init_clksel_parent,
1119         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1120         .enable_bit     = OMAP_EN_GFX_SHIFT,
1121         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1122         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1123         .clksel         = gfx_l3_clksel,
1124         .flags          = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1125         .recalc         = &omap2_clksel_recalc,
1126 };
1127
1128 static struct clk gfx_l3_ick = {
1129         .name           = "gfx_l3_ick",
1130         .parent         = &l3_ick,
1131         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1132         .enable_bit     = OMAP_EN_GFX_SHIFT,
1133         .flags          = CLOCK_IN_OMAP3430ES1,
1134         .recalc         = &followparent_recalc,
1135 };
1136
1137 static struct clk gfx_cg1_ck = {
1138         .name           = "gfx_cg1_ck",
1139         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1140         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1141         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1142         .flags          = CLOCK_IN_OMAP3430ES1,
1143         .recalc         = &followparent_recalc,
1144 };
1145
1146 static struct clk gfx_cg2_ck = {
1147         .name           = "gfx_cg2_ck",
1148         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1149         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1150         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1151         .flags          = CLOCK_IN_OMAP3430ES1,
1152         .recalc         = &followparent_recalc,
1153 };
1154
1155 /* SGX power domain - 3430ES2 only */
1156
1157 static const struct clksel_rate sgx_core_rates[] = {
1158         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1159         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1160         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1161         { .div = 0 },
1162 };
1163
1164 static const struct clksel_rate sgx_96m_rates[] = {
1165         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1166         { .div = 0 },
1167 };
1168
1169 static const struct clksel sgx_clksel[] = {
1170         { .parent = &core_ck,    .rates = sgx_core_rates },
1171         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1172         { .parent = NULL },
1173 };
1174
1175 static struct clk sgx_fck = {
1176         .name           = "sgx_fck",
1177         .init           = &omap2_init_clksel_parent,
1178         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1179         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1180         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1181         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1182         .clksel         = sgx_clksel,
1183         .flags          = CLOCK_IN_OMAP3430ES2,
1184         .recalc         = &omap2_clksel_recalc,
1185 };
1186
1187 static struct clk sgx_ick = {
1188         .name           = "sgx_ick",
1189         .parent         = &l3_ick,
1190         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1191         .enable_bit     = OMAP3430ES2_EN_SGX_SHIFT,
1192         .flags          = CLOCK_IN_OMAP3430ES2,
1193         .recalc         = &followparent_recalc,
1194 };
1195
1196 /* CORE power domain */
1197
1198 static struct clk d2d_26m_fck = {
1199         .name           = "d2d_26m_fck",
1200         .parent         = &sys_ck,
1201         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1202         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1203         .flags          = CLOCK_IN_OMAP3430ES1,
1204         .recalc         = &followparent_recalc,
1205 };
1206
1207 static const struct clksel omap343x_gpt_clksel[] = {
1208         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1209         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1210         { .parent = NULL}
1211 };
1212
1213 static struct clk gpt10_fck = {
1214         .name           = "gpt10_fck",
1215         .parent         = &sys_ck,
1216         .init           = &omap2_init_clksel_parent,
1217         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1218         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1219         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1220         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1221         .clksel         = omap343x_gpt_clksel,
1222         .flags          = CLOCK_IN_OMAP343X,
1223         .recalc         = &omap2_clksel_recalc,
1224 };
1225
1226 static struct clk gpt11_fck = {
1227         .name           = "gpt11_fck",
1228         .parent         = &sys_ck,
1229         .init           = &omap2_init_clksel_parent,
1230         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1231         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1232         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1233         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1234         .clksel         = omap343x_gpt_clksel,
1235         .flags          = CLOCK_IN_OMAP343X,
1236         .recalc         = &omap2_clksel_recalc,
1237 };
1238
1239 static struct clk cpefuse_fck = {
1240         .name           = "cpefuse_fck",
1241         .parent         = &sys_ck,
1242         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1243         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1244         .flags          = CLOCK_IN_OMAP3430ES2,
1245         .recalc         = &followparent_recalc,
1246 };
1247
1248 static struct clk ts_fck = {
1249         .name           = "ts_fck",
1250         .parent         = &omap_32k_fck,
1251         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1252         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1253         .flags          = CLOCK_IN_OMAP3430ES2,
1254         .recalc         = &followparent_recalc,
1255 };
1256
1257 static struct clk usbtll_fck = {
1258         .name           = "usbtll_fck",
1259         .parent         = &omap_120m_fck,
1260         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1261         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1262         .flags          = CLOCK_IN_OMAP3430ES2,
1263         .recalc         = &followparent_recalc,
1264 };
1265
1266 /* CORE 96M FCLK-derived clocks */
1267
1268 static struct clk core_96m_fck = {
1269         .name           = "core_96m_fck",
1270         .parent         = &omap_96m_fck,
1271         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1272                                 PARENT_CONTROLS_CLOCK,
1273         .recalc         = &followparent_recalc,
1274 };
1275
1276 static struct clk mmchs3_fck = {
1277         .name           = "mmchs_fck",
1278         .id             = 3,
1279         .parent         = &core_96m_fck,
1280         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1281         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1282         .flags          = CLOCK_IN_OMAP3430ES2,
1283         .recalc         = &followparent_recalc,
1284 };
1285
1286 static struct clk mmchs2_fck = {
1287         .name           = "mmchs_fck",
1288         .id             = 2,
1289         .parent         = &core_96m_fck,
1290         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1291         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1292         .flags          = CLOCK_IN_OMAP343X,
1293         .recalc         = &followparent_recalc,
1294 };
1295
1296 static struct clk mspro_fck = {
1297         .name           = "mspro_fck",
1298         .parent         = &core_96m_fck,
1299         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1300         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1301         .flags          = CLOCK_IN_OMAP343X,
1302         .recalc         = &followparent_recalc,
1303 };
1304
1305 static struct clk mmchs1_fck = {
1306         .name           = "mmchs_fck",
1307         .id             = 1,
1308         .parent         = &core_96m_fck,
1309         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1310         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1311         .flags          = CLOCK_IN_OMAP343X,
1312         .recalc         = &followparent_recalc,
1313 };
1314
1315 static struct clk i2c3_fck = {
1316         .name           = "i2c_fck",
1317         .id             = 3,
1318         .parent         = &core_96m_fck,
1319         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1320         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1321         .flags          = CLOCK_IN_OMAP343X,
1322         .recalc         = &followparent_recalc,
1323 };
1324
1325 static struct clk i2c2_fck = {
1326         .name           = "i2c_fck",
1327         .id             = 2,
1328         .parent         = &core_96m_fck,
1329         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1330         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1331         .flags          = CLOCK_IN_OMAP343X,
1332         .recalc         = &followparent_recalc,
1333 };
1334
1335 static struct clk i2c1_fck = {
1336         .name           = "i2c_fck",
1337         .id             = 1,
1338         .parent         = &core_96m_fck,
1339         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1340         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1341         .flags          = CLOCK_IN_OMAP343X,
1342         .recalc         = &followparent_recalc,
1343 };
1344
1345 /*
1346  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1347  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1348  */
1349 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1350         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1351         { .div = 0 }
1352 };
1353
1354 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1355         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1356         { .div = 0 }
1357 };
1358
1359 static const struct clksel mcbsp_15_clksel[] = {
1360         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1361         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1362         { .parent = NULL }
1363 };
1364
1365 static struct clk mcbsp5_fck = {
1366         .name           = "mcbsp5_fck",
1367         .init           = &omap2_init_clksel_parent,
1368         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1369         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1370         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1371         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1372         .clksel         = mcbsp_15_clksel,
1373         .flags          = CLOCK_IN_OMAP343X,
1374         .recalc         = &omap2_clksel_recalc,
1375 };
1376
1377 static struct clk mcbsp1_fck = {
1378         .name           = "mcbsp1_fck",
1379         .init           = &omap2_init_clksel_parent,
1380         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1381         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1382         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1383         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1384         .clksel         = mcbsp_15_clksel,
1385         .flags          = CLOCK_IN_OMAP343X,
1386         .recalc         = &omap2_clksel_recalc,
1387 };
1388
1389 /* CORE_48M_FCK-derived clocks */
1390
1391 static struct clk core_48m_fck = {
1392         .name           = "core_48m_fck",
1393         .parent         = &omap_48m_fck,
1394         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1395                                 PARENT_CONTROLS_CLOCK,
1396         .recalc         = &followparent_recalc,
1397 };
1398
1399 static struct clk mcspi4_fck = {
1400         .name           = "mcspi_fck",
1401         .id             = 4,
1402         .parent         = &core_48m_fck,
1403         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1404         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1405         .flags          = CLOCK_IN_OMAP343X,
1406         .recalc         = &followparent_recalc,
1407 };
1408
1409 static struct clk mcspi3_fck = {
1410         .name           = "mcspi_fck",
1411         .id             = 3,
1412         .parent         = &core_48m_fck,
1413         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1414         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1415         .flags          = CLOCK_IN_OMAP343X,
1416         .recalc         = &followparent_recalc,
1417 };
1418
1419 static struct clk mcspi2_fck = {
1420         .name           = "mcspi_fck",
1421         .id             = 2,
1422         .parent         = &core_48m_fck,
1423         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1424         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1425         .flags          = CLOCK_IN_OMAP343X,
1426         .recalc         = &followparent_recalc,
1427 };
1428
1429 static struct clk mcspi1_fck = {
1430         .name           = "mcspi_fck",
1431         .id             = 1,
1432         .parent         = &core_48m_fck,
1433         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1434         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1435         .flags          = CLOCK_IN_OMAP343X,
1436         .recalc         = &followparent_recalc,
1437 };
1438
1439 static struct clk uart2_fck = {
1440         .name           = "uart2_fck",
1441         .parent         = &core_48m_fck,
1442         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1443         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1444         .flags          = CLOCK_IN_OMAP343X,
1445         .recalc         = &followparent_recalc,
1446 };
1447
1448 static struct clk uart1_fck = {
1449         .name           = "uart1_fck",
1450         .parent         = &core_48m_fck,
1451         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1452         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1453         .flags          = CLOCK_IN_OMAP343X,
1454         .recalc         = &followparent_recalc,
1455 };
1456
1457 static struct clk fshostusb_fck = {
1458         .name           = "fshostusb_fck",
1459         .parent         = &core_48m_fck,
1460         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1461         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1462         .flags          = CLOCK_IN_OMAP3430ES1,
1463         .recalc         = &followparent_recalc,
1464 };
1465
1466 /* CORE_12M_FCK based clocks */
1467
1468 static struct clk core_12m_fck = {
1469         .name           = "core_12m_fck",
1470         .parent         = &omap_12m_fck,
1471         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1472                                 PARENT_CONTROLS_CLOCK,
1473         .recalc         = &followparent_recalc,
1474 };
1475
1476 static struct clk hdq_fck = {
1477         .name           = "hdq_fck",
1478         .parent         = &core_12m_fck,
1479         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1480         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1481         .flags          = CLOCK_IN_OMAP343X,
1482         .recalc         = &followparent_recalc,
1483 };
1484
1485 /* DPLL3-derived clock */
1486
1487 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1488         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1489         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1490         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1491         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1492         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1493         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1494         { .div = 0 }
1495 };
1496
1497 static const struct clksel ssi_ssr_clksel[] = {
1498         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1499         { .parent = NULL }
1500 };
1501
1502 static struct clk ssi_ssr_fck = {
1503         .name           = "ssi_ssr_fck",
1504         .init           = &omap2_init_clksel_parent,
1505         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1506         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1507         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1508         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1509         .clksel         = ssi_ssr_clksel,
1510         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1511         .recalc         = &omap2_clksel_recalc,
1512 };
1513
1514 static struct clk ssi_sst_fck = {
1515         .name           = "ssi_sst_fck",
1516         .parent         = &ssi_ssr_fck,
1517         .fixed_div      = 2,
1518         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1519         .recalc         = &omap2_fixed_divisor_recalc,
1520 };
1521
1522
1523
1524 /* CORE_L3_ICK based clocks */
1525
1526 static struct clk core_l3_ick = {
1527         .name           = "core_l3_ick",
1528         .parent         = &l3_ick,
1529         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1530                                 PARENT_CONTROLS_CLOCK,
1531         .recalc         = &followparent_recalc,
1532 };
1533
1534 static struct clk hsotgusb_ick = {
1535         .name           = "hsotgusb_ick",
1536         .parent         = &core_l3_ick,
1537         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1538         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1539         .flags          = CLOCK_IN_OMAP343X,
1540         .recalc         = &followparent_recalc,
1541 };
1542
1543 static struct clk sdrc_ick = {
1544         .name           = "sdrc_ick",
1545         .parent         = &core_l3_ick,
1546         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1547         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1548         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1549         .recalc         = &followparent_recalc,
1550 };
1551
1552 static struct clk gpmc_fck = {
1553         .name           = "gpmc_fck",
1554         .parent         = &core_l3_ick,
1555         .flags          = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1556                                 ENABLE_ON_INIT,
1557         .recalc         = &followparent_recalc,
1558 };
1559
1560 /* SECURITY_L3_ICK based clocks */
1561
1562 static struct clk security_l3_ick = {
1563         .name           = "security_l3_ick",
1564         .parent         = &l3_ick,
1565         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1566                                 PARENT_CONTROLS_CLOCK,
1567         .recalc         = &followparent_recalc,
1568 };
1569
1570 static struct clk pka_ick = {
1571         .name           = "pka_ick",
1572         .parent         = &security_l3_ick,
1573         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1574         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1575         .flags          = CLOCK_IN_OMAP343X,
1576         .recalc         = &followparent_recalc,
1577 };
1578
1579 /* CORE_L4_ICK based clocks */
1580
1581 static struct clk core_l4_ick = {
1582         .name           = "core_l4_ick",
1583         .parent         = &l4_ick,
1584         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1585                                 PARENT_CONTROLS_CLOCK,
1586         .recalc         = &followparent_recalc,
1587 };
1588
1589 static struct clk usbtll_ick = {
1590         .name           = "usbtll_ick",
1591         .parent         = &core_l4_ick,
1592         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1593         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1594         .flags          = CLOCK_IN_OMAP3430ES2,
1595         .recalc         = &followparent_recalc,
1596 };
1597
1598 static struct clk mmchs3_ick = {
1599         .name           = "mmchs_ick",
1600         .id             = 3,
1601         .parent         = &core_l4_ick,
1602         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1603         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1604         .flags          = CLOCK_IN_OMAP3430ES2,
1605         .recalc         = &followparent_recalc,
1606 };
1607
1608 /* Intersystem Communication Registers - chassis mode only */
1609 static struct clk icr_ick = {
1610         .name           = "icr_ick",
1611         .parent         = &core_l4_ick,
1612         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1613         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1614         .flags          = CLOCK_IN_OMAP343X,
1615         .recalc         = &followparent_recalc,
1616 };
1617
1618 static struct clk aes2_ick = {
1619         .name           = "aes2_ick",
1620         .parent         = &core_l4_ick,
1621         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1622         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1623         .flags          = CLOCK_IN_OMAP343X,
1624         .recalc         = &followparent_recalc,
1625 };
1626
1627 static struct clk sha12_ick = {
1628         .name           = "sha12_ick",
1629         .parent         = &core_l4_ick,
1630         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1631         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1632         .flags          = CLOCK_IN_OMAP343X,
1633         .recalc         = &followparent_recalc,
1634 };
1635
1636 static struct clk des2_ick = {
1637         .name           = "des2_ick",
1638         .parent         = &core_l4_ick,
1639         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1640         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1641         .flags          = CLOCK_IN_OMAP343X,
1642         .recalc         = &followparent_recalc,
1643 };
1644
1645 static struct clk mmchs2_ick = {
1646         .name           = "mmchs_ick",
1647         .id             = 2,
1648         .parent         = &core_l4_ick,
1649         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1650         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1651         .flags          = CLOCK_IN_OMAP343X,
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk mmchs1_ick = {
1656         .name           = "mmchs_ick",
1657         .id             = 1,
1658         .parent         = &core_l4_ick,
1659         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1660         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1661         .flags          = CLOCK_IN_OMAP343X,
1662         .recalc         = &followparent_recalc,
1663 };
1664
1665 static struct clk mspro_ick = {
1666         .name           = "mspro_ick",
1667         .parent         = &core_l4_ick,
1668         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1669         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1670         .flags          = CLOCK_IN_OMAP343X,
1671         .recalc         = &followparent_recalc,
1672 };
1673
1674 static struct clk hdq_ick = {
1675         .name           = "hdq_ick",
1676         .parent         = &core_l4_ick,
1677         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1678         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1679         .flags          = CLOCK_IN_OMAP343X,
1680         .recalc         = &followparent_recalc,
1681 };
1682
1683 static struct clk mcspi4_ick = {
1684         .name           = "mcspi_ick",
1685         .id             = 4,
1686         .parent         = &core_l4_ick,
1687         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1688         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1689         .flags          = CLOCK_IN_OMAP343X,
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 static struct clk mcspi3_ick = {
1694         .name           = "mcspi_ick",
1695         .id             = 3,
1696         .parent         = &core_l4_ick,
1697         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1698         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1699         .flags          = CLOCK_IN_OMAP343X,
1700         .recalc         = &followparent_recalc,
1701 };
1702
1703 static struct clk mcspi2_ick = {
1704         .name           = "mcspi_ick",
1705         .id             = 2,
1706         .parent         = &core_l4_ick,
1707         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1708         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1709         .flags          = CLOCK_IN_OMAP343X,
1710         .recalc         = &followparent_recalc,
1711 };
1712
1713 static struct clk mcspi1_ick = {
1714         .name           = "mcspi_ick",
1715         .id             = 1,
1716         .parent         = &core_l4_ick,
1717         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1719         .flags          = CLOCK_IN_OMAP343X,
1720         .recalc         = &followparent_recalc,
1721 };
1722
1723 static struct clk i2c3_ick = {
1724         .name           = "i2c_ick",
1725         .id             = 3,
1726         .parent         = &core_l4_ick,
1727         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1728         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1729         .flags          = CLOCK_IN_OMAP343X,
1730         .recalc         = &followparent_recalc,
1731 };
1732
1733 static struct clk i2c2_ick = {
1734         .name           = "i2c_ick",
1735         .id             = 2,
1736         .parent         = &core_l4_ick,
1737         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1738         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1739         .flags          = CLOCK_IN_OMAP343X,
1740         .recalc         = &followparent_recalc,
1741 };
1742
1743 static struct clk i2c1_ick = {
1744         .name           = "i2c_ick",
1745         .id             = 1,
1746         .parent         = &core_l4_ick,
1747         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1748         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1749         .flags          = CLOCK_IN_OMAP343X,
1750         .recalc         = &followparent_recalc,
1751 };
1752
1753 static struct clk uart2_ick = {
1754         .name           = "uart2_ick",
1755         .parent         = &core_l4_ick,
1756         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1757         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1758         .flags          = CLOCK_IN_OMAP343X,
1759         .recalc         = &followparent_recalc,
1760 };
1761
1762 static struct clk uart1_ick = {
1763         .name           = "uart1_ick",
1764         .parent         = &core_l4_ick,
1765         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1766         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1767         .flags          = CLOCK_IN_OMAP343X,
1768         .recalc         = &followparent_recalc,
1769 };
1770
1771 static struct clk gpt11_ick = {
1772         .name           = "gpt11_ick",
1773         .parent         = &core_l4_ick,
1774         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1775         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1776         .flags          = CLOCK_IN_OMAP343X,
1777         .recalc         = &followparent_recalc,
1778 };
1779
1780 static struct clk gpt10_ick = {
1781         .name           = "gpt10_ick",
1782         .parent         = &core_l4_ick,
1783         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1784         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1785         .flags          = CLOCK_IN_OMAP343X,
1786         .recalc         = &followparent_recalc,
1787 };
1788
1789 static struct clk mcbsp5_ick = {
1790         .name           = "mcbsp5_ick",
1791         .parent         = &core_l4_ick,
1792         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1793         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1794         .flags          = CLOCK_IN_OMAP343X,
1795         .recalc         = &followparent_recalc,
1796 };
1797
1798 static struct clk mcbsp1_ick = {
1799         .name           = "mcbsp1_ick",
1800         .parent         = &core_l4_ick,
1801         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1802         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1803         .flags          = CLOCK_IN_OMAP343X,
1804         .recalc         = &followparent_recalc,
1805 };
1806
1807 static struct clk fac_ick = {
1808         .name           = "fac_ick",
1809         .parent         = &core_l4_ick,
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
1812         .flags          = CLOCK_IN_OMAP3430ES1,
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk mailboxes_ick = {
1817         .name           = "mailboxes_ick",
1818         .parent         = &core_l4_ick,
1819         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1820         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
1821         .flags          = CLOCK_IN_OMAP343X,
1822         .recalc         = &followparent_recalc,
1823 };
1824
1825 static struct clk omapctrl_ick = {
1826         .name           = "omapctrl_ick",
1827         .parent         = &core_l4_ick,
1828         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1829         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
1830         .flags          = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1831         .recalc         = &followparent_recalc,
1832 };
1833
1834 /* SSI_L4_ICK based clocks */
1835
1836 static struct clk ssi_l4_ick = {
1837         .name           = "ssi_l4_ick",
1838         .parent         = &l4_ick,
1839         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1840         .recalc         = &followparent_recalc,
1841 };
1842
1843 static struct clk ssi_ick = {
1844         .name           = "ssi_ick",
1845         .parent         = &ssi_l4_ick,
1846         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1847         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1848         .flags          = CLOCK_IN_OMAP343X,
1849         .recalc         = &followparent_recalc,
1850 };
1851
1852 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1853  * but l4_ick makes more sense to me */
1854
1855 static const struct clksel usb_l4_clksel[] = {
1856         { .parent = &l4_ick, .rates = div2_rates },
1857         { .parent = NULL },
1858 };
1859
1860 static struct clk usb_l4_ick = {
1861         .name           = "usb_l4_ick",
1862         .parent         = &l4_ick,
1863         .init           = &omap2_init_clksel_parent,
1864         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1865         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1866         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1867         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1868         .clksel         = usb_l4_clksel,
1869         .flags          = CLOCK_IN_OMAP3430ES1,
1870         .recalc         = &omap2_clksel_recalc,
1871 };
1872
1873 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1874
1875 /* SECURITY_L4_ICK2 based clocks */
1876
1877 static struct clk security_l4_ick2 = {
1878         .name           = "security_l4_ick2",
1879         .parent         = &l4_ick,
1880         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1881                                 PARENT_CONTROLS_CLOCK,
1882         .recalc         = &followparent_recalc,
1883 };
1884
1885 static struct clk aes1_ick = {
1886         .name           = "aes1_ick",
1887         .parent         = &security_l4_ick2,
1888         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1889         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
1890         .flags          = CLOCK_IN_OMAP343X,
1891         .recalc         = &followparent_recalc,
1892 };
1893
1894 static struct clk rng_ick = {
1895         .name           = "rng_ick",
1896         .parent         = &security_l4_ick2,
1897         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1898         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
1899         .flags          = CLOCK_IN_OMAP343X,
1900         .recalc         = &followparent_recalc,
1901 };
1902
1903 static struct clk sha11_ick = {
1904         .name           = "sha11_ick",
1905         .parent         = &security_l4_ick2,
1906         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1907         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
1908         .flags          = CLOCK_IN_OMAP343X,
1909         .recalc         = &followparent_recalc,
1910 };
1911
1912 static struct clk des1_ick = {
1913         .name           = "des1_ick",
1914         .parent         = &security_l4_ick2,
1915         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1916         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
1917         .flags          = CLOCK_IN_OMAP343X,
1918         .recalc         = &followparent_recalc,
1919 };
1920
1921 /* DSS */
1922 static const struct clksel dss1_alwon_fck_clksel[] = {
1923         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
1924         { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
1925         { .parent = NULL }
1926 };
1927
1928 static struct clk dss1_alwon_fck = {
1929         .name           = "dss1_alwon_fck",
1930         .parent         = &dpll4_m4x2_ck,
1931         .init           = &omap2_init_clksel_parent,
1932         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1933         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
1934         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1935         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
1936         .clksel         = dss1_alwon_fck_clksel,
1937         .flags          = CLOCK_IN_OMAP343X,
1938         .recalc         = &omap2_clksel_recalc,
1939 };
1940
1941 static struct clk dss_tv_fck = {
1942         .name           = "dss_tv_fck",
1943         .parent         = &omap_54m_fck,
1944         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1945         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1946         .flags          = CLOCK_IN_OMAP343X,
1947         .recalc         = &followparent_recalc,
1948 };
1949
1950 static struct clk dss_96m_fck = {
1951         .name           = "dss_96m_fck",
1952         .parent         = &omap_96m_fck,
1953         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1954         .enable_bit     = OMAP3430_EN_TV_SHIFT,
1955         .flags          = CLOCK_IN_OMAP343X,
1956         .recalc         = &followparent_recalc,
1957 };
1958
1959 static struct clk dss2_alwon_fck = {
1960         .name           = "dss2_alwon_fck",
1961         .parent         = &sys_ck,
1962         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1963         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
1964         .flags          = CLOCK_IN_OMAP343X,
1965         .recalc         = &followparent_recalc,
1966 };
1967
1968 static struct clk dss_ick = {
1969         /* Handles both L3 and L4 clocks */
1970         .name           = "dss_ick",
1971         .parent         = &l4_ick,
1972         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
1973         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
1974         .flags          = CLOCK_IN_OMAP343X,
1975         .recalc         = &followparent_recalc,
1976 };
1977
1978 /* CAM */
1979
1980 static const struct clksel cam_mclk_clksel[] = {
1981         { .parent = &sys_ck,        .rates = dpll_bypass_rates },
1982         { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
1983         { .parent = NULL }
1984 };
1985
1986 static struct clk cam_mclk = {
1987         .name           = "cam_mclk",
1988         .parent         = &dpll4_m5x2_ck,
1989         .init           = &omap2_init_clksel_parent,
1990         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1991         .clksel_mask    = OMAP3430_ST_PERIPH_CLK,
1992         .clksel         = cam_mclk_clksel,
1993         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1994         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
1995         .flags          = CLOCK_IN_OMAP343X,
1996         .recalc         = &omap2_clksel_recalc,
1997 };
1998
1999 static struct clk cam_l3_ick = {
2000         .name           = "cam_l3_ick",
2001         .parent         = &l3_ick,
2002         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2003         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2004         .flags          = CLOCK_IN_OMAP343X,
2005         .recalc         = &followparent_recalc,
2006 };
2007
2008 static struct clk cam_l4_ick = {
2009         .name           = "cam_l4_ick",
2010         .parent         = &l4_ick,
2011         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2012         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2013         .flags          = CLOCK_IN_OMAP343X,
2014         .recalc         = &followparent_recalc,
2015 };
2016
2017 /* USBHOST - 3430ES2 only */
2018
2019 static struct clk usbhost_120m_fck = {
2020         .name           = "usbhost_120m_fck",
2021         .parent         = &omap_120m_fck,
2022         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2023         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2024         .flags          = CLOCK_IN_OMAP3430ES2,
2025         .recalc         = &followparent_recalc,
2026 };
2027
2028 static struct clk usbhost_48m_fck = {
2029         .name           = "usbhost_48m_fck",
2030         .parent         = &omap_48m_fck,
2031         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2032         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2033         .flags          = CLOCK_IN_OMAP3430ES2,
2034         .recalc         = &followparent_recalc,
2035 };
2036
2037 static struct clk usbhost_l3_ick = {
2038         .name           = "usbhost_l3_ick",
2039         .parent         = &l3_ick,
2040         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2041         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2042         .flags          = CLOCK_IN_OMAP3430ES2,
2043         .recalc         = &followparent_recalc,
2044 };
2045
2046 static struct clk usbhost_l4_ick = {
2047         .name           = "usbhost_l4_ick",
2048         .parent         = &l4_ick,
2049         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2050         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2051         .flags          = CLOCK_IN_OMAP3430ES2,
2052         .recalc         = &followparent_recalc,
2053 };
2054
2055 static struct clk usbhost_sar_fck = {
2056         .name           = "usbhost_sar_fck",
2057         .parent         = &osc_sys_ck,
2058         .enable_reg     = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2059         .enable_bit     = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2060         .flags          = CLOCK_IN_OMAP3430ES2,
2061         .recalc         = &followparent_recalc,
2062 };
2063
2064 /* WKUP */
2065
2066 static const struct clksel_rate usim_96m_rates[] = {
2067         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2068         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2069         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2070         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2071         { .div = 0 },
2072 };
2073
2074 static const struct clksel_rate usim_120m_rates[] = {
2075         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2076         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2077         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2078         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2079         { .div = 0 },
2080 };
2081
2082 static const struct clksel usim_clksel[] = {
2083         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2084         { .parent = &omap_120m_fck,     .rates = usim_120m_rates },
2085         { .parent = &sys_ck,            .rates = div2_rates },
2086         { .parent = NULL },
2087 };
2088
2089 /* 3430ES2 only */
2090 static struct clk usim_fck = {
2091         .name           = "usim_fck",
2092         .init           = &omap2_init_clksel_parent,
2093         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2094         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2095         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2096         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2097         .clksel         = usim_clksel,
2098         .flags          = CLOCK_IN_OMAP3430ES2,
2099         .recalc         = &omap2_clksel_recalc,
2100 };
2101
2102 static struct clk gpt1_fck = {
2103         .name           = "gpt1_fck",
2104         .init           = &omap2_init_clksel_parent,
2105         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2106         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2107         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2108         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2109         .clksel         = omap343x_gpt_clksel,
2110         .flags          = CLOCK_IN_OMAP343X,
2111         .recalc         = &omap2_clksel_recalc,
2112 };
2113
2114 static struct clk wkup_32k_fck = {
2115         .name           = "wkup_32k_fck",
2116         .parent         = &omap_32k_fck,
2117         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2118         .recalc         = &followparent_recalc,
2119 };
2120
2121 static struct clk gpio1_fck = {
2122         .name           = "gpio1_fck",
2123         .parent         = &wkup_32k_fck,
2124         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2125         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2126         .flags          = CLOCK_IN_OMAP343X,
2127         .recalc         = &followparent_recalc,
2128 };
2129
2130 static struct clk wdt2_fck = {
2131         .name           = "wdt2_fck",
2132         .parent         = &wkup_32k_fck,
2133         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2134         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2135         .flags          = CLOCK_IN_OMAP343X,
2136         .recalc         = &followparent_recalc,
2137 };
2138
2139 static struct clk wkup_l4_ick = {
2140         .name           = "wkup_l4_ick",
2141         .parent         = &sys_ck,
2142         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2143         .recalc         = &followparent_recalc,
2144 };
2145
2146 /* 3430ES2 only */
2147 /* Never specifically named in the TRM, so we have to infer a likely name */
2148 static struct clk usim_ick = {
2149         .name           = "usim_ick",
2150         .parent         = &wkup_l4_ick,
2151         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2152         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2153         .flags          = CLOCK_IN_OMAP3430ES2,
2154         .recalc         = &followparent_recalc,
2155 };
2156
2157 static struct clk wdt2_ick = {
2158         .name           = "wdt2_ick",
2159         .parent         = &wkup_l4_ick,
2160         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2161         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2162         .flags          = CLOCK_IN_OMAP343X,
2163         .recalc         = &followparent_recalc,
2164 };
2165
2166 static struct clk wdt1_ick = {
2167         .name           = "wdt1_ick",
2168         .parent         = &wkup_l4_ick,
2169         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2170         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2171         .flags          = CLOCK_IN_OMAP343X,
2172         .recalc         = &followparent_recalc,
2173 };
2174
2175 static struct clk gpio1_ick = {
2176         .name           = "gpio1_ick",
2177         .parent         = &wkup_l4_ick,
2178         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2179         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2180         .flags          = CLOCK_IN_OMAP343X,
2181         .recalc         = &followparent_recalc,
2182 };
2183
2184 static struct clk omap_32ksync_ick = {
2185         .name           = "omap_32ksync_ick",
2186         .parent         = &wkup_l4_ick,
2187         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2188         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2189         .flags          = CLOCK_IN_OMAP343X,
2190         .recalc         = &followparent_recalc,
2191 };
2192
2193 static struct clk gpt12_ick = {
2194         .name           = "gpt12_ick",
2195         .parent         = &wkup_l4_ick,
2196         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2197         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2198         .flags          = CLOCK_IN_OMAP343X,
2199         .recalc         = &followparent_recalc,
2200 };
2201
2202 static struct clk gpt1_ick = {
2203         .name           = "gpt1_ick",
2204         .parent         = &wkup_l4_ick,
2205         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2206         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2207         .flags          = CLOCK_IN_OMAP343X,
2208         .recalc         = &followparent_recalc,
2209 };
2210
2211
2212
2213 /* PER clock domain */
2214
2215 static struct clk per_96m_fck = {
2216         .name           = "per_96m_fck",
2217         .parent         = &omap_96m_alwon_fck,
2218         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2219                                 PARENT_CONTROLS_CLOCK,
2220         .recalc         = &followparent_recalc,
2221 };
2222
2223 static struct clk per_48m_fck = {
2224         .name           = "per_48m_fck",
2225         .parent         = &omap_48m_fck,
2226         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2227                                 PARENT_CONTROLS_CLOCK,
2228         .recalc         = &followparent_recalc,
2229 };
2230
2231 static struct clk uart3_fck = {
2232         .name           = "uart3_fck",
2233         .parent         = &per_48m_fck,
2234         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2235         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2236         .flags          = CLOCK_IN_OMAP343X,
2237         .recalc         = &followparent_recalc,
2238 };
2239
2240 static struct clk gpt2_fck = {
2241         .name           = "gpt2_fck",
2242         .init           = &omap2_init_clksel_parent,
2243         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2244         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2245         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2246         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2247         .clksel         = omap343x_gpt_clksel,
2248         .flags          = CLOCK_IN_OMAP343X,
2249         .recalc         = &omap2_clksel_recalc,
2250 };
2251
2252 static struct clk gpt3_fck = {
2253         .name           = "gpt3_fck",
2254         .init           = &omap2_init_clksel_parent,
2255         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2256         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2257         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2258         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2259         .clksel         = omap343x_gpt_clksel,
2260         .flags          = CLOCK_IN_OMAP343X,
2261         .recalc         = &omap2_clksel_recalc,
2262 };
2263
2264 static struct clk gpt4_fck = {
2265         .name           = "gpt4_fck",
2266         .init           = &omap2_init_clksel_parent,
2267         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2268         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2269         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2270         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2271         .clksel         = omap343x_gpt_clksel,
2272         .flags          = CLOCK_IN_OMAP343X,
2273         .recalc         = &omap2_clksel_recalc,
2274 };
2275
2276 static struct clk gpt5_fck = {
2277         .name           = "gpt5_fck",
2278         .init           = &omap2_init_clksel_parent,
2279         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2280         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2281         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2282         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2283         .clksel         = omap343x_gpt_clksel,
2284         .flags          = CLOCK_IN_OMAP343X,
2285         .recalc         = &omap2_clksel_recalc,
2286 };
2287
2288 static struct clk gpt6_fck = {
2289         .name           = "gpt6_fck",
2290         .init           = &omap2_init_clksel_parent,
2291         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2292         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2293         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2294         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2295         .clksel         = omap343x_gpt_clksel,
2296         .flags          = CLOCK_IN_OMAP343X,
2297         .recalc         = &omap2_clksel_recalc,
2298 };
2299
2300 static struct clk gpt7_fck = {
2301         .name           = "gpt7_fck",
2302         .init           = &omap2_init_clksel_parent,
2303         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2304         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2305         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2306         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2307         .clksel         = omap343x_gpt_clksel,
2308         .flags          = CLOCK_IN_OMAP343X,
2309         .recalc         = &omap2_clksel_recalc,
2310 };
2311
2312 static struct clk gpt8_fck = {
2313         .name           = "gpt8_fck",
2314         .init           = &omap2_init_clksel_parent,
2315         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2316         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2317         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2318         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2319         .clksel         = omap343x_gpt_clksel,
2320         .flags          = CLOCK_IN_OMAP343X,
2321         .recalc         = &omap2_clksel_recalc,
2322 };
2323
2324 static struct clk gpt9_fck = {
2325         .name           = "gpt9_fck",
2326         .init           = &omap2_init_clksel_parent,
2327         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2328         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2329         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2330         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2331         .clksel         = omap343x_gpt_clksel,
2332         .flags          = CLOCK_IN_OMAP343X,
2333         .recalc         = &omap2_clksel_recalc,
2334 };
2335
2336 static struct clk per_32k_alwon_fck = {
2337         .name           = "per_32k_alwon_fck",
2338         .parent         = &omap_32k_fck,
2339         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2340         .recalc         = &followparent_recalc,
2341 };
2342
2343 static struct clk gpio6_fck = {
2344         .name           = "gpio6_fck",
2345         .parent         = &per_32k_alwon_fck,
2346         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2347         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2348         .flags          = CLOCK_IN_OMAP343X,
2349         .recalc         = &followparent_recalc,
2350 };
2351
2352 static struct clk gpio5_fck = {
2353         .name           = "gpio5_fck",
2354         .parent         = &per_32k_alwon_fck,
2355         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2356         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2357         .flags          = CLOCK_IN_OMAP343X,
2358         .recalc         = &followparent_recalc,
2359 };
2360
2361 static struct clk gpio4_fck = {
2362         .name           = "gpio4_fck",
2363         .parent         = &per_32k_alwon_fck,
2364         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2365         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2366         .flags          = CLOCK_IN_OMAP343X,
2367         .recalc         = &followparent_recalc,
2368 };
2369
2370 static struct clk gpio3_fck = {
2371         .name           = "gpio3_fck",
2372         .parent         = &per_32k_alwon_fck,
2373         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2374         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2375         .flags          = CLOCK_IN_OMAP343X,
2376         .recalc         = &followparent_recalc,
2377 };
2378
2379 static struct clk gpio2_fck = {
2380         .name           = "gpio2_fck",
2381         .parent         = &per_32k_alwon_fck,
2382         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2383         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2384         .flags          = CLOCK_IN_OMAP343X,
2385         .recalc         = &followparent_recalc,
2386 };
2387
2388 static struct clk wdt3_fck = {
2389         .name           = "wdt3_fck",
2390         .parent         = &per_32k_alwon_fck,
2391         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2392         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2393         .flags          = CLOCK_IN_OMAP343X,
2394         .recalc         = &followparent_recalc,
2395 };
2396
2397 static struct clk per_l4_ick = {
2398         .name           = "per_l4_ick",
2399         .parent         = &l4_ick,
2400         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2401                                 PARENT_CONTROLS_CLOCK,
2402         .recalc         = &followparent_recalc,
2403 };
2404
2405 static struct clk gpio6_ick = {
2406         .name           = "gpio6_ick",
2407         .parent         = &per_l4_ick,
2408         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2409         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2410         .flags          = CLOCK_IN_OMAP343X,
2411         .recalc         = &followparent_recalc,
2412 };
2413
2414 static struct clk gpio5_ick = {
2415         .name           = "gpio5_ick",
2416         .parent         = &per_l4_ick,
2417         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2418         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2419         .flags          = CLOCK_IN_OMAP343X,
2420         .recalc         = &followparent_recalc,
2421 };
2422
2423 static struct clk gpio4_ick = {
2424         .name           = "gpio4_ick",
2425         .parent         = &per_l4_ick,
2426         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2427         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2428         .flags          = CLOCK_IN_OMAP343X,
2429         .recalc         = &followparent_recalc,
2430 };
2431
2432 static struct clk gpio3_ick = {
2433         .name           = "gpio3_ick",
2434         .parent         = &per_l4_ick,
2435         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2436         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2437         .flags          = CLOCK_IN_OMAP343X,
2438         .recalc         = &followparent_recalc,
2439 };
2440
2441 static struct clk gpio2_ick = {
2442         .name           = "gpio2_ick",
2443         .parent         = &per_l4_ick,
2444         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2445         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2446         .flags          = CLOCK_IN_OMAP343X,
2447         .recalc         = &followparent_recalc,
2448 };
2449
2450 static struct clk wdt3_ick = {
2451         .name           = "wdt3_ick",
2452         .parent         = &per_l4_ick,
2453         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2454         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2455         .flags          = CLOCK_IN_OMAP343X,
2456         .recalc         = &followparent_recalc,
2457 };
2458
2459 static struct clk uart3_ick = {
2460         .name           = "uart3_ick",
2461         .parent         = &per_l4_ick,
2462         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2463         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2464         .flags          = CLOCK_IN_OMAP343X,
2465         .recalc         = &followparent_recalc,
2466 };
2467
2468 static struct clk gpt9_ick = {
2469         .name           = "gpt9_ick",
2470         .parent         = &per_l4_ick,
2471         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2472         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2473         .flags          = CLOCK_IN_OMAP343X,
2474         .recalc         = &followparent_recalc,
2475 };
2476
2477 static struct clk gpt8_ick = {
2478         .name           = "gpt8_ick",
2479         .parent         = &per_l4_ick,
2480         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2481         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2482         .flags          = CLOCK_IN_OMAP343X,
2483         .recalc         = &followparent_recalc,
2484 };
2485
2486 static struct clk gpt7_ick = {
2487         .name           = "gpt7_ick",
2488         .parent         = &per_l4_ick,
2489         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2490         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2491         .flags          = CLOCK_IN_OMAP343X,
2492         .recalc         = &followparent_recalc,
2493 };
2494
2495 static struct clk gpt6_ick = {
2496         .name           = "gpt6_ick",
2497         .parent         = &per_l4_ick,
2498         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2499         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2500         .flags          = CLOCK_IN_OMAP343X,
2501         .recalc         = &followparent_recalc,
2502 };
2503
2504 static struct clk gpt5_ick = {
2505         .name           = "gpt5_ick",
2506         .parent         = &per_l4_ick,
2507         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2508         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2509         .flags          = CLOCK_IN_OMAP343X,
2510         .recalc         = &followparent_recalc,
2511 };
2512
2513 static struct clk gpt4_ick = {
2514         .name           = "gpt4_ick",
2515         .parent         = &per_l4_ick,
2516         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2517         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2518         .flags          = CLOCK_IN_OMAP343X,
2519         .recalc         = &followparent_recalc,
2520 };
2521
2522 static struct clk gpt3_ick = {
2523         .name           = "gpt3_ick",
2524         .parent         = &per_l4_ick,
2525         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2526         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2527         .flags          = CLOCK_IN_OMAP343X,
2528         .recalc         = &followparent_recalc,
2529 };
2530
2531 static struct clk gpt2_ick = {
2532         .name           = "gpt2_ick",
2533         .parent         = &per_l4_ick,
2534         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2535         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2536         .flags          = CLOCK_IN_OMAP343X,
2537         .recalc         = &followparent_recalc,
2538 };
2539
2540 static struct clk mcbsp2_ick = {
2541         .name           = "mcbsp2_ick",
2542         .parent         = &per_l4_ick,
2543         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2544         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2545         .flags          = CLOCK_IN_OMAP343X,
2546         .recalc         = &followparent_recalc,
2547 };
2548
2549 static struct clk mcbsp3_ick = {
2550         .name           = "mcbsp3_ick",
2551         .parent         = &per_l4_ick,
2552         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2553         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2554         .flags          = CLOCK_IN_OMAP343X,
2555         .recalc         = &followparent_recalc,
2556 };
2557
2558 static struct clk mcbsp4_ick = {
2559         .name           = "mcbsp4_ick",
2560         .parent         = &per_l4_ick,
2561         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2562         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2563         .flags          = CLOCK_IN_OMAP343X,
2564         .recalc         = &followparent_recalc,
2565 };
2566
2567 static const struct clksel mcbsp_234_clksel[] = {
2568         { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2569         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2570         { .parent = NULL }
2571 };
2572
2573 static struct clk mcbsp2_fck = {
2574         .name           = "mcbsp2_fck",
2575         .init           = &omap2_init_clksel_parent,
2576         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2577         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2578         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2579         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2580         .clksel         = mcbsp_234_clksel,
2581         .flags          = CLOCK_IN_OMAP343X,
2582         .recalc         = &omap2_clksel_recalc,
2583 };
2584
2585 static struct clk mcbsp3_fck = {
2586         .name           = "mcbsp3_fck",
2587         .init           = &omap2_init_clksel_parent,
2588         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2589         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2590         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2591         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2592         .clksel         = mcbsp_234_clksel,
2593         .flags          = CLOCK_IN_OMAP343X,
2594         .recalc         = &omap2_clksel_recalc,
2595 };
2596
2597 static struct clk mcbsp4_fck = {
2598         .name           = "mcbsp4_fck",
2599         .init           = &omap2_init_clksel_parent,
2600         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2601         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2602         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2603         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2604         .clksel         = mcbsp_234_clksel,
2605         .flags          = CLOCK_IN_OMAP343X,
2606         .recalc         = &omap2_clksel_recalc,
2607 };
2608
2609 /* EMU clocks */
2610
2611 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2612
2613 static const struct clksel_rate emu_src_sys_rates[] = {
2614         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2615         { .div = 0 },
2616 };
2617
2618 static const struct clksel_rate emu_src_core_rates[] = {
2619         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2620         { .div = 0 },
2621 };
2622
2623 static const struct clksel_rate emu_src_per_rates[] = {
2624         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2625         { .div = 0 },
2626 };
2627
2628 static const struct clksel_rate emu_src_mpu_rates[] = {
2629         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2630         { .div = 0 },
2631 };
2632
2633 static const struct clksel emu_src_clksel[] = {
2634         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2635         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2636         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2637         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2638         { .parent = NULL },
2639 };
2640
2641 /*
2642  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2643  * to switch the source of some of the EMU clocks.
2644  * XXX Are there CLKEN bits for these EMU clks?
2645  */
2646 static struct clk emu_src_ck = {
2647         .name           = "emu_src_ck",
2648         .init           = &omap2_init_clksel_parent,
2649         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2650         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2651         .clksel         = emu_src_clksel,
2652         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2653         .recalc         = &omap2_clksel_recalc,
2654 };
2655
2656 static const struct clksel_rate pclk_emu_rates[] = {
2657         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2658         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2659         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2660         { .div = 6, .val = 6, .flags = RATE_IN_343X },
2661         { .div = 0 },
2662 };
2663
2664 static const struct clksel pclk_emu_clksel[] = {
2665         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2666         { .parent = NULL },
2667 };
2668
2669 static struct clk pclk_fck = {
2670         .name           = "pclk_fck",
2671         .init           = &omap2_init_clksel_parent,
2672         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2673         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
2674         .clksel         = pclk_emu_clksel,
2675         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2676         .recalc         = &omap2_clksel_recalc,
2677 };
2678
2679 static const struct clksel_rate pclkx2_emu_rates[] = {
2680         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2681         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2682         { .div = 3, .val = 3, .flags = RATE_IN_343X },
2683         { .div = 0 },
2684 };
2685
2686 static const struct clksel pclkx2_emu_clksel[] = {
2687         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2688         { .parent = NULL },
2689 };
2690
2691 static struct clk pclkx2_fck = {
2692         .name           = "pclkx2_fck",
2693         .init           = &omap2_init_clksel_parent,
2694         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2695         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
2696         .clksel         = pclkx2_emu_clksel,
2697         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2698         .recalc         = &omap2_clksel_recalc,
2699 };
2700
2701 static const struct clksel atclk_emu_clksel[] = {
2702         { .parent = &emu_src_ck, .rates = div2_rates },
2703         { .parent = NULL },
2704 };
2705
2706 static struct clk atclk_fck = {
2707         .name           = "atclk_fck",
2708         .init           = &omap2_init_clksel_parent,
2709         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2710         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
2711         .clksel         = atclk_emu_clksel,
2712         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2713         .recalc         = &omap2_clksel_recalc,
2714 };
2715
2716 static struct clk traceclk_src_fck = {
2717         .name           = "traceclk_src_fck",
2718         .init           = &omap2_init_clksel_parent,
2719         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2720         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
2721         .clksel         = emu_src_clksel,
2722         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2723         .recalc         = &omap2_clksel_recalc,
2724 };
2725
2726 static const struct clksel_rate traceclk_rates[] = {
2727         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2728         { .div = 2, .val = 2, .flags = RATE_IN_343X },
2729         { .div = 4, .val = 4, .flags = RATE_IN_343X },
2730         { .div = 0 },
2731 };
2732
2733 static const struct clksel traceclk_clksel[] = {
2734         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2735         { .parent = NULL },
2736 };
2737
2738 static struct clk traceclk_fck = {
2739         .name           = "traceclk_fck",
2740         .init           = &omap2_init_clksel_parent,
2741         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2742         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
2743         .clksel         = traceclk_clksel,
2744         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2745         .recalc         = &omap2_clksel_recalc,
2746 };
2747
2748 /* SR clocks */
2749
2750 /* SmartReflex fclk (VDD1) */
2751 static struct clk sr1_fck = {
2752         .name           = "sr1_fck",
2753         .parent         = &sys_ck,
2754         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2755         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
2756         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2757         .recalc         = &followparent_recalc,
2758 };
2759
2760 /* SmartReflex fclk (VDD2) */
2761 static struct clk sr2_fck = {
2762         .name           = "sr2_fck",
2763         .parent         = &sys_ck,
2764         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2765         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
2766         .flags          = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2767         .recalc         = &followparent_recalc,
2768 };
2769
2770 static struct clk sr_l4_ick = {
2771         .name           = "sr_l4_ick",
2772         .parent         = &l4_ick,
2773         .flags          = CLOCK_IN_OMAP343X,
2774         .recalc         = &followparent_recalc,
2775 };
2776
2777 /* SECURE_32K_FCK clocks */
2778
2779 static struct clk gpt12_fck = {
2780         .name           = "gpt12_fck",
2781         .parent         = &secure_32k_fck,
2782         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2783         .recalc         = &followparent_recalc,
2784 };
2785
2786 static struct clk wdt1_fck = {
2787         .name           = "wdt1_fck",
2788         .parent         = &secure_32k_fck,
2789         .flags          = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2790         .recalc         = &followparent_recalc,
2791 };
2792
2793 static struct clk *onchip_34xx_clks[] __initdata = {
2794         &omap_32k_fck,
2795         &virt_12m_ck,
2796         &virt_13m_ck,
2797         &virt_16_8m_ck,
2798         &virt_19_2m_ck,
2799         &virt_26m_ck,
2800         &virt_38_4m_ck,
2801         &osc_sys_ck,
2802         &sys_ck,
2803         &sys_altclk,
2804         &mcbsp_clks,
2805         &sys_clkout1,
2806         &dpll1_ck,
2807         &dpll1_x2_ck,
2808         &dpll1_x2m2_ck,
2809         &dpll2_ck,
2810         &dpll2_m2_ck,
2811         &dpll3_ck,
2812         &core_ck,
2813         &dpll3_x2_ck,
2814         &dpll3_m2_ck,
2815         &dpll3_m2x2_ck,
2816         &dpll3_m3_ck,
2817         &dpll3_m3x2_ck,
2818         &emu_core_alwon_ck,
2819         &dpll4_ck,
2820         &dpll4_x2_ck,
2821         &omap_96m_alwon_fck,
2822         &omap_96m_fck,
2823         &cm_96m_fck,
2824         &virt_omap_54m_fck,
2825         &omap_54m_fck,
2826         &omap_48m_fck,
2827         &omap_12m_fck,
2828         &dpll4_m2_ck,
2829         &dpll4_m2x2_ck,
2830         &dpll4_m3_ck,
2831         &dpll4_m3x2_ck,
2832         &dpll4_m4_ck,
2833         &dpll4_m4x2_ck,
2834         &dpll4_m5_ck,
2835         &dpll4_m5x2_ck,
2836         &dpll4_m6_ck,
2837         &dpll4_m6x2_ck,
2838         &emu_per_alwon_ck,
2839         &dpll5_ck,
2840         &dpll5_m2_ck,
2841         &omap_120m_fck,
2842         &clkout2_src_ck,
2843         &sys_clkout2,
2844         &corex2_fck,
2845         &dpll1_fck,
2846         &mpu_ck,
2847         &arm_fck,
2848         &emu_mpu_alwon_ck,
2849         &dpll2_fck,
2850         &iva2_ck,
2851         &l3_ick,
2852         &l4_ick,
2853         &rm_ick,
2854         &gfx_l3_fck,
2855         &gfx_l3_ick,
2856         &gfx_cg1_ck,
2857         &gfx_cg2_ck,
2858         &sgx_fck,
2859         &sgx_ick,
2860         &d2d_26m_fck,
2861         &gpt10_fck,
2862         &gpt11_fck,
2863         &cpefuse_fck,
2864         &ts_fck,
2865         &usbtll_fck,
2866         &core_96m_fck,
2867         &mmchs3_fck,
2868         &mmchs2_fck,
2869         &mspro_fck,
2870         &mmchs1_fck,
2871         &i2c3_fck,
2872         &i2c2_fck,
2873         &i2c1_fck,
2874         &mcbsp5_fck,
2875         &mcbsp1_fck,
2876         &core_48m_fck,
2877         &mcspi4_fck,
2878         &mcspi3_fck,
2879         &mcspi2_fck,
2880         &mcspi1_fck,
2881         &uart2_fck,
2882         &uart1_fck,
2883         &fshostusb_fck,
2884         &core_12m_fck,
2885         &hdq_fck,
2886         &ssi_ssr_fck,
2887         &ssi_sst_fck,
2888         &core_l3_ick,
2889         &hsotgusb_ick,
2890         &sdrc_ick,
2891         &gpmc_fck,
2892         &security_l3_ick,
2893         &pka_ick,
2894         &core_l4_ick,
2895         &usbtll_ick,
2896         &mmchs3_ick,
2897         &icr_ick,
2898         &aes2_ick,
2899         &sha12_ick,
2900         &des2_ick,
2901         &mmchs2_ick,
2902         &mmchs1_ick,
2903         &mspro_ick,
2904         &hdq_ick,
2905         &mcspi4_ick,
2906         &mcspi3_ick,
2907         &mcspi2_ick,
2908         &mcspi1_ick,
2909         &i2c3_ick,
2910         &i2c2_ick,
2911         &i2c1_ick,
2912         &uart2_ick,
2913         &uart1_ick,
2914         &gpt11_ick,
2915         &gpt10_ick,
2916         &mcbsp5_ick,
2917         &mcbsp1_ick,
2918         &fac_ick,
2919         &mailboxes_ick,
2920         &omapctrl_ick,
2921         &ssi_l4_ick,
2922         &ssi_ick,
2923         &usb_l4_ick,
2924         &security_l4_ick2,
2925         &aes1_ick,
2926         &rng_ick,
2927         &sha11_ick,
2928         &des1_ick,
2929         &dss1_alwon_fck,
2930         &dss_tv_fck,
2931         &dss_96m_fck,
2932         &dss2_alwon_fck,
2933         &dss_ick,
2934         &cam_mclk,
2935         &cam_l3_ick,
2936         &cam_l4_ick,
2937         &usbhost_120m_fck,
2938         &usbhost_48m_fck,
2939         &usbhost_l3_ick,
2940         &usbhost_l4_ick,
2941         &usbhost_sar_fck,
2942         &usim_fck,
2943         &gpt1_fck,
2944         &wkup_32k_fck,
2945         &gpio1_fck,
2946         &wdt2_fck,
2947         &wkup_l4_ick,
2948         &usim_ick,
2949         &wdt2_ick,
2950         &wdt1_ick,
2951         &gpio1_ick,
2952         &omap_32ksync_ick,
2953         &gpt12_ick,
2954         &gpt1_ick,
2955         &per_96m_fck,
2956         &per_48m_fck,
2957         &uart3_fck,
2958         &gpt2_fck,
2959         &gpt3_fck,
2960         &gpt4_fck,
2961         &gpt5_fck,
2962         &gpt6_fck,
2963         &gpt7_fck,
2964         &gpt8_fck,
2965         &gpt9_fck,
2966         &per_32k_alwon_fck,
2967         &gpio6_fck,
2968         &gpio5_fck,
2969         &gpio4_fck,
2970         &gpio3_fck,
2971         &gpio2_fck,
2972         &wdt3_fck,
2973         &per_l4_ick,
2974         &gpio6_ick,
2975         &gpio5_ick,
2976         &gpio4_ick,
2977         &gpio3_ick,
2978         &gpio2_ick,
2979         &wdt3_ick,
2980         &uart3_ick,
2981         &gpt9_ick,
2982         &gpt8_ick,
2983         &gpt7_ick,
2984         &gpt6_ick,
2985         &gpt5_ick,
2986         &gpt4_ick,
2987         &gpt3_ick,
2988         &gpt2_ick,
2989         &mcbsp2_ick,
2990         &mcbsp3_ick,
2991         &mcbsp4_ick,
2992         &mcbsp2_fck,
2993         &mcbsp3_fck,
2994         &mcbsp4_fck,
2995         &emu_src_ck,
2996         &pclk_fck,
2997         &pclkx2_fck,
2998         &atclk_fck,
2999         &traceclk_src_fck,
3000         &traceclk_fck,
3001         &sr1_fck,
3002         &sr2_fck,
3003         &sr_l4_ick,
3004         &secure_32k_fck,
3005         &gpt12_fck,
3006         &wdt1_fck,
3007 };
3008
3009 #endif