2 * SDRC register values for RX51
4 * Copyright (C) 2008 Nokia Corporation
6 * Lauri Leukkunen <lauri.leukkunen@nokia.com>
8 * Original code by Juha Yrjola <juha.yrjola@solidboot.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/kernel.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
21 #include <plat/common.h>
22 #include <plat/clock.h>
23 #include <plat/sdrc.h>
26 /* In picoseconds, except for tREF (ns), tXP, tCKE, tWTR (clks) */
27 struct sdram_timings {
46 struct omap_sdrc_params rx51_sdrc_params[4];
48 static const struct sdram_timings rx51_timings[] = {
69 static unsigned long sdrc_get_fclk_period(long rate)
72 return 1000000000 / rate;
75 static unsigned int sdrc_ps_to_ticks(unsigned int time_ps, long rate)
77 unsigned long tick_ps;
79 /* Calculate in picosecs to yield more exact results */
80 tick_ps = sdrc_get_fclk_period(rate);
82 return (time_ps + tick_ps - 1) / tick_ps;
86 static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
87 int ticks, long rate, const char *name)
89 static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit,
95 nr_bits = end_bit - st_bit + 1;
96 if (ticks >= 1 << nr_bits)
98 mask = (1 << nr_bits) - 1;
99 *regval &= ~(mask << st_bit);
100 *regval |= ticks << st_bit;
102 printk(KERN_INFO "SDRC %s: %i ticks %i ns\n", name, ticks,
103 (unsigned int)sdrc_get_fclk_period(rate) * ticks /
111 #define SDRC_SET_ONE(reg, st, end, field, rate) \
112 if (set_sdrc_timing_regval((reg), (st), (end), \
113 rx51_timings->field, (rate), #field) < 0) \
116 #define SDRC_SET_ONE(reg, st, end, field, rate) \
117 if (set_sdrc_timing_regval((reg), (st), (end), \
118 rx51_timings->field) < 0) \
123 static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
124 int time, long rate, const char *name)
126 static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit,
136 ticks = sdrc_ps_to_ticks(time, rate);
139 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks,
142 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks);
149 #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
150 if (set_sdrc_timing_regval_ps((reg), (st), (end), \
151 rx51_timings->field, \
152 (rate), #field) < 0) \
156 #define SDRC_SET_ONE_PS(reg, st, end, field, rate) \
157 if (set_sdrc_timing_regval_ps((reg), (st), (end), \
158 rx51_timings->field, (rate)) < 0) \
162 static int sdrc_timings(int id, long rate)
166 u32 actim_ctrla = 0, actim_ctrlb = 0;
169 long l3_rate = rate / 1000;
171 SDRC_SET_ONE_PS(&actim_ctrla, 0, 4, tDAL, l3_rate);
172 SDRC_SET_ONE_PS(&actim_ctrla, 6, 8, tDPL, l3_rate);
173 SDRC_SET_ONE_PS(&actim_ctrla, 9, 11, tRRD, l3_rate);
174 SDRC_SET_ONE_PS(&actim_ctrla, 12, 14, tRCD, l3_rate);
175 SDRC_SET_ONE_PS(&actim_ctrla, 15, 17, tRP, l3_rate);
176 SDRC_SET_ONE_PS(&actim_ctrla, 18, 21, tRAS, l3_rate);
177 SDRC_SET_ONE_PS(&actim_ctrla, 22, 26, tRC, l3_rate);
178 SDRC_SET_ONE_PS(&actim_ctrla, 27, 31, tRFC, l3_rate);
180 SDRC_SET_ONE_PS(&actim_ctrlb, 0, 7, tXSR, l3_rate);
182 SDRC_SET_ONE(&actim_ctrlb, 8, 10, tXP, l3_rate);
183 SDRC_SET_ONE(&actim_ctrlb, 12, 14, tCKE, l3_rate);
184 SDRC_SET_ONE(&actim_ctrlb, 16, 17, tWTR, l3_rate);
186 ticks_per_ms = l3_rate;
187 rfr = rx51_timings[0].tREF * ticks_per_ms / 1000000;
188 if (rfr > 65535 + 50)
194 printk(KERN_INFO "SDRC tREF: %i ticks\n", rfr);
198 rfr_ctrl = l | 0x1; /* autorefresh, reload counter with 1xARCV */
200 rx51_sdrc_params[id].rate = rate;
201 rx51_sdrc_params[id].actim_ctrla = actim_ctrla;
202 rx51_sdrc_params[id].actim_ctrlb = actim_ctrlb;
203 rx51_sdrc_params[id].rfr_ctrl = rfr_ctrl;
204 rx51_sdrc_params[id].mr = 0x32;
206 rx51_sdrc_params[id + 1].rate = 0;
211 struct omap_sdrc_params *rx51_get_sdram_timings(void)
215 err = sdrc_timings(0, 41500000);
216 err |= sdrc_timings(1, 83000000);
217 err |= sdrc_timings(2, 166000000);
219 return &rx51_sdrc_params[0];