2 * linux/arch/arm/mach-omap2/board-n800-flash.c
4 * Copyright (C) 2006 Nokia Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/platform_device.h>
14 #include <asm/mach/flash.h>
15 #include <linux/mtd/onenand_regs.h>
18 #include <asm/arch/onenand.h>
19 #include <asm/arch/board.h>
20 #include <asm/arch/gpmc.h>
22 struct mtd_partition n800_partitions[ONENAND_MAX_PARTITIONS];
24 int n800_onenand_setup(void __iomem *, int freq);
26 static struct omap_onenand_platform_data n800_onenand_data = {
28 .parts = n800_partitions,
29 .nr_parts = 0, /* filled later */
30 .onenand_setup = n800_onenand_setup,
33 static struct platform_device n800_onenand_device = {
34 .name = "omap2-onenand",
37 .platform_data = &n800_onenand_data,
41 static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
43 struct gpmc_timings t;
46 const int t_avdp = 12;
47 const int t_aavdh = 7;
51 const int t_cez = 20; /* max of t_cez, t_oez */
56 memset(&t, 0, sizeof(t));
62 t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
63 t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh);
64 t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa);
65 t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce));
66 t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe));
67 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
68 t.cs_rd_off = t.oe_off;
69 t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez);
72 t.adv_wr_off = t.adv_rd_off;
74 if (cpu_is_omap34xx()) {
75 t.wr_data_mux_bus = t.we_on;
76 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
78 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
79 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
80 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
82 /* Configure GPMC for asynchronous read */
83 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
84 GPMC_CONFIG1_DEVICESIZE_16 |
85 GPMC_CONFIG1_MUXADDDATA);
87 return gpmc_cs_set_timings(cs, &t);
90 static unsigned short omap2_onenand_readw(void __iomem *addr)
95 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
100 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
101 int sync_write, int hf)
105 reg = omap2_onenand_readw(onenand_base + ONENAND_REG_SYS_CFG1);
106 reg &= ~((0x7 << ONENAND_SYS_CFG1_BRL_SHIFT) | (0x7 << 9));
107 reg |= (latency << ONENAND_SYS_CFG1_BRL_SHIFT) |
108 ONENAND_SYS_CFG1_SYNC_READ |
109 ONENAND_SYS_CFG1_BL_16;
111 reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
113 reg &= ~ONENAND_SYS_CFG1_SYNC_WRITE;
115 reg |= ONENAND_SYS_CFG1_HF;
117 reg &= ~ONENAND_SYS_CFG1_HF;
118 omap2_onenand_writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
121 static int omap2_onenand_set_sync_mode(int cs, void __iomem *onenand_base,
124 struct gpmc_timings t;
125 const int t_cer = 15;
126 const int t_avdp = 12;
127 const int t_cez = 20; /* max of t_cez, t_oez */
129 const int t_wpl = 40;
130 const int t_wph = 30;
131 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
132 int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
133 int err, ticks_cez, sync_write = 0, first_time = 0, hf = 0;
137 /* Very first call freq is not known */
138 err = omap2_onenand_set_async_mode(cs, onenand_base);
141 reg = omap2_onenand_readw(onenand_base +
142 ONENAND_REG_VERSION_ID);
143 switch ((reg >> 4) & 0xf) {
168 min_gpmc_clk_period = 12; /* 83 MHz */
175 if (cpu_is_omap34xx())
179 min_gpmc_clk_period = 15; /* 66 MHz */
186 if (cpu_is_omap34xx())
190 min_gpmc_clk_period = 18; /* 54 MHz */
200 tick_ns = gpmc_ticks_to_ns(1);
201 div = gpmc_cs_calc_divider(cs, min_gpmc_clk_period);
202 gpmc_clk_ns = gpmc_ticks_to_ns(div);
203 if (gpmc_clk_ns < 15) /* >66Mhz */
207 else if (gpmc_clk_ns >= 25) /* 40 MHz*/
213 set_onenand_cfg(onenand_base, latency, sync_write, hf);
216 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
218 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
219 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
221 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
222 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
225 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
227 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
229 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG2, reg);
230 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG3);
232 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG3, reg);
233 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG4);
236 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG4, reg);
239 /* Set synchronous read timings */
240 memset(&t, 0, sizeof(t));
241 t.sync_clk = min_gpmc_clk_period;
244 fclk_offset_ns = gpmc_round_ns_to_ticks(max_t(int, t_ces, t_avds));
245 fclk_offset = gpmc_ns_to_ticks(fclk_offset_ns);
246 t.page_burst_access = gpmc_clk_ns;
249 t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
250 t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
251 t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
252 t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
253 t.cs_rd_off = t.oe_off;
254 ticks_cez = ((gpmc_ns_to_ticks(t_cez) + div - 1) / div) * div;
255 t.rd_cycle = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div +
260 t.adv_wr_off = t.adv_rd_off;
262 t.we_off = t.cs_rd_off;
263 t.cs_wr_off = t.cs_rd_off;
264 t.wr_cycle = t.rd_cycle;
265 if (cpu_is_omap34xx()) {
266 t.wr_data_mux_bus = gpmc_ticks_to_ns(fclk_offset +
267 gpmc_ns_to_ticks(min_gpmc_clk_period +
269 t.wr_access = t.access;
272 t.adv_wr_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer));
273 t.we_on = t.adv_wr_off + gpmc_round_ns_to_ticks(t_aavdh);
274 t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl);
275 t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph);
276 t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez);
277 if (cpu_is_omap34xx()) {
278 t.wr_data_mux_bus = t.we_on;
279 t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds);
283 /* Configure GPMC for synchronous read */
284 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1,
285 GPMC_CONFIG1_WRAPBURST_SUPP |
286 GPMC_CONFIG1_READMULTIPLE_SUPP |
287 GPMC_CONFIG1_READTYPE_SYNC |
288 (sync_write ? GPMC_CONFIG1_WRITEMULTIPLE_SUPP : 0) |
289 (sync_write ? GPMC_CONFIG1_WRITETYPE_SYNC : 0) |
290 GPMC_CONFIG1_CLKACTIVATIONTIME(fclk_offset) |
291 GPMC_CONFIG1_PAGE_LEN(2) |
292 (cpu_is_omap34xx() ? 0 :
293 (GPMC_CONFIG1_WAIT_READ_MON |
294 GPMC_CONFIG1_WAIT_PIN_SEL(0))) |
295 GPMC_CONFIG1_DEVICESIZE_16 |
296 GPMC_CONFIG1_DEVICETYPE_NOR |
297 GPMC_CONFIG1_MUXADDDATA);
299 err = gpmc_cs_set_timings(cs, &t);
303 set_onenand_cfg(onenand_base, latency, sync_write, hf);
308 int n800_onenand_setup(void __iomem *onenand_base, int freq)
310 struct omap_onenand_platform_data *datap = &n800_onenand_data;
311 struct device *dev = &n800_onenand_device.dev;
313 /* Set sync timings in GPMC */
314 if (omap2_onenand_set_sync_mode(datap->cs, onenand_base, freq) < 0) {
315 dev_err(dev, "Unable to set synchronous mode\n");
322 void __init n800_flash_init(void)
324 const struct omap_partition_config *part;
327 n800_onenand_data.gpio_irq = cpu_is_omap34xx() ? 65 : 26;
329 while ((part = omap_get_nr_config(OMAP_TAG_PARTITION,
330 struct omap_partition_config, i)) != NULL) {
331 struct mtd_partition *mpart;
333 mpart = n800_partitions + i;
334 mpart->name = (char *) part->name;
335 mpart->size = part->size;
336 mpart->offset = part->offset;
337 mpart->mask_flags = part->mask_flags;
339 if (i == ARRAY_SIZE(n800_partitions)) {
340 printk(KERN_ERR "Too many partitions supplied\n");
344 n800_onenand_data.nr_parts = i;
345 if (platform_device_register(&n800_onenand_device) < 0) {
346 printk(KERN_ERR "Unable to register OneNAND device\n");